Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Stefan Roese, 01 Aug 2005:
+ - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
+ (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
+ for details.
+ - Sycamore (PPC405GPr) eval board added (Walnut port is extended
+ to run on both 405GP and 405GPr eval boards).
+
+* Patch by Steven Blakeslee, 27 Jul 2005:
+ - Add support for AMCC PPC440EP/GR.
+ - Add support for AMCC Yosemite PPC440EP eval board.
+ - Add support for AMCC Yellowstone PPC440GR eval board.
+
* Fix sysmon POST problem: check I2C error codes
This fixes a problem of displaying bogus voltages when the voltages
are so low that the I2C devices start failing while the rest of the
GEN860T MPC860T
GEN860T_SC MPC860T
+Stefan Roese <sr@denx.de>
+
+ sycamore PPC4xx
+ walnut PPC4xx
+
Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
CRAYL1 PPC4xx
ERIC PPC4xx
- WALNUT405 PPC4xx
MOUSSE MPC824x
#########################################################################
LIST_4xx=" \
- ADCIOP AR405 ASH405 BUBINGA405EP \
+ ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
- EBONY ERIC EXBITGEN HUB405 \
+ ebony ERIC EXBITGEN HUB405 \
JSE MIP405 MIP405T ML2 \
- ml300 OCOTEA OCRTC ORSG \
+ ml300 ocotea OCRTC ORSG \
PCI405 PIP405 PLU405 PMC405 \
PPChameleonEVB VOH405 W7OLMC W7OLMG \
- WALNUT405 WUH405 XPEDITE1K \
+ walnut WUH405 XPEDITE1K yellowstone \
+ yosemite \
"
#########################################################################
ASH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
-BUBINGA405EP_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
+bamboo_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
+
+bubinga_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
CANBT_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
DU405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
-EBONY_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ebony
+ebony_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
ERIC_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx eric
ml300_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
-OCOTEA_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ocotea
+ocotea_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
OCRTC_config \
ORSG_config: unconfig
sbc405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sbc405
+sycamore_config: unconfig
+ @echo "Configuring for sycamore board as subset of walnut..."
+ @./mkconfig -a walnut ppc ppc4xx walnut amcc
+
VOH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
W7OLMG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx w7o
-WALNUT405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx walnut405
+walnut_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
WUH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
XPEDITE1K_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+yosemite_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
+
+yellowstone_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
+
#########################################################################
## MPC8220 Systems
#########################################################################
CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC
CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG
- CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT405
+ CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT
CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900
CONFIG_FPS860L CONFIG_ZUMA
FADS850SAR_config omap1610h2_config TQM850L_config
FADS860T_config omap1610inn_config TQM855L_config
FPS850L_config omap5912osk_config TQM860L_config
- omap2420h4_config WALNUT405_config
+ omap2420h4_config walnut_config
Yukon8220_config
ZPC1900_config
CFG_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
- Walnut405.h should work for you. I'd set it to a value larger
+ walnut.h should work for you. I'd set it to a value larger
than your SDRAM module. If you have a 64MB SDRAM module, set
it above 400_0000. Just make sure your board has no resources
that are supposed to respond to that address! That code in
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+#OBJS += flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+
+#if 0 /* test-only */
+ mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
+
+ mtebc(pb1ap, 0x00000000);
+ mtebc(pb1cr, 0x00000000);
+
+ mtebc(pb2ap, 0x04814500);
+ /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
+#else
+ mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
+#endif
+
+ mtebc(pb3ap, 0x00000000);
+ mtebc(pb3cr, 0x00000000);
+
+ mtebc(pb4ap, 0x00000000);
+ mtebc(pb4cr, 0x00000000);
+
+ mtebc(pb5ap, 0x00000000);
+ mtebc(pb5cr, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /*CPLD cs */
+ /*setup Address lines for flash sizes larger than 16Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+
+ /*setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /*UART1 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+ /*setup USB 2.0 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+ out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+
+ /*--------------------------------------------------------------------
+ * Setup other serial configuration
+ *-------------------------------------------------------------------*/
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
+ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+#if 0 /* test-only */
+ /*clear tmrclk divisor */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+ /*enable ethernet */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+ /*enable usb 1.1 fs device and remove usb 2.0 reset */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+
+ /*get rid of flash write protect */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ sys_info_t sysinfo;
+ unsigned char *s = getenv("serial#");
+
+ get_sys_info(&sysinfo);
+
+ printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ return (0);
+}
+
+/*************************************************************************
+ * sdram_init -- doesn't use serial presence detect.
+ *
+ * Assumes: 256 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+void sdram_init(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_clktr, 0x40000000); /* ?? */
+ mtsdram(mem_wddctr, 0x40000000); /* ?? */
+
+ /*clear this first, if the DDR is enabled by a debugger
+ then you can not make changes. */
+ mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+
+ mtsdram(mem_tr0, 0x410a4012); /* ?? */
+ mtsdram(mem_tr1, 0x8080080b); /* ?? */
+ mtsdram(mem_rtr, 0x04080000); /* ?? */
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(mem_cfg0, 0x84000000); /* Enable */
+
+ for (;;) {
+ mfsdram(mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+}
+
+/*************************************************************************
+ * long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+ sdram_init();
+ return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_KBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+ unsigned long addr;
+
+ /*--------------------------------------------------------------------------+
+ * Bamboo is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PAE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return 0;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 EP PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Bamboo is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ /*
+ 0xf0000000 must be first, before relocation SA_I must be off to use the
+ dcache as stack. It is patched after relocation to enable SA_I
+ */
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/bamboo/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+long int spd_sdram(void);
+
+#include <common.h>
+#include <asm/processor.h>
+
+int board_early_init_f(void)
+{
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000010);
+ mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
+ mtdcr(uictr, 0x00000010); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned char *s = getenv("serial#");
+
+ puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+/* -------------------------------------------------------------------------
+ initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ the necessary info for SDRAM controller configuration
+ ------------------------------------------------------------------------- */
+long int initdram(int board_type)
+{
+ long int ret;
+
+ ret = spd_sdram();
+ return ret;
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("test: xxx MB - ok\n");
+
+ return (0);
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CFG_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ }
+
+ /* 2 banks */
+ else {
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b1 = -size_b1;
+ pbcr = (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb1cr = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb1cr);
+ base_b0 = base_b1 - size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb0cr = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - CFG_MONITOR_LEN,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 - CFG_MONITOR_LEN,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - CFG_MONITOR_LEN,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+long int fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+ uint reg;
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char status;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(ebccfga, xbcfg);
+ reg = mfdcr(ebccfgd);
+ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
+
+ mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
+ mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
+ mtebc(pb7ap, 0x01015280); /* FPGA registers */
+ mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
+
+ /* read FPGA_REG0 and set the bus controller */
+ status = *fpga_base;
+ if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+ mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
+ mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
+ } else {
+ mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
+ mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
+
+ /* set CS2 if FLASH_ONBD_N == 0 */
+ if (!(status & FLASH_ONBD_N)) {
+ mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
+ mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
+ }
+ }
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ sys_info_t sysinfo;
+ unsigned char *s = getenv("serial#");
+
+ get_sys_info(&sysinfo);
+
+ printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ return (0);
+}
+
+long int initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram(0);
+#else
+ dram_size = fixed_sdram();
+#endif
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x08000000;
+ uint *p;
+
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram(void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram(mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The ebony board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ strap = mfdcr(cpc0_strp1);
+ if ((strap & 0x00100000) == 0) {
+ printf("PCI: CPC0_STRP1[PAE] not set.\n");
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r(PCIX0_PIM0SA, 0); /* disable */
+ out32r(PCIX0_PIM1SA, 0); /* disable */
+ out32r(PCIX0_PIM2SA, 0); /* disable */
+ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAH, 0);
+ out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+
+ out32r(PCIX0_BAR0, 0);
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+ out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* The ebony board is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
+ {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
+ {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
+ {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
+ {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/ebony/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IBM 440GX Reference Platform (Ocotea) board
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
+ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
+ {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
+ {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
+ {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] =
+ flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbtab_end
--- /dev/null
+/*
+ * Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include "ocotea.h"
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <440gx_enet.h>
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+long int fixed_sdram (void);
+void fpga_init (void);
+
+int board_early_init_f (void)
+{
+ unsigned long mfr;
+ unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned long cs0_base;
+ unsigned long cs0_size;
+ unsigned long cs0_twt;
+ unsigned long cs2_base;
+ unsigned long cs2_size;
+ unsigned long cs2_twt;
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+ EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+ EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ if (switch_status & 0x40) {
+ cs0_base = 0xFFE00000;
+ cs0_size = EBC_BXCR_BS_2MB;
+ cs0_twt = 8;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_4MB;
+ cs2_twt = 10;
+ } else {
+ cs0_base = 0xFFC00000;
+ cs0_size = EBC_BXCR_BS_4MB;
+ cs0_twt = 10;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_2MB;
+ cs2_twt = 8;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+ cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | 4 MB FLASH. Initialize bank 2 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+ cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+ mtdcr (uic0er, 0x00000000); /* disable all */
+ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
+ mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+ mtdcr (uic1er, 0x00000000); /* disable all */
+ mtdcr (uic1cr, 0x00000000); /* all non-critical */
+ mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
+ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+ mtdcr (uic2er, 0x00000000); /* disable all */
+ mtdcr (uic2cr, 0x00000000); /* all non-critical */
+ mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr (uicb0sr, 0xfc000000); /* clear all */
+ mtdcr (uicb0er, 0x00000000); /* disable all */
+ mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+ mtdcr (uicb0pr, 0xfc000000); /* */
+ mtdcr (uicb0tr, 0x00000000); /* */
+ mtdcr (uicb0vr, 0x00000001); /* */
+ mfsdr (sdr_mfr, mfr);
+ mfr &= ~SDR0_MFR_ECS_MASK;
+/* mtsdr(sdr_mfr, mfr); */
+ fpga_init();
+
+ return 0;
+}
+
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ unsigned char *s = getenv ("serial#");
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
+ if (s != NULL) {
+ puts (", serial# ");
+ puts (s);
+ }
+ putc ('\n');
+
+ printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+ printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+ printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram (0);
+#else
+ dram_size = fixed_sdram ();
+#endif
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) 0x08000000;
+ uint *p;
+
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram (mem_mcsts, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+ unsigned long strap;
+
+ /*--------------------------------------------------------------------------+
+ * The ocotea board is always configured as the host & requires the
+ * PCI arbiter to be enabled.
+ *--------------------------------------------------------------------------*/
+ mfsdr(sdr_sdstp1, strap);
+ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /*--------------------------------------------------------------------------+
+ * Disable everything
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0SA, 0 ); /* disable */
+ out32r( PCIX0_PIM1SA, 0 ); /* disable */
+ out32r( PCIX0_PIM2SA, 0 ); /* disable */
+ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+ /*--------------------------------------------------------------------------+
+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+ * options to not support sizes such as 128/256 MB.
+ *--------------------------------------------------------------------------*/
+ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAH, 0 );
+ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+ out32r( PCIX0_BAR0, 0 );
+
+ /*--------------------------------------------------------------------------+
+ * Program the board's subsystem id/vendor id
+ *--------------------------------------------------------------------------*/
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* The ocotea board is always configured as host. */
+ return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+void fpga_init(void)
+{
+ unsigned long group;
+ unsigned long sdr0_pfc0;
+ unsigned long sdr0_pfc1;
+ unsigned long sdr0_cust0;
+ unsigned long pvr;
+
+ mfsdr (sdr_pfc0, sdr0_pfc0);
+ mfsdr (sdr_pfc1, sdr0_pfc1);
+ group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
+ pvr = get_pvr ();
+
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
+ if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_ENABLE);
+ mtsdr (sdr_pfc0, sdr0_pfc0);
+ mtsdr (sdr_pfc1, sdr0_pfc1);
+ } else {
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
+ switch (group)
+ {
+ case 0:
+ case 1:
+ case 2:
+ /* CPU trace A */
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_ENABLE);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+ mtsdr (sdr_pfc0, sdr0_pfc0);
+ mtsdr (sdr_pfc1, sdr0_pfc1);
+ break;
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ /* CPU trace B - Over EBMI */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
+ mtsdr (sdr_pfc0, sdr0_pfc0);
+ mtsdr (sdr_pfc1, sdr0_pfc1);
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_DISABLE);
+ break;
+ }
+ }
+
+ /* Initialize the ethernet specific functions in the fpga */
+ mfsdr(sdr_pfc1, sdr0_pfc1);
+ mfsdr(sdr_cust0, sdr0_cust0);
+ if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
+ ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
+ (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+ FPGA_REG3_ENET_GROUP7);
+ }
+ else
+ {
+ if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_GROUP7);
+ }
+ else
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_GROUP8);
+ }
+ }
+ }
+ else
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+ FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+ }
+ else
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+ }
+ }
+ out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
+ FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
+ FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
+
+ /* reset the gigabyte phy if necessary */
+ if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
+ }
+ else
+ {
+ out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
+ }
+ }
+
+ /* Turn off the LED's */
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
+ FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
+ FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
+
+ return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+ return (ctrlc());
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Board specific FPGA stuff ... */
+#define FPGA_REG0 (CFG_FPGA_BASE + 0x00)
+#define FPGA_REG0_SSCG_MASK 0x80
+#define FPGA_REG0_SSCG_DISABLE 0x00
+#define FPGA_REG0_SSCG_ENABLE 0x80
+#define FPGA_REG0_BOOT_MASK 0x40
+#define FPGA_REG0_BOOT_LARGE_FLASH 0x00
+#define FPGA_REG0_BOOT_SMALL_FLASH 0x40
+#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ARBITER_MASK 0x04
+#define FPGA_REG0_ARBITER_EXT 0x00
+#define FPGA_REG0_ARBITER_INT 0x04
+#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02
+#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00
+#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
+#define FPGA_REG0_FLASH 0x01
+#define FPGA_REG1 (CFG_FPGA_BASE + 0x01)
+#define FPGA_REG1_9772_FSELFBX_MASK 0x80
+#define FPGA_REG1_9772_FSELFBX_6 0x00
+#define FPGA_REG1_9772_FSELFBX_10 0x80
+#define FPGA_REG1_9531_SX_MASK 0x60
+#define FPGA_REG1_9531_SX_33MHZ 0x00
+#define FPGA_REG1_9531_SX_100MHZ 0x20
+#define FPGA_REG1_9531_SX_66MHZ 0x40
+#define FPGA_REG1_9531_SX_133MHZ 0x60
+#define FPGA_REG1_9772_FSELBX_MASK 0x18
+#define FPGA_REG1_9772_FSELBX_4 0x00
+#define FPGA_REG1_9772_FSELBX_6 0x08
+#define FPGA_REG1_9772_FSELBX_8 0x10
+#define FPGA_REG1_9772_FSELBX_10 0x18
+#define FPGA_REG1_SOURCE_MASK 0x07
+#define FPGA_REG1_SOURCE_TC 0x00
+#define FPGA_REG1_SOURCE_66MHZ 0x01
+#define FPGA_REG1_SOURCE_50MHZ 0x02
+#define FPGA_REG1_SOURCE_33MHZ 0x03
+#define FPGA_REG1_SOURCE_25MHZ 0x04
+#define FPGA_REG1_SOURCE_SSDIV1 0x05
+#define FPGA_REG1_SOURCE_SSDIV2 0x06
+#define FPGA_REG1_SOURCE_SSDIV4 0x07
+#define FPGA_REG2 (CFG_FPGA_BASE + 0x02)
+#define FPGA_REG2_TC0 0x80
+#define FPGA_REG2_TC1 0x40
+#define FPGA_REG2_TC2 0x20
+#define FPGA_REG2_TC3 0x10
+#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG2_EXT_INTFACE_MASK 0x04
+#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
+#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
+#define FPGA_REG2_DEFAULT_UART1_N 0x01
+#define FPGA_REG3 (CFG_FPGA_BASE + 0x03)
+#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
+#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/
+#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG3_ENET_GROUP0 0x00
+#define FPGA_REG3_ENET_GROUP1 0x10
+#define FPGA_REG3_ENET_GROUP2 0x20
+#define FPGA_REG3_ENET_GROUP3 0x30
+#define FPGA_REG3_ENET_GROUP4 0x40
+#define FPGA_REG3_ENET_GROUP5 0x50
+#define FPGA_REG3_ENET_GROUP6 0x60
+#define FPGA_REG3_ENET_GROUP7 0x70
+#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
+#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
+#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
+#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
+#define FPGA_REG3_STAT_MASK 0x0F
+#define FPGA_REG3_STAT_LED8_ENAB 0x08
+#define FPGA_REG3_STAT_LED4_ENAB 0x04
+#define FPGA_REG3_STAT_LED2_ENAB 0x02
+#define FPGA_REG3_STAT_LED1_ENAB 0x01
+#define FPGA_REG3_STAT_LED8_DISAB 0x00
+#define FPGA_REG3_STAT_LED4_DISAB 0x00
+#define FPGA_REG3_STAT_LED2_DISAB 0x00
+#define FPGA_REG3_STAT_LED1_DISAB 0x00
+#define FPGA_REG4 (CFG_FPGA_BASE + 0x04)
+#define FPGA_REG4_GPHY_MODE10 0x80
+#define FPGA_REG4_GPHY_MODE100 0x40
+#define FPGA_REG4_GPHY_MODE1000 0x20
+#define FPGA_REG4_GPHY_FRC_DPLX 0x10
+#define FPGA_REG4_GPHY_ANEG_DIS 0x08
+#define FPGA_REG4_CONNECT_PHYS 0x04
+
+
+#define SDR0_CUST0_ENET3_MASK 0x00000080
+#define SDR0_CUST0_ENET3_COPPER 0x00000000
+#define SDR0_CUST0_ENET3_FIBER 0x00000080
+#define SDR0_CUST0_RGMII3_MASK 0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB 0x00000000
+#define SDR0_CUST0_RGMII3_RTBI 0x00000040
+#define SDR0_CUST0_RGMII3_RGMII 0x00000050
+#define SDR0_CUST0_RGMII3_TBI 0x00000060
+#define SDR0_CUST0_RGMII3_GMII 0x00000070
+#define SDR0_CUST0_ENET2_MASK 0x00000008
+#define SDR0_CUST0_ENET2_COPPER 0x00000000
+#define SDR0_CUST0_ENET2_FIBER 0x00000008
+#define SDR0_CUST0_RGMII2_MASK 0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB 0x00000000
+#define SDR0_CUST0_RGMII2_RTBI 0x00000004
+#define SDR0_CUST0_RGMII2_RGMII 0x00000005
+#define SDR0_CUST0_RGMII2_TBI 0x00000006
+#define SDR0_CUST0_RGMII2_GMII 0x00000007
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/amcc/ocotea/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/440gx_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CFG_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ } else {
+ /* 2 banks */
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b1 = -size_b1;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb1cr = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb1cr);
+ base_b0 = base_b1 - size_b0;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(ebccfgd, pbcr);
+ /* printf("pb0cr = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 -
+ monitor_flash_len,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 -
+ monitor_flash_len,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the Walnut/Sycamore board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+ | IRQ 27 (EXT IRQ 2) Not Used
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for Walnut board:
+ | An interrupt taken for the FPGA (IRQ 25) indicates that either
+ | the Mouse, Keyboard, IRDA, or External Expansion caused the
+ | interrupt. The FPGA must be read to determine which device
+ | caused the interrupt. The default setting of the FPGA clears
+ |
+ +-------------------------------------------------------------------------*/
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /* set UART1 control to select CTS/RTS */
+#define FPGA_BRDC 0xF0300004
+ *(volatile char *)(FPGA_BRDC) |= 0x1;
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned char *s = getenv("serial#");
+ uint pvr = get_pvr();
+
+ if (pvr == PVR_405GPR_RB) {
+ puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+ } else {
+ puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
+ }
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+/*
+ * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * the necessary info for SDRAM controller configuration
+ */
+long int initdram(int board_type)
+{
+ return spd_sdram(0);
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("test: xxx MB - ok\n");
+
+ return (0);
+}
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(BOARD).a
-
-OBJS = $(BOARD).o flash.o
-SOBJS = init.o
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-long int spd_sdram (void);
-
-#include <common.h>
-#include <asm/processor.h>
-
-
-int board_early_init_f (void)
-{
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000010);
- mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
- mtdcr (uictr, 0x00000010); /* set int trigger levels */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-
-#if 0
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
- /* CS1 */
- /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb1ap, 0x02815480);
- mtebc (pb1cr, 0xF0018000);
-
- p = (unsigned int*)0xEF600708;
- t = *p;
- t = t | 0x00000400;
- *p = t;
-
- /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb2ap, 0x04815A80);
- mtebc (pb2cr, 0xF0118000);
-
- /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb3ap, 0x01815280);
- mtebc (pb3cr, 0xF0218000);
-
- /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb7ap, 0x01815280);
- mtebc (pb7cr, 0xF0318000);
-
-
- /* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC 0xF0300004
- *(volatile char *) (FPGA_BRDC) |= 0x1;
-
-#endif
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- unsigned char *s = getenv ("serial#");
-
- puts ("Board: IBM 405EP Eval Board");
-
- if (s != NULL) {
- puts (", serial# ");
- puts (s);
- }
- putc ('\n');
-
- return (0);
-}
-
-
-/* -------------------------------------------------------------------------
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
- ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- long int ret;
-
- ret = spd_sdram ();
- return ret;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_BUBINGA405EP
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Only one bank */
- if (CFG_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1,
- &flash_info[0]);
- /* Also protect sector containing initial power-up instruction */
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
- size_b1 = 0;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else {
- size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr (ebccfga, pb0cr);
- pbcr = mfdcr (ebccfgd);
- mtdcr (ebccfga, pb0cr);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 |
- (((size_b1 / 1024 / 1024) - 1) << 17);
- mtdcr (ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr (ebccfga, pb1cr);
- pbcr = mfdcr (ebccfgd);
- mtdcr (ebccfga, pb1cr);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 |
- (((size_b0 / 1024 / 1024) - 1) << 17);
- mtdcr (ebccfgd, pbcr);
- /* printf("pb0cr = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- base_b0 + size_b0 - CFG_MONITOR_LEN,
- base_b0 + size_b0 - 1, &flash_info[0]);
- /* Also protect sector containing initial power-up instruction */
- /* (flash_protect() checks address range - other call ignored) */
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
- (void) flash_protect (FLAG_PROTECT_SET,
- 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- base_b1 + size_b1 - CFG_MONITOR_LEN,
- base_b1 + size_b1 - 1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void) flash_protect (FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - CFG_MONITOR_LEN,
- base_b0 + size_b0 - 1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- } /* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-#if 0 /* test-only */
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " "
-#else
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " "
-#endif
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- /* printf("\ndev_code=%x\n", value); */
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE) AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE) SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *) info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer (0);
- last = 0;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
- printf ("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay (1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7 (info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7 (info, l_sect);
-
- DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*------------------------------------------------------------------------------+ */
-/* */
-/* This source code has been made available to you by IBM on an AS-IS */
-/* basis. Anyone receiving this source is licensed under IBM */
-/* copyrights to use it in any way he or she deems fit, including */
-/* copying it, modifying it, compiling it, and redistributing it either */
-/* with or without modifications. No license under IBM patents or */
-/* patent applications is to be implied by the copyright license. */
-/* */
-/* Any user of this software should understand that IBM cannot provide */
-/* technical support for this software and will not be responsible for */
-/* any consequences resulting from the use of this software. */
-/* */
-/* Any person who transfers this source code or any derivative work */
-/* must include the IBM copyright notice, this paragraph, and the */
-/* preceding two paragraphs in the transferred software. */
-/* */
-/* COPYRIGHT I B M CORPORATION 1995 */
-/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
-/*----------------------------------------------------------------------------- */
-/* Function: sdram_init */
-/* Description: Dummy implementation here - done in C later */
-/*----------------------------------------------------------------------------- */
- .globl sdram_init
-sdram_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/bubinga405ep/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
-/*
- cpu/ppc4xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
-*/
- cpu/ppc4xx/start.o (.text)
- board/bubinga405ep/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-
- common/environment.o(.text)
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(BOARD).a
-
-OBJS = $(BOARD).o flash.o
-SOBJS = init.o
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFF80000
-endif
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include "ebony.h"
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-long int fixed_sdram (void);
-
-int board_early_init_f (void)
-{
- uint reg;
- unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
- unsigned char status;
-
-
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtdcr (ebccfga, xbcfg);
- reg = mfdcr (ebccfgd);
- mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */
-
- mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */
- mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
- mtebc (pb7ap, 0x01015280); /* FPGA registers */
- mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
-
- /* read FPGA_REG0 and set the bus controller */
- status = *fpga_base;
- if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
- mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */
- mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
- mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */
- mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
- } else {
- mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */
- mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
-
- /* set CS2 if FLASH_ONBD_N == 0 */
- if (!(status & FLASH_ONBD_N)) {
- mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */
- mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
- }
- }
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- return 0;
-}
-
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
-
- get_sys_info (&sysinfo);
-
- printf ("Board: IBM 440GP Evaluation Board (Ebony)\n");
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
- return (0);
-}
-
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram (0);
-#else
- dram_size = fixed_sdram ();
-#endif
- return dram_size;
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) 0x08000000;
- uint *p;
-
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- *
- * Assumes: 128 MB, non-ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-long int fixed_sdram (void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
- for (;;) {
- mfsdram (mem_mcsts, reg);
- if (reg & 0x80000000)
- break;
- }
-
- return (128 * 1024 * 1024); /* 128 MB */
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ebony board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- strap = mfdcr(cpc0_strp1);
- if( (strap & 0x00100000) == 0 ){
- printf("PCI: CPC0_STRP1[PAE] not set.\n");
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIX0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The ebony board is always configured as host. */
- return(1);
-}
-#endif /* defined(CONFIG_PCI) */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
-
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
- {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
- {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
- {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
- {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
- {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
- {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t *info);
-#endif
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_EBONY
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void) {
- unsigned long total_b = 0;
- unsigned long size_b[CFG_MAX_FLASH_BANKS];
- unsigned char * fpga_base = (unsigned char *)CFG_FPGA_BASE;
- unsigned char switch_status;
- unsigned short index = 0;
- int i;
-
-
- /* read FPGA base register FPGA_REG0 */
- switch_status = *fpga_base;
-
- /* check the bitmap of switch status */
- if (switch_status & BOOT_SMALL_FLASH) {
- index += BOOT_SMALL_FLASH_VAL;
- }
- if (switch_status & FLASH_ONBD_N) {
- index += FLASH_ONBD_N_VAL;
- }
- if (switch_status & FLASH_SRAM_SEL) {
- index += FLASH_SRAM_SEL_VAL;
- }
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size(
- (vu_long *)flash_addr_table[index][i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i]<<20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- return total_b;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
- );
- }
- printf ("\n");
- return;
- }
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
- static ulong flash_get_size (vu_long *addr, flash_info_t *info)
- {
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
- udelay(1000);
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_F016D:
- info->flash_id += FLASH_AMD016;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (FLASH_WORD_SIZE)STM_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040) ||
- (info->flash_id == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *)info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
- }
-
- int wait_for_DQ7(flash_info_t *info, int sect)
- {
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
- }
-
-/*-----------------------------------------------------------------------
- */
-
- int flash_erase (flash_info_t *info, int s_first, int s_last)
- {
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
- DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
- }
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
- int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
- {
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
- }
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
- static int write_word (flash_info_t * info, ulong dest, ulong data)
- {
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
- }
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/ebony/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- ppc/vsprintf.o (.text)
- ppc/crc32.o (.text)
- ppc/extable.o (.text)
-
- common/environment.o(.text)
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(BOARD).a
-
-OBJS = $(BOARD).o flash.o
-SOBJS = init.o
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend *~
-
-#########################################################################
-
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# IBM 440GX Reference Platform (Ocotea) board
-#
-
-#TEXT_BASE = 0xFFFE0000
-
-ifeq ($(ramsym),1)
-TEXT_BASE = 0x07FD0000
-else
-TEXT_BASE = 0xFFFC0000
-endif
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif /* DEBUG */
-
-#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-#define BOOT_SMALL_FLASH_VAL 4
-#define FLASH_ONBD_N_VAL 2
-#define FLASH_SRAM_SEL_VAL 1
-
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
- {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
- {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
- {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
- {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
- {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
- {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
- {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
- {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-
-#ifdef CONFIG_OCOTEA
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- unsigned long total_b = 0;
- unsigned long size_b[CFG_MAX_FLASH_BANKS];
- unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
- unsigned char switch_status;
- unsigned short index = 0;
- int i;
-
- /* read FPGA base register FPGA_REG0 */
- switch_status = *fpga_base;
-
- /* check the bitmap of switch status */
- if (switch_status & BOOT_SMALL_FLASH) {
- index += BOOT_SMALL_FLASH_VAL;
- }
- if (switch_status & FLASH_ONBD_N) {
- index += FLASH_ONBD_N_VAL;
- }
- if (switch_status & FLASH_SRAM_SEL) {
- index += FLASH_SRAM_SEL_VAL;
- }
-
- DEBUGF("\n");
- DEBUGF("FLASH: Index: %d\n", index);
-
- /* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
-
- /* check whether the address is 0 */
- if (flash_addr_table[index][i] == 0) {
- continue;
- }
-
- /* call flash_get_size() to initialize sector address */
- size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]);
- flash_info[i].size = size_b[i];
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, size_b[i], size_b[i] << 20);
- flash_info[i].sector_count = -1;
- flash_info[i].size = 0;
- }
-
- total_b += flash_info[i].size;
- }
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
- 0xffffffff,
- &flash_info[2]);
-
- return total_b;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_STM:
- printf("STM ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf("SST ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDLV033C:
- printf("AM29LV033C (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A:
- printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A:
- printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *) info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ", info->protect[i] ? "RO " : " ");
- }
- printf("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr);
-
- /* Write auto select command: read Manufacturer ID */
- udelay(10000);
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- udelay(1000);
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- udelay(1000);
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
- udelay(1000);
-
- value = addr2[0];
- DEBUGF("FLASH MANUFACT: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (FLASH_WORD_SIZE) STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[1]; /* device ID */
-
- DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) STM_ID_M29W040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE) AMD_ID_LV033C:
- info->flash_id += FLASH_AMDLV033C;
- info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
-
- /* For AMD29033C flash we need to resend the command of *
- * reading flash protection for upper 8 Mb of flash */
- if ( i == 32 ) {
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /* issue bank reset to return to read mode */
- addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- /* ? ? ? */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t * info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr =
- (FLASH_WORD_SIZE *) (info->start[sect]);
-
- start = get_timer(0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- for (i = 0; i < 50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
-
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+++ /dev/null
-/*
- * Copyright (C) 2004 PaulReynolds@lhsolutions.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include "ocotea.h"
-#include <asm/processor.h>
-#include <spd_sdram.h>
-#include <440gx_enet.h>
-
-#define BOOT_SMALL_FLASH 32 /* 00100000 */
-#define FLASH_ONBD_N 2 /* 00000010 */
-#define FLASH_SRAM_SEL 1 /* 00000001 */
-
-long int fixed_sdram (void);
-void fpga_init (void);
-
-int board_early_init_f (void)
-{
- unsigned long mfr;
- unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
- unsigned char switch_status;
- unsigned long cs0_base;
- unsigned long cs0_size;
- unsigned long cs0_twt;
- unsigned long cs2_base;
- unsigned long cs2_size;
- unsigned long cs2_twt;
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------------*/
- mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
- EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
- EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-
- /*-------------------------------------------------------------------------+
- | FPGA. Initialize bank 7 with default values.
- +-------------------------------------------------------------------------*/
- mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
- EBC_BXAP_BCE_DISABLE|
- EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
- EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
- EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
- EBC_BXAP_BEM_WRITEONLY|
- EBC_BXAP_PEN_DISABLED);
- mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
- EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
-
- /* read FPGA base register FPGA_REG0 */
- switch_status = *fpga_base;
-
- if (switch_status & 0x40) {
- cs0_base = 0xFFE00000;
- cs0_size = EBC_BXCR_BS_2MB;
- cs0_twt = 8;
- cs2_base = 0xFF800000;
- cs2_size = EBC_BXCR_BS_4MB;
- cs2_twt = 10;
- } else {
- cs0_base = 0xFFC00000;
- cs0_size = EBC_BXCR_BS_4MB;
- cs0_twt = 10;
- cs2_base = 0xFF800000;
- cs2_size = EBC_BXCR_BS_2MB;
- cs2_twt = 8;
- }
-
- /*-------------------------------------------------------------------------+
- | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
- +-------------------------------------------------------------------------*/
- mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
- EBC_BXAP_BCE_DISABLE|
- EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
- EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
- EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
- EBC_BXAP_BEM_WRITEONLY|
- EBC_BXAP_PEN_DISABLED);
- mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
- cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
-
- /*-------------------------------------------------------------------------+
- | 8KB NVRAM/RTC. Initialize bank 1 with default values.
- +-------------------------------------------------------------------------*/
- mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
- EBC_BXAP_BCE_DISABLE|
- EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
- EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
- EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
- EBC_BXAP_BEM_WRITEONLY|
- EBC_BXAP_PEN_DISABLED);
- mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
- EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
-
- /*-------------------------------------------------------------------------+
- | 4 MB FLASH. Initialize bank 2 with default values.
- +-------------------------------------------------------------------------*/
- mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
- EBC_BXAP_BCE_DISABLE|
- EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
- EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
- EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
- EBC_BXAP_BEM_WRITEONLY|
- EBC_BXAP_PEN_DISABLED);
- mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
- cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
-
- /*-------------------------------------------------------------------------+
- | FPGA. Initialize bank 7 with default values.
- +-------------------------------------------------------------------------*/
- mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
- EBC_BXAP_BCE_DISABLE|
- EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
- EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
- EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
- EBC_BXAP_BEM_WRITEONLY|
- EBC_BXAP_PEN_DISABLED);
- mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
- EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr (uic0sr, 0xffffffff); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic0sr, 0xffffffff); /* clear all */
-
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non-critical */
- mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uicb0sr, 0xfc000000); /* clear all */
- mtdcr (uicb0er, 0x00000000); /* disable all */
- mtdcr (uicb0cr, 0x00000000); /* all non-critical */
- mtdcr (uicb0pr, 0xfc000000); /* */
- mtdcr (uicb0tr, 0x00000000); /* */
- mtdcr (uicb0vr, 0x00000001); /* */
- mfsdr (sdr_mfr, mfr);
- mfr &= ~SDR0_MFR_ECS_MASK;
-/* mtsdr(sdr_mfr, mfr); */
- fpga_init();
-
- return 0;
-}
-
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
-
- get_sys_info (&sysinfo);
-
- printf ("Board: IBM 440GX Evaluation Board\n");
- printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
- return (0);
-}
-
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram (0);
-#else
- dram_size = fixed_sdram ();
-#endif
- return dram_size;
-}
-
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) 0x00000000;
- uint *pend = (uint *) 0x08000000;
- uint *p;
-
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- *
- * Assumes: 128 MB, non-ECC, non-registered
- * PLB @ 133 MHz
- *
- ************************************************************************/
-long int fixed_sdram (void)
-{
- uint reg;
-
- /*--------------------------------------------------------------------
- * Setup some default
- *------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
-
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
-
- /*--------------------------------------------------------------------
- * Enable the controller, then wait for DCEN to complete
- *------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
- for (;;) {
- mfsdram (mem_mcsts, reg);
- if (reg & 0x80000000)
- break;
- }
-
- return (128 * 1024 * 1024); /* 128 MB */
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
-int pci_pre_init(struct pci_controller * hose )
-{
- unsigned long strap;
-
- /*--------------------------------------------------------------------------+
- * The ocotea board is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
- printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
- return 0;
- }
-
- return 1;
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIX0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
- /* The ocotea board is always configured as host. */
- return(1);
-}
-#endif /* defined(CONFIG_PCI) */
-
-
-void fpga_init(void)
-{
- unsigned long group;
- unsigned long sdr0_pfc0;
- unsigned long sdr0_pfc1;
- unsigned long sdr0_cust0;
- unsigned long pvr;
-
- mfsdr (sdr_pfc0, sdr0_pfc0);
- mfsdr (sdr_pfc1, sdr0_pfc1);
- group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
- pvr = get_pvr ();
-
- sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
- if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
- sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
- out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
- FPGA_REG2_EXT_INTFACE_ENABLE);
- mtsdr (sdr_pfc0, sdr0_pfc0);
- mtsdr (sdr_pfc1, sdr0_pfc1);
- } else {
- sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
- switch (group)
- {
- case 0:
- case 1:
- case 2:
- /* CPU trace A */
- out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
- FPGA_REG2_EXT_INTFACE_ENABLE);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
- mtsdr (sdr_pfc0, sdr0_pfc0);
- mtsdr (sdr_pfc1, sdr0_pfc1);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- /* CPU trace B - Over EBMI */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
- mtsdr (sdr_pfc0, sdr0_pfc0);
- mtsdr (sdr_pfc1, sdr0_pfc1);
- out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
- FPGA_REG2_EXT_INTFACE_DISABLE);
- break;
- }
- }
-
- /* Initialize the ethernet specific functions in the fpga */
- mfsdr(sdr_pfc1, sdr0_pfc1);
- mfsdr(sdr_cust0, sdr0_cust0);
- if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
- ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
- (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
- {
- if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
- {
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
- FPGA_REG3_ENET_GROUP7);
- }
- else
- {
- if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
- {
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
- FPGA_REG3_ENET_GROUP7);
- }
- else
- {
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
- FPGA_REG3_ENET_GROUP8);
- }
- }
- }
- else
- {
- if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
- {
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
- FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
- }
- else
- {
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
- FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
- }
- }
- out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
- FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
- FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
-
- /* reset the gigabyte phy if necessary */
- if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
- {
- if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
- {
- out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
- udelay(10000);
- out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
- }
- else
- {
- out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
- udelay(10000);
- out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
- }
- }
-
- /* Turn off the LED's */
- out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
- FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
- FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
-
- return;
-}
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-
- return (ctrlc());
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Board specific FPGA stuff ... */
-#define FPGA_REG0 (CFG_FPGA_BASE + 0x00)
-#define FPGA_REG0_SSCG_MASK 0x80
-#define FPGA_REG0_SSCG_DISABLE 0x00
-#define FPGA_REG0_SSCG_ENABLE 0x80
-#define FPGA_REG0_BOOT_MASK 0x40
-#define FPGA_REG0_BOOT_LARGE_FLASH 0x00
-#define FPGA_REG0_BOOT_SMALL_FLASH 0x40
-#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */
-#define FPGA_REG0_ARBITER_MASK 0x04
-#define FPGA_REG0_ARBITER_EXT 0x00
-#define FPGA_REG0_ARBITER_INT 0x04
-#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02
-#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00
-#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
-#define FPGA_REG0_FLASH 0x01
-#define FPGA_REG1 (CFG_FPGA_BASE + 0x01)
-#define FPGA_REG1_9772_FSELFBX_MASK 0x80
-#define FPGA_REG1_9772_FSELFBX_6 0x00
-#define FPGA_REG1_9772_FSELFBX_10 0x80
-#define FPGA_REG1_9531_SX_MASK 0x60
-#define FPGA_REG1_9531_SX_33MHZ 0x00
-#define FPGA_REG1_9531_SX_100MHZ 0x20
-#define FPGA_REG1_9531_SX_66MHZ 0x40
-#define FPGA_REG1_9531_SX_133MHZ 0x60
-#define FPGA_REG1_9772_FSELBX_MASK 0x18
-#define FPGA_REG1_9772_FSELBX_4 0x00
-#define FPGA_REG1_9772_FSELBX_6 0x08
-#define FPGA_REG1_9772_FSELBX_8 0x10
-#define FPGA_REG1_9772_FSELBX_10 0x18
-#define FPGA_REG1_SOURCE_MASK 0x07
-#define FPGA_REG1_SOURCE_TC 0x00
-#define FPGA_REG1_SOURCE_66MHZ 0x01
-#define FPGA_REG1_SOURCE_50MHZ 0x02
-#define FPGA_REG1_SOURCE_33MHZ 0x03
-#define FPGA_REG1_SOURCE_25MHZ 0x04
-#define FPGA_REG1_SOURCE_SSDIV1 0x05
-#define FPGA_REG1_SOURCE_SSDIV2 0x06
-#define FPGA_REG1_SOURCE_SSDIV4 0x07
-#define FPGA_REG2 (CFG_FPGA_BASE + 0x02)
-#define FPGA_REG2_TC0 0x80
-#define FPGA_REG2_TC1 0x40
-#define FPGA_REG2_TC2 0x20
-#define FPGA_REG2_TC3 0x10
-#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/
-#define FPGA_REG2_EXT_INTFACE_MASK 0x04
-#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
-#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
-#define FPGA_REG2_DEFAULT_UART1_N 0x01
-#define FPGA_REG3 (CFG_FPGA_BASE + 0x03)
-#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
-#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/
-#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/
-#define FPGA_REG3_ENET_GROUP0 0x00
-#define FPGA_REG3_ENET_GROUP1 0x10
-#define FPGA_REG3_ENET_GROUP2 0x20
-#define FPGA_REG3_ENET_GROUP3 0x30
-#define FPGA_REG3_ENET_GROUP4 0x40
-#define FPGA_REG3_ENET_GROUP5 0x50
-#define FPGA_REG3_ENET_GROUP6 0x60
-#define FPGA_REG3_ENET_GROUP7 0x70
-#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/
-#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
-#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
-#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
-#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
-#define FPGA_REG3_STAT_MASK 0x0F
-#define FPGA_REG3_STAT_LED8_ENAB 0x08
-#define FPGA_REG3_STAT_LED4_ENAB 0x04
-#define FPGA_REG3_STAT_LED2_ENAB 0x02
-#define FPGA_REG3_STAT_LED1_ENAB 0x01
-#define FPGA_REG3_STAT_LED8_DISAB 0x00
-#define FPGA_REG3_STAT_LED4_DISAB 0x00
-#define FPGA_REG3_STAT_LED2_DISAB 0x00
-#define FPGA_REG3_STAT_LED1_DISAB 0x00
-#define FPGA_REG4 (CFG_FPGA_BASE + 0x04)
-#define FPGA_REG4_GPHY_MODE10 0x80
-#define FPGA_REG4_GPHY_MODE100 0x40
-#define FPGA_REG4_GPHY_MODE1000 0x20
-#define FPGA_REG4_GPHY_FRC_DPLX 0x10
-#define FPGA_REG4_GPHY_ANEG_DIS 0x08
-#define FPGA_REG4_CONNECT_PHYS 0x04
-
-
-#define SDR0_CUST0_ENET3_MASK 0x00000080
-#define SDR0_CUST0_ENET3_COPPER 0x00000000
-#define SDR0_CUST0_ENET3_FIBER 0x00000080
-#define SDR0_CUST0_RGMII3_MASK 0x00000070
-#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
-#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
-#define SDR0_CUST0_RGMII3_DISAB 0x00000000
-#define SDR0_CUST0_RGMII3_RTBI 0x00000040
-#define SDR0_CUST0_RGMII3_RGMII 0x00000050
-#define SDR0_CUST0_RGMII3_TBI 0x00000060
-#define SDR0_CUST0_RGMII3_GMII 0x00000070
-#define SDR0_CUST0_ENET2_MASK 0x00000008
-#define SDR0_CUST0_ENET2_COPPER 0x00000000
-#define SDR0_CUST0_ENET2_FIBER 0x00000008
-#define SDR0_CUST0_RGMII2_MASK 0x00000007
-#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
-#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
-#define SDR0_CUST0_RGMII2_DISAB 0x00000000
-#define SDR0_CUST0_RGMII2_RTBI 0x00000004
-#define SDR0_CUST0_RGMII2_RGMII 0x00000005
-#define SDR0_CUST0_RGMII2_TBI 0x00000006
-#define SDR0_CUST0_RGMII2_GMII 0x00000007
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/ocotea/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/ocotea/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* common/environment.o(.text) */
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(BOARD).a
-
-OBJS = $(BOARD).o flash.o
-SOBJS = init.o
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# esd ADCIOP boards
-#
-
-#TEXT_BASE = 0xFFFE0000
-TEXT_BASE = 0xFFF80000
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-#ifdef CONFIG_ADCIOP
-#define ADDR0 0x0aa9
-#define ADDR1 0x0556
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-#ifdef CONFIG_CPCI405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned short
-#endif
-
-#ifdef CONFIG_WALNUT405
-#define ADDR0 0x5555
-#define ADDR1 0x2aaa
-#define FLASH_WORD_SIZE unsigned char
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Only one bank */
- if (CFG_MAX_FLASH_BANKS == 1)
- {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM+monitor_flash_len-1,
- &flash_info[0]);
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- }
-
- /* 2 banks */
- else
- {
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1)
- {
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
- }
-
- if (size_b0)
- {
- mtdcr(ebccfga, pb1cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb1cr);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb0cr = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b0+size_b0-monitor_flash_len,
- base_b0+size_b0-1,
- &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1+size_b1-monitor_flash_len,
- base_b1+size_b1-1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0+size_b0-monitor_flash_len,
- base_b0+size_b0-1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- }/* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)){
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
- break;
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-#if 0 /* test-only */
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
-#else
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " "
-#endif
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
-
-#ifdef CONFIG_ADCIOP
- value = addr2[2];
-#else
- value = addr2[0];
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-#ifdef CONFIG_ADCIOP
- value = addr2[0]; /* device ID */
- /* printf("\ndev_code=%x\n", value); */
-#else
- value = addr2[1]; /* device ID */
-#endif
-
- switch (value) {
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
- break;
- case (FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- case (FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- (info->flash_id == FLASH_AM040)){
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[4] & 1;
-#else
- addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
-#endif
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
-#if 0 /* test-only */
-#ifdef CONFIG_ADCIOP
- addr2 = (volatile unsigned char *)info->start[0];
- addr2[ADDR0] = 0xAA;
- addr2[ADDR1] = 0x55;
- addr2[ADDR0] = 0xF0; /* reset bank */
-#else
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif
-#else /* test-only */
- addr2 = (FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-#endif /* test-only */
- }
-
- return (info->size);
-}
-
-int wait_for_DQ7(flash_info_t *info, int sect)
-{
- ulong start, now, last;
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
-
- start = get_timer (0);
- last = start;
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
- printf("Erasing sector %p\n", addr2); /* CLH */
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- /*
- * Wait for each sector to complete, it's more
- * reliable. According to AMD Spec, you must
- * issue all erase commands within a specified
- * timeout. This has been seen to fail, especially
- * if printf()s are included (for debug)!!
- */
- wait_for_DQ7(info, sect);
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
-#if 0
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
- wait_for_DQ7(info, l_sect);
-
-DONE:
-#endif
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *) dest) &
- (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- int flag;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-
- if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*------------------------------------------------------------------------------+ */
-/* */
-/* This source code has been made available to you by IBM on an AS-IS */
-/* basis. Anyone receiving this source is licensed under IBM */
-/* copyrights to use it in any way he or she deems fit, including */
-/* copying it, modifying it, compiling it, and redistributing it either */
-/* with or without modifications. No license under IBM patents or */
-/* patent applications is to be implied by the copyright license. */
-/* */
-/* Any user of this software should understand that IBM cannot provide */
-/* technical support for this software and will not be responsible for */
-/* any consequences resulting from the use of this software. */
-/* */
-/* Any person who transfers this source code or any derivative work */
-/* must include the IBM copyright notice, this paragraph, and the */
-/* preceding two paragraphs in the transferred software. */
-/* */
-/* COPYRIGHT I B M CORPORATION 1995 */
-/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
- /* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 0 (Flash and SRAM) initialization */
- /*----------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr ebccfgd,r4
-
- blr
-
-
-/*----------------------------------------------------------------------------- */
-/* Function: sdram_init */
-/* Description: Dummy implementation here - done in C later */
-/*----------------------------------------------------------------------------- */
- .globl sdram_init
-sdram_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- cpu/ppc4xx/start.o (.text)
- board/walnut405/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/405gp_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
-
- common/environment.o(.text)
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include "walnut405.h"
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-int board_early_init_f (void)
-{
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the Walnut board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
- | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
- | IRQ 27 (EXT IRQ 2) Not Used
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for Walnut board:
- | An interrupt taken for the FPGA (IRQ 25) indicates that either
- | the Mouse, Keyboard, IRDA, or External Expansion caused the
- | interrupt. The FPGA must be read to determine which device
- | caused the interrupt. The default setting of the FPGA clears
- |
- +-------------------------------------------------------------------------*/
-
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
-
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
- /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb1ap, 0x02815480);
- mtebc (pb1cr, 0xF0018000);
-
- /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb2ap, 0x04815A80);
- mtebc (pb2cr, 0xF0118000);
-
- /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
- mtebc (pb3ap, 0x01815280);
- mtebc (pb3cr, 0xF0218000);
-
- /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
- mtebc (pb7ap, 0x01815280);
- mtebc (pb7cr, 0xF0318000);
-
- /* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC 0xF0300004
- *(volatile char *) (FPGA_BRDC) |= 0x1;
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
-
- puts ("Board: ");
-
- if (!s || strncmp (s, "WALNUT405", 9)) {
- puts ("### No HW ID - assuming WALNUT405");
- } else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
- for (; s < e; ++s) {
- putc (*s);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-
-/* -------------------------------------------------------------------------
- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
- ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- return spd_sdram (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
--- /dev/null
+---------------------------------------------------------------------
+Cleanup of AMCC eval boards (Walnut/Sycamore, Bubinga, Ebony, Ocotea)
+---------------------------------------------------------------------
+
+Changes to all AMCC eval boards:
+--------------------------------
+
+o Changed u-boot image size to 256 kBytes instead of 512 kBytes on most
+ boards.
+
+o Use 115200 baud as default console baudrate.
+
+o Added config option to use redundant environment in flash. This is also
+ the default setting. Option for environment in nvram is still available
+ for backward compatibility.
+
+o Merged board specific flash drivers to common flash driver:
+ board/amcc/common/flash.c
+
+
+Sycamore/Walnut (one port supporting both eval boards):
+-------------------------------------------------------
+
+o Cleanup to allow easier "cloning" for different (custom) boards:
+
+ o Moved EBC configuration from board specific asm-file "init.S"
+ using defines in board configuration file. No board specific
+ asm file needed anymore.
+
+
+August 01 2005, Stefan Roese <sr@denx.de>
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Debug options */
-/*#define __DEBUG_START_FROM_SRAM__ */
-/*#define DEBUG 1*/
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_BUBINGA405EP 1 /* ...on a BUBINGA405EP board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_NO_SERIAL_EEPROM
-/*#undef CONFIG_NO_SERIAL_EEPROM*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-------------------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-------------------------------------------------------------------------------
-*/
-#define AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/*
-!-------------------------------------------------------------------------------
-! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
-! assuming a 33MHz input clock to the 405EP from the C9531.
-!-------------------------------------------------------------------------------
-*/
-#define PLLMR0_DEFAULT PLLMR0_266_133_66
-#define PLLMR1_DEFAULT PLLMR1_266_133_66
-
-#endif
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-
-/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
-#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#if 0
-#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
-#else
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#endif
-
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-
-#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
-
-/*
-#ifndef __DEBUG_START_FROM_SRAM__
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-#else
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_DATE | \
- CFG_CMD_ELF )
-#endif
-*/
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- 0 )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-
-#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
-
-#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
-#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#endif
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CFG_KEY_REG_BASE_ADDR 0xF0100000
-#define CFG_IR_REG_BASE_ADDR 0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE 0x00000000
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CFG_SRAM_BASE 0xFFF80000
-#define CFG_FLASH_BASE 0xFFF00000
-#define CFG_MONITOR_BASE CFG_SRAM_BASE
-#else
-#define CFG_SRAM_BASE 0xFFF00000
-#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#endif
-
-
-/*#define CFG_MONITOR_LEN (200 * 1024) /XXX* Reserve 200 kB for Monitor */
-#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 200 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
-#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
-#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash/SRAM) initialization */
-#define CFG_EBC_PB0AP 0x04006000
-#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization */
-#define CFG_EBC_PB1AP 0x04041000
-#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (not used) initialization */
-#define CFG_EBC_PB2AP 0x00000000
-#define CFG_EBC_PB2CR 0x00000000
-
-/* Memory Bank 2 (not used) initialization */
-#define CFG_EBC_PB3AP 0x00000000
-#define CFG_EBC_PB3CR 0x00000000
-
-/* Memory Bank 4 (FPGA regs) initialization */
-#define CFG_EBC_PB4AP 0x01815000
-#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x55
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CFG_GPIO0_OSRH 0x55555555
-#define CFG_GPIO0_OSRL 0x40000110
-#define CFG_GPIO0_ISR1H 0x00000000
-#define CFG_GPIO0_ISR1L 0x15555445
-#define CFG_GPIO0_TSRH 0x00000000
-#define CFG_GPIO0_TSRL 0x00000000
-#define CFG_GPIO0_TCR 0xFFFF8014
-
-/*-----------------------------------------------------------------------
- * Some BUBINGA stuff...
- */
-#define NVRAM_BASE 0xF0000000
-#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
-#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
-#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
-#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
-
-#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
-#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
-#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
-#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
-#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
-#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
-
-#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
-#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
-#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
-#define FPGA_REG1_CLOCK_BIT_SHIFT 4
-#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
-#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
-#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
-#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_EBONY 1 /* Board is ebony */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 9600
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY -1 /* disable autoboot */
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 8 /* PHY address */
-
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_I2C | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
-#define CFG_PCI_TARGET_INIT /* let board init pci target */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************
- * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
- * Adapted to current Das U-Boot source
- ***********************************************************************/
-
-
-/************************************************************************
- * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
- ***********************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_OCOTEA 1 /* Board is ebony */
-#define CONFIG_440_GX 1 /* Specifc GX support */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-
-#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
-#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
-
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CFG_TEMP_STACK_OCM 1
-#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
-#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
-#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
-
-/*-----------------------------------------------------------------------
- * FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
-#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
-
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-
-
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
-#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
-#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
-#define CONFIG_ENV_OVERWRITE 1
-
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
-
-#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY -1 /* disable autoboot */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_NET_MULTI 1
-#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
-#define CONFIG_PHY1_ADDR 2
-#define CONFIG_PHY2_ADDR 0x10
-#define CONFIG_PHY3_ADDR 0x18
-#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.1.2.3
-#define CONFIG_ETHADDR 00:04:AC:E3:28:8A
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:04:AC:E3:28:8B
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:04:AC:E3:28:8C
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:04:AC:E3:28:8D
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_SERVERIP 10.1.2.2
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_ELF | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_SNTP )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
-#define CFG_PCI_TARGET_INIT /* let board init pci target */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
-#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */
-#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_FLASH
-#else
-#ifdef CFG_ENV_IS_IN_FLASH
-#undef CFG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#if 0
-#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
-#else
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#endif
-
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
-
-#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_KGDB | \
- CFG_CMD_DHCP | \
- CFG_CMD_DATE | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_ELF )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-#define CFG_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
-#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CFG_KEY_REG_BASE_ADDR 0xF0100000
-#define CFG_IR_REG_BASE_ADDR 0xF0200000
-#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
- */
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFF80000
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
-
-#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * bamboo.h - configuration for BAMBOO board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
+#define CONFIG_440_EP 1 /* Specific PPC440EP support */
+
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#undef CFG_DRAM_TEST /* disable - takes long time! */
+//#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE 0x50000000
+#define CFG_NVRAM_BASE_ADDR 0x80000000
+#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
+#define CFG_INIT_RAM_END 0x2000
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
+//#define CFG_SDRAM_BANKS (2)
+#define CFG_SDRAM_BANKS (1)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
+ * The DS1558 code assumes this condition
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#if 0 /* test-only */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
+#else
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#define CFG_ENV_IS_IN_EEPROM 1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
+#define CONFIG_BOOTDELAY 3 /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1 /* required for netconsole */
+#define CONFIG_PHY1_ADDR 3
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 10.0.4.251
+#define CONFIG_ETHADDR 00:10:EC:00:12:34
+#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SERVERIP 10.0.4.115
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440_EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440_EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG /* watchdog */
+#endif
+
+#ifdef CONFIG_440_EP
+ /* Need to define POST */
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ /* CFG_CMD_EXT2 |*/ \
+ /* CFG_CMD_FAT |*/ \
+ CFG_CMD_I2C | \
+ /* CFG_CMD_IDE |*/ \
+ CFG_CMD_IRQ | \
+ /* CFG_CMD_KGDB |*/ \
+ CFG_CMD_MII | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_FLASH | \
+ /* CFG_CMD_SPI |*/ \
+ CFG_CMD_USB | \
+ 0 ) & ~CFG_CMD_IMLS)
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ /* CFG_CMD_EXT2 |*/ \
+ /* CFG_CMD_FAT |*/ \
+ CFG_CMD_I2C | \
+ /* CFG_CMD_IDE |*/ \
+ CFG_CMD_IRQ | \
+ /* CFG_CMD_KGDB |*/ \
+ CFG_CMD_MII | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_FLASH | \
+ /* CFG_CMD_SPI |*/ \
+ 0 ) & ~CFG_CMD_IMLS)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI 1 /* support kdi files */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+! are plugged in the board will be utilized as non-ECC DIMMs.
+!-------------------------------------------------------------------------------
+*/
+#define AUTO_MEMORY_CONFIG
+#define DIMM_READ_ADDR 0xAB
+#define DIMM_WRITE_ADDR 0xAA
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=bubinga\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/bubinga/uImage\0" \
+ "kernel_addr=fff80000\0" \
+ "ramdisk_addr=fff90000\0" \
+ "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define CFG_KEY_REG_BASE_ADDR 0xF0100000
+#define CFG_IR_REG_BASE_ADDR 0xF0200000
+#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SRAM_BASE 0xFFF00000
+#define CFG_FLASH_BASE 0xFFF80000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_SIZE 0x1000
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CFG_EBC_PB0AP 0x04006000
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CFG_EBC_PB1AP 0x04041000
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 2 (not used) initialization */
+#define CFG_EBC_PB2AP 0x00000000
+#define CFG_EBC_PB2CR 0x00000000
+
+/* Memory Bank 2 (not used) initialization */
+#define CFG_EBC_PB3AP 0x00000000
+#define CFG_EBC_PB3CR 0x00000000
+
+/* Memory Bank 4 (FPGA regs) initialization */
+#define CFG_EBC_PB4AP 0x01815000
+#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS 0x55
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0] - External Bus Controller BLAST output
+ * GPIO0[1-9] - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH 0x55555555
+#define CFG_GPIO0_OSRL 0x40000110
+#define CFG_GPIO0_ISR1H 0x00000000
+#define CFG_GPIO0_ISR1L 0x15555445
+#define CFG_GPIO0_TSRH 0x00000000
+#define CFG_GPIO0_TSRL 0x00000000
+#define CFG_GPIO0_TCR 0xFFFF8014
+
+/*-----------------------------------------------------------------------
+ * Some BUBINGA stuff...
+ */
+#define NVRAM_BASE 0xF0000000
+#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
+#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
+#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
+#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
+
+#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
+#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
+#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
+#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
+#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
+#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
+
+#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
+#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
+#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
+#define FPGA_REG1_CLOCK_BIT_SHIFT 4
+#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
+#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
+#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
+#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY 1 /* Board is ebony */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#undef CFG_DRAM_TEST /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=ebony\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/ebony/uImage\0" \
+ "kernel_addr=ff800000\0" \
+ "ramdisk_addr=ff810000\0" \
+ "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 8 /* PHY address */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+
+
+/************************************************************************
+ * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_OCOTEA 1 /* Board is ebony */
+#define CONFIG_440_GX 1 /* Specifc GX support */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#undef CFG_DRAM_TEST /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=ocotea\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/ocotea/uImage\0" \
+ "kernel_addr=fff00000\0" \
+ "ramdisk_addr=fff10000\0" \
+ "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_PHY1_ADDR 2
+#define CONFIG_PHY2_ADDR 0x10
+#define CONFIG_PHY3_ADDR 0x18
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2000-2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
+ /* ...and on a SYCAMORE board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=walnut\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):$(netdev):off panic=1\0" \
+ "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=/tftpboot/walnut/uImage\0" \
+ "kernel_addr=fff80000\0" \
+ "ramdisk_addr=fff80000\0" \
+ "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
+ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
+ "cp.b 100000 fffc0000 40000;" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD 691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFF80000
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ * supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+ /* have only 8kB, 16kB is save here */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x9B015480
+#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB1AP 0x02815480
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB2AP 0x04815A80
+#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB3AP 0x01815280
+#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
+
+#define CFG_EBC_PB7AP 0x01815280
+#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define CFG_KEY_REG_BASE_ADDR 0xF0100000
+#define CFG_IR_REG_BASE_ADDR 0xF0200000
+#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
+
+#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
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