#define MVUSB0_BASE \
(mvebu_soc_family() == MVEBU_SOC_A38X ? \
MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
+#define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12)
/*
* Once all the older Marvell SoC's (Orion, Kirkwood) are converted
* to the common mvebu archticture including the mbus setup, this
* will be the only function needed to configure the access windows
*/
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
{
const struct mbus_dram_target_info *dram;
int i;
dram = mvebu_mbus_dram_info();
for (i = 0; i < 4; i++) {
- writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
- writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
+ writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
+ writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}
for (i = 0; i < dram->num_cs; i++) {
/* Write size, attributes and target id to control register */
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
- MVUSB0_BASE + USB_WINDOW_CTRL(i));
+ MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
/* Write base address to base register */
- writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i));
+ writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}
}
#else
-static void usb_brg_adrdec_setup(void)
+#define MVUSB_BASE(port) MVUSB0_BASE
+
+static void usb_brg_adrdec_setup(int index)
{
int i;
u32 size, base, attrib;
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- usb_brg_adrdec_setup();
+ usb_brg_adrdec_setup(index);
- *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));