+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.1.1\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
- *\r
- * + The code that is common to all RISC-V chips is implemented in\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
- * portASM.S file because the same file is used no matter which RISC-V chip is\r
- * in use.\r
- *\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- * RISC-V chip that both includes a standard CLINT and does not add to the\r
- * base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- * that do not include a standard CLINT or do add to the base set of RISC-V\r
- * registers.\r
- *\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
- *\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
- * that include a standard CLINT and do not add to the base set of RISC-V\r
- * registers.\r
- *\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-#define portasmHAS_CLINT 1\r
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */\r
-\r
-.macro portasmSAVE_ADDITIONAL_REGISTERS\r
- /* No additional registers to save, so this macro does nothing. */\r
- .endm\r
-\r
-/* Restore the additional registers found on the Pulpino. */\r
-.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
- /* No additional registers to restore, so this macro does nothing. */\r
- .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
+++ /dev/null
-/*\r
- * FreeRTOS Kernel V10.1.1\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
- *\r
- * + The code that is common to all RISC-V chips is implemented in\r
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
- * portASM.S file because the same file is used no matter which RISC-V chip is\r
- * in use.\r
- *\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
- * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- * RISC-V chip that both includes a standard CLINT and does not add to the\r
- * base set of RISC-V registers. There are additional\r
- * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- * that do not include a standard CLINT or do add to the base set of RISC-V\r
- * registers.\r
- *\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
- *\r
- * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy\r
- * devices, developed and tested using the Vega board RV32M1RM.\r
- *\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-#define portasmHAS_CLINT 0\r
-\r
-/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
-#define lpstart0 0x7b0\r
-#define lpend0 0x7b1\r
-#define lpcount0 0x7b2\r
-#define lpstart1 0x7b4\r
-#define lpend1 0x7b5\r
-#define lpcount1 0x7b6\r
-\r
-/* Six additional registers to save and restore, as per the #defines above. */\r
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
-\r
-/* Save additional registers found on the Pulpino. */\r
-.macro portasmSAVE_ADDITIONAL_REGISTERS\r
- addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
- csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */\r
- csrr t1, lpend0\r
- csrr t2, lpcount0\r
- csrr t3, lpstart1\r
- csrr t4, lpend1\r
- csrr t5, lpcount1\r
- sw t0, 1 * portWORD_SIZE( sp )\r
- sw t1, 2 * portWORD_SIZE( sp )\r
- sw t2, 3 * portWORD_SIZE( sp )\r
- sw t3, 4 * portWORD_SIZE( sp )\r
- sw t4, 5 * portWORD_SIZE( sp )\r
- sw t5, 6 * portWORD_SIZE( sp )\r
- .endm\r
-\r
-/* Restore the additional registers found on the Pulpino. */\r
-.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
- lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */\r
- lw t1, 2 * portWORD_SIZE( sp )\r
- lw t2, 3 * portWORD_SIZE( sp )\r
- lw t3, 4 * portWORD_SIZE( sp )\r
- lw t4, 5 * portWORD_SIZE( sp )\r
- lw t5, 6 * portWORD_SIZE( sp )\r
- csrw lpstart0, t0\r
- csrw lpend0, t1\r
- csrw lpcount0, t2\r
- csrw lpstart1, t3\r
- csrw lpend1, t4\r
- csrw lpcount1, t5\r
- addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
- .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
+ * portASM.S file because the same file is used no matter which RISC-V chip is\r
+ * in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
+ * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ * RISC-V chip that both includes a standard CLINT and does not add to the\r
+ * base set of RISC-V registers. There are additional\r
+ * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ * that do not include a standard CLINT or do add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy\r
+ * devices, developed and tested using the Vega board RV32M1RM.\r
+ *\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 0\r
+\r
+/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
+#define lpstart0 0x7b0\r
+#define lpend0 0x7b1\r
+#define lpcount0 0x7b2\r
+#define lpstart1 0x7b4\r
+#define lpend1 0x7b5\r
+#define lpcount1 0x7b6\r
+\r
+/* Six additional registers to save and restore, as per the #defines above. */\r
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
+\r
+/* Save additional registers found on the Pulpino. */\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+ addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
+ csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */\r
+ csrr t1, lpend0\r
+ csrr t2, lpcount0\r
+ csrr t3, lpstart1\r
+ csrr t4, lpend1\r
+ csrr t5, lpcount1\r
+ sw t0, 1 * portWORD_SIZE( sp )\r
+ sw t1, 2 * portWORD_SIZE( sp )\r
+ sw t2, 3 * portWORD_SIZE( sp )\r
+ sw t3, 4 * portWORD_SIZE( sp )\r
+ sw t4, 5 * portWORD_SIZE( sp )\r
+ sw t5, 6 * portWORD_SIZE( sp )\r
+ .endm\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */\r
+ lw t1, 2 * portWORD_SIZE( sp )\r
+ lw t2, 3 * portWORD_SIZE( sp )\r
+ lw t3, 4 * portWORD_SIZE( sp )\r
+ lw t4, 5 * portWORD_SIZE( sp )\r
+ lw t5, 6 * portWORD_SIZE( sp )\r
+ csrw lpstart0, t0\r
+ csrw lpend0, t1\r
+ csrw lpcount0, t2\r
+ csrw lpstart1, t3\r
+ csrw lpend1, t4\r
+ csrw lpcount1, t5\r
+ addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
+ .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
+ * portASM.S file because the same file is used no matter which RISC-V chip is\r
+ * in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
+ * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ * RISC-V chip that both includes a standard CLINT and does not add to the\r
+ * base set of RISC-V registers. There are additional\r
+ * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ * that do not include a standard CLINT or do add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
+ * that include a standard CLINT and do not add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 1\r
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */\r
+\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+ /* No additional registers to save, so this macro does nothing. */\r
+ .endm\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+ /* No additional registers to restore, so this macro does nothing. */\r
+ .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
+ * portASM.S file because the same file is used no matter which RISC-V chip is\r
+ * in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ * chip is implemented in freertos_risc_v_port_specific_extensions.h. There\r
+ * is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ * RISC-V chip that both includes a standard CLINT and does not add to the\r
+ * base set of RISC-V registers. There are additional\r
+ * freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ * that do not include a standard CLINT or do add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
+ * that include a standard CLINT and do not add to the base set of RISC-V\r
+ * registers.\r
projects / freertos / commitdiff