- python-virtualenv
- swig
- libpython-dev
- - gcc-powerpc-linux-gnu
- iasl
- grub-efi-ia32-bin
- rpm2cpio
- device-tree-compiler
- lzop
+before_install:
+ - sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y
+ - sudo apt-get update -q
+ - sudo apt-get install libisl15 -y
+
install:
# Clone uboot-test-hooks
- git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
# prepare buildman environment
- echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
- - echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
- echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman
- cat ~/.buildman
- virtualenv /tmp/venv
- . /tmp/venv/bin/activate
- if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
- if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
- if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
- - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
+ - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi
- if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
./tools/buildman/buildman --fetch-arch x86_64;
- echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
+ echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-7.3.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
fi
- if [[ "${TOOLCHAIN}" == arc ]]; then
wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
fi
# If TOOLCHAIN is unset, we're on some flavour of ARM.
- if [[ "${TOOLCHAIN}" == "" ]]; then
- wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/aarch64-linux-gnu/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
- wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/arm-linux-gnueabihf/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz &&
- tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
- tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz;
+ ./tools/buildman/buildman --fetch-arch arm &&
+ ./tools/buildman/buildman --fetch-arch aarch64;
fi
+ - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi
- if [[ "${TOOLCHAIN}" == "riscv" ]]; then
- wget https://github.com/PkmX/riscv-prebuilt-toolchains/releases/download/20180111/riscv32-unknown-elf-toolchain.tar.gz &&
- tar -C /tmp -xf riscv32-unknown-elf-toolchain.tar.gz &&
- echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv32-unknown-elf/bin/riscv32-unknown-elf-" >> ~/.buildman;
+ wget https://github.com/andestech/prebuilt/releases/download/20180530/riscv64-unknown-linux-gnu.tar.gz &&
+ tar -C /tmp -xf riscv64-unknown-linux-gnu.tar.gz &&
+ echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-" >> ~/.buildman;
fi
- if [[ "${QEMU_TARGET}" != "" ]]; then
git clone git://git.qemu.org/qemu.git /tmp/qemu;
- BUILDMAN="arc"
TOOLCHAIN="arc"
- env:
- - BUILDMAN="arm11"
- - env:
- - BUILDMAN="arm7"
- - env:
- - BUILDMAN="arm920t"
+ - BUILDMAN="arm11 arm7 arm920t arm946es"
- env:
- JOB="arm926ejs"
BUILDMAN="arm926ejs -x mx,siemens,atmel"
- - env:
- - BUILDMAN="arm946es"
- env:
- BUILDMAN="atmel"
- env:
- BUILDMAN="aries"
- env:
- - JOB="Boundary Devices"
- BUILDMAN="boundary"
- - env:
- - JOB="engicam"
- BUILDMAN="engicam"
+ BUILDMAN="boundary engicam toradex"
- env:
- JOB="Freescale ARM32"
BUILDMAN="freescale -x powerpc,m68k,aarch64"
- env:
- BUILDMAN="k2"
- env:
- - BUILDMAN="samsung"
- - env:
- - BUILDMAN="socfpga"
+ - BUILDMAN="samsung socfpga"
- env:
- BUILDMAN="sun4i"
- env:
- BUILDMAN="sun50i"
- env:
- JOB="Catch-all ARM"
- BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip,toradex,socfpga,k2,xilinx"
+ BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
- env:
- BUILDMAN="sandbox x86"
TOOLCHAIN="x86_64"
- - env:
- - BUILDMAN="toradex"
- env:
- BUILDMAN="kirkwood"
- env:
- BUILDMAN="mips"
TOOLCHAIN="mips"
- env:
- - BUILDMAN="mpc83xx"
+ - JOB="Non-Freescale PowerPC"
+ BUILDMAN="powerpc -x freescale"
+ TOOLCHAIN="powerpc"
- env:
- - BUILDMAN="mpc85xx -x freescale"
+ - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+ TOOLCHAIN="powerpc"
- env:
- - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+ - BUILDMAN="t208xrdb corenet_ds"
+ TOOLCHAIN="powerpc"
- env:
- - BUILDMAN="t208xrdb"
- - env:
- - BUILDMAN="t4qds"
+ - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+ TOOLCHAIN="powerpc"
- env:
- BUILDMAN="t102*"
+ TOOLCHAIN="powerpc"
- env:
- BUILDMAN="p1_p2_rdb_pc"
+ TOOLCHAIN="powerpc"
- env:
- - BUILDMAN="p1010rdb"
- - env:
- - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
- - env:
- - BUILDMAN="mpc86xx"
- - env:
- - BUILDMAN="mpc8xx"
+ - BUILDMAN="p1010rdb bsc91"
+ TOOLCHAIN="powerpc"
- env:
- BUILDMAN="siemens"
- env:
- JOB="am33xx"
BUILDMAN="am33xx -x siemens"
- env:
- - BUILDMAN="omap3"
- - env:
- - BUILDMAN="omap4"
- - env:
- - BUILDMAN="omap5"
+ - BUILDMAN="omap"
- env:
- BUILDMAN="uniphier"
- env:
- - JOB="aarch64"
- BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
+ - JOB="Catch-all AArch64"
+ BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip,xilinx"
- env:
- BUILDMAN="rockchip"
- env:
- - BUILDMAN="sh4"
- TOOLCHAIN="sh4"
+ - JOB="sh"
+ BUILDMAN="sh -x arm"
+ TOOLCHAIN="sh"
- env:
- JOB="Xilinx (ARM)"
BUILDMAN="xilinx -x microblaze"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="ppc-softmmu"
BUILDMAN="^qemu-ppce500$"
+ TOOLCHAIN="powerpc"
- env:
- TEST_PY_BD="qemu-x86"
TEST_PY_TEST_SPEC="not sleep"
--- /dev/null
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _________________ HOST controller
+ | _ |
+ | / 1|________________|
+ |_ PHY port#2 ----| |________________
+ | \_0| |
+ |_ UTMI switch_______| OTG controller
+
+
+Phy provider node
+=================
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- #address-cells: number of address cells for phys sub-nodes, must be <1>
+- #size-cells: number of size cells for phys sub-nodes, must be <0>
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+
+Required nodes: one sub-node per port the controller provides.
+
+Phy sub-nodes
+==============
+
+Required properties:
+- reg: phy port index
+- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
+ see phy-bindings.txt in the same directory.
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
+ port#1 and must be <1> for PHY port#2, to select USB controller
+
+
+Example:
+ usbphyc: usb-phy@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc_clk USBPHY_K>;
+ resets = <&rcc_rst USBPHY_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphyc_port0: usb-phy@0 {
+ reg = <0>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>
+ #phy-cells = <0>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ reg = <1>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>
+ #phy-cells = <1>;
+ };
+ };
depends on SPL
select SPL_OF_LIBFDT
+config SPL_FIT_PRINT
+ bool "Support FIT printing within SPL"
+ depends on SPL_FIT
+ help
+ Support printing the content of the fitImage in a verbose manner in SPL.
+
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
particular it can handle selecting from multiple device tree
and passing the correct one to U-Boot.
+config SPL_LOAD_FIT_FULL
+ bool "Enable SPL loading U-Boot as a FIT"
+ select SPL_FIT
+ help
+ Normally with the SPL framework a legacy image is generated as part
+ of the build. This contains U-Boot along with information as to
+ where it should be loaded. This option instead enables generation
+ of a FIT (Flat Image Tree) which provides more flexibility. In
+ particular it can handle selecting from multiple device tree
+ and passing the correct one to U-Boot.
+
config SPL_FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by the SPL"
depends on SPL_LOAD_FIT
+SPDX-License-Identifier: GPL-2.0
+
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and
many others who contributed code (see the actual source code and the
git commit messages for details). You can redistribute U-Boot and/or
To make this easier, such license headers in the source files will be
replaced with a single line reference to Unique License Identifiers
-as defined by the Linux Foundation's SPDX project [1]. For example,
-in a source file the full "GPL v2.0 or later" header text will be
-replaced by a single line:
-
- SPDX-License-Identifier: GPL-2.0+
-
-Ideally, the license terms of all files in the source tree should be
-defined by such License Identifiers; in no case a file can contain
-more than one such License Identifier list.
+as defined by the Linux Foundation's SPDX project [1].
If a "SPDX-License-Identifier:" line references more than one Unique
License Identifier, then this means that the respective file can be
used under the terms of either of these licenses, i. e. with
- SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
you can choose between GPL-2.0+ and BSD-3-Clause licensing.
We use the SPDX Unique License Identifiers here; these are available
at [2].
+License identifier syntax
+-------------------------
+
+1. Placement:
+
+ The SPDX license identifier in U-Boot files shall be added at the first
+ possible line in a file which can contain a comment. For the majority
+ or files this is the first line, except for scripts which require the
+ '#!PATH_TO_INTERPRETER' in the first line. For those scripts the SPDX
+ identifier goes into the second line.
+
+|
+
+2. Style:
+
+ The SPDX license identifier is added in form of a comment. The comment
+ style depends on the file type::
+
+ C source: // SPDX-License-Identifier: <SPDX License Expression>
+ C header: /* SPDX-License-Identifier: <SPDX License Expression> */
+ ASM: /* SPDX-License-Identifier: <SPDX License Expression> */
+ scripts: # SPDX-License-Identifier: <SPDX License Expression>
+ .rst: .. SPDX-License-Identifier: <SPDX License Expression>
+ .dts{i}: // SPDX-License-Identifier: <SPDX License Expression>
+
+ If a specific tool cannot handle the standard comment style, then the
+ appropriate comment mechanism which the tool accepts shall be used. This
+ is the reason for having the "/\* \*/" style comment in C header
+ files. There was build breakage observed with generated .lds files where
+ 'ld' failed to parse the C++ comment. This has been fixed by now, but
+ there are still older assembler tools which cannot handle C++ style
+ comments.
+
+|
+
+3. Syntax:
+
+ A <SPDX License Expression> is either an SPDX short form license
+ identifier found on the SPDX License List, or the combination of two
+ SPDX short form license identifiers separated by "WITH" when a license
+ exception applies. When multiple licenses apply, an expression consists
+ of keywords "AND", "OR" separating sub-expressions and surrounded by
+ "(", ")" .
+
+ License identifiers for licenses like [L]GPL with the 'or later' option
+ are constructed by using a "+" for indicating the 'or later' option.::
+
+ // SPDX-License-Identifier: GPL-2.0+
+ // SPDX-License-Identifier: LGPL-2.1+
+
+ WITH should be used when there is a modifier to a license needed.
+ For example, the linux kernel UAPI files use the expression::
+
+ // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
+ // SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note
+
+ Other examples using WITH exceptions found in the linux kernel are::
+
+ // SPDX-License-Identifier: GPL-2.0 WITH mif-exception
+ // SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
+
+ Exceptions can only be used with particular License identifiers. The
+ valid License identifiers are listed in the tags of the exception text
+ file.
+
+ OR should be used if the file is dual licensed and only one license is
+ to be selected. For example, some dtsi files are available under dual
+ licenses::
+
+ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+
+ Examples from U-Boot for license expressions in dual licensed files::
+
+ // SPDX-License-Identifier: GPL-2.0 OR MIT
+ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+
+ AND should be used if the file has multiple licenses whose terms all
+ apply to use the file. For example, if code is inherited from another
+ project and permission has been given to put it in U-Boot, but the
+ original license terms need to remain in effect::
+
+ // SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) AND MIT
+
+ Another other example where both sets of license terms need to be
+ adhered to is::
+
+ // SPDX-License-Identifier: GPL-1.0+ AND LGPL-2.1+
+
[1] http://spdx.org/
[2] http://spdx.org/licenses/
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
+F: drivers/ata/ahci_mvebu.c
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
F: arch/arm/mach-stm32mp
F: drivers/clk/clk_stm32mp1.c
+F: drivers/misc/stm32mp_fuse.c
F: drivers/ram/stm32mp1/
ARM STM STV0991
$(if $(CONFIG_TOOLS_DEBUG),-g)
HOSTCXXFLAGS = -O2
+# With the move to GCC 6, we have implicitly upgraded our language
+# standard to GNU11 (see https://gcc.gnu.org/gcc-5/porting_to.html).
+# Some Linux distributions (including RHEL7, SLES13, Debian 8) still
+# have older compilers as their default, so we make it explicit for
+# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
+ifeq ($(HOSTOS),linux)
+HOSTCFLAGS += --std=gnu11
+endif
+
ifeq ($(HOSTOS),cygwin)
HOSTCFLAGS += -ansi
endif
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
-- Marvell Family Member
- CONFIG_SYS_MVFS - define it if you want to enable
- multiple fs option at one time
- for marvell soc family
-
- 85xx CPU Options:
CONFIG_SYS_PPC64
CONFIG_SUPPORT_EMMC_BOOT
Enable some additional features of the eMMC boot partitions.
- CONFIG_SUPPORT_EMMC_RPMB
- Enable the commands for reading, writing and programming the
- key for the Replay Protection Memory Block partition in eMMC.
-
- USB Device Firmware Update (DFU) class support:
CONFIG_DFU_OVER_USB
This enables the USB portion of the DFU USB class
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
- CONFIG_FIT_SPL_PRINT
+ CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
/* Initialize reserved area - note: r0 already contains address */
bl board_init_f_init_reserve
+#ifdef CONFIG_DEBUG_UART
+ /* Earliest point to set up early debug uart */
+ bl debug_uart_init
+#endif
+
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
bl board_init_f
select THUMB2_KERNEL
select SYS_CACHE_SHIFT_5
select SYS_ARM_MPU
+ select SYS_THUMB_BUILD
config CPU_V7R
bool
config ARCH_AT91
bool "Atmel AT91"
- select SPL_BOARD_INIT if SPL
+ select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
config TARGET_EDB93XX
bool "Support edb93xx"
select SUPPORT_SPL
select PL011_SERIAL
-config TARGET_MX31PDK
- bool "Support mx31pdk"
- select BOARD_LATE_INIT
- select CPU_ARM1136
- select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
select PL011_SERIAL
select SUPPORT_SPL
+config ARCH_MX31
+ bool "NXP i.MX31 family"
+ select CPU_ARM1136
+
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
+ select ARCH_EARLY_INIT_R
+ select ARCH_MISC_INIT
select CPU_V7A
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_OF_CONTROL
select DM
+ select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK
- select ARCH_EARLY_INIT_R
- select ARCH_MISC_INIT
+ select OF_CONTROL
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBDISK_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_MMC_SUPPORT if DM_MMC
+ select SPL_NAND_SUPPORT if SPL_NAND_DENALI
+ select SPL_OF_CONTROL
+ select SPL_SERIAL_SUPPORT
+ select SPL_DM_SERIAL
+ select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
+ select SPL_SPI_SUPPORT if DM_SPI
+ select SPL_WATCHDOG_SUPPORT
+ select SUPPORT_SPL
+ select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ select SYS_NS16550
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
select DM_SERIAL
select OF_CONTROL
select OF_LIBFDT
+ select MISC
select PINCTRL
select REGMAP
select SUPPORT_SPL
source "arch/arm/mach-imx/mx2/Kconfig"
+source "arch/arm/mach-imx/mx3/Kconfig"
+
source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-imx/mx6/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/mx31pdk/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/gdsys/a38x/Kconfig"
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7, -march=armv5))
+arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
arch-$(CONFIG_ARM64) =-march=armv8-a
# (C) Copyright 2015
# Kamil Lulko, <kamil.lulko@gmail.com>
-PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access
+PLATFORM_CPPFLAGS += -mno-unaligned-access
return ticks;
}
+
+ulong timer_get_boot_us(void)
+{
+ u64 val = get_ticks() * 1000000;
+
+ return val / get_tbclk();
+}
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
- socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
- socfpga_cyclone5_de0_nano_soc.dtb \
+ socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_de10_nano.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
- socfpga_stratix10_socdk.dtb \
- socfpga_cyclone5_vining_fpga.dtb
+ socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
- imx6sl-evk.dtb \
- imx6sll-evk.dtb \
+dtb-$(CONFIG_MX6QDL) += \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
+ imx6dl-mamoj.dtb \
imx6q-cm-fx6.dtb \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
- imx6q-logicpd.dtb \
+ imx6q-logicpd.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sll-evk.dtb
+
+dtb-$(CONFIG_MX6SX) += \
imx6sx-sabreauto.dtb \
- imx6sx-sdb.dtb \
+ imx6sx-sdb.dtb
+
+dtb-$(CONFIG_MX6UL) += \
imx6ul-geam-kit.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb
+dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
+
dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb.dtb
1 3 0 0 0 0 0 0 0 3 >;
};
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
&cpm_pinctl {
/* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins
status = "okay";
};
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&cps_pinctl {
/* MPP Bus:
* [0-11] RGMII0
status = "okay";
};
+/* uSD slot */
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&cpm_comphy {
/*
* CP0 Serdes Configuration:
};
ap_pinctl: ap-pinctl@6F4000 {
- compatible = "marvell,armada-ap806-pinctrl";
+ compatible = "marvell,ap806-pinctrl";
bank-name ="apn-806";
reg = <0x6F4000 0x10>;
pin-count = <20>;
cpm_pinctl: cpm-pinctl@440000 {
compatible = "marvell,mvebu-pinctrl",
- "marvell,a70x0-pinctrl",
- "marvell,a80x0-cp0-pinctrl";
+ "marvell,armada-7k-pinctrl",
+ "marvell,armada-8k-cpm-pinctrl";
bank-name ="cp0-110";
reg = <0x440000 0x20>;
pin-count = <63>;
cps_pinctl: cps-pinctl@440000 {
compatible = "marvell,mvebu-pinctrl",
- "marvell,a80x0-cp1-pinctrl";
+ "marvell,armada-8k-cps-pinctrl";
bank-name ="cp1-110";
reg = <0x440000 0x20>;
pin-count = <63>;
/dts-v1/;
#include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
ranges = <0x0 0x0 0x0 0xffffffff>;
compatible = "simple-bus";
+ pinctrl: qcom,tlmm@1000000 {
+ compatible = "qcom,tlmm-apq8016";
+ reg = <0x1000000 0x400000>;
+
+ blsp1_uart: uart {
+ function = "blsp1_uart";
+ pins = "GPIO_4", "GPIO_5";
+ drive-strength = <DRIVE_STRENGTH_8MA>;
+ bias-disable;
+ };
+ };
clkc: qcom,gcc@1800000 {
compatible = "qcom,gcc-apq8016";
reg = <0x1800000 0x80000>;
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b0000 0x200>;
clock = <&clkc 4>;
+ pinctrl-names = "uart";
+ pinctrl-0 = <&blsp1_uart>;
};
soc_gpios: pinctrl@1000000 {
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+
+ clock-controller@300000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@75b0000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
&pm8994_pon {
key_vol_down {
gpios = <&pm8994_pon 1 0>;
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
+ clock = <&gcc 4>;
};
sdhc2: sdhci@74a4900 {
--- /dev/null
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx53.dtsi"
+#include "imx53-pinfunc.h"
+
+/ {
+ model = "K+P iMX53";
+ compatible = "kp,imx53-kp", "fsl,imx53";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 0>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ clock_frequency = <100000>;
+
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+
+ pmic: mc34708@8 {
+ compatible = "fsl,mc34708";
+ reg = <0x8>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ clock_frequency = <100000>;
+
+ scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx53-kp {
+ pinctrl_eth: ethgrp {
+ fsl,pins = <
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ /* The RX_ER pin needs to be pull down */
+ /* for this device */
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* PHY RESET */
+ MX53_PAD_PATA_DA_0__GPIO7_6 0x182
+ /* VBUS_PWR_EN */
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+ /* BOOSTER_OFF */
+ MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA
+ (0x1ee | IMX_PAD_SION)
+ MX53_PAD_KEY_COL3__I2C2_SCL
+ (0x1ee | IMX_PAD_SION)
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2grpgpio {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
+ MX53_PAD_KEY_COL3__GPIO4_12 0x1e4
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION)
+ MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION)
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3grpgpio {
+ fsl,pins = <
+ MX53_PAD_GPIO_6__GPIO1_6 0x1e4
+ MX53_PAD_GPIO_5__GPIO1_5 0x1e4
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ >;
+ };
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
#ifndef __DTS_IMX53_PINFUNC_H
#define __DTS_IMX53_PINFUNC_H
+#define IMX_PAD_SION 0x40000000
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
/ {
aliases {
serial1 = &uart2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
};
tzic: tz-interrupt-controller@fffc000 {
#clock-cells = <1>;
};
+ gpio1: gpio@53f84000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53f84000 0x4000>;
+ interrupts = <50 51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@53f88000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53f88000 0x4000>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@53f8c000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53f8c000 0x4000>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@53f90000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53f90000 0x4000>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@53fdc000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53fdc000 0x4000>;
+ interrupts = <103 104>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@53fe0000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+ reg = <0x53fe0000 0x4000>;
+ interrupts = <105 106>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gpio7: gpio@53fe4000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fe4000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ i2c3: i2c@53fec000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+ reg = <0x53fec000 0x4000>;
+ interrupts = <64>;
+ clocks = <&clks IMX5_CLK_I2C3_GATE>;
+ status = "disabled";
+ };
};
aips@60000000 { /* AIPS2 */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
-
fec: ethernet@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
+
+ i2c2: i2c@63fc4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+ reg = <0x63fc4000 0x4000>;
+ interrupts = <63>;
+ clocks = <&clks IMX5_CLK_I2C2_GATE>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@63fc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+ reg = <0x63fc8000 0x4000>;
+ interrupts = <62>;
+ clocks = <&clks IMX5_CLK_I2C1_GATE>;
+ status = "disabled";
+ };
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
};
&usdhc3 {
- u-boot,dm-spl;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 BTicino
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+ model = "BTicino i.MX6DL Mamoj board";
+ compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ /* CPU vdd_arm core */
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ /* SOC vdd_soc */
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ /* I/O power GEN_3V3 */
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* DDR memory */
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* DDR memory */
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* not used */
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* not used */
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ /* PMIC vsnvs. EX boot mode */
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* not used */
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ /* not used */
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ /* not used */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* 1v8 general power */
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* 2v8 general power IMX6 */
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* 3v3 Ethernet */
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
+ MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
+ MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
+ MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
};
&usdhc3 {
- u-boot,dm-spl;
status = "okay";
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&usdhc4 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc4 {
+ u-boot,dm-spl;
+};
};
&usdhc3 {
- u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
&usdhc4 {
- u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc4>;
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
};
pinctrl_usdhc3: usdhc3grp {
- u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
};
pinctrl_usdhc4: usdhc4grp {
- u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
};
&usdhc1 {
- u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
};
pinctrl_usdhc3: usdhc3grp {
- u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+ soc {
+ u-boot,dm-spl;
+
+ aips-bus@02000000 {
+ u-boot,dm-spl;
+ };
+
+ aips-bus@02100000 {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
- u-boot,dm-spl;
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
- u-boot,dm-spl;
};
ldb: ldb@020e0008 {
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- u-boot,dm-spl;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ u-boot,dm-spl;
+ };
+};
};
&usdhc1 {
- u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
};
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-isiot-u-boot.dtsi"
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
/dts-v1/;
+#include "imx6ul.dtsi"
#include "imx6ul-isiot.dtsi"
/ {
&usdhc2 {
u-boot,dm-spl;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
- bus-width = <8>;
- no-1-8-v;
status = "okay";
};
-
-&iomuxc {
- pinctrl_usdhc2: usdhc2grp {
- u-boot,dm-spl;
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
- MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
- MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
- MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
- MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
- MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
- >;
- };
-};
/dts-v1/;
+#include "imx6ul.dtsi"
#include "imx6ul-isiot.dtsi"
/ {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
/ {
memory {
};
&usdhc1 {
- u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+ bus-width = <8>;
+ no-1-8-v;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
};
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
+
+ pinctrl_usdhc2: usdhc2grp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
+ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
+ >;
+ };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+ soc {
+ u-boot,dm-spl;
+ };
+};
+
+&aips1 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
- u-boot,dm-spl;
pmu {
compatible = "arm,cortex-a7-pmu";
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
- u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
- u-boot,dm-spl;
};
gpio5: gpio@020ac000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
- u-boot,dm-spl;
};
gpr: iomuxc-gpr@020e4000 {
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- u-boot,dm-spl;
usbotg1: usb@02184000 {
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ mbus@f1000000 {
+ pciec: pcie@82000000 {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
+
+ pcie0: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc 9>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ compatible = "marvell,88f6192-pinctrl";
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp5", "mpp21", "mpp23";
+ marvell,function = "sata0";
+ };
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp4", "mpp20", "mpp22";
+ marvell,function = "sata1";
+ };
+ pmx_sdio: pmx-sdio {
+ marvell,pins = "mpp12", "mpp13", "mpp14",
+ "mpp15", "mpp16", "mpp17";
+ marvell,function = "sdio";
+ };
+ };
+
+ rtc: rtc@10300 {
+ compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <53>;
+ clocks = <&gate_clk 7>;
+ };
+
+ sata: sata@80000 {
+ compatible = "marvell,orion-sata";
+ reg = <0x80000 0x5000>;
+ interrupts = <21>;
+ clocks = <&gate_clk 14>, <&gate_clk 15>;
+ clock-names = "0", "1";
+ phys = <&sata_phy0>, <&sata_phy1>;
+ phy-names = "port0", "port1";
+ status = "disabled";
+ };
+
+ sdio: mvsdio@90000 {
+ compatible = "marvell,orion-sdio";
+ reg = <0x90000 0x200>;
+ interrupts = <28>;
+ clocks = <&gate_clk 4>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ mbus@f1000000 {
+ pciec: pcie@82000000 {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
+
+ pcie0: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc 9>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ compatible = "marvell,88f6281-pinctrl";
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp5", "mpp21", "mpp23";
+ marvell,function = "sata0";
+ };
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp4", "mpp20", "mpp22";
+ marvell,function = "sata1";
+ };
+ pmx_sdio: pmx-sdio {
+ marvell,pins = "mpp12", "mpp13", "mpp14",
+ "mpp15", "mpp16", "mpp17";
+ marvell,function = "sdio";
+ };
+ };
+
+ rtc: rtc@10300 {
+ compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <53>;
+ clocks = <&gate_clk 7>;
+ };
+
+ sata: sata@80000 {
+ compatible = "marvell,orion-sata";
+ reg = <0x80000 0x5000>;
+ interrupts = <21>;
+ clocks = <&gate_clk 14>, <&gate_clk 15>;
+ clock-names = "0", "1";
+ phys = <&sata_phy0>, <&sata_phy1>;
+ phy-names = "port0", "port1";
+ status = "disabled";
+ };
+
+ sdio: mvsdio@90000 {
+ compatible = "marvell,orion-sdio";
+ reg = <0x90000 0x200>;
+ interrupts = <28>;
+ clocks = <&gate_clk 4>;
+ pinctrl-0 = <&pmx_sdio>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ mbus@f1000000 {
+ pciec: pcie@82000000 {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
+
+ pcie0: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc 9>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ compatible = "marvell,98dx4122-pinctrl";
+
+ };
+ };
+};
+
+&sata_phy0 {
+ status = "disabled";
+};
+
+&sata_phy1 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Seagate Blackarmor NAS220
+ *
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+
+/ {
+ model = "Seagate Blackarmor NAS220";
+ compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
+ "marvell,kirkwood";
+
+ memory { /* 128 MB */
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "Reset";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ button {
+ label = "Power";
+ linux,code = <KEY_SLEEP>;
+ gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue-power {
+ label = "nas220:blue:power";
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+ pinctrl-names = "default";
+
+ sata0_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA0 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+
+ sata1_power: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/*
+ * Serial port routed to connector CN5
+ *
+ * pin 1 - TX (CPU's TX)
+ * pin 4 - RX (CPU's RX)
+ * pin 6 - GND
+ */
+&uart0 {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-0 = <&pmx_button_reset &pmx_button_power>;
+ pinctrl-names = "default";
+
+ pmx_act_sata0: pmx-act-sata0 {
+ marvell,pins = "mpp15";
+ marvell,function = "sata0";
+ };
+
+ pmx_act_sata1: pmx-act-sata1 {
+ marvell,pins = "mpp16";
+ marvell,function = "sata1";
+ };
+
+ pmx_power_sata0: pmx-power-sata0 {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ pmx_power_sata1: pmx-power-sata1 {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ pmx_button_reset: pmx-button-reset {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_button_power: pmx-button-power {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+};
+
+&sata {
+ status = "okay";
+ nr-ports = <2>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ adt7476: thermal@2e {
+ compatible = "adi,adt7476";
+ reg = <0x2e>;
+ };
+};
+
+&nand {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for d2 Network v2
+ *
+ * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org>
+ *
+*/
+
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-netxbig.dtsi"
+
+/ {
+ model = "LaCie d2 Network v2";
+ compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ ns2-leds {
+ compatible = "lacie,ns2-leds";
+
+ blue-sata {
+ label = "d2net_v2:blue:sata";
+ slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ modes-map = <NS_V2_LED_OFF 1 0
+ NS_V2_LED_ON 0 1
+ NS_V2_LED_ON 1 1
+ NS_V2_LED_SATA 0 0>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ red-fail {
+ label = "d2net_v2:red:fail";
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-dnskw.dtsi"
+
+/ {
+ model = "D-Link DNS-325 NAS (Rev A1)";
+ compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+ &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+ &pmx_led_white_usb>;
+ pinctrl-names = "default";
+
+ white-power {
+ label = "dns325:white:power";
+ gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+ white-usb {
+ label = "dns325:white:usb";
+ gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
+ };
+ red-l_hdd {
+ label = "dns325:red:l_hdd";
+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ };
+ red-r_hdd {
+ label = "dns325:red:r_hdd";
+ gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+ };
+ red-usb {
+ label = "dns325:red:usb";
+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ ocp@f1000000 {
+ i2c@11000 {
+ status = "okay";
+
+ lm75: lm75@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+ };
+ serial@12000 {
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "D-Link DNS NASes (kirkwood-based)";
+ compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+ &pmx_button_reset>;
+ pinctrl-names = "default";
+
+ power {
+ label = "Power button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+ eject {
+ label = "USB unmount button";
+ linux,code = <KEY_EJECTCD>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+ reset {
+ label = "Reset button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_fan {
+ /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW
+ &gpio1 13 GPIO_ACTIVE_LOW>;
+ gpio-fan,speed-map = <0 0
+ 3000 1
+ 6000 2>;
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pmx_power_off>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+
+ pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
+ &pmx_present_sata1 &pmx_fan_tacho
+ &pmx_temp_alarm>;
+ pinctrl-names = "default";
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp20";
+ marvell,function = "sata1";
+ };
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp21";
+ marvell,function = "sata0";
+ };
+ pmx_led_power: pmx-led-power {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+ pmx_led_red_right_hdd: pmx-led-red-right-hdd {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+ pmx_led_red_left_hdd: pmx-led-red-left-hdd {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+ pmx_led_red_usb_325: pmx-led-red-usb-325 {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ pmx_button_power: pmx-button-power {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ pmx_led_red_usb_320: pmx-led-red-usb-320 {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+ pmx_power_off: pmx-power-off {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+ pmx_power_back_on: pmx-power-back-on {
+ marvell,pins = "mpp37";
+ marvell,function = "gpio";
+ };
+ pmx_power_sata0: pmx-power-sata0 {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+ pmx_power_sata1: pmx-power-sata1 {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+ pmx_present_sata0: pmx-present-sata0 {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+ pmx_present_sata1: pmx-present-sata1 {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+ pmx_led_white_usb: pmx-led-white-usb {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ pmx_fan_tacho: pmx-fan-tacho {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+ pmx_fan_high_speed: pmx-fan-high-speed {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+ pmx_fan_low_speed: pmx-fan-low-speed {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_button_unmount: pmx-button-unmount {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ pmx_button_reset: pmx-button-reset {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+ pmx_temp_alarm: pmx-temp-alarm {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+ };
+ sata@80000 {
+ pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <2>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+ pinctrl-names = "default";
+
+ sata0_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA0 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 7 0>;
+ };
+ sata1_power: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "SATA1 Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio1 8 0>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+ chip-delay = <35>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x500000>;
+ };
+
+ partition@600000 {
+ label = "ramdisk";
+ reg = <0x0600000 0x500000>;
+ };
+
+ partition@b00000 {
+ label = "image";
+ reg = <0x0b00000 0x6600000>;
+ };
+
+ partition@7100000 {
+ label = "mini firmware";
+ reg = <0x7100000 0xa00000>;
+ };
+
+ partition@7b00000 {
+ label = "config";
+ reg = <0x7b00000 0x500000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Seagate FreeAgent Dockstar";
+ compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_usb_power_enable: pmx-usb-power-enable {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ pmx_led_green: pmx-led-green {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_led_orange: pmx-led-orange {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "ok";
+ };
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+ pinctrl-names = "default";
+
+ health {
+ label = "status:green:health";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+ fault {
+ label = "status:orange:fault";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power_enable>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 29 0>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "data";
+ reg = <0x0500000 0xfb00000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "marvell,88e1116";
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Globalscale Technologies Dreamplug";
+ compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_led_bluetooth: pmx-led-bluetooth {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ pmx_led_wifi: pmx-led-wifi {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+ pmx_led_wifi_ap: pmx-led-wifi-ap {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "ok";
+ };
+
+ spi@10600 {
+ status = "okay";
+
+ m25p40@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l1606e", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@0 {
+ reg = <0x0 0x80000>;
+ label = "u-boot";
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x10000>;
+ label = "u-boot env";
+ };
+
+ partition@180000 {
+ reg = <0x180000 0x10000>;
+ label = "dtb";
+ };
+ };
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <1>;
+ };
+
+ mvsdio@90000 {
+ pinctrl-0 = <&pmx_sdio>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ broken-cd;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+ &pmx_led_wifi_ap >;
+ pinctrl-names = "default";
+
+ bluetooth {
+ label = "dreamplug:blue:bluetooth";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+ wifi {
+ label = "dreamplug:green:wifi";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ wifi-ap {
+ label = "dreamplug:green:wifi_ap";
+ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+
+/ {
+ model = "Synology DS109, DS110, DS110jv20";
+ compatible = "synology,ds109", "synology,ds110jv20",
+ "synology,ds110", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ gpio-fan-150-32-35 {
+ status = "okay";
+ };
+
+ gpio-leds-hdd-21-1 {
+ status = "okay";
+ };
+};
+
+&rs5c372 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Seagate GoFlex Net";
+ compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_usb_power_enable: pmx-usb-power-enable {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ pmx_led_right_cap_0: pmx-led_right_cap_0 {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+ pmx_led_right_cap_1: pmx-led_right_cap_1 {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+ pmx_led_right_cap_2: pmx-led_right_cap_2 {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+ pmx_led_right_cap_3: pmx-led_right_cap_3 {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+ pmx_led_left_cap_0: pmx-led_left_cap_0 {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+ pmx_led_left_cap_1: pmx-led_left_cap_1 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ pmx_led_left_cap_2: pmx-led_left_cap_2 {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+ pmx_led_left_cap_3: pmx-led_left_cap_3 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+ pmx_led_green: pmx-led_green {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_led_orange: pmx-led_orange {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "ok";
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ };
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = < &pmx_led_orange
+ &pmx_led_left_cap_0 &pmx_led_left_cap_1
+ &pmx_led_left_cap_2 &pmx_led_left_cap_3
+ &pmx_led_right_cap_0 &pmx_led_right_cap_1
+ &pmx_led_right_cap_2 &pmx_led_right_cap_3
+ >;
+ pinctrl-names = "default";
+
+ health {
+ label = "status:green:health";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+ fault {
+ label = "status:orange:fault";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+ left0 {
+ label = "status:white:left0";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+ left1 {
+ label = "status:white:left1";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+ left2 {
+ label = "status:white:left2";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+ left3 {
+ label = "status:white:left3";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ right0 {
+ label = "status:white:right0";
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ };
+ right1 {
+ label = "status:white:right1";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+ right2 {
+ label = "status:white:right2";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+ right3 {
+ label = "status:white:right3";
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power_enable>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&nand {
+ chip-delay = <40>;
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "pogoplug";
+ reg = <0x0500000 0x2000000>;
+ };
+
+ partition@2500000 {
+ label = "root";
+ reg = <0x02500000 0xd800000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Globalscale Technologies Guruplug Server Plus";
+ compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_led_health_r: pmx-led-health-r {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_led_health_g: pmx-led-health-g {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ pmx_led_wmode_r: pmx-led-wmode-r {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+ pmx_led_wmode_g: pmx-led-wmode-g {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "ok";
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <1>;
+ };
+
+ /* AzureWave AW-GH381 WiFi/BT */
+ mvsdio@90000 {
+ status = "okay";
+ non-removable;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+ &pmx_led_wmode_r &pmx_led_wmode_g >;
+ pinctrl-names = "default";
+
+ health-r {
+ label = "guruplug:red:health";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ };
+ health-g {
+ label = "guruplug:green:health";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+ wmode-r {
+ label = "guruplug:red:wmode";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ wmode-g {
+ label = "guruplug:green:wmode";
+ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x00100000 0x00400000>;
+ };
+
+ partition@500000 {
+ label = "data";
+ reg = <0x00500000 0x1fb00000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ /* Marvell 88E1121R */
+ compatible = "ethernet-phy-id0141.0cb0",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ /* Marvell 88E1121R */
+ compatible = "ethernet-phy-id0141.0cb0",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ phy-connection-type = "rgmii-id";
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
+ compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_led_os_red: pmx-led-os-red {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+ pmx_power_off: pmx-power-off {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+ pmx_led_os_green: pmx-led-os-green {
+ marvell,pins = "mpp25";
+ marvell,function = "gpio";
+ };
+ pmx_led_usb_transfer: pmx-led-usb-transfer {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+ pmx_button_reset: pmx-button-reset {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+ pmx_button_usb_copy: pmx-button-usb-copy {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+ pinctrl-names = "default";
+
+ copy {
+ label = "USB Copy";
+ linux,code = <KEY_COPY>;
+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ };
+ reset {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+ &pmx_led_usb_transfer>;
+ pinctrl-names = "default";
+
+ green-os {
+ label = "ib62x0:green:os";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+ red-os {
+ label = "ib62x0:red:os";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ };
+ usb-copy {
+ label = "ib62x0:red:usb_copy";
+ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pmx_power_off>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "u-boot environment";
+ reg = <0xe0000 0x20000>;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x600000>;
+ };
+
+ partition@700000 {
+ label = "root";
+ reg = <0x0700000 0xf900000>;
+ };
+
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Iomega Iconnect";
+ compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ linux,initrd-start = <0x4500040>;
+ linux,initrd-end = <0x4800000>;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_button_reset: pmx-button-reset {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+ pmx_button_otb: pmx-button-otb {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+ pmx_led_level: pmx-led-level {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+ pmx_led_power_blue: pmx-led-power-blue {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+ pmx_led_power_red: pmx-power-red {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ pmx_led_usb1: pmx-led-usb1 {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+ pmx_led_usb2: pmx-led-usb2 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+ pmx_led_usb3: pmx-led-usb3 {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_led_usb4: pmx-led-usb4 {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ pmx_led_otb: pmx-led-otb {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+ };
+ i2c@11000 {
+ status = "okay";
+
+ lm63: lm63@4c {
+ compatible = "national,lm63";
+ reg = <0x4c>;
+ };
+ };
+ serial@12000 {
+ status = "ok";
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+ &pmx_led_power_red &pmx_led_usb1
+ &pmx_led_usb2 &pmx_led_usb3
+ &pmx_led_usb4 &pmx_led_otb >;
+ pinctrl-names = "default";
+
+ led-level {
+ label = "led_level";
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ power-blue {
+ label = "power:blue";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ };
+ power-red {
+ label = "power:red";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+ usb1 {
+ label = "usb1:blue";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+ usb2 {
+ label = "usb2:blue";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ usb3 {
+ label = "usb3:blue";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+ usb4 {
+ label = "usb4:blue";
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+ otb {
+ label = "otb:blue";
+ gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+ pinctrl-names = "default";
+
+ otb {
+ label = "OTB Button";
+ linux,code = <KEY_COPY>;
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ debounce-interval = <100>;
+ };
+ reset {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ debounce-interval = <100>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0000000 0xc0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0xa0000 0x20000>;
+ };
+
+ partition@100000 {
+ label = "zImage";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@540000 {
+ label = "initrd";
+ reg = <0x540000 0x300000>;
+ };
+
+ partition@980000 {
+ label = "boot";
+ reg = <0x980000 0x1f400000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@11 {
+ reg = <11>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+ model = "LaCie Internet Space v2";
+ compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ pinctrl-0 = <&pmx_ns2_sata0>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <1>;
+ };
+ };
+
+ ns2-leds {
+ compatible = "lacie,ns2-leds";
+
+ blue-sata {
+ label = "ns2:blue:sata";
+ slow-gpio = <&gpio0 29 0>;
+ cmd-gpio = <&gpio0 30 0>;
+ modes-map = <NS_V2_LED_OFF 1 0
+ NS_V2_LED_ON 0 1
+ NS_V2_LED_ON 1 1
+ NS_V2_LED_SATA 0 0>;
+ };
+ };
+};
+
+ðphy0 { reg = <8>; };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
+ pinctrl-names = "default";
+
+ pmx_i2c_gpio_sda: pmx-gpio-sda {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+ pmx_i2c_gpio_scl: pmx-gpio-scl {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+ };
+
+ i2c {
+ compatible = "i2c-gpio";
+ gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */
+ &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ };
+};
+
+&nand {
+ status = "okay";
+ chip-delay = <25>;
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+#include "kirkwood-km_common.dtsi"
+
+/ {
+ model = "Keymile Kirkwood Reference Design";
+ compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-lsxl.dtsi"
+
+/ {
+ model = "Buffalo Linkstation LS-CHLv2";
+ compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-lsxl.dtsi"
+
+/ {
+ model = "Buffalo Linkstation LS-XHL";
+ compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_power_hdd: pmx-power-hdd {
+ marvell,pins = "mpp10";
+ marvell,function = "gpo";
+ };
+ pmx_usb_vbus: pmx-usb-vbus {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+ pmx_fan_high: pmx-fan-high {
+ marvell,pins = "mpp18";
+ marvell,function = "gpo";
+ };
+ pmx_fan_low: pmx-fan-low {
+ marvell,pins = "mpp19";
+ marvell,function = "gpo";
+ };
+ pmx_led_function_blue: pmx-led-function-blue {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+ pmx_led_alarm: pmx-led-alarm {
+ marvell,pins = "mpp37";
+ marvell,function = "gpio";
+ };
+ pmx_led_info: pmx-led-info {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+ pmx_led_power: pmx-led-power {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+ pmx_fan_lock: pmx-fan-lock {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+ pmx_button_function: pmx-button-function {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+ pmx_power_switch: pmx-power-switch {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+ pmx_power_auto_switch: pmx-power-auto-switch {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ pmx_led_function_red: pmx-led-function_red {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ };
+ sata@80000 {
+ status = "okay";
+ nr-ports = <1>;
+ };
+
+ spi@10600 {
+ status = "okay";
+
+ m25p40@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p40", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ mode = <0>;
+
+ partition@0 {
+ reg = <0x0 0x60000>;
+ label = "uboot";
+ read-only;
+ };
+
+ partition@60000 {
+ reg = <0x60000 0x10000>;
+ label = "dtb";
+ read-only;
+ };
+
+ partition@70000 {
+ reg = <0x70000 0x10000>;
+ label = "uboot_env";
+ };
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_button_function &pmx_power_switch
+ &pmx_power_auto_switch>;
+ pinctrl-names = "default";
+
+ option {
+ label = "Function Button";
+ linux,code = <KEY_OPTION>;
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+ reserved {
+ label = "Power-on Switch";
+ linux,code = <KEY_RESERVED>;
+ linux,input-type = <5>;
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ };
+ power {
+ label = "Power-auto Switch";
+ linux,code = <KEY_ESC>;
+ linux,input-type = <5>;
+ gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+ &pmx_led_info &pmx_led_power
+ &pmx_led_function_blue>;
+ pinctrl-names = "default";
+
+ func_blue {
+ label = "lsxl:blue:func";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ };
+
+ alarm {
+ label = "lsxl:red:alarm";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+
+ info {
+ label = "lsxl:amber:info";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ power {
+ label = "lsxl:blue:power";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+
+ func_red {
+ label = "lsxl:red:func";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_fan {
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW
+ &gpio0 18 GPIO_ACTIVE_LOW>;
+ gpio-fan,speed-map = <0 3
+ 1500 2
+ 3250 1
+ 5000 0>;
+ alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ restart_poweroff {
+ compatible = "restart-poweroff";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 11 0>;
+ };
+ hdd_power: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "HDD Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 10 0>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for LaCie 2Big Network v2
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * Based on netxbig_v2-setup.c,
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+*/
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-netxbig.dtsi"
+
+/ {
+ model = "LaCie 2Big Network v2";
+ compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ fan {
+ compatible = "gpio-fan";
+ alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ };
+};
+
+®ulators {
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "hdd1power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ clocks {
+ g762_clk: g762-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&i2c0 {
+ g762@3e {
+ compatible = "gmt,g762";
+ reg = <0x3e>;
+ clocks = <&g762_clk>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree common file for LaCie 2Big and 5Big Network v2
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * Based on netxbig_v2-setup.c,
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+*/
+
+#include <dt-bindings/leds/leds-netxbig.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ serial@12000 {
+ status = "okay";
+ };
+
+ spi@10600 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l4005a", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ mode = <0>;
+
+ partition@0 {
+ reg = <0x0 0x80000>;
+ label = "u-boot";
+ };
+ };
+ };
+
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * esc and power represent a three position rocker
+ * switch. Thus the conventional KEY_POWER does not fit
+ */
+ exc {
+ label = "Back power switch (on|auto)";
+ linux,code = <KEY_ESC>;
+ linux,input-type = <5>;
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ };
+ power {
+ label = "Back power switch (auto|off)";
+ linux,code = <KEY_1>;
+ linux,input-type = <5>;
+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+ };
+ option {
+ label = "Function button";
+ linux,code = <KEY_OPTION>;
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulators: regulators {
+ status = "okay";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd0power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ netxbig_gpio_ext: netxbig-gpio-ext {
+ compatible = "lacie,netxbig-gpio-ext";
+
+ addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
+ &gpio1 16 GPIO_ACTIVE_HIGH
+ &gpio1 17 GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
+ &gpio1 13 GPIO_ACTIVE_HIGH
+ &gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ netxbig-leds {
+ compatible = "lacie,netxbig-leds";
+
+ gpio-ext = <&netxbig_gpio_ext>;
+
+ timers = <NETXBIG_LED_TIMER1 500 500
+ NETXBIG_LED_TIMER2 500 1000>;
+
+ blue-power {
+ label = "netxbig:blue:power";
+ mode-addr = <0>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 1
+ NETXBIG_LED_TIMER1 3
+ NETXBIG_LED_TIMER2 7>;
+ bright-addr = <1>;
+ max-brightness = <7>;
+ };
+ red-power {
+ label = "netxbig:red:power";
+ mode-addr = <0>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <1>;
+ max-brightness = <7>;
+ };
+ blue-sata0 {
+ label = "netxbig:blue:sata0";
+ mode-addr = <3>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 7
+ NETXBIG_LED_SATA 1
+ NETXBIG_LED_TIMER1 3>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ red-sata0 {
+ label = "netxbig:red:sata0";
+ mode-addr = <3>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ blue-sata1 {
+ label = "netxbig:blue:sata1";
+ mode-addr = <4>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 7
+ NETXBIG_LED_SATA 1
+ NETXBIG_LED_TIMER1 3>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ red-sata1 {
+ label = "netxbig:red:sata1";
+ mode-addr = <4>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <8>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+
+ pmx_button_function: pmx-button-function {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ pmx_button_power_off: pmx-button-power-off {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+ pmx_button_power_on: pmx-button-power-on {
+ marvell,pins = "mpp13";
+ marvell,function = "gpio";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_ns2_sata0: pmx-ns2-sata0 {
+ marvell,pins = "mpp21";
+ marvell,function = "sata0";
+ };
+ pmx_ns2_sata1: pmx-ns2-sata1 {
+ marvell,pins = "mpp20";
+ marvell,function = "sata1";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ spi@10600 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25l4005a", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ mode = <0>;
+
+ partition@0 {
+ reg = <0x0 0x80000>;
+ label = "u-boot";
+ };
+ };
+ };
+
+ i2c@11000 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power {
+ label = "Power push button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ red-fail {
+ label = "ns2:red:fail";
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio_poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+ };
+
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@X {
+ /* overwrite reg property in board file */
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+ model = "LaCie Network Space v2";
+ compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ pinctrl-0 = <&pmx_ns2_sata0>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <1>;
+ };
+ };
+
+ ns2-leds {
+ compatible = "lacie,ns2-leds";
+
+ blue-sata {
+ label = "ns2:blue:sata";
+ slow-gpio = <&gpio0 29 0>;
+ cmd-gpio = <&gpio0 30 0>;
+ modes-map = <NS_V2_LED_OFF 1 0
+ NS_V2_LED_ON 0 1
+ NS_V2_LED_ON 1 1
+ NS_V2_LED_SATA 0 0>;
+ };
+ };
+};
+
+ðphy0 { reg = <8>; };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+ model = "LaCie Network Space Lite v2";
+ compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ pinctrl-0 = <&pmx_ns2_sata0>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue-sata {
+ label = "ns2:blue:sata";
+ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+};
+
+ðphy0 { reg = <0>; };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+ model = "LaCie Network Space Max v2";
+ compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <2>;
+ };
+ };
+
+ gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+ &gpio0 7 GPIO_ACTIVE_LOW
+ &gpio1 1 GPIO_ACTIVE_LOW
+ &gpio0 23 GPIO_ACTIVE_LOW>;
+ gpio-fan,speed-map =
+ < 0 0
+ 1500 15
+ 1700 14
+ 1800 13
+ 2100 12
+ 3100 11
+ 3300 10
+ 4300 9
+ 5500 8>;
+ alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ };
+
+ ns2-leds {
+ compatible = "lacie,ns2-leds";
+
+ blue-sata {
+ label = "ns2:blue:sata";
+ slow-gpio = <&gpio0 29 0>;
+ cmd-gpio = <&gpio0 30 0>;
+ modes-map = <NS_V2_LED_OFF 1 0
+ NS_V2_LED_ON 0 1
+ NS_V2_LED_ON 1 1
+ NS_V2_LED_SATA 0 0>;
+ };
+ };
+};
+
+ðphy0 { reg = <8>; };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+ /* This machine is embedded in the first LaCie CloudBox product. */
+ model = "LaCie Network Space Mini v2";
+ compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x8000000>;
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ pinctrl-0 = <&pmx_ns2_sata0>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <1>;
+ };
+ };
+
+ gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW
+ &gpio0 7 GPIO_ACTIVE_LOW
+ &gpio1 1 GPIO_ACTIVE_LOW
+ &gpio0 23 GPIO_ACTIVE_LOW>;
+ gpio-fan,speed-map =
+ < 0 0
+ 3000 15
+ 3180 14
+ 4140 13
+ 4570 12
+ 6760 11
+ 7140 10
+ 7980 9
+ 9200 8>;
+ alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ };
+
+ ns2-leds {
+ compatible = "lacie,ns2-leds";
+
+ blue-sata {
+ label = "ns2:blue:sata";
+ slow-gpio = <&gpio0 29 0>;
+ cmd-gpio = <&gpio0 30 0>;
+ modes-map = <NS_V2_LED_OFF 1 0
+ NS_V2_LED_ON 0 1
+ NS_V2_LED_ON 1 1
+ NS_V2_LED_SATA 0 0>;
+ };
+ };
+};
+
+ðphy0 { reg = <0>; };
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Marvell OpenRD Base Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * base variant of the Marvell Kirkwood Development Board.
+ */
+
+/dts-v1/;
+
+#include "kirkwood-openrd.dtsi"
+
+/ {
+ model = "OpenRD Base";
+ compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ ocp@f1000000 {
+ serial@12100 {
+ status = "okay";
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Marvell OpenRD Client Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * client variant of the Marvell Kirkwood Development Board.
+ */
+
+/dts-v1/;
+
+#include "kirkwood-openrd.dtsi"
+
+/ {
+ model = "OpenRD Client";
+ compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ ocp@f1000000 {
+ audio-controller@a0000 {
+ status = "okay";
+ };
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ cs42l51: cs42l51@4a {
+ compatible = "cirrus,cs42l51";
+ reg = <0x4a>;
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&audio0 0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&cs42l51>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+ ethphy1: ethernet-phy@24 {
+ reg = <24>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Marvell OpenRD Ultimate Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * ultimate variant of the Marvell Kirkwood Development Board.
+ */
+
+/dts-v1/;
+
+#include "kirkwood-openrd.dtsi"
+
+/ {
+ model = "OpenRD Ultimate";
+ compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ ocp@f1000000 {
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ cs42l51: cs42l51@4a {
+ compatible = "cirrus,cs42l51";
+ reg = <0x4a>;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Marvell OpenRD (Base|Client|Ultimate) Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file contains the definitions that are common between the three
+ * variants of the Marvell Kirkwood Development Board.
+ */
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
+ pinctrl-names = "default";
+
+ pmx_select28: pmx-select-rs232-rs485 {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+ pmx_sdio_cd: pmx-sdio-cd {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ pmx_select34: pmx-select-uart-sd {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "okay";
+
+ };
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+ mvsdio@90000 {
+ status = "okay";
+ cd-gpios = <&gpio0 29 9>;
+ };
+ gpio@10100 {
+ p28 {
+ gpio-hog;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ /*
+ * SelRS232or485 selects between RS-232 or RS-485
+ * mode for the second UART.
+ *
+ * Low: RS-232
+ * High: RS-485
+ *
+ * To use the second UART, you need to change also
+ * the SelUARTorSD.
+ */
+ output-low;
+ line-name = "SelRS232or485";
+ };
+ };
+ gpio@10140 {
+ p2 {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ /*
+ * SelUARTorSD selects between the second UART
+ * (serial@12100) and SD (mvsdio@90000).
+ *
+ * Low: UART
+ * High: SD
+ *
+ * When changing this line make sure the newly
+ * selected device node is enabled and the
+ * previously selected device node is disabled.
+ */
+ output-high; /* Select SD by default */
+ line-name = "SelUARTorSD";
+ };
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@600000 {
+ label = "root";
+ reg = <0x0600000 0x1FA00000>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02
+ *
+ * Copyright (C) 2015 Christoph Junghans <ottxor@gentoo.org>
+ *
+ * based on information of dts files from
+ * Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com>
+ * OpenWrt by Felix Kaechele <heffer@fedoraproject.org>
+ *
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Cloud Engines Pogoplug E02";
+ compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281",
+ "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ health {
+ label = "pogo_e02:green:health";
+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+ fault {
+ label = "pogo_e02:orange:fault";
+ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power_enable>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
+ &pmx_led_green >;
+ pinctrl-names = "default";
+
+ pmx_usb_power_enable: pmx-usb-power-enable {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_green: pmx-led-green {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ pmx_led_orange: pmx-led-orange {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&nand {
+ chip-delay = <40>;
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "pogoplug";
+ reg = <0x0500000 0x2000000>;
+ };
+
+ partition@2500000 {
+ label = "root";
+ reg = <0x02500000 0x5b00000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ */
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+
+ pmx_usb_power_enable: pmx-usb-power-enable {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+ pmx_led_red: pmx-led-red {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ pmx_led_blue: pmx-led-blue {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+ pmx_sdio_cd: pmx-sdio-cd {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+ pmx_sdio_wp: pmx-sdio-wp {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+ };
+ serial@12000 {
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_usb_power_enable>;
+ pinctrl-names = "default";
+
+ usb_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "USB Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 29 0>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "uImage";
+ reg = <0x0100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "root";
+ reg = <0x0500000 0x1fb00000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+ model = "Globalscale Technologies SheevaPlug";
+ compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ ocp@f1000000 {
+ mvsdio@90000 {
+ pinctrl-0 = <&pmx_sdio>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ broken-cd;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
+ pinctrl-names = "default";
+
+ health {
+ label = "sheevaplug:blue:health";
+ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ };
+
+ misc {
+ label = "sheevaplug:red:misc";
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nodes for Marvell 628x Synology devices
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ */
+
+/ {
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pmx_alarmled_12: pmx-alarmled-12 {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanctrl_15: pmx-fanctrl-15 {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanctrl_16: pmx-fanctrl-16 {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanctrl_17: pmx-fanctrl-17 {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanalarm_18: pmx-fanalarm-18 {
+ marvell,pins = "mpp18";
+ marvell,function = "gpo";
+ };
+
+ pmx_hddled_20: pmx-hddled-20 {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_21: pmx-hddled-21 {
+ marvell,pins = "mpp21";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_22: pmx-hddled-22 {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_23: pmx-hddled-23 {
+ marvell,pins = "mpp23";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_24: pmx-hddled-24 {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_25: pmx-hddled-25 {
+ marvell,pins = "mpp25";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_26: pmx-hddled-26 {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_27: pmx-hddled-27 {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_28: pmx-hddled-28 {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
+ marvell,pins = "mpp30";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanctrl_32: pmx-fanctrl-32 {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanctrl_33: pmx-fanctrl-33 {
+ marvell,pins = "mpp33";
+ marvell,function = "gpo";
+ };
+
+ pmx_fanctrl_34: pmx-fanctrl-34 {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanalarm_35: pmx-fanalarm-35 {
+ marvell,pins = "mpp35";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_36: pmx-hddled-36 {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_37: pmx-hddled-37 {
+ marvell,pins = "mpp37";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_38: pmx-hddled-38 {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_39: pmx-hddled-39 {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_40: pmx-hddled-40 {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_41: pmx-hddled-41 {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_42: pmx-hddled-42 {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_43: pmx-hddled-43 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_44: pmx-hddled-44 {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ pmx_hddled_45: pmx-hddled-45 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanalarm_44: pmx-fanalarm-44 {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+
+ pmx_fanalarm_45: pmx-fanalarm-45 {
+ marvell,pins = "mpp45";
+ marvell,function = "gpio";
+ };
+ };
+
+ rtc@10300 {
+ status = "disabled";
+ };
+
+ spi@10600 {
+ status = "okay";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ mode = <0>;
+
+ partition@0 {
+ reg = <0x00000000 0x00080000>;
+ label = "RedBoot";
+ };
+
+ partition@80000 {
+ reg = <0x00080000 0x00200000>;
+ label = "zImage";
+ };
+
+ partition@280000 {
+ reg = <0x00280000 0x00140000>;
+ label = "rd.gz";
+ };
+
+ partition@3c0000 {
+ reg = <0x003c0000 0x00010000>;
+ label = "vendor";
+ };
+
+ partition@3d0000 {
+ reg = <0x003d0000 0x00020000>;
+ label = "RedBoot config";
+ };
+
+ partition@3f0000 {
+ reg = <0x003f0000 0x00010000>;
+ label = "FIS directory";
+ };
+ };
+ };
+
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rs5c372: rs5c372@32 {
+ status = "disabled";
+ compatible = "ricoh,rs5c372";
+ reg = <0x32>;
+ };
+
+ s35390a: s35390a@30 {
+ status = "disabled";
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ serial@12100 {
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "synology,power-off";
+ reg = <0x12100 0x100>;
+ clocks = <&gate_clk 7>;
+ };
+
+ sata@80000 {
+ pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+ pinctrl-names = "default";
+ status = "okay";
+ nr-ports = <2>;
+ };
+ };
+
+ gpio-fan-150-32-35 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
+ &pmx_fanalarm_35>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
+ &gpio1 1 GPIO_ACTIVE_HIGH
+ &gpio1 2 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2200 1
+ 2500 2
+ 3000 4
+ 3300 3
+ 3700 5
+ 3800 6
+ 4200 7 >;
+ };
+
+ gpio-fan-150-15-18 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+ &pmx_fanalarm_18>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+ &gpio0 16 GPIO_ACTIVE_HIGH
+ &gpio0 17 GPIO_ACTIVE_HIGH>;
+ alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2200 1
+ 2500 2
+ 3000 4
+ 3300 3
+ 3700 5
+ 3800 6
+ 4200 7 >;
+ };
+
+ gpio-fan-100-32-35 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
+ &pmx_fanalarm_35>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
+ &gpio1 1 GPIO_ACTIVE_HIGH
+ &gpio1 2 GPIO_ACTIVE_HIGH>;
+ alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2500 1
+ 3100 2
+ 3800 3
+ 4600 4
+ 4800 5
+ 4900 6
+ 5000 7 >;
+ };
+
+ gpio-fan-100-15-18 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+ &pmx_fanalarm_18>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+ &gpio0 16 GPIO_ACTIVE_HIGH
+ &gpio0 17 GPIO_ACTIVE_HIGH>;
+ alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2500 1
+ 3100 2
+ 3800 3
+ 4600 4
+ 4800 5
+ 4900 6
+ 5000 7 >;
+ };
+
+ gpio-fan-100-15-35-1 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+ &pmx_fanalarm_35>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+ &gpio0 16 GPIO_ACTIVE_HIGH
+ &gpio0 17 GPIO_ACTIVE_HIGH>;
+ alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2500 1
+ 3100 2
+ 3800 3
+ 4600 4
+ 4800 5
+ 4900 6
+ 5000 7 >;
+ };
+
+ gpio-fan-100-15-35-3 {
+ status = "disabled";
+ compatible = "gpio-fan";
+ pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+ &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>;
+ pinctrl-names = "default";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+ &gpio0 16 GPIO_ACTIVE_HIGH
+ &gpio0 17 GPIO_ACTIVE_HIGH>;
+ alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
+ &gpio1 12 GPIO_ACTIVE_HIGH
+ &gpio1 13 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 2500 1
+ 3100 2
+ 3800 3
+ 4600 4
+ 4800 5
+ 4900 6
+ 5000 7 >;
+ };
+
+ gpio-leds-alarm-12 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_alarmled_12>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:alarm";
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds-hdd-20 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22
+ &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25
+ &pmx_hddled_26 &pmx_hddled_27>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:green:hdd1";
+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd1-amber {
+ label = "synology:amber:hdd1";
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-green {
+ label = "synology:green:hdd2";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-amber {
+ label = "synology:amber:hdd2";
+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd3-green {
+ label = "synology:green:hdd3";
+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd3-amber {
+ label = "synology:amber:hdd3";
+ gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd4-green {
+ label = "synology:green:hdd4";
+ gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd4-amber {
+ label = "synology:amber:hdd4";
+ gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds-hdd-21-1 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:green:hdd1";
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd1-amber {
+ label = "synology:amber:hdd1";
+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds-hdd-21-2 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:green:hdd1";
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd1-amber {
+ label = "synology:amber:hdd1";
+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-green {
+ label = "synology:green:hdd2";
+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-amber {
+ label = "synology:amber:hdd2";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds-hdd-36 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38
+ &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41
+ &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44
+ &pmx_hddled_45>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:green:hdd1";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd1-amber {
+ label = "synology:amber:hdd1";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-green {
+ label = "synology:green:hdd2";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-amber {
+ label = "synology:amber:hdd2";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd3-green {
+ label = "synology:green:hdd3";
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd3-amber {
+ label = "synology:amber:hdd3";
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd4-green {
+ label = "synology:green:hdd4";
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd4-amber {
+ label = "synology:amber:hdd4";
+ gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd5-green {
+ label = "synology:green:hdd5";
+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd5-amber {
+ label = "synology:amber:hdd5";
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds-hdd-38 {
+ status = "disabled";
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
+ pinctrl-names = "default";
+
+ hdd1-green {
+ label = "synology:green:hdd1";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd1-amber {
+ label = "synology:amber:hdd1";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-green {
+ label = "synology:green:hdd2";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ };
+
+ hdd2-amber {
+ label = "synology:amber:hdd2";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ regulators-hdd-29 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd1power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "hdd2power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators-hdd-30-1 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd1_pwr_30>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd1power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators-hdd-30-2 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd1power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "hdd2power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators-hdd-30-4 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
+ &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd1power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "hdd2power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "hdd3power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "hdd4power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators-hdd-31 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd2_pwr_31>;
+ pinctrl-names = "default";
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "hdd2power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators-hdd-34 {
+ status = "disabled";
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
+ &pmx_hdd4_pwr_45>;
+ pinctrl-names = "default";
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "hdd2power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "hdd3power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "hdd4power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ startup-delay-us = <5000000>;
+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ device_type = "ethernet-phy";
+ reg = <8>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ reg = <9>;
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
+
+ð1 {
+ status = "disabled";
+
+ ethernet1-port@0 {
+ phy-handle = <ðphy1>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/include/ "skeleton.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+ compatible = "marvell,kirkwood";
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "marvell,feroceon";
+ reg = <0>;
+ clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+ clock-names = "cpu_clk", "ddrclk", "powersave";
+ };
+ };
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ i2c0 = &i2c0;
+ };
+
+ mbus@f1000000 {
+ compatible = "marvell,kirkwood-mbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* If a board file needs to change this ranges it must replace it completely */
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
+ MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
+ MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
+ >;
+ controller = <&mbusc>;
+ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
+ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
+
+ nand: nand@12f {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cle = <0>;
+ ale = <1>;
+ bank-width = <1>;
+ compatible = "marvell,orion-nand";
+ reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
+ chip-delay = <25>;
+ /* set partition map and/or chip-delay in board dts */
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ crypto_sram: sa-sram@301 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
+ clocks = <&gate_clk 17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ ocp@f1000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf1000000 0x0100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pinctrl: pin-controller@10000 {
+ /* set compatible property in SoC file */
+ reg = <0x10000 0x20>;
+
+ pmx_ge1: pmx-ge1 {
+ marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
+ "mpp24", "mpp25", "mpp26", "mpp27",
+ "mpp30", "mpp31", "mpp32", "mpp33";
+ marvell,function = "ge1";
+ };
+
+ pmx_nand: pmx-nand {
+ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+ "mpp4", "mpp5", "mpp18", "mpp19";
+ marvell,function = "nand";
+ };
+
+ /*
+ * Default SPI0 pinctrl setting with CSn on mpp0,
+ * overwrite marvell,pins on board level if required.
+ */
+ pmx_spi: pmx-spi {
+ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+ marvell,function = "spi";
+ };
+
+ pmx_twsi0: pmx-twsi0 {
+ marvell,pins = "mpp8", "mpp9";
+ marvell,function = "twsi0";
+ };
+
+ /*
+ * Default UART pinctrl setting without RTS/CTS,
+ * overwrite marvell,pins on board level if required.
+ */
+ pmx_uart0: pmx-uart0 {
+ marvell,pins = "mpp10", "mpp11";
+ marvell,function = "uart0";
+ };
+
+ pmx_uart1: pmx-uart1 {
+ marvell,pins = "mpp13", "mpp14";
+ marvell,function = "uart1";
+ };
+ };
+
+ core_clk: core-clocks@10030 {
+ compatible = "marvell,kirkwood-core-clock";
+ reg = <0x10030 0x4>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@10600 {
+ compatible = "marvell,orion-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <23>;
+ reg = <0x10600 0x28>;
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_spi>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ gpio0: gpio@10100 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x10100 0x40>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <35>, <36>, <37>, <38>;
+ clocks = <&gate_clk 7>;
+ };
+
+ gpio1: gpio@10140 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x10140 0x40>;
+ ngpios = <18>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <39>, <40>, <41>;
+ clocks = <&gate_clk 7>;
+ };
+
+ i2c0: i2c@11000 {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <29>;
+ clock-frequency = <100000>;
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_twsi0>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart0: serial@12000 {
+ compatible = "ns16550a";
+ reg = <0x12000 0x100>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_uart0>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart1: serial@12100 {
+ compatible = "ns16550a";
+ reg = <0x12100 0x100>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ clocks = <&gate_clk 7>;
+ pinctrl-0 = <&pmx_uart1>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x80>, <0x1500 0x20>;
+ };
+
+ sysc: system-controller@20000 {
+ compatible = "marvell,orion-system-controller";
+ reg = <0x20000 0x120>;
+ };
+
+ bridge_intc: bridge-interrupt-ctrl@20110 {
+ compatible = "marvell,orion-bridge-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x20110 0x8>;
+ interrupts = <1>;
+ marvell,#interrupts = <6>;
+ };
+
+ gate_clk: clock-gating-control@2011c {
+ compatible = "marvell,kirkwood-gating-clock";
+ reg = <0x2011c 0x4>;
+ clocks = <&core_clk 0>;
+ #clock-cells = <1>;
+ };
+
+ l2: l2-cache@20128 {
+ compatible = "marvell,kirkwood-cache";
+ reg = <0x20128 0x4>;
+ };
+
+ intc: main-interrupt-ctrl@20200 {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x10>, <0x20210 0x10>;
+ };
+
+ timer: timer@20300 {
+ compatible = "marvell,orion-timer";
+ reg = <0x20300 0x20>;
+ interrupt-parent = <&bridge_intc>;
+ interrupts = <1>, <2>;
+ clocks = <&core_clk 0>;
+ };
+
+ wdt: watchdog-timer@20300 {
+ compatible = "marvell,orion-wdt";
+ reg = <0x20300 0x28>, <0x20108 0x4>;
+ interrupt-parent = <&bridge_intc>;
+ interrupts = <3>;
+ clocks = <&gate_clk 7>;
+ status = "okay";
+ };
+
+ cesa: crypto@30000 {
+ compatible = "marvell,kirkwood-crypto";
+ reg = <0x30000 0x10000>;
+ reg-names = "regs";
+ interrupts = <22>;
+ clocks = <&gate_clk 17>;
+ marvell,crypto-srams = <&crypto_sram>;
+ marvell,crypto-sram-size = <0x800>;
+ status = "okay";
+ };
+
+ usb0: ehci@50000 {
+ compatible = "marvell,orion-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <19>;
+ clocks = <&gate_clk 3>;
+ status = "okay";
+ };
+
+ dma0: xor@60800 {
+ compatible = "marvell,orion-xor";
+ reg = <0x60800 0x100
+ 0x60A00 0x100>;
+ status = "okay";
+ clocks = <&gate_clk 8>;
+
+ xor00 {
+ interrupts = <5>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <6>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ dma1: xor@60900 {
+ compatible = "marvell,orion-xor";
+ reg = <0x60900 0x100
+ 0x60B00 0x100>;
+ status = "okay";
+ clocks = <&gate_clk 16>;
+
+ xor00 {
+ interrupts = <7>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <8>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ eth0: ethernet-controller@72000 {
+ compatible = "marvell,kirkwood-eth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72000 0x4000>;
+ clocks = <&gate_clk 0>;
+ marvell,tx-checksum-limit = <1600>;
+ status = "disabled";
+
+ eth0port: ethernet0-port@0 {
+ compatible = "marvell,kirkwood-eth-port";
+ reg = <0>;
+ interrupts = <11>;
+ /* overwrite MAC address in bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ /* set phy-handle property in board file */
+ };
+ };
+
+ mdio: mdio-bus@72004 {
+ compatible = "marvell,orion-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72004 0x84>;
+ interrupts = <46>;
+ clocks = <&gate_clk 0>;
+ status = "disabled";
+
+ /* add phy nodes in board file */
+ };
+
+ eth1: ethernet-controller@76000 {
+ compatible = "marvell,kirkwood-eth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x76000 0x4000>;
+ clocks = <&gate_clk 19>;
+ marvell,tx-checksum-limit = <1600>;
+ pinctrl-0 = <&pmx_ge1>;
+ pinctrl-names = "default";
+ status = "disabled";
+
+ eth1port: ethernet1-port@0 {
+ compatible = "marvell,kirkwood-eth-port";
+ reg = <0>;
+ interrupts = <15>;
+ /* overwrite MAC address in bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ /* set phy-handle property in board file */
+ };
+ };
+
+ sata_phy0: sata-phy@82000 {
+ compatible = "marvell,mvebu-sata-phy";
+ reg = <0x82000 0x0334>;
+ clocks = <&gate_clk 14>;
+ clock-names = "sata";
+ #phy-cells = <0>;
+ status = "ok";
+ };
+
+ sata_phy1: sata-phy@84000 {
+ compatible = "marvell,mvebu-sata-phy";
+ reg = <0x84000 0x0334>;
+ clocks = <&gate_clk 15>;
+ clock-names = "sata";
+ #phy-cells = <0>;
+ status = "ok";
+ };
+
+ audio0: audio-controller@a0000 {
+ compatible = "marvell,kirkwood-audio";
+ #sound-dai-cells = <0>;
+ reg = <0xa0000 0x2210>;
+ interrupts = <24>;
+ clocks = <&gate_clk 9>;
+ clock-names = "internal";
+ status = "disabled";
+ };
+ };
+};
#include "r8a7792-blanche.dts"
#include "r8a7792-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
uart1: serial1@ffc03000 {
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
rst: rstmgr@ffd05000 {
/*
- * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/altr,rst-mgr-a10.h>
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- spi0 = &spi0;
- spi1 = &spi1;
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-a10-smp";
cpu@0 {
compatible = "arm,cortex-a9";
};
};
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
- reg-names = "soc_clock_manager_OCP_SLV";
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- cb_intosc_ls_clk: cb_intosc_ls_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
- f2s_free_clk: f2s_free_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
- osc1: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
- main_pll: main_pll {
+ clocks {
#address-cells = <1>;
#size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>;
- reg = <0x40>;
- main_mpu_base_clk: main_mpu_base_clk {
+ cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x140 0 11>;
+ compatible = "fixed-clock";
};
- main_noc_base_clk: main_noc_base_clk {
+ cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- div-reg = <0x144 0 11>;
+ compatible = "fixed-clock";
};
- main_emaca_clk: main_emaca_clk {
+ f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x68>;
+ compatible = "fixed-clock";
};
- main_emacb_clk: main_emacb_clk {
+ osc1: osc1 {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x6C>;
+ compatible = "fixed-clock";
};
- main_emac_ptp_clk: main_emac_ptp_clk {
+ main_pll: main_pll@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x70>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>;
+ reg = <0x40>;
+
+ main_mpu_base_clk: main_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x140 0 11>;
+ };
+
+ main_noc_base_clk: main_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0x144 0 11>;
+ };
+
+ main_emaca_clk: main_emaca_clk@68 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x68>;
+ };
+
+ main_emacb_clk: main_emacb_clk@6c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x6C>;
+ };
+
+ main_emac_ptp_clk: main_emac_ptp_clk@70 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x70>;
+ };
+
+ main_gpio_db_clk: main_gpio_db_clk@74 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x74>;
+ };
+
+ main_sdmmc_clk: main_sdmmc_clk@78 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk"
+;
+ clocks = <&main_pll>;
+ reg = <0x78>;
+ };
+
+ main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x7C>;
+ };
+
+ main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x80>;
+ };
+
+ main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x84>;
+ };
+
+ main_periph_ref_clk: main_periph_ref_clk@9c {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x9C>;
+ };
};
- main_gpio_db_clk: main_gpio_db_clk {
+ periph_pll: periph_pll@c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x74>;
+ compatible = "altr,socfpga-a10-pll-clock";
+ clocks = <&osc1>, <&cb_intosc_ls_clk>,
+ <&f2s_free_clk>, <&main_periph_ref_clk>;
+ reg = <0xC0>;
+
+ peri_mpu_base_clk: peri_mpu_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x140 16 11>;
+ };
+
+ peri_noc_base_clk: peri_noc_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ div-reg = <0x144 16 11>;
+ };
+
+ peri_emaca_clk: peri_emaca_clk@e8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xE8>;
+ };
+
+ peri_emacb_clk: peri_emacb_clk@ec {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xEC>;
+ };
+
+ peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF0>;
+ };
+
+ peri_gpio_db_clk: peri_gpio_db_clk@f4 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF4>;
+ };
+
+ peri_sdmmc_clk: peri_sdmmc_clk@f8 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xF8>;
+ };
+
+ peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0xFC>;
+ };
+
+ peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x100>;
+ };
+
+ peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x104>;
+ };
};
- main_sdmmc_clk: main_sdmmc_clk {
+ mpu_free_clk: mpu_free_clk@60 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x78>;
+ clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x60>;
};
- main_s2f_usr0_clk: main_s2f_usr0_clk {
+ noc_free_clk: noc_free_clk@64 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x7C>;
+ clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x64>;
};
- main_s2f_usr1_clk: main_s2f_usr1_clk {
+ s2f_user1_free_clk: s2f_user1_free_clk@104 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x80>;
+ clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ reg = <0x104>;
};
- main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
+ sdmmc_free_clk: sdmmc_free_clk@f8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x84>;
+ clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
+ <&osc1>, <&cb_intosc_hs_div2_clk>,
+ <&f2s_free_clk>;
+ fixed-divider = <4>;
+ reg = <0xF8>;
};
- main_periph_ref_clk: main_periph_ref_clk {
+ l4_sys_free_clk: l4_sys_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_pll>;
- reg = <0x9C>;
+ clocks = <&noc_free_clk>;
+ fixed-divider = <4>;
};
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-pll-clock";
- clocks = <&osc1>, <&cb_intosc_ls_clk>,
- <&f2s_free_clk>, <&main_periph_ref_clk>;
- reg = <0xC0>;
- peri_mpu_base_clk: peri_mpu_base_clk {
+ l4_main_clk: l4_main_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x140 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 0 2>;
+ clk-gate = <0x48 1>;
};
- peri_noc_base_clk: peri_noc_base_clk {
+ l4_mp_clk: l4_mp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- div-reg = <0x144 16 11>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 8 2>;
+ clk-gate = <0x48 2>;
};
- peri_emaca_clk: peri_emaca_clk {
+ l4_sp_clk: l4_sp_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xE8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&noc_free_clk>;
+ div-reg = <0xA8 16 2>;
+ clk-gate = <0x48 3>;
};
- peri_emacb_clk: peri_emacb_clk {
+ mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xEC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&mpu_free_clk>;
+ fixed-divider = <4>;
+ clk-gate = <0x48 0>;
};
- peri_emac_ptp_clk: peri_emac_ptp_clk {
+ sdmmc_clk: sdmmc_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&sdmmc_free_clk>;
+ clk-gate = <0xC8 5>;
+ clk-phase = <0 135>;
};
- peri_gpio_db_clk: peri_gpio_db_clk {
+ qspi_clk: qspi_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF4>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 11>;
};
- peri_sdmmc_clk: peri_sdmmc_clk {
+ nand_clk: nand_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xF8>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 10>;
};
- peri_s2f_usr0_clk: peri_s2f_usr0_clk {
+ spi_m_clk: spi_m_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0xFC>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_main_clk>;
+ clk-gate = <0xC8 9>;
};
- peri_s2f_usr1_clk: peri_s2f_usr1_clk {
+ usb_clk: usb_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x100>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&l4_mp_clk>;
+ clk-gate = <0xC8 8>;
};
- peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
+ s2f_usr1_clk: s2f_usr1_clk {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x104>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&peri_s2f_usr1_clk>;
+ clk-gate = <0xC8 6>;
};
};
+ };
- mpu_free_clk: mpu_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x60>;
- };
-
- noc_free_clk: noc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x64>;
- };
-
- s2f_user1_free_clk: s2f_user1_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- reg = <0x104>;
- };
-
- sdmmc_free_clk: sdmmc_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
- <&osc1>, <&cb_intosc_hs_div2_clk>,
- <&f2s_free_clk>;
- fixed-divider = <4>;
- reg = <0xF8>;
- };
-
- l4_sys_free_clk: l4_sys_free_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk";
- clocks = <&noc_free_clk>;
- fixed-divider = <4>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 0 2>;
- clk-gate = <0x48 1>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 8 2>;
- clk-gate = <0x48 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&noc_free_clk>;
- div-reg = <0xA8 16 2>;
- clk-gate = <0x48 3>;
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&mpu_free_clk>;
- fixed-divider = <4>;
- clk-gate = <0x48 0>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&sdmmc_free_clk>;
- clk-gate = <0xC8 5>;
- clk-phase = <0 135>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 11>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 10>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_main_clk>;
- clk-gate = <0xC8 9>;
- };
-
- usb_clk: usb_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&l4_mp_clk>;
- clk-gate = <0xC8 8>;
- };
-
- s2f_usr1_clk: s2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-a10-gate-clk";
- clocks = <&peri_s2f_usr1_clk>;
- clk-gate = <0xC8 6>;
- };
- };
+ socfpga_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 0 0>;
};
gmac0: ethernet@ff800000 {
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
status = "disabled";
};
- sdr: sdr@0xffcfb100 {
- compatible = "syscon";
- reg = <0xffcfb100 0x80>;
- };
-
- spi0: spi@ffda4000 {
+ spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0xffda4000 0x100>;
- interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xffda5000 0x100>;
+ interrupts = <0 102 4>;
num-chipselect = <4>;
bus-num = <0>;
+ /*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
clocks = <&spi_m_clk>;
status = "disabled";
};
- spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xffda5000 0x100>;
- interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
- num-chipselect = <4>;
- bus-num = <0>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&spi_m_clk>;
- status = "disabled";
+ sdr: sdr@ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffcfb100 0x80>;
};
L2: l2-cache@fffff000 {
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
};
mmc: dwmmc0@ff808000 {
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
- bus-width = <4>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu";
status = "disabled";
};
+ nand: nand@ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 99 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ status = "disabled";
+ };
+
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
};
- eccmgr: eccmgr@ffd06000 {
+ eccmgr: eccmgr {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
<33 IRQ_TYPE_LEVEL_HIGH>;
};
- sdmmca-ecc@ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
};
};
- qspi: qspi@ff809000 {
+ qspi: spi@ff809000 {
+ compatible = "cdns,qspi-nor", "cadence,qspi";
#address-cells = <1>;
#size-cells = <0>;
- compatible = "cadence,qspi";
reg = <0xff809000 0x100>,
- <0xffa00000 0x100000>;
+ <0xffa00000 0x100000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&l4_main_clk>;
- ext-decoder = <0>; /* external decoder */
- num-chipselect = <4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
- bus-num = <2>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
status = "disabled";
};
- usbphy0: usbphy@0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
--- /dev/null
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Arria 10";
+ compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ a10leds {
+ compatible = "gpio-leds";
+
+ a10sr_led0 {
+ label = "a10sr-led0";
+ gpios = <&a10sr_gpio 0 1>;
+ };
+
+ a10sr_led1 {
+ label = "a10sr-led1";
+ gpios = <&a10sr_gpio 1 1>;
+ };
+
+ a10sr_led2 {
+ label = "a10sr-led2";
+ gpios = <&a10sr_gpio 2 1>;
+ };
+
+ a10sr_led3 {
+ label = "a10sr-led3";
+ gpios = <&a10sr_gpio 3 1>;
+ };
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+
+ /*
+ * These skews assume the user's FPGA design is adding 600ps of delay
+ * for TX_CLK on Arria 10.
+ *
+ * All skews are offset since hardware skew values for the ksz9031
+ * range from a negative skew to a positive skew.
+ * See the micrel-ksz90x1.txt Documentation file for details.
+ */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ resource-manager@0 {
+ compatible = "altr,a10sr";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ /* low-level active IRQ at GPIO1_5 */
+ interrupt-parent = <&portb>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ a10sr_gpio: gpio-controller {
+ compatible = "altr,a10sr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ a10sr_rst: reset-controller {
+ compatible = "altr,a10sr-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ clock-frequency = <100000>;
+ i2c-sda-falling-time-ns = <6000>;
+ i2c-scl-falling-time-ns = <6000>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+
+ ltc@5c {
+ compatible = "ltc2977";
+ reg = <0x5c>;
+ };
+};
+
+&uart1 {
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog1 {
+ status = "okay";
+};
/*
- * Copyright (C) 2015-2017 Altera Corporation. All rights reserved.
+ * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200";
- };
-};
-
-&uart1 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
+#include "socfpga_arria10_socdk.dtsi"
&mmc {
u-boot,dm-pre-reloc;
broken-cd;
bus-width = <4>;
};
+
+&eccmgr {
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
#include "socfpga_arria10.dtsi"
/ {
- model = "Altera SOCFPGA Arria 10";
- compatible = "altr,socfpga-arria10", "altr,socfpga";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
- /* Bootloader setting: uboot.rbf_filename */
- cff-file = "ghrd_10as066n2.periph.rbf";
- early-release-fpga-config;
+ cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */
};
- soc {
+ /* Clock sources */
+ clocks {
u-boot,dm-pre-reloc;
- clkmgr@ffd04000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Clock source: altera_arria10_hps_eosc1 */
+ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "altera_arria10_hps_eosc1-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_cb_intosc_ls */
+ altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
+ };
+
+ /* Clock source: altera_arria10_hps_f2h_free */
+ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "altera_arria10_hps_f2h_free-clk";
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_clk_mgr: clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-clk-init";
+ reg = <0xffd04000 0x00000200>;
+ reg-names = "soc_clock_manager_OCP_SLV";
+
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
+ mainpll {
u-boot,dm-pre-reloc;
- clocks {
- u-boot,dm-pre-reloc;
- osc1 {
- u-boot,dm-pre-reloc;
- clock-frequency = <25000000>;
- clock-output-names = "altera_arria10_hps_eosc1-clk";
- };
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <191>; /* Field: vco1.numer */
+ mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
+ mpuclk-src = <0>; /* Field: mpuclk.src */
+ nocclk-cnt = <0>; /* Field: nocclk.cnt */
+ nocclk-src = <0>; /* Field: nocclk.src */
+ cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
+ cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
+ cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr7clk-src = <0>; /* Field: cntr7clk.src */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ cntr9clk-src = <0>; /* Field: cntr9clk.src */
+ cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
+ nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
+ nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
+ nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
+ nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
+ nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
+ nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
+ };
- cb_intosc_ls_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <60000000>;
- clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
+ perpll {
+ u-boot,dm-pre-reloc;
+ vco0-psrc = <0>; /* Field: vco0.psrc */
+ vco1-denom = <1>; /* Field: vco1.denom */
+ vco1-numer = <159>; /* Field: vco1.numer */
+ cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
+ cntr2clk-src = <1>; /* Field: cntr2clk.src */
+ cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
+ cntr3clk-src = <1>; /* Field: cntr3clk.src */
+ cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
+ cntr4clk-src = <1>; /* Field: cntr4clk.src */
+ cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
+ cntr5clk-src = <1>; /* Field: cntr5clk.src */
+ cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
+ cntr6clk-src = <1>; /* Field: cntr6clk.src */
+ cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
+ cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
+ cntr8clk-src = <0>; /* Field: cntr8clk.src */
+ cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
+ emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
+ emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
+ emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
+ gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
+ };
- f2s_free_clk {
- u-boot,dm-pre-reloc;
- clock-frequency = <200000000>;
- clock-output-names = "altera_arria10_hps_f2h_free-clk";
- };
+ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ nocclk = <0x0384000b>; /* Register: nocclk */
+ mpuclk = <0x03840001>; /* Register: mpuclk */
+ };
+ };
- main_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_mainpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 191 /* Field: vco1.numer */
- 0 /* Field: mpuclk */
- 0 /* Field: mpuclk.cnt */
- 0 /* Field: mpuclk.src */
- 0 /* Field: nocclk */
- 0 /* Field: nocclk.cnt */
- 0 /* Field: nocclk.src */
- 900 /* Field: cntr2clk.cnt */
- 900 /* Field: cntr3clk.cnt */
- 900 /* Field: cntr4clk.cnt */
- 900 /* Field: cntr5clk.cnt */
- 900 /* Field: cntr6clk.cnt */
- 900 /* Field: cntr7clk.cnt */
- 0 /* Field: cntr7clk.src */
- 900 /* Field: cntr8clk.cnt */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: cntr9clk.src */
- 900 /* Field: cntr15clk.cnt */
- 0 /* Field: nocdiv.l4mainclk */
- 0 /* Field: nocdiv.l4mpclk */
- 2 /* Field: nocdiv.l4spclk */
- 0 /* Field: nocdiv.csatclk */
- 1 /* Field: nocdiv.cstraceclk */
- 1 /* Field: nocdiv.cspdbgclk */
- >;
- };
+ /*
+ * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: pinmux
+ */
+ i_io48_pin_mux: pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "pinctrl-single";
+ reg = <0xffd07000 0x00000800>;
+ reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
- periph_pll {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_perpllgrp
- */
- altr,of_reg_value = <
- 0 /* Field: vco0.psrc */
- 1 /* Field: vco1.denom */
- 159 /* Field: vco1.numer */
- 7 /* Field: cntr2clk.cnt */
- 1 /* Field: cntr2clk.src */
- 900 /* Field: cntr3clk.cnt */
- 1 /* Field: cntr3clk.src */
- 19 /* Field: cntr4clk.cnt */
- 1 /* Field: cntr4clk.src */
- 499 /* Field: cntr5clk.cnt */
- 1 /* Field: cntr5clk.src */
- 9 /* Field: cntr6clk.cnt */
- 1 /* Field: cntr6clk.src */
- 900 /* Field: cntr7clk.cnt */
- 900 /* Field: cntr8clk.cnt */
- 0 /* Field: cntr8clk.src */
- 900 /* Field: cntr9clk.cnt */
- 0 /* Field: emacctl.emac0sel */
- 0 /* Field: emacctl.emac1sel */
- 0 /* Field: emacctl.emac2sel */
- 32000 /* Field: gpiodiv.gpiodbclk */
- >;
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
+ shared {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07000 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
+ <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
+ <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
+ <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
+ <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
+ <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
+ <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
+ <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
+ <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
+ <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
+ <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
+ <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
+ <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
+ <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
+ <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
+ <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
+ <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
+ <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
+ <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
+ <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
+ <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
+ <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
+ <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
+ <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
+ <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
+ <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
+ <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
+ <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
+ <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
+ <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
+ <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
+ <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
+ <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
+ <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
+ <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
+ <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
+ <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
+ <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
+ <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
+ <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
+ <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
+ <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
+ };
+
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ pinctrl-single,pins =
+ <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
+ <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
+ <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
+ <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
+ <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
+ <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
+ <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
+ <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
+ <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
+ <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
+ <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
+ <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
+ <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
+ <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
+ };
- altera {
- u-boot,dm-pre-reloc;
- /*
- * Address Block: soc_clock_manager_OCP_SLV.
- * i_clk_mgr_alteragrp
- */
- altr,of_reg_value = <
- 0x0384000b /* Register: nocclk */
- 0x03840001 /* Register: mpuclk */
- >;
- };
- };
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ reg = <0xffd07200 0x00000200>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x003f3f3f>;
+ pinctrl-single,pins =
+ <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
+ <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
+ <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
+ <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
+ <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
+ <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
+ <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
+ <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
+ <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
+ <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
+ <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
+ <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
+ <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
+ <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
+ <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
+ <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
+ <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
+ <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
};
- /*
- * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
- * Binding: pinmux
- */
- i_io48_pin_mux: pinmux@0xffd07000 {
+ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
+ fpga {
u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "pinctrl-single";
- reg = <0xffd07000 0x00000800>;
- reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
+ reg = <0xffd07400 0x00000100>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000001>;
+ pinctrl-single,pins =
+ <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
+ <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
+ <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
+ <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
+ <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
+ <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
+ <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
+ <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
+ <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
+ <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
+ <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
+ <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
+ <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
+ <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
+ <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
+ <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
+ <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
+ };
+ };
+
+ /*
+ * Driver: altera_arria10_soc_noc_arria10_uboot_driver
+ * Version: 1.0
+ * Binding: device
+ */
+ i_noc: noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+ compatible = "altr,socfpga-a10-noc";
+ reg = <0xffd10000 0x00008000>;
+ reg-names = "mpu_m0";
+ firewall {
+ u-boot,dm-pre-reloc;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_shared_3v_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
*/
- shared {
- u-boot,dm-pre-reloc;
- reg = <0xffd07000 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_shared_io_q1_1 */
- <0x00000000 0x00000008>,
- /* Reg: pinmux_shared_io_q1_2 */
- <0x00000004 0x00000008>,
- /* Reg: pinmux_shared_io_q1_3 */
- <0x00000008 0x00000008>,
- /* Reg: pinmux_shared_io_q1_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_shared_io_q1_6 */
- <0x00000014 0x00000008>,
- /* Reg: pinmux_shared_io_q1_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_shared_io_q1_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_shared_io_q1_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_shared_io_q1_10 */
- <0x00000024 0x00000008>,
- /* Reg: pinmux_shared_io_q1_11 */
- <0x00000028 0x00000008>,
- /* Reg: pinmux_shared_io_q1_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_shared_io_q2_1 */
- <0x00000030 0x00000004>,
- /* Reg: pinmux_shared_io_q2_2 */
- <0x00000034 0x00000004>,
- /* Reg: pinmux_shared_io_q2_3 */
- <0x00000038 0x00000004>,
- /* Reg: pinmux_shared_io_q2_4 */
- <0x0000003c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_5 */
- <0x00000040 0x00000004>,
- /* Reg: pinmux_shared_io_q2_6 */
- <0x00000044 0x00000004>,
- /* Reg: pinmux_shared_io_q2_7 */
- <0x00000048 0x00000004>,
- /* Reg: pinmux_shared_io_q2_8 */
- <0x0000004c 0x00000004>,
- /* Reg: pinmux_shared_io_q2_9 */
- <0x00000050 0x00000004>,
- /* Reg: pinmux_shared_io_q2_10 */
- <0x00000054 0x00000004>,
- /* Reg: pinmux_shared_io_q2_11 */
- <0x00000058 0x00000004>,
- /* Reg: pinmux_shared_io_q2_12 */
- <0x0000005c 0x00000004>,
- /* Reg: pinmux_shared_io_q3_1 */
- <0x00000060 0x00000003>,
- /* Reg: pinmux_shared_io_q3_2 */
- <0x00000064 0x00000003>,
- /* Reg: pinmux_shared_io_q3_3 */
- <0x00000068 0x00000003>,
- /* Reg: pinmux_shared_io_q3_4 */
- <0x0000006c 0x00000003>,
- /* Reg: pinmux_shared_io_q3_5 */
- <0x00000070 0x00000003>,
- /* Reg: pinmux_shared_io_q3_6 */
- <0x00000074 0x0000000f>,
- /* Reg: pinmux_shared_io_q3_7 */
- <0x00000078 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_8 */
- <0x0000007c 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_9 */
- <0x00000080 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_10 */
- <0x00000084 0x0000000a>,
- /* Reg: pinmux_shared_io_q3_11 */
- <0x00000088 0x00000001>,
- /* Reg: pinmux_shared_io_q3_12 */
- <0x0000008c 0x00000001>,
- /* Reg: pinmux_shared_io_q4_1 */
- <0x00000090 0x00000000>,
- /* Reg: pinmux_shared_io_q4_2 */
- <0x00000094 0x00000000>,
- /* Reg: pinmux_shared_io_q4_3 */
- <0x00000098 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_4 */
- <0x0000009c 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_5 */
- <0x000000a0 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_6 */
- <0x000000a4 0x0000000f>,
- /* Reg: pinmux_shared_io_q4_7 */
- <0x000000a8 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_8 */
- <0x000000ac 0x0000000a>,
- /* Reg: pinmux_shared_io_q4_9 */
- <0x000000b0 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_10 */
- <0x000000b4 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_11 */
- <0x000000b8 0x0000000c>,
- /* Reg: pinmux_shared_io_q4_12 */
- <0x000000bc 0x0000000c>;
- };
-
+ mpu0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
*/
- dedicated {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x0000000f>;
- pinctrl-single,pins =
- /* Reg: pinmux_dedicated_io_4 */
- <0x0000000c 0x00000008>,
- /* Reg: pinmux_dedicated_io_5 */
- <0x00000010 0x00000008>,
- /* Reg: pinmux_dedicated_io_6 */
- <0x00000014 0x00000008>,
- /* Regi: pinmux_dedicated_io_7 */
- <0x00000018 0x00000008>,
- /* Reg: pinmux_dedicated_io_8 */
- <0x0000001c 0x00000008>,
- /* Reg: pinmux_dedicated_io_9 */
- <0x00000020 0x00000008>,
- /* Reg: pinmux_dedicated_io_10 */
- <0x00000024 0x0000000a>,
- /* Reg: pinmux_dedicated_io_11 */
- <0x00000028 0x0000000a>,
- /* Reg: pinmux_dedicated_io_12 */
- <0x0000002c 0x00000008>,
- /* Reg: pinmux_dedicated_io_13 */
- <0x00000030 0x00000008>,
- /* Reg: pinmux_dedicated_io_14 */
- <0x00000034 0x00000008>,
- /* Reg: pinmux_dedicated_io_15 */
- <0x00000038 0x00000008>,
- /* Reg: pinmux_dedicated_io_16 */
- <0x0000003c 0x0000000d>,
- /* Reg: pinmux_dedicated_io_17 */
- <0x00000040 0x0000000d>;
- };
-
+ l3-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_dedicated_io_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
*/
- dedicated_cfg {
- u-boot,dm-pre-reloc;
- reg = <0xffd07200 0x00000200>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x003f3f3f>;
- pinctrl-single,pins =
- /* Reg: cfg_dedicated_io_bank */
- <0x00000100 0x00000101>,
- /* Reg: cfg_dedicated_io_1 */
- <0x00000104 0x000b080a>,
- /* Reg: cfg_dedicated_io_2 */
- <0x00000108 0x000b080a>,
- /* Reg: cfg_dedicated_io_3 */
- <0x0000010c 0x000b080a>,
- /* Reg: cfg_dedicated_io_4 */
- <0x00000110 0x000a282a>,
- /* Reg: cfg_dedicated_io_5 */
- <0x00000114 0x000a282a>,
- /* Reg: cfg_dedicated_io_6 */
- <0x00000118 0x0008282a>,
- /* Reg: cfg_dedicated_io_7 */
- <0x0000011c 0x000a282a>,
- /* Reg: cfg_dedicated_io_8 */
- <0x00000120 0x000a282a>,
- /* Reg: cfg_dedicated_io_9 */
- <0x00000124 0x000a282a>,
- /* Reg: cfg_dedicated_io_10 */
- <0x00000128 0x00090000>,
- /* Reg: cfg_dedicated_io_11 */
- <0x0000012c 0x00090000>,
- /* Reg: cfg_dedicated_io_12 */
- <0x00000130 0x000b282a>,
- /* Reg: cfg_dedicated_io_13 */
- <0x00000134 0x000b282a>,
- /* Reg: cfg_dedicated_io_14 */
- <0x00000138 0x000b282a>,
- /* Reg: cfg_dedicated_io_15 */
- <0x0000013c 0x000b282a>,
- /* Reg: cfg_dedicated_io_16 */
- <0x00000140 0x0008282a>,
- /* Reg: cfg_dedicated_io_17 */
- <0x00000144 0x000a282a>;
- };
-
+ fpga2sdram0-0 = <0x00000000 0x0000ffff>;
/*
- * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
- * i_io48_pin_mux_fpga_interface_grp
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
*/
- fpga {
- u-boot,dm-pre-reloc;
- reg = <0xffd07400 0x00000100>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x00000001>;
- pinctrl-single,pins =
- /* Reg: pinmux_emac0_usefpga */
- <0x00000000 0x00000000>,
- /* Reg: pinmux_emac1_usefpga */
- <0x00000004 0x00000000>,
- /* Reg: pinmux_emac2_usefpga */
- <0x00000008 0x00000000>,
- /* Reg: pinmux_i2c0_usefpga */
- <0x0000000c 0x00000000>,
- /* Reg: pinmux_i2c1_usefpga */
- <0x00000010 0x00000000>,
- /* Reg: pinmux_i2c_emac0_usefpga */
- <0x00000014 0x00000000>,
- /* Reg: pinmux_i2c_emac1_usefpga */
- <0x00000018 0x00000000>,
- /* Reg: pinmux_i2c_emac2_usefpga */
- <0x0000001c 0x00000000>,
- /* Reg: pinmux_nand_usefpga */
- <0x00000020 0x00000000>,
- /* Reg: pinmux_qspi_usefpga */
- <0x00000024 0x00000000>,
- /* Reg: pinmux_sdmmc_usefpga */
- <0x00000028 0x00000000>,
- /* Reg: pinmux_spim0_usefpga */
- <0x0000002c 0x00000000>,
- /* Reg: pinmux_spim1_usefpga */
- <0x00000030 0x00000000>,
- /* Reg: pinmux_spis0_usefpga */
- <0x00000034 0x00000000>,
- /* Reg: pinmux_spis1_usefpga */
- <0x00000038 0x00000000>,
- /* Reg: pinmux_uart0_usefpga */
- <0x0000003c 0x00000000>,
- /* Reg: pinmux_uart1_usefpga */
- <0x00000040 0x00000000>;
- };
- };
-
- i_noc: noc@0xffd10000 {
- u-boot,dm-pre-reloc;
- compatible = "altr,socfpga-a10-noc";
- reg = <0xffd10000 0x00008000>;
- reg-names = "mpu_m0";
-
- firewall {
- u-boot,dm-pre-reloc;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * mpuregion0addr.limit
- */
- altr,mpu0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
- * hpsregion0addr.limit
- */
- altr,l3-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram0region0addr.limit
- */
- altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram1region0addr.limit
- */
- altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
- /*
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.base
- * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
- * I_NOC.mpu_m0.
- * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
- * fpga2sdram2region0addr.limit
- */
- altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
- };
+ fpga2sdram1-0 = <0x00000000 0x0000ffff>;
+ /*
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
+ * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
+ */
+ fpga2sdram2-0 = <0x00000000 0x0000ffff>;
};
+ };
- hps_fpgabridge0: fpgabridge@0 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge0: fpgabridge@0 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge1: fpgabridge@1 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge1: fpgabridge@1 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge2: fpgabridge@2 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge2: fpgabridge@2 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge3: fpgabridge@3 {
- compatible = "altr,socfpga-fpga2sdram0-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge3: fpgabridge@3 {
+ compatible = "altr,socfpga-fpga2sdram0-bridge";
+ init-val = <1>;
+ };
- hps_fpgabridge4: fpgabridge@4 {
- compatible = "altr,socfpga-fpga2sdram1-bridge";
- altr,init-val = <0>;
- };
+ hps_fpgabridge4: fpgabridge@4 {
+ compatible = "altr,socfpga-fpga2sdram1-bridge";
+ init-val = <0>;
+ };
- hps_fpgabridge5: fpgabridge@5 {
- compatible = "altr,socfpga-fpga2sdram2-bridge";
- altr,init-val = <1>;
- };
+ hps_fpgabridge5: fpgabridge@5 {
+ compatible = "altr,socfpga-fpga2sdram2-bridge";
+ init-val = <1>;
};
};
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
+ u-boot,dm-pre-reloc;
clkmgr@ffd1000 {
compatible = "altr,clk-mgr";
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC0_RESET>;
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC1_RESET>;
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
- resets = <&rst EMAC2_RESET>;
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
+ bank-name = "porta";
};
};
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 111 4>;
+ bank-name = "portb";
};
};
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
+ reset-names = "i2c";
status = "disabled";
};
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
- resets = <&rst SDMMC_RESET>;
- reset-names = "reset";
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
};
spi0: spi@ffda4000 {
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
+ u-boot,dm-pre-reloc;
status = "disabled";
};
&mmc {
status = "okay";
cap-sd-highspeed;
+ cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ drvsel = <3>;
+ smplsel = <0>;
};
&uart0 {
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
+ st,syscfg = <&syscfg>;
+ st,swp_fmc = <1>;
u-boot,dm-pre-reloc;
/*
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
- cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
+ clock-names = "ether";
clocks = <&sys_clk 6>;
+ reset-names = "ether";
resets = <&sys_rst 6>;
- phy-mode = "rmii";
+ phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
mdio: mdio {
#address-cells = <1>;
reg = <0>;
};
};
+
+&pinctrl_ether_rgmii {
+ tx {
+ pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
+ "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
+ drive-strength = <9>;
+ };
+};
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
- cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clock-names = "ether";
clocks = <&sys_clk 6>;
+ reset-names = "ether";
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
mdio: mdio {
#address-cells = <1>;
has-transaction-translator;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
- clocks = <&sys_clk 6>;
- resets = <&sys_rst 6>;
+ clock-names = "gio", "ether", "ether-gb", "ether-phy";
+ clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
+ <&sys_clk 10>;
+ reset-names = "gio", "ether";
+ resets = <&sys_rst 12>, <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
mdio: mdio {
#address-cells = <1>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clock-names = "ether";
clocks = <&sys_clk 6>;
+ reset-names = "ether";
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
mdio: mdio {
#address-cells = <1>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
- cdns,phy-input-delay-legacy = <4>;
+ cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clock-names = "ether";
clocks = <&sys_clk 6>;
+ reset-names = "ether";
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
mdio0: mdio {
#address-cells = <1>;
interrupts = <0 67 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether1_rgmii>;
+ clock-names = "ether";
clocks = <&sys_clk 7>;
+ reset-names = "ether";
resets = <&sys_rst 7>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 1>;
mdio1: mdio {
#address-cells = <1>;
#include <common.h>
-#ifdef CONFIG_MX31_HCLK_FREQ
#define MXC_HCLK CONFIG_MX31_HCLK_FREQ
-#else
-#define MXC_HCLK 26000000
-#endif
-#ifdef CONFIG_MX31_CLK32
#define MXC_CLK32 CONFIG_MX31_CLK32
-#else
-#define MXC_CLK32 32768
-#endif
enum mxc_clock {
MXC_ARM_CLK,
#define ARASAN_NAND_BASEADDR 0xFF100000
-#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
-#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
-
#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
#define ZYNQMP_TCM_SIZE 0x40000
efi_print_image_infos((void *)instruction_pointer(regs));
}
+static void dump_instr(struct pt_regs *regs)
+{
+ unsigned long addr = instruction_pointer(regs);
+ const int thumb = thumb_mode(regs);
+ const int width = thumb ? 4 : 8;
+ int i;
+
+ if (thumb)
+ addr &= ~1L;
+ else
+ addr &= ~3L;
+ printf("Code: ");
+ for (i = -4; i < 1 + !!thumb; i++) {
+ unsigned int val;
+
+ if (thumb)
+ val = ((u16 *)addr)[i];
+ else
+ val = ((u32 *)addr)[i];
+ printf(i == 0 ? "(%0*x) " : "%0*x ", width, val);
+ }
+ printf("\n");
+}
+
void show_regs (struct pt_regs *regs)
{
unsigned long __maybe_unused flags;
fast_interrupts_enabled (regs) ? "on" : "off",
processor_modes[processor_mode (regs)],
thumb_mode (regs) ? " (T)" : "");
+ dump_instr(regs);
}
/* fixup PC to point to the instruction leading to the exception */
#include <asm/arch/clk.h>
#include <spl.h>
-#if defined(CONFIG_AT91SAM9_WATCHDOG)
-void at91_disable_wdt(void) { }
-#else
+#if !defined(CONFIG_AT91SAM9_WATCHDOG)
void at91_disable_wdt(void)
{
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
void board_init_f(ulong dummy)
{
lowlevel_clock_init();
+#if !defined(CONFIG_AT91SAM9_WATCHDOG)
at91_disable_wdt();
+#endif
/*
* At this stage the main oscillator is supposed to be enabled
configure_2nd_sram_as_l2_cache();
#endif
+#if !defined(CONFIG_AT91SAM9_WATCHDOG)
/* disable watchdog */
at91_disable_wdt();
+#endif
/* PMC configuration */
at91_pmc_init();
--- /dev/null
+if ARCH_MX31
+
+config MX31
+ bool
+ default y
+choice
+ prompt "MX31 board select"
+ optional
+
+config TARGET_MX31PDK
+ bool "Support the i.MX31 PDK board from Freescale/NXP"
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+ select BOARD_EARLY_INIT_F
+
+endchoice
+
+config MX31_HCLK_FREQ
+ int "i.MX31 HCLK frequency"
+ default 26000000
+ help
+ Frequency in Hz of the high frequency input clock. Typically
+ 26000000 Hz.
+
+config MX31_CLK32
+ int "i.MX31 CLK32 Frequency"
+ default 32768
+ help
+ Frequency in Hz of the low frequency input clock. Typically
+ 32768 or 32000 Hz.
+
+source "board/freescale/mx31pdk/Kconfig"
+
+endif
prompt "MX5 board select"
optional
+config TARGET_KP_IMX53
+ bool "Support K+P imx53 board"
+ select BOARD_LATE_INIT
+ select MX53
+ select DM
+ select DM_SERIAL
+ select DM_ETH
+ select DM_I2C
+ select DM_GPIO
+ select DM_PMIC
+
config TARGET_M53EVK
bool "Support m53evk"
select MX53
source "board/freescale/mx53smd/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
+source "board/k+p/kp_imx53/Kconfig"
source "board/technologic/ts4800/Kconfig"
endif
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
+ select MP
bool
config MX6
bool "embestmx6boards"
select BOARD_LATE_INIT
-config TARGET_GE_B450V3
- bool "General Electric B450v3"
- select BOARD_LATE_INIT
- select MX6Q
-
-config TARGET_GE_B650V3
- bool "General Electric B650v3"
- select BOARD_LATE_INIT
- select MX6Q
-
-config TARGET_GE_B850V3
- bool "General Electric B850v3"
+config TARGET_GE_BX50V3
+ bool "General Electric Bx50v3"
select BOARD_LATE_INIT
select MX6Q
config TARGET_MX6QARM2
bool "mx6qarm2"
+config TARGET_MX6DL_MAMOJ
+ bool "Support BTicino Mamoj"
+ select MX6QDL
+ select OF_CONTROL
+ select PINCTRL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_PMIC
+ select DM_PMIC_PFUZE100
+ select DM_THERMAL
+ select SPL
+ select SUPPORT_SPL
+ select SPL_DM if SPL
+ select SPL_OF_LIBFDT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_GPIO_SUPPORT if SPL
+ select SPL_LIBCOMMON_SUPPORT if SPL
+ select SPL_LIBDISK_SUPPORT if SPL
+ select SPL_LIBGENERIC_SUPPORT if SPL
+ select SPL_MMC_SUPPORT if SPL
+ select SPL_SERIAL_SUPPORT if SPL
+ select SPL_USB_HOST_SUPPORT if SPL
+ select SPL_USB_GADGET_SUPPORT if SPL
+ select SPL_USB_SDP_SUPPORT if SPL
+ select SPL_WATCHDOG_SUPPORT if SPL
+
config TARGET_MX6Q_ENGICAM
bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
+source "board/bticino/mamoj/Kconfig"
source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
obj-$(CONFIG_ARMADA_3700) += armada3700/
obj-$(CONFIG_ARMADA_8K) += armada8k/
obj-y += arm64-common.o
-obj-$(CONFIG_AHCI) += sata.o
else # CONFIG_ARM64
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <dm.h>
-
-/*
- * Dummy implementation that can be overwritten by a board
- * specific function
- */
-__weak int board_ahci_enable(void)
-{
- return 0;
-}
-
-#ifdef CONFIG_ARMADA_8K
-/* CP110 has different AHCI port addresses */
-void __iomem *ahci_port_base(void __iomem *base, u32 port)
-{
- return base + 0x10000 + (port * 0x10000);
-}
-#endif
-
-static int mvebu_ahci_probe(struct udevice *dev)
-{
- /*
- * Board specific SATA / AHCI enable code, e.g. enable the
- * AHCI power or deassert reset
- */
- board_ahci_enable();
-
- ahci_init(devfdt_get_addr_ptr(dev));
-
- return 0;
-}
-
-static const struct udevice_id mvebu_ahci_ids[] = {
- { .compatible = "marvell,armada-3700-ahci" },
- { .compatible = "marvell,armada-8k-ahci" },
- { }
-};
-
-U_BOOT_DRIVER(ahci_mvebu_drv) = {
- .name = "ahci_mvebu",
- .id = UCLASS_AHCI,
- .of_match = mvebu_ahci_ids,
- .probe = mvebu_ahci_probe,
-};
bool "Blanche board"
select DM
select DM_SERIAL
+ select USE_TINY_PRINTF
config TARGET_GOSE
bool "Gose board"
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
+obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
-obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
-obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
-obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
+obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
-obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
#elif defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
-#elif defined(CONFIG_R8A7790)
-#include "r8a7790-gpio.h"
-void r8a7790_pinmux_init(void);
-#elif defined(CONFIG_R8A7791)
-#include "r8a7791-gpio.h"
-void r8a7791_pinmux_init(void);
-#elif defined(CONFIG_R8A7792)
-#include "r8a7792-gpio.h"
-void r8a7792_pinmux_init(void);
-#elif defined(CONFIG_R8A7793)
-#include "r8a7793-gpio.h"
-void r8a7793_pinmux_init(void);
-#elif defined(CONFIG_R8A7794)
-#include "r8a7794-gpio.h"
-void r8a7794_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */
+++ /dev/null
-#ifndef __ASM_R8A7790_GPIO_H__
-#define __ASM_R8A7790_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
- GPIO_GP_1_28, GPIO_GP_1_29,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
- GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
- GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
- GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
- GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
-
- /* IPSR0 */
- GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
- GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
- GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
- GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
- GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
- GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
- GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
- GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
- GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
- GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
- GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
- GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
- GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
-
- /* IPSR1 */
- GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
- GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
- GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
- GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
- GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
- GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
- GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
- GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
- GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
- GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
- GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
- GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
- GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
- GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
- GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
-
- /* IPSR2 */
- GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
- GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
- GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
- GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
- GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
- GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
- GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
- GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
- GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
- GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
- GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
-
- /* IPSR3 */
- GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
- GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
- GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
- GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
- GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
- GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
- GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
- GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
- GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
- GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
- GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
- GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
- GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
-
- /* IPSR4 */
- GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
- GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
- GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
- GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
- GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
- GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
- GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
- GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
- GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
- GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
- GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
- GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
- GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
- GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
- GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
-
- /* IPSR5 */
- GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
- GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
- GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
- GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
- GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
- GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
- GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
- GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
- GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
- GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
- GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
- GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
- GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
- GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
- GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
- GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
- GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
- GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
- GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
- GPIO_FN_SSI_WS78_B,
-
- /* IPSR6 */
- GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
- GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
- GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
- GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
- GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
- GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
- GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
- GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
- GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
- GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
- GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
- GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
- GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
- GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
- GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
- GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
- GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
- GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
- GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
- GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
- GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
-
- /* IPSR7 */
- GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
- GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
- GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
- GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
- GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
- GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
- GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
- GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
- GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
- GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
- GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
- GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
- GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
- GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
- GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
- GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
- GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
- GPIO_FN_MII_RXD2,
-
- /* IPSR8 */
- GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
- GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
- GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
- GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
- GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
- GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
- GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
- GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
- GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
- GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
- GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
- GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
- GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
- GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
- GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
- GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
- GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
- GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
-
- /* IPSR9 */
- GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
- GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
- GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
- GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
- GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
- GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
- GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
- GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
- GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
- GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
- GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
- GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
- GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
- GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
- GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
- GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
- GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
- GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
- GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
- GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
- GPIO_FN_VI3_CLK_B,
-
- /* IPSR10 */
- GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
- GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
- GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
- GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
- GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
- GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
- GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
- GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
- GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
- GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
- GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
- GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
- GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
- GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
- GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
- GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
- GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
- GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
- GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
- GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
- GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
- GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
-
- /* IPSR11 */
- GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
- GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
- GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
- GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
- GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
- GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
- GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
- GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
- GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
- GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
- GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
- GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
- GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
- GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
- GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
- GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
- GPIO_FN_MOUT0,
-
- /* IPSR12 */
- GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
- GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
- GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
- GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
- GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
- GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
- GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
- GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
- GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
- GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
- GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
- GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
- GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
- GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
- GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
- GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
- GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
- GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
- GPIO_FN_CAN_DEBUGOUT4,
-
- /* IPSR13 */
- GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
- GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
- GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
- GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
- GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
- GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
- GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
- GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
- GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
- GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
- GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
- GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
- GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
- GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
- GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
- GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
- GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
- GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
- GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
- GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
- GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
- GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
-
- /* IPSR14 */
- GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
- GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
- GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
- GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
- GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
- GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
- GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
- GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
- GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
- GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
- GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
- GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
- GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
- GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
- GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
- GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
- GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
- GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
- GPIO_FN_HRTS0_N_C,
-
- /* IPSR15 */
- GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
- GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
- GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
- GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
- GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
- GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
- GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
- GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
- GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
- GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
- GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
- GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
- GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
- GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
- GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
-
- /* IPSR16 */
- GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
- GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
- GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
- GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
- GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
- GPIO_FN_TCLK1_B,
-};
-
-#endif /* __ASM_R8A7790_GPIO_H__ */
+++ /dev/null
-#ifndef __ASM_R8A7791_GPIO_H__
-#define __ASM_R8A7791_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
- GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
- GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
- GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
- GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
-
- GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
- GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
- GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
- GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
- GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
- GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
- GPIO_GP_7_24, GPIO_GP_7_25,
-
- GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
- GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
- GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
- GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
- GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
- GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
-
- /* IPSR0 */
- GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
- GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
- GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
- GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
- GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
- GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
- GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
- GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
-
- /* IPSR1 */
- GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
- GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
- GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
- GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
- GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
- GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
- GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
- GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
- GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
- GPIO_FN_A15, GPIO_FN_BPFCLK_C,
- GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
- GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
- GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
-
- /* IPSR2 */
- GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
- GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
- GPIO_FN_A20, GPIO_FN_SPCLK,
- GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
- GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
- GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
- GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
- GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
- GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
- GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
- GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
- GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
- GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
- GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
- GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
- GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
- GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
- GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
-
- /* IPSR3 */
- GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
- GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
- GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
- GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
- GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
- GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
- GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
- GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
- GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
- GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
- GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
- GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
- GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
- GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
- GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
- GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
- GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
- GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
- GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
- GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
- GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
- GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
- GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
-
- /* IPSR4 */
- GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
- GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
- GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
- GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
- GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
- GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
- GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
- GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
- GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
- GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
- GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
- GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
- GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
- GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
- GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
- GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
- GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
- GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
- GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
- GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
- GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
-
- /* IPSR5 */
- GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
- GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
- GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
- GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
- GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
- GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
- GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
- GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
- GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
- GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
- GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
- GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
- GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
- GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
- GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
- GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
- GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
-
- /* IPSR6 */
- GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
- GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
- GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
- GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
- GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
- GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
- GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
- GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
- GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
- GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
- GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
- GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
- GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
- GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
- GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
- GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
- GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
- GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
- GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
- GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
-
- /* IPSR7 */
- GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
- GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
- GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
- GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
- GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
- GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
- GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
- GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
- GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
- GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
- GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
- GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
- GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
- GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
- GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
- GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
- GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
- GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
-
- /* IPSR8 */
- GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
- GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
- GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
- GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
- GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
- GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
- GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
- GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
- GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
- GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
- GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
- GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
- GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
- GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
- GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
- GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
- GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
- GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
- GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
- GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
- GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
-
- /* IPSR9 */
- GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
- GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
- GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
- GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
- GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
- GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
- GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
- GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
- GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
- GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
- GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
- GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
- GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
- GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
- GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
- GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
- GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
- GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
- GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
- GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
- GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
- GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
- GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
- GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
-
- /* IPSR10 */
- GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
- GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
- GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
- GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
- GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
- GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
- GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
- GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
- GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
- GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
- GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
- GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
- GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
- GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
- GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
- GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
- GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
- GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
- GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
- GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
- GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
- GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
- GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
-
- /* IPSR11 */
- GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
- GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
- GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
- GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
- GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
- GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
- GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
- GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
- GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
- GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
- GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
- GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
- GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
- GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
- GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
- GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
- GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
- GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
- GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
- GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
- GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
- GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
-
- /* IPSR12 */
- GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
- GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
- GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
- GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
- GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
- GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
- GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
- GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
- GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
- GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
- GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
- GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
- GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
- GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
- GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
- GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
- GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
- GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
- GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
- GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
- GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
- GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
- GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
- GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
- GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
- GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
- GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
- GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
- GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
- GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
- GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
- GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
- GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
- GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
- GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
- GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
- GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
- GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
- GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
- GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
-
- /* IPSR14 */
- GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
- GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
- GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
- GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
- GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
- GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
- GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
- GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
- GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
- GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
- GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
- GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
- GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
- GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
- GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
- GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
- GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
- GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
- GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
- GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
-
- /* IPSR15 */
- GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
- GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
- GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
- GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
- GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
- GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
- GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
- GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
- GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
- GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
- GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
- GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
- GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
- GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
- GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
- GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
- GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
- GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
- GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
-
- /* IPSR16 */
- GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
- GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
- GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
- GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
- GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
- GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
- GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
- GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
- GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
-};
-
-#endif /* __ASM_R8A7791_GPIO_H__ */
+++ /dev/null
-#ifndef __ASM_R8A7792_GPIO_H__
-#define __ASM_R8A7792_GPIO_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16,
-
- GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
- GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
- GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
- GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
- GPIO_GP_7_16,
-
- GPIO_GP_8_0, GPIO_GP_8_1, GPIO_GP_8_2, GPIO_GP_8_3,
- GPIO_GP_8_4, GPIO_GP_8_5, GPIO_GP_8_6, GPIO_GP_8_7,
- GPIO_GP_8_8, GPIO_GP_8_9, GPIO_GP_8_10, GPIO_GP_8_11,
- GPIO_GP_8_12, GPIO_GP_8_13, GPIO_GP_8_14, GPIO_GP_8_15,
- GPIO_GP_8_16,
-
- GPIO_GP_9_0, GPIO_GP_9_1, GPIO_GP_9_2, GPIO_GP_9_3,
- GPIO_GP_9_4, GPIO_GP_9_5, GPIO_GP_9_6, GPIO_GP_9_7,
- GPIO_GP_9_8, GPIO_GP_9_9, GPIO_GP_9_10, GPIO_GP_9_11,
- GPIO_GP_9_12, GPIO_GP_9_13, GPIO_GP_9_14, GPIO_GP_9_15,
- GPIO_GP_9_16,
-
- GPIO_GP_10_0, GPIO_GP_10_1, GPIO_GP_10_2, GPIO_GP_10_3,
- GPIO_GP_10_4, GPIO_GP_10_5, GPIO_GP_10_6, GPIO_GP_10_7,
- GPIO_GP_10_8, GPIO_GP_10_9, GPIO_GP_10_10, GPIO_GP_10_11,
- GPIO_GP_10_12, GPIO_GP_10_13, GPIO_GP_10_14, GPIO_GP_10_15,
- GPIO_GP_10_16, GPIO_GP_10_17, GPIO_GP_10_18, GPIO_GP_10_19,
- GPIO_GP_10_20, GPIO_GP_10_21, GPIO_GP_10_22, GPIO_GP_10_23,
- GPIO_GP_10_24, GPIO_GP_10_25, GPIO_GP_10_26, GPIO_GP_10_27,
- GPIO_GP_10_28, GPIO_GP_10_29, GPIO_GP_10_30, GPIO_GP_10_31,
-
- GPIO_GP_11_0, GPIO_GP_11_1, GPIO_GP_11_2, GPIO_GP_11_3,
- GPIO_GP_11_4, GPIO_GP_11_5, GPIO_GP_11_6, GPIO_GP_11_7,
- GPIO_GP_11_8, GPIO_GP_11_9, GPIO_GP_11_10, GPIO_GP_11_11,
- GPIO_GP_11_12, GPIO_GP_11_13, GPIO_GP_11_14, GPIO_GP_11_15,
- GPIO_GP_11_16, GPIO_GP_11_17, GPIO_GP_11_18, GPIO_GP_11_19,
- GPIO_GP_11_20, GPIO_GP_11_21, GPIO_GP_11_22, GPIO_GP_11_23,
- GPIO_GP_11_24, GPIO_GP_11_25, GPIO_GP_11_26, GPIO_GP_11_27,
- GPIO_GP_11_28, GPIO_GP_11_29,
-
- GPIO_FN_DU1_DB2_C0_DATA12, GPIO_FN_DU1_DB3_C1_DATA13,
- GPIO_FN_DU1_DB4_C2_DATA14, GPIO_FN_DU1_DB5_C3_DATA15,
- GPIO_FN_DU1_DB6_C4, GPIO_FN_DU1_DB7_C5, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
- GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_DU1_DISP, GPIO_FN_DU1_CDE,
-
- GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
- GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, GPIO_FN_D11,
- GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, GPIO_FN_A0, GPIO_FN_A1,
- GPIO_FN_A2, GPIO_FN_A3, GPIO_FN_A4, GPIO_FN_A5, GPIO_FN_A6, GPIO_FN_A7,
- GPIO_FN_A8, GPIO_FN_A9, GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
- GPIO_FN_A14, GPIO_FN_A15,
-
- GPIO_FN_A16, GPIO_FN_A17, GPIO_FN_A18, GPIO_FN_A19,
- GPIO_FN_CS1_A26, GPIO_FN_EX_CS0, GPIO_FN_EX_CS1, GPIO_FN_EX_CS2,
- GPIO_FN_EX_CS3, GPIO_FN_EX_CS4, GPIO_FN_EX_CS5, GPIO_FN_BS,
- GPIO_FN_RD, GPIO_FN_RD_WR, GPIO_FN_WE0, GPIO_FN_WE1, GPIO_FN_EX_WAIT0,
- GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_CS0,
-
- GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_VSYNC,
- GPIO_FN_VI0_D0_B0_C0, GPIO_FN_VI0_D1_B1_C1, GPIO_FN_VI0_D2_B2_C2, GPIO_FN_VI0_D3_B3_C3,
- GPIO_FN_VI0_D4_B4_C4, GPIO_FN_VI0_D5_B5_C5, GPIO_FN_VI0_D6_B6_C6, GPIO_FN_VI0_D7_B7_C7,
- GPIO_FN_VI0_D8_G0_Y0, GPIO_FN_VI0_D9_G1_Y1, GPIO_FN_VI0_D10_G2_Y2, GPIO_FN_VI0_D11_G3_Y3,
- GPIO_FN_VI0_FIELD,
-
- GPIO_FN_VI1_CLK, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_HSYNC,
- GPIO_FN_VI1_VSYNC, GPIO_FN_VI1_D0_B0_C0, GPIO_FN_VI1_D1_B1_C1,
- GPIO_FN_VI1_D2_B2_C2, GPIO_FN_VI1_D3_B3_C3, GPIO_FN_VI1_D4_B4_C4,
- GPIO_FN_VI1_D5_B5_C5, GPIO_FN_VI1_D6_B6_C6, GPIO_FN_VI1_D7_B7_C7,
- GPIO_FN_VI1_D8_G0_Y0, GPIO_FN_VI1_D9_G1_Y1, GPIO_FN_VI1_D10_G2_Y2,
- GPIO_FN_VI1_D11_G3_Y3, GPIO_FN_VI1_FIELD,
-
- GPIO_FN_VI3_D10_Y2, GPIO_FN_VI3_FIELD,
-
- GPIO_FN_VI4_CLK,
-
- GPIO_FN_VI5_CLK, GPIO_FN_VI5_D9_Y1, GPIO_FN_VI5_D10_Y2, GPIO_FN_VI5_D11_Y3, GPIO_FN_VI5_FIELD,
-
- GPIO_FN_HRTS0, GPIO_FN_HCTS1, GPIO_FN_SCK0, GPIO_FN_CTS0, GPIO_FN_RTS0, GPIO_FN_TX0,
- GPIO_FN_RX0, GPIO_FN_SCK1, GPIO_FN_CTS1, GPIO_FN_RTS1, GPIO_FN_TX1, GPIO_FN_RX1,
- GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_TX, GPIO_FN_CAN0_RX,
- GPIO_FN_CAN_CLK, GPIO_FN_CAN1_TX, GPIO_FN_CAN1_RX,
-
- GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, GPIO_FN_SD0_DAT0,
- GPIO_FN_SD0_DAT1, GPIO_FN_SD0_DAT2, GPIO_FN_SD0_DAT3,
- GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, GPIO_FN_ADICLK,
- GPIO_FN_ADICS_SAMP, GPIO_FN_ADIDATA, GPIO_FN_ADICHS0,
- GPIO_FN_ADICHS1, GPIO_FN_ADICHS2, GPIO_FN_AVS1, GPIO_FN_AVS2,
-
- GPIO_FN_DU0_DR0_DATA0, GPIO_FN_DU0_DR1_DATA1, GPIO_FN_DU0_DR2_Y4_DATA2,
- GPIO_FN_DU0_DR3_Y5_DATA3, GPIO_FN_DU0_DR4_Y6_DATA4, GPIO_FN_DU0_DR5_Y7_DATA5,
- GPIO_FN_DU0_DR6_Y8_DATA6, GPIO_FN_DU0_DR7_Y9_DATA7, GPIO_FN_DU0_DG0_DATA8,
- GPIO_FN_DU0_DG1_DATA9, GPIO_FN_DU0_DG2_C6_DATA10, GPIO_FN_DU0_DG3_C7_DATA11,
- GPIO_FN_DU0_DG4_Y0_DATA12, GPIO_FN_DU0_DG5_Y1_DATA13, GPIO_FN_DU0_DG6_Y2_DATA14,
- GPIO_FN_DU0_DG7_Y3_DATA15, GPIO_FN_DU0_DB0, GPIO_FN_DU0_DB1,
- GPIO_FN_DU0_DB2_C0, GPIO_FN_DU0_DB3_C1, GPIO_FN_DU0_DB4_C2,
- GPIO_FN_DU0_DB5_C3, GPIO_FN_DU0_DB6_C4, GPIO_FN_DU0_DB7_C5,
-
- GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_DU0_EXVSYNC_DU0_VSYNC,
- GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_DU0_DISP, GPIO_FN_DU0_CDE,
- GPIO_FN_DU1_DR2_Y4_DATA0, GPIO_FN_DU1_DR3_Y5_DATA1, GPIO_FN_DU1_DR4_Y6_DATA2,
- GPIO_FN_DU1_DR5_Y7_DATA3, GPIO_FN_DU1_DR6_DATA4, GPIO_FN_DU1_DR7_DATA5,
- GPIO_FN_DU1_DG2_C6_DATA6, GPIO_FN_DU1_DG3_C7_DATA7, GPIO_FN_DU1_DG4_Y0_DATA8,
- GPIO_FN_DU1_DG5_Y1_DATA9, GPIO_FN_DU1_DG6_Y2_DATA10, GPIO_FN_DU1_DG7_Y3_DATA11,
- GPIO_FN_A20, GPIO_FN_MOSI_IO0, GPIO_FN_A21, GPIO_FN_MISO_IO1, GPIO_FN_A22, GPIO_FN_IO2,
- GPIO_FN_A23, GPIO_FN_IO3, GPIO_FN_A24, GPIO_FN_SPCLK, GPIO_FN_A25, GPIO_FN_SSL,
-
- GPIO_FN_VI2_CLK, GPIO_FN_AVB_RX_CLK, GPIO_FN_VI2_CLKENB, GPIO_FN_AVB_RX_DV,
- GPIO_FN_VI2_HSYNC, GPIO_FN_AVB_RXD0, GPIO_FN_VI2_VSYNC, GPIO_FN_AVB_RXD1,
- GPIO_FN_VI2_D0_C0, GPIO_FN_AVB_RXD2, GPIO_FN_VI2_D1_C1, GPIO_FN_AVB_RXD3,
- GPIO_FN_VI2_D2_C2, GPIO_FN_AVB_RXD4, GPIO_FN_VI2_D3_C3, GPIO_FN_AVB_RXD5,
- GPIO_FN_VI2_D4_C4, GPIO_FN_AVB_RXD6, GPIO_FN_VI2_D5_C5, GPIO_FN_AVB_RXD7,
- GPIO_FN_VI2_D6_C6, GPIO_FN_AVB_RX_ER, GPIO_FN_VI2_D7_C7, GPIO_FN_AVB_COL,
- GPIO_FN_VI2_D8_Y0, GPIO_FN_AVB_TXD3, GPIO_FN_VI2_D9_Y1, GPIO_FN_AVB_TX_EN,
- GPIO_FN_VI2_D10_Y2, GPIO_FN_AVB_TXD0, GPIO_FN_VI2_D11_Y3, GPIO_FN_AVB_TXD1,
- GPIO_FN_VI2_FIELD, GPIO_FN_AVB_TXD2,
-
- GPIO_FN_VI3_CLK, GPIO_FN_AVB_TX_CLK, GPIO_FN_VI3_CLKENB, GPIO_FN_AVB_TXD4,
- GPIO_FN_VI3_HSYNC, GPIO_FN_AVB_TXD5, GPIO_FN_VI3_VSYNC, GPIO_FN_AVB_TXD6,
- GPIO_FN_VI3_D0_C0, GPIO_FN_AVB_TXD7, GPIO_FN_VI3_D1_C1, GPIO_FN_AVB_TX_ER,
- GPIO_FN_VI3_D2_C2, GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI3_D3_C3, GPIO_FN_AVB_MDC,
- GPIO_FN_VI3_D4_C4, GPIO_FN_AVB_MDIO, GPIO_FN_VI3_D5_C5, GPIO_FN_AVB_LINK,
- GPIO_FN_VI3_D6_C6, GPIO_FN_AVB_MAGIC, GPIO_FN_VI3_D7_C7, GPIO_FN_AVB_PHY_INT,
- GPIO_FN_VI3_D8_Y0, GPIO_FN_AVB_CRS, GPIO_FN_VI3_D9_Y1, GPIO_FN_AVB_GTXREFCLK,
- GPIO_FN_VI3_D11_Y3,
-
- GPIO_FN_VI4_CLKENB, GPIO_FN_VI0_D12_G4_Y4, GPIO_FN_VI4_HSYNC, GPIO_FN_VI0_D13_G5_Y5,
- GPIO_FN_VI4_VSYNC, GPIO_FN_VI0_D14_G6_Y6, GPIO_FN_VI4_D0_C0, GPIO_FN_VI0_D15_G7_Y7,
- GPIO_FN_VI4_D1_C1, GPIO_FN_VI0_D16_R0, GPIO_FN_VI1_D12_G4_Y4_0,
- GPIO_FN_VI4_D2_C2, GPIO_FN_VI0_D17_R1, GPIO_FN_VI1_D13_G5_Y5_0,
- GPIO_FN_VI4_D3_C3, GPIO_FN_VI0_D18_R2, GPIO_FN_VI1_D14_G6_Y6_0,
- GPIO_FN_VI4_D4_C4, GPIO_FN_VI0_D19_R3, GPIO_FN_VI1_D15_G7_Y7_0,
- GPIO_FN_VI4_D5_C5, GPIO_FN_VI0_D20_R4, GPIO_FN_VI2_D12_Y4,
- GPIO_FN_VI4_D6_C6, GPIO_FN_VI0_D21_R5, GPIO_FN_VI2_D13_Y5,
- GPIO_FN_VI4_D7_C7, GPIO_FN_VI0_D22_R6, GPIO_FN_VI2_D14_Y6,
- GPIO_FN_VI4_D8_Y0, GPIO_FN_VI0_D23_R7, GPIO_FN_VI2_D15_Y7,
- GPIO_FN_VI4_D9_Y1, GPIO_FN_VI3_D12_Y4, GPIO_FN_VI4_D10_Y2, GPIO_FN_VI3_D13_Y5,
- GPIO_FN_VI4_D11_Y3, GPIO_FN_VI3_D14_Y6, GPIO_FN_VI4_FIELD, GPIO_FN_VI3_D15_Y7,
-
- GPIO_FN_VI5_CLKENB, GPIO_FN_VI1_D12_G4_Y4_1, GPIO_FN_VI5_HSYNC, GPIO_FN_VI1_D13_G5_Y5_1,
- GPIO_FN_VI5_VSYNC, GPIO_FN_VI1_D14_G6_Y6_1, GPIO_FN_VI5_D0_C0, GPIO_FN_VI1_D15_G7_Y7_1,
- GPIO_FN_VI5_D1_C1, GPIO_FN_VI1_D16_R0, GPIO_FN_VI5_D2_C2, GPIO_FN_VI1_D17_R1,
- GPIO_FN_VI5_D3_C3, GPIO_FN_VI1_D18_R2, GPIO_FN_VI5_D4_C4, GPIO_FN_VI1_D19_R3,
- GPIO_FN_VI5_D5_C5, GPIO_FN_VI1_D20_R4, GPIO_FN_VI5_D6_C6, GPIO_FN_VI1_D21_R5,
- GPIO_FN_VI5_D7_C7, GPIO_FN_VI1_D22_R6, GPIO_FN_VI5_D8_Y0, GPIO_FN_VI1_D23_R7,
-
- GPIO_FN_MSIOF0_SCK, GPIO_FN_HSCK0, GPIO_FN_MSIOF0_SYNC, GPIO_FN_HCTS0,
- GPIO_FN_MSIOF0_TXD, GPIO_FN_HTX0, GPIO_FN_MSIOF0_RXD, GPIO_FN_HRX0,
- GPIO_FN_MSIOF1_SCK, GPIO_FN_HSCK1, GPIO_FN_MSIOF1_SYNC, GPIO_FN_HRTS1,
- GPIO_FN_MSIOF1_TXD, GPIO_FN_HTX1, GPIO_FN_MSIOF1_RXD, GPIO_FN_HRX1,
- GPIO_FN_DRACK0, GPIO_FN_SCK2, GPIO_FN_DACK0, GPIO_FN_TX2,
- GPIO_FN_DREQ0, GPIO_FN_RX2, GPIO_FN_DACK1, GPIO_FN_SCK3,
- GPIO_FN_TX3, GPIO_FN_DREQ1, GPIO_FN_RX3,
-
- GPIO_FN_PWM0, GPIO_FN_TCLK1, GPIO_FN_FSO_CFE_0,
- GPIO_FN_PWM1, GPIO_FN_TCLK2, GPIO_FN_FSO_CFE_1,
- GPIO_FN_PWM2, GPIO_FN_TCLK3, GPIO_FN_FSO_TOE,
- GPIO_FN_PWM3, GPIO_FN_PWM4, GPIO_FN_SSI_SCK3, GPIO_FN_TPU0TO0,
- GPIO_FN_SSI_WS3, GPIO_FN_TPU0TO1, GPIO_FN_SSI_SDATA3, GPIO_FN_TPU0TO2,
- GPIO_FN_SSI_SCK4, GPIO_FN_TPU0TO3, GPIO_FN_SSI_WS4,
- GPIO_FN_SSI_SDATA4, GPIO_FN_AUDIO_CLKOUT,
- GPIO_FN_AUDIO_CLKA, GPIO_FN_AUDIO_CLKB,
-};
-
-#endif /* __ASM_R8A7792_GPIO_H__ */
+++ /dev/null
-#ifndef __ASM_R8A7793_H__
-#define __ASM_R8A7793_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
- GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
- GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
- GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
- GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
-
- GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
- GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
- GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
- GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
- GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
- GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
- GPIO_GP_7_24, GPIO_GP_7_25,
-
- GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
- GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
- GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
- GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
- GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
- GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
-
- /* IPSR0 */
- GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
- GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
- GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
- GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
- GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
- GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
- GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
- GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
-
- /* IPSR1 */
- GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
- GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
- GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
- GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
- GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
- GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
- GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
- GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
- GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
- GPIO_FN_A15, GPIO_FN_BPFCLK_C,
- GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
- GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
- GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
-
- /* IPSR2 */
- GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
- GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
- GPIO_FN_A20, GPIO_FN_SPCLK,
- GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
- GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
- GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
- GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
- GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
- GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
- GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
- GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
- GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
- GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
- GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
- GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
- GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
- GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
- GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
-
- /* IPSR3 */
- GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
- GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
- GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
- GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
- GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
- GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
- GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
- GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
- GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
- GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
- GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
- GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
- GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
- GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
- GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
- GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
- GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
- GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
- GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
- GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
- GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
- GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
- GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
-
- /* IPSR4 */
- GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
- GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
- GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
- GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
- GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
- GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
- GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
- GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
- GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
- GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
- GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
- GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
- GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
- GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
- GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
- GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
- GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
- GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
- GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
- GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
- GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
-
- /* IPSR5 */
- GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
- GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
- GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
- GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
- GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
- GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
- GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
- GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
- GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
- GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
- GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
- GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
- GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
- GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
- GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
- GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
- GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
-
- /* IPSR6 */
- GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
- GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
- GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
- GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
- GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
- GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
- GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
- GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
- GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
- GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
- GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
- GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
- GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
- GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
- GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
- GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
- GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
- GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
- GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
- GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
-
- /* IPSR7 */
- GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
- GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
- GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
- GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
- GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
- GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
- GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
- GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
- GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
- GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
- GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
- GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
- GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
- GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
- GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
- GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
- GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
- GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
-
- /* IPSR8 */
- GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
- GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
- GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
- GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
- GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
- GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
- GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
- GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
- GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
- GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
- GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
- GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
- GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
- GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
- GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
- GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
- GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
- GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
- GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
- GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
- GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
-
- /* IPSR9 */
- GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
- GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
- GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
- GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
- GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
- GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
- GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
- GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
- GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
- GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
- GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
- GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
- GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
- GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
- GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
- GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
- GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
- GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
- GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
- GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
- GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
- GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
- GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
- GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
-
- /* IPSR10 */
- GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
- GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
- GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
- GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
- GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
- GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
- GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
- GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
- GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
- GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
- GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
- GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
- GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
- GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
- GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
- GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
- GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
- GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
- GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
- GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
- GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
- GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
- GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
-
- /* IPSR11 */
- GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
- GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
- GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
- GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
- GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
- GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
- GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
- GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
- GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
- GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
- GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
- GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
- GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
- GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
- GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
- GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
- GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
- GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
- GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
- GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
- GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
- GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
-
- /* IPSR12 */
- GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
- GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
- GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
- GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
- GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
- GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
- GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
- GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
- GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
- GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
- GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
- GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
- GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
- GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
- GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
- GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
- GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
- GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
- GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
- GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
- GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
- GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
- GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
- GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
- GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
- GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
- GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
- GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
- GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
- GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
- GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
- GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
- GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
- GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
- GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
- GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
- GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
- GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
- GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
- GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
-
- /* IPSR14 */
- GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
- GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
- GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
- GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
- GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
- GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
- GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
- GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
- GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
- GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
- GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
- GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
- GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
- GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
- GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
- GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
- GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
- GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
- GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
- GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
-
- /* IPSR15 */
- GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
- GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
- GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
- GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
- GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
- GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
- GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
- GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
- GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
- GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
- GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
- GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
- GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
- GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
- GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
- GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
- GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
- GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
- GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
-
- /* IPSR16 */
- GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
- GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
- GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
- GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
- GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
- GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
- GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
- GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
- GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
-};
-
-#endif /* __ASM_R8A7793_H__ */
+++ /dev/null
-#ifndef __ASM_R8A7794_H__
-#define __ASM_R8A7794_H__
-
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
- GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
- GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
- GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
- GPIO_GP_6_24, GPIO_GP_6_25,
-
- GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
- GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
- GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
- GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
- GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
- GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
- GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
-
- /* IPSR0 */
- GPIO_FN_SD1_CD, GPIO_FN_CAN0_RX, GPIO_FN_SD1_WP, GPIO_FN_IRQ7,
- GPIO_FN_CAN0_TX, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CLK, GPIO_FN_MMC_CMD,
- GPIO_FN_SD2_CMD, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D1,
- GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA2,
- GPIO_FN_MMC_D3, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D4,
- GPIO_FN_SD2_CD, GPIO_FN_MMC_D5, GPIO_FN_SD2_WP, GPIO_FN_MMC_D6,
- GPIO_FN_SCIF0_RXD, GPIO_FN_I2C2_SCL_B, GPIO_FN_CAN1_RX, GPIO_FN_MMC_D7,
- GPIO_FN_SCIF0_TXD, GPIO_FN_I2C2_SDA_B, GPIO_FN_CAN1_TX, GPIO_FN_D0,
- GPIO_FN_SCIFA3_SCK_B, GPIO_FN_IRQ4, GPIO_FN_D1, GPIO_FN_SCIFA3_RXD_B,
- GPIO_FN_D2, GPIO_FN_SCIFA3_TXD_B, GPIO_FN_D3, GPIO_FN_I2C3_SCL_B,
- GPIO_FN_SCIF5_RXD_B, GPIO_FN_D4, GPIO_FN_I2C3_SDA_B,
- GPIO_FN_SCIF5_TXD_B, GPIO_FN_D5, GPIO_FN_SCIF4_RXD_B,
- GPIO_FN_I2C0_SCL_D,
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
- GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
- GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
- GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
- GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
- GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
- GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
- GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
- GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
- GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
- GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
- GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
- GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
- GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
- GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
- GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
- GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
- GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
- GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
-
- /* IPSR7 */
- GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
- GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
- GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
- GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
- GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
- GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
- GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
- GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
- GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
- GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
- GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
- GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
- GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
- GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
- GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
- GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
- GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
- GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
- GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
- GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
-
- /* IPSR8 */
- GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
- GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
- GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
- GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
- GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
- GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
- GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
- GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
- GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
- GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
- GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
- GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
- GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
- GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
- GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
- GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
- GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
- GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
- GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
- GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
- GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
-
- /* IPSR9 */
- GPIO_FN_MSIOF0_TXD, GPIO_FN_SCIF5_TXD, GPIO_FN_I2C2_SDA_C,
- GPIO_FN_DU1_DR3, GPIO_FN_RIF1_D1_B, GPIO_FN_TS_SPSYNC_D, GPIO_FN_FMIN_C,
- GPIO_FN_RDS_DATA, GPIO_FN_MSIOF0_SCK, GPIO_FN_IRQ0, GPIO_FN_TS_SDATA,
- GPIO_FN_DU1_DR4, GPIO_FN_RIF1_SYNC, GPIO_FN_TPUTO1_C,
- GPIO_FN_MSIOF0_SYNC, GPIO_FN_PWM1, GPIO_FN_TS_SCK, GPIO_FN_DU1_DR5,
- GPIO_FN_RIF1_CLK, GPIO_FN_BPFCLK_B, GPIO_FN_MSIOF0_SS1,
- GPIO_FN_SCIFA0_RXD, GPIO_FN_TS_SDEN, GPIO_FN_DU1_DR6, GPIO_FN_RIF1_D0,
- GPIO_FN_FMCLK_B, GPIO_FN_RDS_CLK_B, GPIO_FN_MSIOF0_SS2,
- GPIO_FN_SCIFA0_TXD, GPIO_FN_TS_SPSYNC, GPIO_FN_DU1_DR7, GPIO_FN_RIF1_D1,
- GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA_B, GPIO_FN_HSCIF1_HRX,
- GPIO_FN_I2C4_SCL, GPIO_FN_PWM6, GPIO_FN_DU1_DG0, GPIO_FN_HSCIF1_HTX,
- GPIO_FN_I2C4_SDA, GPIO_FN_TPUTO1, GPIO_FN_DU1_DG1, GPIO_FN_HSCIF1_HSCK,
- GPIO_FN_PWM2, GPIO_FN_IETX, GPIO_FN_DU1_DG2, GPIO_FN_REMOCON_B,
- GPIO_FN_SPEEDIN_B, GPIO_FN_VSP_B, GPIO_FN_HSCIF1_HCTS_N,
- GPIO_FN_SCIFA4_RXD, GPIO_FN_IECLK, GPIO_FN_DU1_DG3, GPIO_FN_SSI_SCK1_B,
- GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_CC50_STATE32,
- GPIO_FN_HSCIF1_HRTS_N, GPIO_FN_SCIFA4_TXD, GPIO_FN_IERX,
- GPIO_FN_DU1_DG4, GPIO_FN_SSI_WS1_B, GPIO_FN_CAN_STEP0,
- GPIO_FN_CC50_STATE33, GPIO_FN_SCIF1_SCK, GPIO_FN_PWM3, GPIO_FN_TCLK2,
- GPIO_FN_DU1_DG5, GPIO_FN_SSI_SDATA1_B, GPIO_FN_CAN_TXCLK,
- GPIO_FN_CC50_STATE34,
-
- /* IPSR10 */
- GPIO_FN_SCIF1_RXD, GPIO_FN_IIC0_SCL, GPIO_FN_DU1_DG6,
- GPIO_FN_SSI_SCK2_B, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_CC50_STATE35,
- GPIO_FN_SCIF1_TXD, GPIO_FN_IIC0_SDA, GPIO_FN_DU1_DG7, GPIO_FN_SSI_WS2_B,
- GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_CC50_STATE36, GPIO_FN_SCIF2_RXD,
- GPIO_FN_IIC1_SCL, GPIO_FN_DU1_DB0, GPIO_FN_SSI_SDATA2_B,
- GPIO_FN_USB0_EXTLP, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_CC50_STATE37,
- GPIO_FN_SCIF2_TXD, GPIO_FN_IIC1_SDA, GPIO_FN_DU1_DB1,
- GPIO_FN_SSI_SCK9_B, GPIO_FN_USB0_OVC1, GPIO_FN_CAN_DEBUGOUT3,
- GPIO_FN_CC50_STATE38, GPIO_FN_SCIF2_SCK, GPIO_FN_IRQ1, GPIO_FN_DU1_DB2,
- GPIO_FN_SSI_WS9_B, GPIO_FN_USB0_IDIN, GPIO_FN_CAN_DEBUGOUT4,
- GPIO_FN_CC50_STATE39, GPIO_FN_SCIF3_SCK, GPIO_FN_IRQ2, GPIO_FN_BPFCLK_D,
- GPIO_FN_DU1_DB3, GPIO_FN_SSI_SDATA9_B, GPIO_FN_TANS2,
- GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_CC50_OSCOUT, GPIO_FN_SCIF3_RXD,
- GPIO_FN_I2C1_SCL_E, GPIO_FN_FMCLK_D, GPIO_FN_DU1_DB4,
- GPIO_FN_AUDIO_CLKA_C, GPIO_FN_SSI_SCK4_B, GPIO_FN_CAN_DEBUGOUT6,
- GPIO_FN_RDS_CLK_C, GPIO_FN_SCIF3_TXD, GPIO_FN_I2C1_SDA_E,
- GPIO_FN_FMIN_D, GPIO_FN_DU1_DB5, GPIO_FN_AUDIO_CLKB_C,
- GPIO_FN_SSI_WS4_B, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_RDS_DATA_C,
- GPIO_FN_I2C2_SCL, GPIO_FN_SCIFA5_RXD, GPIO_FN_DU1_DB6,
- GPIO_FN_AUDIO_CLKC_C, GPIO_FN_SSI_SDATA4_B, GPIO_FN_CAN_DEBUGOUT8,
- GPIO_FN_I2C2_SDA, GPIO_FN_SCIFA5_TXD, GPIO_FN_DU1_DB7,
- GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SCK5,
- GPIO_FN_SCIFA3_SCK, GPIO_FN_CAN_DEBUGOUT10,
- GPIO_FN_DU1_DOTCLKIN,
-
- /* IPSR11 */
- GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
- GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
- GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
- GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
- GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
- GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
- GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
- GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
- GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
- GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
- GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
- GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
- GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
- GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
- GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
- GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
- GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
- GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
-
- /* IPSR12 */
- GPIO_FN_SSI_SCK34, GPIO_FN_MSIOF1_SYNC_B, GPIO_FN_SCIFA1_SCK_C,
- GPIO_FN_ADICHS0_B, GPIO_FN_AD_NCS_N_B, GPIO_FN_DREQ1_N_B,
- GPIO_FN_SSI_WS34, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_SCIFA1_RXD_C,
- GPIO_FN_ADICHS1_B, GPIO_FN_CAN1_RX_C, GPIO_FN_DACK1_B,
- GPIO_FN_SSI_SDATA3, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_SCIFA1_TXD_C,
- GPIO_FN_ADICHS2_B, GPIO_FN_CAN1_TX_C, GPIO_FN_DREQ2_N, GPIO_FN_SSI_SCK4,
- GPIO_FN_MLB_CK, GPIO_FN_IETX_B, GPIO_FN_IRD_TX, GPIO_FN_SSI_WS4,
- GPIO_FN_MLB_SIG, GPIO_FN_IECLK_B, GPIO_FN_IRD_RX, GPIO_FN_SSI_SDATA4,
- GPIO_FN_MLB_DAT, GPIO_FN_IERX_B, GPIO_FN_IRD_SCK, GPIO_FN_SSI_SDATA8,
- GPIO_FN_SCIF1_SCK_B, GPIO_FN_PWM1_B, GPIO_FN_IRQ9, GPIO_FN_REMOCON,
- GPIO_FN_DACK2, GPIO_FN_ETH_MDIO_B, GPIO_FN_SSI_SCK1,
- GPIO_FN_SCIF1_RXD_B, GPIO_FN_IIC1_SCL_C, GPIO_FN_VI1_CLK,
- GPIO_FN_CAN0_RX_D, GPIO_FN_AVB_AVTP_CAPTURE, GPIO_FN_ETH_CRS_DV_B,
- GPIO_FN_SSI_WS1, GPIO_FN_SCIF1_TXD_B, GPIO_FN_IIC1_SDA_C,
- GPIO_FN_VI1_DATA0, GPIO_FN_CAN0_TX_D, GPIO_FN_AVB_AVTP_MATCH,
- GPIO_FN_ETH_RX_ER_B, GPIO_FN_SSI_SDATA1, GPIO_FN_HSCIF1_HRX_B,
- GPIO_FN_VI1_DATA1, GPIO_FN_SDATA, GPIO_FN_ATAG0_N, GPIO_FN_ETH_RXD0_B,
- GPIO_FN_SSI_SCK2, GPIO_FN_HSCIF1_HTX_B, GPIO_FN_VI1_DATA2,
- GPIO_FN_MDATA, GPIO_FN_ATAWR0_N, GPIO_FN_ETH_RXD1_B,
-
- /* IPSR13 */
- GPIO_FN_SSI_WS2, GPIO_FN_HSCIF1_HCTS_N_B, GPIO_FN_SCIFA0_RXD_D,
- GPIO_FN_VI1_DATA3, GPIO_FN_SCKZ, GPIO_FN_ATACS00_N, GPIO_FN_ETH_LINK_B,
- GPIO_FN_SSI_SDATA2, GPIO_FN_HSCIF1_HRTS_N_B, GPIO_FN_SCIFA0_TXD_D,
- GPIO_FN_VI1_DATA4, GPIO_FN_STM_N, GPIO_FN_ATACS10_N,
- GPIO_FN_ETH_REFCLK_B, GPIO_FN_SSI_SCK9, GPIO_FN_SCIF2_SCK_B,
- GPIO_FN_PWM2_B, GPIO_FN_VI1_DATA5, GPIO_FN_MTS_N, GPIO_FN_EX_WAIT1,
- GPIO_FN_ETH_TXD1_B, GPIO_FN_SSI_WS9, GPIO_FN_SCIF2_RXD_B,
- GPIO_FN_I2C3_SCL_E, GPIO_FN_VI1_DATA6, GPIO_FN_ATARD0_N,
- GPIO_FN_ETH_TX_EN_B, GPIO_FN_SSI_SDATA9, GPIO_FN_SCIF2_TXD_B,
- GPIO_FN_I2C3_SDA_E, GPIO_FN_VI1_DATA7, GPIO_FN_ATADIR0_N,
- GPIO_FN_ETH_MAGIC_B, GPIO_FN_AUDIO_CLKA, GPIO_FN_I2C0_SCL_B,
- GPIO_FN_SCIFA4_RXD_D, GPIO_FN_VI1_CLKENB, GPIO_FN_TS_SDATA_C,
- GPIO_FN_RIF0_SYNC_B, GPIO_FN_ETH_TXD0_B, GPIO_FN_AUDIO_CLKB,
- GPIO_FN_I2C0_SDA_B, GPIO_FN_SCIFA4_TXD_D, GPIO_FN_VI1_FIELD,
- GPIO_FN_TS_SCK_C, GPIO_FN_RIF0_CLK_B, GPIO_FN_BPFCLK_E,
- GPIO_FN_ETH_MDC_B, GPIO_FN_AUDIO_CLKC, GPIO_FN_I2C4_SCL_B,
- GPIO_FN_SCIFA5_RXD_D, GPIO_FN_VI1_HSYNC_N, GPIO_FN_TS_SDEN_C,
- GPIO_FN_RIF0_D0_B, GPIO_FN_FMCLK_E, GPIO_FN_RDS_CLK_D,
- GPIO_FN_AUDIO_CLKOUT, GPIO_FN_I2C4_SDA_B, GPIO_FN_SCIFA5_TXD_D,
- GPIO_FN_VI1_VSYNC_N, GPIO_FN_TS_SPSYNC_C, GPIO_FN_RIF0_D1_B,
- GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D,
-};
-
-#endif /* __ASM_R8A7794_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
- * This file is r8a7790 processor support - PFC hardware block.
- *
- * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Magnus Damm
- * Copyright (C) 2012 Renesas Solutions Corp.
- * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-#include "pfc-r8a7790.h"
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
- FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
- FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
- FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
- FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
- FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
- FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
- FN_IP3_14_12, FN_IP3_17_15,
-
- /* GPSR1 */
- FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
- FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
- FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
- FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
- FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
- FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
-
- /* GPSR2 */
- FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
- FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
- FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
- FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
- FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
- FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
- FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
-
- /* GPSR3 */
- FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
- FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
- FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
- FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
- FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
- FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
- FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
-
- /* GPSR4 */
- FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
- FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
- FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
- FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
- FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
- FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
- FN_IP14_15_12, FN_IP14_18_16,
-
- /* GPSR5 */
- FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
- FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
- FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
- FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
- FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
- FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
- FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
-
- /* IPSR0 - IPSR5 */
- /* IPSR6 */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
- FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
- FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
- FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
- FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
- FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
- FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
- FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
- FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
- FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
- FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
- FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
- FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
- FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
- FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
- FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
- FN_STP_IVCXO27_1_B, FN_HRX0_F,
-
- /* IPSR7 */
- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
- FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
- FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
- FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
- FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
- FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
- FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
- FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
- FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
- FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
- FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
- FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
- FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
- FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
- FN_MII_RXD2,
-
- /* IPSR8 */
- FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
- FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
- FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
- FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
- FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
- FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
- FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
- FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
- FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
- FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
- FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
- FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
- FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
- FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
- FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
- FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
- FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
- FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
-
- /* IPSR9 */
- FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
- FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
- FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
- FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
- FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
- FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
- FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
- FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
- FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
- FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
- FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
- FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
- FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
- FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
- FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
- FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
- FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
- FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
- FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
- FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
- FN_VI3_CLK_B,
-
- /* IPSR10 */
- FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
- FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
- FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
- FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
- FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
- FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
- FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
- FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
- FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
- FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
- FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
- FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
- FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
- FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
- FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
- FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
- FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
- FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
- FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
- FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
- FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
- FN_GLO_I0_B, FN_VI3_DATA6_B,
-
- /* IPSR11 */
- FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
- FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
- FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
- FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
- FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
- FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
- FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
- FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
- FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
- FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
- FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
- FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
- FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
- FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
- FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
- FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
- FN_MOUT0,
-
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIF1_4,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFB1_4,
- FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_SOF1_0, FN_SEL_SOF1_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
- FN_SEL_SSI6_0, FN_SEL_SSI6_1,
- FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
- FN_SEL_VI3_0, FN_SEL_VI3_1,
- FN_SEL_VI2_0, FN_SEL_VI2_1,
- FN_SEL_VI1_0, FN_SEL_VI1_1,
- FN_SEL_VI0_0, FN_SEL_VI0_1,
- FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
- FN_SEL_LBS_0, FN_SEL_LBS_1,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF3_0, FN_SEL_SOF3_1,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1,
-
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- FN_SEL_ADI_0, FN_SEL_ADI_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
- FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
- FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
- FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
- FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
-
- FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC2_4,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
- FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
- FN_SEL_I2C2_4,
- FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- VI1_DATA7_VI1_B7_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
- USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
- DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
-
- D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
- D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
- VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
- VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
- VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
- SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
- VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
- SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
- VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
- SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
- SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
- VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
- D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
- VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
-
- D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
- VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
- SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
- VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
- SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
- VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
- D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
- VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
- D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
- VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
- SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
- VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
- D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
- VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
- A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
-
- A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
- PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
- TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
- A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
- SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
- A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
- VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
- A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
- VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
- A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
- VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
-
- A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
- VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
- A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
- VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
- A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
- MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
- VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
- ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
- ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
- A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
- AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
- ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
- VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
-
- A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
- A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
- VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
- VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
- VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
- VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
- VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
- VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
- CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
- VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
- VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
- MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
- HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
- VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
- VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
-
- EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
- VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
- EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
- VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
- INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
- MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
- VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
- SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
- CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
- CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
- VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
- INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
- VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
- WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
- VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
- IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
- VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
- MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
- VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
- SSI_WS78_B_MARK,
-
- DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
- VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
- DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
- SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
- INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
- DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
- MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
- SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
- ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
- TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
- SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
- STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
- SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
- STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
- SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
- RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
- TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
- RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
- STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
- ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
- STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
-
- ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
- SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
- RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
- ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
- HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
- SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
- STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
- ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
- TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
- SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
- GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
- STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
- PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
- PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
- AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
- ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
- VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
- MII_RXD2_MARK,
-
- VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
- MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
- AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
- AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
- AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
- AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
- MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
- MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
- MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
- AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
- SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
- VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
- MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
- AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
- AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
- AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
- SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
- SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
-
- SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
- SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
- SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
- SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
- SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
- GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
- SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
- MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
- GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
- SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
- AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
- AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
- SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
- SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
- MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
- AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
- SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
- SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
- TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
- SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
- VI3_CLK_B_MARK,
-
- SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
- GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
- SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
- VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
- VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
- VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
- TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
- SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
- VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
- TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
- SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
- VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
- TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
- SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
- VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
- GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
- MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
- HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
- VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
- TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
- VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
- GLO_I0_B_MARK, VI3_DATA6_B_MARK,
-
- SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
- GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
- TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
- SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
- MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
- SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
- MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
- SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
- VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
- MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
- RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
- RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
- MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
- SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
- SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
- RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
- MOUT0_MARK,
-
- SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
- SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
- SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
- SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
- SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
- MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
- STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
- CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
- SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
- SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
- MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
- SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
- MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
- SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
- CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
- IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
- CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
- IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
- CAN_DEBUGOUT4_MARK,
-
- SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
- LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
- SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
- DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
- BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
- SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
- LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
- FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
- CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
- SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
- CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
- SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
- LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
- STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
- TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
- BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
- FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
- STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
- CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
- STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
- SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
- SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
-
- AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
- DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
- REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
- MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
- SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
- DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
- TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
- HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
- LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
- SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
- MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
- SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
- DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
- SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
- LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
- CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
- SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
- MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
- HRTS0_N_C_MARK,
-
- SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
- LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
- DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
- SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
- SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
- DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
- DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
- LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
- LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
- LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
- DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
- SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
- SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
- DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
- DU2_DG6_MARK, LCDOUT14_MARK,
-
- MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
- DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
- MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
- ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
- USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
- TCLK1_B_MARK,
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
- PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
- PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
- PINMUX_DATA(AVS1_MARK, FN_AVS1),
- PINMUX_DATA(AVS2_MARK, FN_AVS2),
- PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
- PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
-
- PINMUX_IPSR_DATA(IP6_2_0, DACK0),
- PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
- PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
- PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP6_8_6, DACK1),
- PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
- PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
- PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_13_11, DACK2),
- PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
- PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
- PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
- PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
- PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
- PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
- PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
- PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
- PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
-
- PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
- PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
- PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
- PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
- PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
- PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
- PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_18_16, PWM0),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PWM1),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
- PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
- PINMUX_IPSR_DATA(IP7_24_22, PWM2),
- PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
- PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
- PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
- PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
- PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
- PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
- PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
- PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
- PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
- PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
-
- PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
- PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
- PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
- PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
- PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
- PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
- PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
- PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
- PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
- PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
- PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
- PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
- PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
- PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
- PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
- PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
- PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
- PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
- PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
- PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
- PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
- PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
-
- PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
- PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
- PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
- PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
- PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
- PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
- PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
- PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
- PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
- PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
- PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
- PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
- PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
- PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
- PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
- PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
- PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
- PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
- PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
- PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
- PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
- PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
- PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
- PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
- PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
-
- PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
- PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
- PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
- PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
- PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
- PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
- PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
- PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
- PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
- PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
-
- PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
- PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
- PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
- PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
- PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
- PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
- PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
- PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
- PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
- PINMUX_IPSR_DATA(IP11_8_7, STM_N),
- PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
- PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
- PINMUX_IPSR_DATA(IP11_10_9, MDATA),
- PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
- PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
- PINMUX_IPSR_DATA(IP11_12_11, SDATA),
- PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
- PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
- PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
- PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
- PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
- PINMUX_IPSR_DATA(IP11_17_15, VSP),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
- PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
- PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
- PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
- PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
- PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
- PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
- PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
-
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS),
- GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2),
- GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2),
-
- /* IPSR0 - IPSR5 */
- /*IPSR6*/
- GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
- GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
- GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
- GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
- GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
- GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
- GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
- GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
- GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
- GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
- GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
- GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
- GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
- GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
- GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
- GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
- GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
- GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
- GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
- GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
- GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
- GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
-
- /*IPSR7*/
- GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
- GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
- GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
- GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
- GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
- GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
- GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
- GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
- GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
- GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
- GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
- GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
- GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
- GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
- GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
- GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
- GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
- GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
-
- /*IPSR8*/
- GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3),
- GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N),
- GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N),
- GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N),
- GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1),
- GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER),
- GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK),
- GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV),
- GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D),
- GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1),
- GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC),
- GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO),
- GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D),
- GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4),
- GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC),
- GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT),
- GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK),
- GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD),
- GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B),
-
- /*IPSR9*/
- GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B),
- GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B),
- GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B),
- GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B),
- GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B),
- GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B),
- GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B),
- GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B),
- GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B),
- GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN),
- GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER),
- GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK),
- GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1),
- GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B),
- GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL),
- GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0),
- GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD),
- GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP),
- GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D),
- GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B),
-
- /*IPSR10*/
- GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1),
- GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B),
- GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B),
- GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK),
- GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B),
- GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD),
- GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E),
- GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B),
- GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0),
- GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E),
- GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B),
- GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1),
- GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B),
- GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C),
- GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2),
- GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK),
- GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B),
- GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3),
- GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B),
- GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B),
- GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4),
- GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0),
- GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B),
- GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B),
-
- /*IPSR11*/
- GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B),
- GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B),
- GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B),
- GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK),
- GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0),
- GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1),
- GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA),
- GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD),
- GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0),
- GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5),
- GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B),
- GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F),
- GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B),
- GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D),
- GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT),
- GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C),
- GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129),
- GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0),
-
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP3_17_15,
- GP_0_30_FN, FN_IP3_14_12,
- GP_0_29_FN, FN_IP3_11_8,
- GP_0_28_FN, FN_IP3_7_4,
- GP_0_27_FN, FN_IP3_3_0,
- GP_0_26_FN, FN_IP2_28_26,
- GP_0_25_FN, FN_IP2_25_22,
- GP_0_24_FN, FN_IP2_21_18,
- GP_0_23_FN, FN_IP2_17_15,
- GP_0_22_FN, FN_IP2_14_12,
- GP_0_21_FN, FN_IP2_11_9,
- GP_0_20_FN, FN_IP2_8_6,
- GP_0_19_FN, FN_IP2_5_3,
- GP_0_18_FN, FN_IP2_2_0,
- GP_0_17_FN, FN_IP1_29_28,
- GP_0_16_FN, FN_IP1_27_26,
- GP_0_15_FN, FN_IP1_25_22,
- GP_0_14_FN, FN_IP1_21_18,
- GP_0_13_FN, FN_IP1_17_15,
- GP_0_12_FN, FN_IP1_14_12,
- GP_0_11_FN, FN_IP1_11_8,
- GP_0_10_FN, FN_IP1_7_4,
- GP_0_9_FN, FN_IP1_3_0,
- GP_0_8_FN, FN_IP0_30_27,
- GP_0_7_FN, FN_IP0_26_23,
- GP_0_6_FN, FN_IP0_22_20,
- GP_0_5_FN, FN_IP0_19_16,
- GP_0_4_FN, FN_IP0_15_12,
- GP_0_3_FN, FN_IP0_11_9,
- GP_0_2_FN, FN_IP0_8_6,
- GP_0_1_FN, FN_IP0_5_3,
- GP_0_0_FN, FN_IP0_2_0 }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- GP_1_29_FN, FN_IP6_13_11,
- GP_1_28_FN, FN_IP6_10_9,
- GP_1_27_FN, FN_IP6_8_6,
- GP_1_26_FN, FN_IP6_5_3,
- GP_1_25_FN, FN_IP6_2_0,
- GP_1_24_FN, FN_IP5_29_27,
- GP_1_23_FN, FN_IP5_26_24,
- GP_1_22_FN, FN_IP5_23_21,
- GP_1_21_FN, FN_IP5_20_18,
- GP_1_20_FN, FN_IP5_17_15,
- GP_1_19_FN, FN_IP5_14_13,
- GP_1_18_FN, FN_IP5_12_10,
- GP_1_17_FN, FN_IP5_9_6,
- GP_1_16_FN, FN_IP5_5_3,
- GP_1_15_FN, FN_IP5_2_0,
- GP_1_14_FN, FN_IP4_29_27,
- GP_1_13_FN, FN_IP4_26_24,
- GP_1_12_FN, FN_IP4_23_21,
- GP_1_11_FN, FN_IP4_20_18,
- GP_1_10_FN, FN_IP4_17_15,
- GP_1_9_FN, FN_IP4_14_12,
- GP_1_8_FN, FN_IP4_11_9,
- GP_1_7_FN, FN_IP4_8_6,
- GP_1_6_FN, FN_IP4_5_3,
- GP_1_5_FN, FN_IP4_2_0,
- GP_1_4_FN, FN_IP3_31_29,
- GP_1_3_FN, FN_IP3_28_26,
- GP_1_2_FN, FN_IP3_25_23,
- GP_1_1_FN, FN_IP3_22_20,
- GP_1_0_FN, FN_IP3_19_18, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_2_29_FN, FN_IP7_15_13,
- GP_2_28_FN, FN_IP7_12_10,
- GP_2_27_FN, FN_IP7_9_8,
- GP_2_26_FN, FN_IP7_7_6,
- GP_2_25_FN, FN_IP7_5_3,
- GP_2_24_FN, FN_IP7_2_0,
- GP_2_23_FN, FN_IP6_31_29,
- GP_2_22_FN, FN_IP6_28_26,
- GP_2_21_FN, FN_IP6_25_23,
- GP_2_20_FN, FN_IP6_22_20,
- GP_2_19_FN, FN_IP6_19_17,
- GP_2_18_FN, FN_IP6_16_14,
- GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
- GP_2_16_FN, FN_IP8_27,
- GP_2_15_FN, FN_IP8_26,
- GP_2_14_FN, FN_IP8_25_24,
- GP_2_13_FN, FN_IP8_23_22,
- GP_2_12_FN, FN_IP8_21_20,
- GP_2_11_FN, FN_IP8_19_18,
- GP_2_10_FN, FN_IP8_17_16,
- GP_2_9_FN, FN_IP8_15_14,
- GP_2_8_FN, FN_IP8_13_12,
- GP_2_7_FN, FN_IP8_11_10,
- GP_2_6_FN, FN_IP8_9_8,
- GP_2_5_FN, FN_IP8_7_6,
- GP_2_4_FN, FN_IP8_5_4,
- GP_2_3_FN, FN_IP8_3_2,
- GP_2_2_FN, FN_IP8_1_0,
- GP_2_1_FN, FN_IP7_30_29,
- GP_2_0_FN, FN_IP7_28_27 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP11_21_18,
- GP_3_30_FN, FN_IP11_17_15,
- GP_3_29_FN, FN_IP11_14_13,
- GP_3_28_FN, FN_IP11_12_11,
- GP_3_27_FN, FN_IP11_10_9,
- GP_3_26_FN, FN_IP11_8_7,
- GP_3_25_FN, FN_IP11_6_5,
- GP_3_24_FN, FN_IP11_4,
- GP_3_23_FN, FN_IP11_3_0,
- GP_3_22_FN, FN_IP10_29_26,
- GP_3_21_FN, FN_IP10_25_23,
- GP_3_20_FN, FN_IP10_22_19,
- GP_3_19_FN, FN_IP10_18_15,
- GP_3_18_FN, FN_IP10_14_11,
- GP_3_17_FN, FN_IP10_10_7,
- GP_3_16_FN, FN_IP10_6_4,
- GP_3_15_FN, FN_IP10_3_0,
- GP_3_14_FN, FN_IP9_31_28,
- GP_3_13_FN, FN_IP9_27_26,
- GP_3_12_FN, FN_IP9_25_24,
- GP_3_11_FN, FN_IP9_23_22,
- GP_3_10_FN, FN_IP9_21_20,
- GP_3_9_FN, FN_IP9_19_18,
- GP_3_8_FN, FN_IP9_17_16,
- GP_3_7_FN, FN_IP9_15_12,
- GP_3_6_FN, FN_IP9_11_8,
- GP_3_5_FN, FN_IP9_7_6,
- GP_3_4_FN, FN_IP9_5_4,
- GP_3_3_FN, FN_IP9_3_2,
- GP_3_2_FN, FN_IP9_1_0,
- GP_3_1_FN, FN_IP8_30_29,
- GP_3_0_FN, FN_IP8_28 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP14_18_16,
- GP_4_30_FN, FN_IP14_15_12,
- GP_4_29_FN, FN_IP14_11_9,
- GP_4_28_FN, FN_IP14_8_6,
- GP_4_27_FN, FN_IP14_5_3,
- GP_4_26_FN, FN_IP14_2_0,
- GP_4_25_FN, FN_IP13_30_29,
- GP_4_24_FN, FN_IP13_28_26,
- GP_4_23_FN, FN_IP13_25_23,
- GP_4_22_FN, FN_IP13_22_19,
- GP_4_21_FN, FN_IP13_18_16,
- GP_4_20_FN, FN_IP13_15_13,
- GP_4_19_FN, FN_IP13_12_10,
- GP_4_18_FN, FN_IP13_9_7,
- GP_4_17_FN, FN_IP13_6_3,
- GP_4_16_FN, FN_IP13_2_0,
- GP_4_15_FN, FN_IP12_30_28,
- GP_4_14_FN, FN_IP12_27_25,
- GP_4_13_FN, FN_IP12_24_23,
- GP_4_12_FN, FN_IP12_22_20,
- GP_4_11_FN, FN_IP12_19_17,
- GP_4_10_FN, FN_IP12_16_14,
- GP_4_9_FN, FN_IP12_13_11,
- GP_4_8_FN, FN_IP12_10_8,
- GP_4_7_FN, FN_IP12_7_6,
- GP_4_6_FN, FN_IP12_5_4,
- GP_4_5_FN, FN_IP12_3_2,
- GP_4_4_FN, FN_IP12_1_0,
- GP_4_3_FN, FN_IP11_31_30,
- GP_4_2_FN, FN_IP11_29_27,
- GP_4_1_FN, FN_IP11_26_24,
- GP_4_0_FN, FN_IP11_23_22 }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP7_24_22,
- GP_5_30_FN, FN_IP7_21_19,
- GP_5_29_FN, FN_IP7_18_16,
- GP_5_28_FN, FN_DU_DOTCLKIN2,
- GP_5_27_FN, FN_IP7_26_25,
- GP_5_26_FN, FN_DU_DOTCLKIN0,
- GP_5_25_FN, FN_AVS2,
- GP_5_24_FN, FN_AVS1,
- GP_5_23_FN, FN_USB2_OVC,
- GP_5_22_FN, FN_USB2_PWEN,
- GP_5_21_FN, FN_IP16_7,
- GP_5_20_FN, FN_IP16_6,
- GP_5_19_FN, FN_USB0_OVC_VBUS,
- GP_5_18_FN, FN_USB0_PWEN,
- GP_5_17_FN, FN_IP16_5_3,
- GP_5_16_FN, FN_IP16_2_0,
- GP_5_15_FN, FN_IP15_29_28,
- GP_5_14_FN, FN_IP15_27_26,
- GP_5_13_FN, FN_IP15_25_23,
- GP_5_12_FN, FN_IP15_22_20,
- GP_5_11_FN, FN_IP15_19_18,
- GP_5_10_FN, FN_IP15_17_16,
- GP_5_9_FN, FN_IP15_15_14,
- GP_5_8_FN, FN_IP15_13_12,
- GP_5_7_FN, FN_IP15_11_9,
- GP_5_6_FN, FN_IP15_8_6,
- GP_5_5_FN, FN_IP15_5_3,
- GP_5_4_FN, FN_IP15_2_0,
- GP_5_3_FN, FN_IP14_30_28,
- GP_5_2_FN, FN_IP14_27_25,
- GP_5_1_FN, FN_IP14_24_22,
- GP_5_0_FN, FN_IP14_21_19 }
- },
- /* IPSR0 - IPSR5 */
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
- /* IP6_31_29 [3] */
- FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
- FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
- /* IP6_28_26 [3] */
- FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
- FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
- /* IP6_25_23 [3] */
- FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
- FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
- /* IP6_22_20 [3] */
- FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
- FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
- /* IP6_19_17 [3] */
- FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
- FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
- /* IP6_16_14 [3] */
- FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
- FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
- FN_SCL2_CIS_E, 0,
- /* IP6_13_11 [3] */
- FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
- FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
- /* IP6_10_9 [2] */
- FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
- /* IP6_8_6 [3] */
- FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
- FN_SSI_SDATA8_C, 0, 0, 0,
- /* IP6_5_3 [3] */
- FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
- FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
- /* IP6_2_0 [3] */
- FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
- FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
- /* IP7_31 [1] */
- 0, 0,
- /* IP7_30_29 [2] */
- FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
- FN_MII_RXD2,
- /* IP7_28_27 [2] */
- FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
- /* IP7_26_25 [2] */
- FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
- /* IP7_24_22 [3] */
- FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
- 0, 0, 0,
- /* IP7_21_19 [3] */
- FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
- FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
- /* IP7_18_16 [3] */
- FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
- FN_GLO_SS_C, 0, 0, 0,
- /* IP7_15_13 [3] */
- FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
- FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
- /* IP7_12_10 [3] */
- FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
- FN_GLO_SCLK_C, 0, 0, 0,
- /* IP7_9_8 [2] */
- FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
- /* IP7_7_6 [2] */
- FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
- /* IP7_5_3 [3] */
- FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
- 0, 0, 0,
- /* IP7_2_0 [3] */
- FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
- FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2) {
- /* IP8_31 [1] */
- 0, 0,
- /* IP8_30_29 [2] */
- FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
- /* IP8_28 [1] */
- FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
- /* IP8_27 [1] */
- FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
- /* IP8_26 [1] */
- FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
- /* IP8_25_24 [2] */
- FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
- FN_AVB_MAGIC, FN_MII_MAGIC,
- /* IP8_23_22 [2] */
- FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
- /* IP8_21_20 [2] */
- FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
- FN_MII_MDIO,
- /* IP8_19_18 [2] */
- FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
- /* IP8_17_16 [2] */
- FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
- /* IP8_15_14 [2] */
- FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
- /* IP8_13_12 [2] */
- FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
- /* IP8_11_10 [2] */
- FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
- /* IP8_9_8 [2] */
- FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
- /* IP8_7_6 [2] */
- FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
- /* IP8_5_4 [2] */
- FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
- /* IP8_3_2 [2] */
- FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
- /* IP8_1_0 [2] */
- FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
- },
- { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
- 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
- /* IP9_31_28 [4] */
- FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
- FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
- FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
- /* IP9_27_26 [2] */
- FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
- /* IP9_25_24 [2] */
- FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
- /* IP9_23_22 [2] */
- FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
- /* IP9_21_20 [2] */
- FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
- /* IP9_19_18 [2] */
- FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
- /* IP9_17_16 [2] */
- FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
- /* IP9_15_12 [4] */
- FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
- FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
- FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
- /* IP9_11_8 [4] */
- FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
- FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
- FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
- /* IP9_7_6 [2] */
- FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
- /* IP9_5_4 [2] */
- FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
- /* IP9_3_2 [2] */
- FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
- /* IP9_1_0 [2] */
- FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
- 2, 4, 3, 4, 4, 4, 4, 3, 4) {
- /* IP10_31_30 [2] */
- 0, 0, 0, 0,
- /* IP10_29_26 [4] */
- FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
- FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
- FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
- /* IP10_25_23 [3] */
- FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
- FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
- /* IP10_22_19 [4] */
- FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
- FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
- FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
- /* IP10_18_15 [4] */
- FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
- FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
- FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
- 0, 0, 0, 0, 0, 0,
- /* IP10_14_11 [4] */
- FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
- FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
- FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
- 0, 0, 0, 0, 0, 0, 0,
- /* IP10_10_7 [4] */
- FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
- FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
- FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
- 0, 0, 0, 0, 0, 0, 0,
- /* IP10_6_4 [3] */
- FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
- FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
- FN_VI3_DATA0_B, 0,
- /* IP10_3_0 [4] */
- FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
- FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
- FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
- /* IP11_31_30 [2] */
- FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
- /* IP11_29_27 [3] */
- FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
- FN_RDS_CLK_B, 0, 0,
- /* IP11_26_24 [3] */
- FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
- 0, 0, 0,
- /* IP11_23_22 [2] */
- FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
- /* IP11_21_18 [4] */
- FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
- FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
- FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
- /* IP11_17_15 [3] */
- FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
- FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
- /* IP11_14_13 [2] */
- FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
- /* IP11_12_11 [2] */
- FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
- /* IP11_10_9 [2] */
- FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
- /* IP11_8_7 [2] */
- FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
- /* IP11_6_5 [2] */
- FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
- /* IP11_4 [1] */
- FN_SD3_CLK, FN_MMC1_CLK,
- /* IP11_3_0 [4] */
- FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
- FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
- FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
- 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
- /* SEL_SCIF1 [3] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIF1_4, 0, 0, 0,
- /* SEL_SCIFB [2] */
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
- /* SEL_SCIFB2 [2] */
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
- /* SEL_SCIFB1 [3] */
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
- FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
- FN_SEL_SCIFB1_6, 0,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
- FN_SEL_SCIFA1_3,
- /* SEL_SCIF0 [1] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
- /* SEL_SCIFA [1] */
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- /* SEL_SOF1 [1] */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1,
- /* SEL_SSI7 [2] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
- /* SEL_SSI6 [1] */
- FN_SEL_SSI6_0, FN_SEL_SSI6_1,
- /* SEL_SSI5 [2] */
- FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
- /* SEL_VI3 [1] */
- FN_SEL_VI3_0, FN_SEL_VI3_1,
- /* SEL_VI2 [1] */
- FN_SEL_VI2_0, FN_SEL_VI2_1,
- /* SEL_VI1 [1] */
- FN_SEL_VI1_0, FN_SEL_VI1_1,
- /* SEL_VI0 [1] */
- FN_SEL_VI0_0, FN_SEL_VI0_1,
- /* SEL_TSIF1 [2] */
- FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
- /* RESERVED [1] */
- 0, 0,
- /* SEL_LBS [1] */
- FN_SEL_LBS_0, FN_SEL_LBS_1,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_SOF3 [1] */
- FN_SEL_SOF3_0, FN_SEL_SOF3_1,
- /* SEL_SOF0 [1] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 2, 1, 1, 1, 1, 2, 1, 2, 1,
- 2, 1, 1, 1, 3, 3, 2, 3, 2, 2) {
- /* RESEVED [2] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_TMU1 [1] */
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- /* SEL_HSCIF1 [1] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* SEL_SCIFCLK [1] */
- FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
- /* SEL_CAN0 [2] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- /* SEL_CANCLK [1] */
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- /* SEL_SCIFA2 [2] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
- /* SEL_CAN1 [1] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- /* RESEVED [2] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_ADI [1] */
- FN_SEL_ADI_0, FN_SEL_ADI_1,
- /* SEL_SSP [1] */
- FN_SEL_SSP_0, FN_SEL_SSP_1,
- /* SEL_FM [3] */
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
- FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
- /* SEL_HSCIF0 [3] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
- FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
- /* SEL_GPS [2] */
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
- /* SEL_RDS [3] */
- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
- FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
- /* SEL_SIM [2] */
- FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
- /* SEL_SSI8 [2] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 1, 1, 2, 4, 4, 2, 2,
- 4, 2, 3, 2, 3, 2) {
- /* SEL_IICDVFS [1] */
- FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
- /* SEL_IIC0 [1] */
- FN_SEL_IIC0_0, FN_SEL_IIC0_1,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* RESEVED [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IIC2 [3] */
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC2_4, 0, 0, 0,
- /* SEL_IIC1 [2] */
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
- /* SEL_I2C2 [3] */
- FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
- FN_SEL_I2C2_4, 0, 0, 0,
- /* SEL_I2C1 [2] */
- FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- GP_1_29_IN, GP_1_29_OUT,
- GP_1_28_IN, GP_1_28_OUT,
- GP_1_27_IN, GP_1_27_OUT,
- GP_1_26_IN, GP_1_26_OUT,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
- 0, 0,
- 0, 0,
- GP_2_29_IN, GP_2_29_OUT,
- GP_2_28_IN, GP_2_28_OUT,
- GP_2_27_IN, GP_2_27_OUT,
- GP_2_26_IN, GP_2_26_OUT,
- GP_2_25_IN, GP_2_25_OUT,
- GP_2_24_IN, GP_2_24_OUT,
- GP_2_23_IN, GP_2_23_OUT,
- GP_2_22_IN, GP_2_22_OUT,
- GP_2_21_IN, GP_2_21_OUT,
- GP_2_20_IN, GP_2_20_OUT,
- GP_2_19_IN, GP_2_19_OUT,
- GP_2_18_IN, GP_2_18_OUT,
- GP_2_17_IN, GP_2_17_OUT,
- GP_2_16_IN, GP_2_16_OUT,
- GP_2_15_IN, GP_2_15_OUT,
- GP_2_14_IN, GP_2_14_OUT,
- GP_2_13_IN, GP_2_13_OUT,
- GP_2_12_IN, GP_2_12_OUT,
- GP_2_11_IN, GP_2_11_OUT,
- GP_2_10_IN, GP_2_10_OUT,
- GP_2_9_IN, GP_2_9_OUT,
- GP_2_8_IN, GP_2_8_OUT,
- GP_2_7_IN, GP_2_7_OUT,
- GP_2_6_IN, GP_2_6_OUT,
- GP_2_5_IN, GP_2_5_OUT,
- GP_2_4_IN, GP_2_4_OUT,
- GP_2_3_IN, GP_2_3_OUT,
- GP_2_2_IN, GP_2_2_OUT,
- GP_2_1_IN, GP_2_1_OUT,
- GP_2_0_IN, GP_2_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, GP_1_29_DATA, GP_1_28_DATA,
- GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
- 0, 0, GP_2_29_DATA, GP_2_28_DATA,
- GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
- GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
- GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
- GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
- GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
- GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
- GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
- },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { },
-};
-
-static struct pinmux_info r8a7790_pinmux_info = {
- .name = "r8a7790_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MOUT0,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7790_pinmux_init(void)
-{
- register_pinmux(&r8a7790_pinmux_info);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-#include "pfc-r8a7790.h"
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
- FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
- FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
- FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
- FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
- FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
-
- /* GPSR1 */
- FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
- FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
- FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
- FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
- FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
- FN_IP3_21_20,
-
- /* GPSR2 */
- FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
- FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
- FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
- FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
- FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
- FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
- FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
- FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
- FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
- FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
- FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
- FN_IP9_18_17,
-
- /* GPSR4 */
- FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
- FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
- FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
- FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
- FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
- FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
- FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
-
- /* GPSR5 */
- FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
- FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
- FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
- FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
- FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
- FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
-
- /* GPSR6 */
- FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
- FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
- FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
- FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
- FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
- FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
-
- /* GPSR7 */
- FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
- FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
- FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
- FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
- FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
- FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
-
- /* IPSR0 - IPSR10 */
-
- /* IPSR11 */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
- FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
- FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
- FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
- FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
- FN_VI1_DATA7, FN_AVB_MDC,
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
-
- /* IPSR12 */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- /* MOD_SEL */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
- FN_SEL_HSCIF1_4,
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
-
- /* MOD_SEL2 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF0_4,
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-
- /* MOD_SEL3 */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
-
- /* MOD_SEL4 */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
- FN_SEL_SCIF2_4,
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
- FN_SEL_SOF2_4,
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- EX_CS0_N_MARK, RD_N_MARK,
-
- AUDIO_CLKA_MARK,
-
- VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
- VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
- VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
-
- /* IPSR0 IPSR10 */
- /* IPSR11 */
- VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
- VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
- VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
- SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
- VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
- TX4_B_MARK, SCIFA4_TXD_B_MARK,
- VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
- RX4_B_MARK, SCIFA4_RXD_B_MARK,
- VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
- VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
- VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
- VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
- VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
- VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
- VI1_DATA7_MARK, AVB_MDC_MARK,
- ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
- ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
-
- /* IPSR12 */
- ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
- ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
- ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
- SCL2_D_MARK, MSIOF1_RXD_E_MARK,
- ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
- SDA2_D_MARK, MSIOF1_SCK_E_MARK,
- ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
- CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
- ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
- CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
- ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
- ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
- ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
- ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
- STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
- ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
- STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
- ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
-
- /* IPSR13 */
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- /* OTHER IPSR0 - IPSR10 */
- /* IPSR11 */
- PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
- PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
- PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
- PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
- PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
- PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
- PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
- PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
- PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
- PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
- PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
-
- /* IPSR12 */
- PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
- PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
- PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
- PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
- PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
- PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
- PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
- PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
-
- /* IPSR13 - IPSR16 */
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- /* OTHER, IPSR0 - IPSR10 */
- /* IPSR11 */
- GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
- GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
- GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
- GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
- GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
- GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
- GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
- GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
- GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
- GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
- GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
- GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
- GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
- GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
- GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
- GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
- GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
- GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
- GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
- GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
-
- /* IPSR12 */
- GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
- GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
- GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
- GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
- GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
- GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
- GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
- GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
- GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
- GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
- GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
- GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
- GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
- GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
-
- /* IPSR13 - IPSR16 */
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP1_22_20,
- GP_0_30_FN, FN_IP1_19_17,
- GP_0_29_FN, FN_IP1_16_14,
- GP_0_28_FN, FN_IP1_13_11,
- GP_0_27_FN, FN_IP1_10_8,
- GP_0_26_FN, FN_IP1_7_6,
- GP_0_25_FN, FN_IP1_5_4,
- GP_0_24_FN, FN_IP1_3_2,
- GP_0_23_FN, FN_IP1_1_0,
- GP_0_22_FN, FN_IP0_30_29,
- GP_0_21_FN, FN_IP0_28_27,
- GP_0_20_FN, FN_IP0_26_25,
- GP_0_19_FN, FN_IP0_24_23,
- GP_0_18_FN, FN_IP0_22_21,
- GP_0_17_FN, FN_IP0_20_19,
- GP_0_16_FN, FN_IP0_18_16,
- GP_0_15_FN, FN_IP0_15,
- GP_0_14_FN, FN_IP0_14,
- GP_0_13_FN, FN_IP0_13,
- GP_0_12_FN, FN_IP0_12,
- GP_0_11_FN, FN_IP0_11,
- GP_0_10_FN, FN_IP0_10,
- GP_0_9_FN, FN_IP0_9,
- GP_0_8_FN, FN_IP0_8,
- GP_0_7_FN, FN_IP0_7,
- GP_0_6_FN, FN_IP0_6,
- GP_0_5_FN, FN_IP0_5,
- GP_0_4_FN, FN_IP0_4,
- GP_0_3_FN, FN_IP0_3,
- GP_0_2_FN, FN_IP0_2,
- GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_IP3_21_20,
- GP_1_24_FN, FN_IP3_19_18,
- GP_1_23_FN, FN_IP3_17_16,
- GP_1_22_FN, FN_IP3_15_14,
- GP_1_21_FN, FN_IP3_13_12,
- GP_1_20_FN, FN_IP3_11_9,
- GP_1_19_FN, FN_RD_N,
- GP_1_18_FN, FN_IP3_8_6,
- GP_1_17_FN, FN_IP3_5_3,
- GP_1_16_FN, FN_IP3_2_0,
- GP_1_15_FN, FN_IP2_29_27,
- GP_1_14_FN, FN_IP2_26_25,
- GP_1_13_FN, FN_IP2_24_23,
- GP_1_12_FN, FN_EX_CS0_N,
- GP_1_11_FN, FN_IP2_22_21,
- GP_1_10_FN, FN_IP2_20_19,
- GP_1_9_FN, FN_IP2_18_16,
- GP_1_8_FN, FN_IP2_15_13,
- GP_1_7_FN, FN_IP2_12_10,
- GP_1_6_FN, FN_IP2_9_7,
- GP_1_5_FN, FN_IP2_6_5,
- GP_1_4_FN, FN_IP2_4_3,
- GP_1_3_FN, FN_IP2_2_0,
- GP_1_2_FN, FN_IP1_31_29,
- GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_3,
- GP_2_29_FN, FN_IP6_2_0,
- GP_2_28_FN, FN_AUDIO_CLKA,
- GP_2_27_FN, FN_IP5_31_29,
- GP_2_26_FN, FN_IP5_28_26,
- GP_2_25_FN, FN_IP5_25_24,
- GP_2_24_FN, FN_IP5_23_22,
- GP_2_23_FN, FN_IP5_21_20,
- GP_2_22_FN, FN_IP5_19_17,
- GP_2_21_FN, FN_IP5_16_15,
- GP_2_20_FN, FN_IP5_14_12,
- GP_2_19_FN, FN_IP5_11_9,
- GP_2_18_FN, FN_IP5_8_6,
- GP_2_17_FN, FN_IP5_5_3,
- GP_2_16_FN, FN_IP5_2_0,
- GP_2_15_FN, FN_IP4_30_28,
- GP_2_14_FN, FN_IP4_27_26,
- GP_2_13_FN, FN_IP4_25_24,
- GP_2_12_FN, FN_IP4_23_22,
- GP_2_11_FN, FN_IP4_21,
- GP_2_10_FN, FN_IP4_20,
- GP_2_9_FN, FN_IP4_19,
- GP_2_8_FN, FN_IP4_18_16,
- GP_2_7_FN, FN_IP4_15_13,
- GP_2_6_FN, FN_IP4_12_10,
- GP_2_5_FN, FN_IP4_9_8,
- GP_2_4_FN, FN_IP4_7_5,
- GP_2_3_FN, FN_IP4_4_2,
- GP_2_2_FN, FN_IP4_1_0,
- GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP9_18_17,
- GP_3_30_FN, FN_IP9_16,
- GP_3_29_FN, FN_IP9_15_13,
- GP_3_28_FN, FN_IP9_12,
- GP_3_27_FN, FN_IP9_11,
- GP_3_26_FN, FN_IP9_10_8,
- GP_3_25_FN, FN_IP9_7,
- GP_3_24_FN, FN_IP9_6,
- GP_3_23_FN, FN_IP9_5_3,
- GP_3_22_FN, FN_IP9_2_0,
- GP_3_21_FN, FN_IP8_30_28,
- GP_3_20_FN, FN_IP8_27_26,
- GP_3_19_FN, FN_IP8_25_24,
- GP_3_18_FN, FN_IP8_23_21,
- GP_3_17_FN, FN_IP8_20_18,
- GP_3_16_FN, FN_IP8_17_15,
- GP_3_15_FN, FN_IP8_14_12,
- GP_3_14_FN, FN_IP8_11_9,
- GP_3_13_FN, FN_IP8_8_6,
- GP_3_12_FN, FN_IP8_5_3,
- GP_3_11_FN, FN_IP8_2_0,
- GP_3_10_FN, FN_IP7_29_27,
- GP_3_9_FN, FN_IP7_26_24,
- GP_3_8_FN, FN_IP7_23_21,
- GP_3_7_FN, FN_IP7_20_19,
- GP_3_6_FN, FN_IP7_18_17,
- GP_3_5_FN, FN_IP7_16_15,
- GP_3_4_FN, FN_IP7_14_13,
- GP_3_3_FN, FN_IP7_12_11,
- GP_3_2_FN, FN_IP7_10_9,
- GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP15_5_4,
- GP_4_30_FN, FN_IP15_3_2,
- GP_4_29_FN, FN_IP15_1_0,
- GP_4_28_FN, FN_IP11_8_6,
- GP_4_27_FN, FN_IP11_5_3,
- GP_4_26_FN, FN_IP11_2_0,
- GP_4_25_FN, FN_IP10_31_29,
- GP_4_24_FN, FN_IP10_28_27,
- GP_4_23_FN, FN_IP10_26_25,
- GP_4_22_FN, FN_IP10_24_22,
- GP_4_21_FN, FN_IP10_21_19,
- GP_4_20_FN, FN_IP10_18_17,
- GP_4_19_FN, FN_IP10_16_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_31_29,
- GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
- GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
- GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
- GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
- GP_4_8_FN, FN_IP9_28_27,
- GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
- GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
- GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
- GP_4_4_FN, FN_IP9_26_25,
- GP_4_3_FN, FN_IP9_24_23,
- GP_4_2_FN, FN_IP9_22_21,
- GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP3_24_22,
- GP_5_30_FN, FN_IP13_9_7,
- GP_5_29_FN, FN_IP13_6_5,
- GP_5_28_FN, FN_IP13_4_3,
- GP_5_27_FN, FN_IP13_2_0,
- GP_5_26_FN, FN_IP12_29_27,
- GP_5_25_FN, FN_IP12_26_24,
- GP_5_24_FN, FN_IP12_23_22,
- GP_5_23_FN, FN_IP12_21_20,
- GP_5_22_FN, FN_IP12_19_18,
- GP_5_21_FN, FN_IP12_17_16,
- GP_5_20_FN, FN_IP12_15_13,
- GP_5_19_FN, FN_IP12_12_10,
- GP_5_18_FN, FN_IP12_9_7,
- GP_5_17_FN, FN_IP12_6_4,
- GP_5_16_FN, FN_IP12_3_2,
- GP_5_15_FN, FN_IP12_1_0,
- GP_5_14_FN, FN_IP11_31_30,
- GP_5_13_FN, FN_IP11_29_28,
- GP_5_12_FN, FN_IP11_27,
- GP_5_11_FN, FN_IP11_26,
- GP_5_10_FN, FN_IP11_25,
- GP_5_9_FN, FN_IP11_24,
- GP_5_8_FN, FN_IP11_23,
- GP_5_7_FN, FN_IP11_22,
- GP_5_6_FN, FN_IP11_21,
- GP_5_5_FN, FN_IP11_20,
- GP_5_4_FN, FN_IP11_19,
- GP_5_3_FN, FN_IP11_18_17,
- GP_5_2_FN, FN_IP11_16_15,
- GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_6_29_FN, FN_IP14_31_29,
- GP_6_28_FN, FN_IP14_28_26,
- GP_6_27_FN, FN_IP14_25_23,
- GP_6_26_FN, FN_IP14_22_20,
- GP_6_25_FN, FN_IP14_19_17,
- GP_6_24_FN, FN_IP14_16_14,
- GP_6_23_FN, FN_IP14_13_11,
- GP_6_22_FN, FN_IP14_10_8,
- GP_6_21_FN, FN_IP14_7,
- GP_6_20_FN, FN_IP14_6,
- GP_6_19_FN, FN_IP14_5,
- GP_6_18_FN, FN_IP14_4,
- GP_6_17_FN, FN_IP14_3,
- GP_6_16_FN, FN_IP14_2,
- GP_6_15_FN, FN_IP14_1_0,
- GP_6_14_FN, FN_IP13_30_28,
- GP_6_13_FN, FN_IP13_27,
- GP_6_12_FN, FN_IP13_26,
- GP_6_11_FN, FN_IP13_25,
- GP_6_10_FN, FN_IP13_24_23,
- GP_6_9_FN, FN_IP13_22,
- 0, 0,
- GP_6_7_FN, FN_IP13_21_19,
- GP_6_6_FN, FN_IP13_18_16,
- GP_6_5_FN, FN_IP13_15,
- GP_6_4_FN, FN_IP13_14,
- GP_6_3_FN, FN_IP13_13,
- GP_6_2_FN, FN_IP13_12,
- GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
- },
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_FN, FN_USB1_PWEN,
- GP_7_24_FN, FN_USB0_OVC,
- GP_7_23_FN, FN_USB0_PWEN,
- GP_7_22_FN, FN_IP15_14_12,
- GP_7_21_FN, FN_IP15_11_9,
- GP_7_20_FN, FN_IP15_8_6,
- GP_7_19_FN, FN_IP7_2_0,
- GP_7_18_FN, FN_IP6_29_27,
- GP_7_17_FN, FN_IP6_26_24,
- GP_7_16_FN, FN_IP6_23_21,
- GP_7_15_FN, FN_IP6_20_19,
- GP_7_14_FN, FN_IP6_18_16,
- GP_7_13_FN, FN_IP6_15_14,
- GP_7_12_FN, FN_IP6_13_12,
- GP_7_11_FN, FN_IP6_11_10,
- GP_7_10_FN, FN_IP6_9_8,
- GP_7_9_FN, FN_IP16_11_10,
- GP_7_8_FN, FN_IP16_9_8,
- GP_7_7_FN, FN_IP16_7_6,
- GP_7_6_FN, FN_IP16_5_3,
- GP_7_5_FN, FN_IP16_2_0,
- GP_7_4_FN, FN_IP15_29_27,
- GP_7_3_FN, FN_IP15_26_24,
- GP_7_2_FN, FN_IP15_23_21,
- GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
- },
- /* IPSR0 - IPSR10 */
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
- /* IP11_31_30 [2] */
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
- /* IP11_29_28 [2] */
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
- /* IP11_27 [1] */
- FN_VI1_DATA7, FN_AVB_MDC,
- /* IP11_26 [1] */
- FN_VI1_DATA6, FN_AVB_MAGIC,
- /* IP11_25 [1] */
- FN_VI1_DATA5, FN_AVB_RX_DV,
- /* IP11_24 [1] */
- FN_VI1_DATA4, FN_AVB_MDIO,
- /* IP11_23 [1] */
- FN_VI1_DATA3, FN_AVB_RX_ER,
- /* IP11_22 [1] */
- FN_VI1_DATA2, FN_AVB_RXD7,
- /* IP11_21 [1] */
- FN_VI1_DATA1, FN_AVB_RXD6,
- /* IP11_20 [1] */
- FN_VI1_DATA0, FN_AVB_RXD5,
- /* IP11_19 [1] */
- FN_VI1_CLK, FN_AVB_RXD4,
- /* IP11_18_17 [2] */
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
- /* IP11_16_15 [2] */
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
- /* IP11_14_12 [3] */
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
- FN_RX4_B, FN_SCIFA4_RXD_B,
- 0, 0, 0,
- /* IP11_11_9 [3] */
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
- FN_TX4_B, FN_SCIFA4_TXD_B,
- 0, 0, 0,
- /* IP11_8_6 [3] */
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
- /* IP11_5_3 [3] */
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
- /* IP12_29_27 [3] */
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
- 0, 0, 0,
- /* IP12_26_24 [3] */
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- 0, 0, 0,
- /* IP12_23_22 [2] */
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
- /* IP12_21_20 [2] */
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
- /* IP12_19_18 [2] */
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
- /* IP12_17_16 [2] */
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- /* IP12_15_13 [3] */
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- 0, 0, 0,
- /* IP12_12_10 [3] */
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- 0, 0, 0,
- /* IP12_9_7 [3] */
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
- FN_SDA2_D, FN_MSIOF1_SCK_E,
- 0, 0, 0,
- /* IP12_6_4 [3] */
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- 0, 0, 0,
- /* IP12_3_2 [2] */
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- /* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
- },
-
- /* IPSR13 - IPSR16 */
-
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- /* SEL_SCIFB [2] */
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- /* SEL_SCIFB2 [2] */
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
- FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- /* SEL_SCIFB1 [3] */
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
- FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- 0, 0, 0, 0,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* SEL_SCFA [1] */
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- /* SEL_QSP [1] */
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_HSCIF1 [3] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
- FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_VI1 [2] */
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_TMU [1] */
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- /* SEL_LBS [2] */
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
- /* SEL_SCIF0 [3] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
- FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF [1] */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* SEL_CAN0 [3] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- 0, 0,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIF4 [2] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_ADG [1] */
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- /* SEL_FM [3] */
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
- FN_SEL_FM_3, FN_SEL_FM_4,
- 0, 0, 0,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_GPS [2] */
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
- /* SEL_SCIFA3 [2] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
- /* SEL_SIM [1] */
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
- /* SEL_HSCIF2 [2] */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- /* SEL_CANCLK [2] */
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- /* SEL_IIC8 [2] */
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
- /* SEL_IIC7 [2] */
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
- /* SEL_IIC4 [2] */
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
- /* SEL_IIC3 [2] */
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- /* SEL_SCIF3 [2] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_MMC [1] */
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- /* SEL_SCIF5 [1] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IIC2 [2] */
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- /* SEL_IIC1 [3] */
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- 0, 0, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
- /* SEL_SOF1 [3] */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- 0, 0, 0,
- /* SEL_HSCIF0 [2] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
- /* SEL_DIS [2] */
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIF2 [3] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
- FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_SOF2 [3] */
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
- FN_SEL_SOF2_3, FN_SEL_SOF2_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI0 [1] */
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- /* SEL_SSP [2] */
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_IN, GP_7_25_OUT,
- GP_7_24_IN, GP_7_24_OUT,
- GP_7_23_IN, GP_7_23_OUT,
- GP_7_22_IN, GP_7_22_OUT,
- GP_7_21_IN, GP_7_21_OUT,
- GP_7_20_IN, GP_7_20_OUT,
- GP_7_19_IN, GP_7_19_OUT,
- GP_7_18_IN, GP_7_18_OUT,
- GP_7_17_IN, GP_7_17_OUT,
- GP_7_16_IN, GP_7_16_OUT,
- GP_7_15_IN, GP_7_15_OUT,
- GP_7_14_IN, GP_7_14_OUT,
- GP_7_13_IN, GP_7_13_OUT,
- GP_7_12_IN, GP_7_12_OUT,
- GP_7_11_IN, GP_7_11_OUT,
- GP_7_10_IN, GP_7_10_OUT,
- GP_7_9_IN, GP_7_9_OUT,
- GP_7_8_IN, GP_7_8_OUT,
- GP_7_7_IN, GP_7_7_OUT,
- GP_7_6_IN, GP_7_6_OUT,
- GP_7_5_IN, GP_7_5_OUT,
- GP_7_4_IN, GP_7_4_OUT,
- GP_7_3_IN, GP_7_3_OUT,
- GP_7_2_IN, GP_7_2_OUT,
- GP_7_1_IN, GP_7_1_OUT,
- GP_7_0_IN, GP_7_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_7_25_DATA, GP_7_24_DATA,
- GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
- GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
- GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
- GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
- GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7791_pinmux_info = {
- .name = "r8a7791_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7791_pinmux_init(void)
-{
- register_pinmux(&r8a7791_pinmux_info);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7792.c
- * This file is r8a7792 processor support - PFC hardware block.
- *
- * Copyright (C) 2016 Renesas Electronics Corporation
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-#include "pfc-r8a7790.h"
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3,
- FN_IP0_4, FN_IP0_5, FN_IP0_6, FN_IP0_7,
- FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
- FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15,
- FN_IP0_16, FN_IP0_17, FN_IP0_18, FN_IP0_19,
- FN_IP0_20, FN_IP0_21, FN_IP0_22, FN_IP0_23,
- FN_IP1_0, FN_IP1_1, FN_IP1_2, FN_IP1_3,
- FN_IP1_4,
-
- /* GPSR1 */
- FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8,
- FN_IP1_9, FN_IP1_10, FN_IP1_11, FN_IP1_12,
- FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
- FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14, FN_DU1_DB5_C3_DATA15,
- FN_DU1_DB6_C4, FN_DU1_DB7_C5, FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
-
- /* GPSR2 */
- FN_D0, FN_D1, FN_D2, FN_D3,
- FN_D4, FN_D5, FN_D6, FN_D7,
- FN_D8, FN_D9, FN_D10, FN_D11,
- FN_D12, FN_D13, FN_D14, FN_D15,
- FN_A0, FN_A1, FN_A2, FN_A3,
- FN_A4, FN_A5, FN_A6, FN_A7,
- FN_A8, FN_A9, FN_A10, FN_A11,
- FN_A12, FN_A13, FN_A14, FN_A15,
-
- /* GPSR3 */
- FN_A16, FN_A17, FN_A18, FN_A19,
- FN_IP1_17, FN_IP1_18, FN_CS1_A26, FN_EX_CS0,
- FN_EX_CS1, FN_EX_CS2, FN_EX_CS3, FN_EX_CS4,
- FN_EX_CS5, FN_BS, FN_RD, FN_RD_WR,
- FN_WE0, FN_WE1, FN_EX_WAIT0, FN_IRQ0,
- FN_IRQ1, FN_IRQ2, FN_IRQ3, FN_IP1_19,
- FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0,
-
- /* GPSR4 */
- FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC, FN_VI0_VSYNC,
- FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
- FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
- FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
- FN_VI0_FIELD,
-
- /* GPSR5 */
- FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC, FN_VI1_VSYNC,
- FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
- FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
- FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
- FN_VI1_FIELD,
-
- /* GPSR6 */
- FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3,
- FN_IP2_4, FN_IP2_5, FN_IP2_6, FN_IP2_7,
- FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11,
- FN_IP2_12, FN_IP2_13, FN_IP2_14, FN_IP2_15,
- FN_IP2_16,
-
- /* GPSR7 */
- FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3,
- FN_IP3_4, FN_IP3_5, FN_IP3_6, FN_IP3_7,
- FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11,
- FN_IP3_12, FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14,
- FN_VI3_FIELD,
-
- /* GPSR8 */
- FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2,
- FN_IP4_4, FN_IP4_6_5, FN_IP4_8_7, FN_IP4_10_9,
- FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15, FN_IP4_18_17,
- FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
-
- /* GPSR9 */
- FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2,
- FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
- FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10,
- FN_IP5_11, FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3,
- FN_VI5_FIELD,
-
- /* GPSR10 */
- FN_IP6_0, FN_IP6_1, FN_HRTS0, FN_IP6_2,
- FN_IP6_3, FN_IP6_4, FN_IP6_5, FN_HCTS1,
- FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0,
- FN_RTS0, FN_TX0, FN_RX0, FN_SCK1,
- FN_CTS1, FN_RTS1, FN_TX1, FN_RX1,
- FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
- FN_IP6_16, FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX,
- FN_CAN0_RX, FN_CAN_CLK, FN_CAN1_TX, FN_CAN1_RX,
-
- /* GPSR11 */
- FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6,
- FN_IP7_7, FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DAT0,
- FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3, FN_SD0_CD,
- FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
- FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18,
- FN_IP7_19, FN_IP7_20, FN_ADICLK, FN_ADICS_SAMP,
- FN_ADIDATA, FN_ADICHS0, FN_ADICHS1, FN_ADICHS2,
- FN_AVS1, FN_AVS2,
-
- /* IPSR0 */
- FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2, FN_DU0_DR3_Y5_DATA3,
- FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5, FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7,
- FN_DU0_DG0_DATA8, FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
- FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14, FN_DU0_DG7_Y3_DATA15,
- FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0, FN_DU0_DB3_C1,
- FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4, FN_DU0_DB7_C5,
-
- /* IPSR1 */
- FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC, FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP,
- FN_DU0_CDE, FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
- FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5, FN_DU1_DG2_C6_DATA6,
- FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8, FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10,
- FN_DU1_DG7_Y3_DATA11, FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1,
- FN_A22, FN_IO2, FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
-
- /* IPSR2 */
- FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
- FN_VI2_HSYNC, FN_AVB_RXD0, FN_VI2_VSYNC, FN_AVB_RXD1,
- FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
- FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
- FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
- FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
- FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
- FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
- FN_VI2_FIELD, FN_AVB_TXD2,
-
- /* IPSR3 */
- FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
- FN_VI3_HSYNC, FN_AVB_TXD5, FN_VI3_VSYNC, FN_AVB_TXD6,
- FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
- FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
- FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
- FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
- FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
- FN_VI3_D11_Y3,
-
- /* IPSR4 */
- FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
- FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
- FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0,
- FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0,
- FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
- FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
- FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
- FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
-
- /* IPSR5 */
- FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1, FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
- FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
- FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
- FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
- FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
- FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
-
- /* IPSR6 */
- FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0,
- FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
- FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1,
- FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
- FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2,
- FN_DREQ0, FN_RX2, FN_DACK1, FN_SCK3,
- FN_TX3, FN_DREQ1, FN_RX3,
-
- /* IPSR7 */
- FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
- FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
- FN_SSI_SCK3, FN_TPU0TO0, FN_SSI_WS3, FN_TPU0TO1,
- FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
- FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
-
- FN_SEL_VI1_0, FN_SEL_VI1_1,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
- DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
- DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
- DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
- DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, DU1_DISP_MARK, DU1_CDE_MARK,
-
- D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
- D6_MARK, D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK,
- D12_MARK, D13_MARK, D14_MARK, D15_MARK, A0_MARK, A1_MARK,
- A2_MARK, A3_MARK, A4_MARK, A5_MARK, A6_MARK, A7_MARK,
- A8_MARK, A9_MARK, A10_MARK, A11_MARK, A12_MARK, A13_MARK,
- A14_MARK, A15_MARK,
-
- A16_MARK, A17_MARK, A18_MARK, A19_MARK,
- CS1_A26_MARK, EX_CS0_MARK, EX_CS1_MARK, EX_CS2_MARK,
- EX_CS3_MARK, EX_CS4_MARK, EX_CS5_MARK, BS_MARK,
- RD_MARK, RD_WR_MARK, WE0_MARK, WE1_MARK, EX_WAIT0_MARK,
- IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_MARK,
-
- VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_MARK, VI0_VSYNC_MARK,
- VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
- VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
- VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
- VI0_FIELD_MARK,
-
- VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_MARK,
- VI1_VSYNC_MARK, VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
- VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK,
- VI1_D5_B5_C5_MARK, VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
- VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK,
- VI1_D11_G3_Y3_MARK, VI1_FIELD_MARK,
-
- VI3_D10_Y2_MARK, VI3_FIELD_MARK,
-
- VI4_CLK_MARK,
-
- VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, VI5_FIELD_MARK,
-
- HRTS0_MARK, HCTS1_MARK, SCK0_MARK, CTS0_MARK, RTS0_MARK, TX0_MARK,
- RX0_MARK, SCK1_MARK, CTS1_MARK, RTS1_MARK, TX1_MARK, RX1_MARK,
- SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
- CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
-
- SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK,
- SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
- SD0_CD_MARK, SD0_WP_MARK, ADICLK_MARK,
- ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
- ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
-
- DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
- DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
- DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
- DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
- DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
- DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
- DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK,
- DU0_DB5_C3_MARK, DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
-
- DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
- DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
- DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
- DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
- DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
- DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
- A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
- A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
-
- VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
- VI2_HSYNC_MARK, AVB_RXD0_MARK, VI2_VSYNC_MARK, AVB_RXD1_MARK,
- VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_RXD3_MARK,
- VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
- VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
- VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
- VI2_D8_Y0_MARK, AVB_TXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
- VI2_D10_Y2_MARK, AVB_TXD0_MARK, VI2_D11_Y3_MARK, AVB_TXD1_MARK,
- VI2_FIELD_MARK, AVB_TXD2_MARK,
-
- VI3_CLK_MARK, AVB_TX_CLK_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
- VI3_HSYNC_MARK, AVB_TXD5_MARK, VI3_VSYNC_MARK, AVB_TXD6_MARK,
- VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
- VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
- VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
- VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
- VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
- VI3_D11_Y3_MARK,
-
- VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_MARK, VI0_D13_G5_Y5_MARK,
- VI4_VSYNC_MARK, VI0_D14_G6_Y6_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK,
- VI4_D1_C1_MARK, VI0_D16_R0_MARK, VI1_D12_G4_Y4_0_MARK,
- VI4_D2_C2_MARK, VI0_D17_R1_MARK, VI1_D13_G5_Y5_0_MARK,
- VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_0_MARK,
- VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_0_MARK,
- VI4_D5_C5_MARK, VI0_D20_R4_MARK, VI2_D12_Y4_MARK,
- VI4_D6_C6_MARK, VI0_D21_R5_MARK, VI2_D13_Y5_MARK,
- VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
- VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK,
- VI4_D9_Y1_MARK, VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK,
- VI4_D11_Y3_MARK, VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
-
- VI5_CLKENB_MARK, VI1_D12_G4_Y4_1_MARK, VI5_HSYNC_MARK, VI1_D13_G5_Y5_1_MARK,
- VI5_VSYNC_MARK, VI1_D14_G6_Y6_1_MARK, VI5_D0_C0_MARK, VI1_D15_G7_Y7_1_MARK,
- VI5_D1_C1_MARK, VI1_D16_R0_MARK, VI5_D2_C2_MARK, VI1_D17_R1_MARK,
- VI5_D3_C3_MARK, VI1_D18_R2_MARK, VI5_D4_C4_MARK, VI1_D19_R3_MARK,
- VI5_D5_C5_MARK, VI1_D20_R4_MARK, VI5_D6_C6_MARK, VI1_D21_R5_MARK,
- VI5_D7_C7_MARK, VI1_D22_R6_MARK, VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
-
- MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_MARK,
- MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
- MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_MARK,
- MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
- DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK,
- DREQ0_MARK, RX2_MARK, DACK1_MARK, SCK3_MARK,
- TX3_MARK, DREQ1_MARK, RX3_MARK,
-
- PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK,
- PWM1_MARK, TCLK2_MARK, FSO_CFE_1_MARK,
- PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK,
- PWM3_MARK, PWM4_MARK, SSI_SCK3_MARK, TPU0TO0_MARK,
- SSI_WS3_MARK, TPU0TO1_MARK, SSI_SDATA3_MARK, TPU0TO2_MARK,
- SSI_SCK4_MARK, TPU0TO3_MARK, SSI_WS4_MARK,
- SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK,
- AUDIO_CLKA_MARK, AUDIO_CLKB_MARK,
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(DU1_DB2_C0_DATA12_MARK, FN_DU1_DB2_C0_DATA12),
- PINMUX_DATA(DU1_DB3_C1_DATA13_MARK, FN_DU1_DB3_C1_DATA13),
- PINMUX_DATA(DU1_DB4_C2_DATA14_MARK, FN_DU1_DB4_C2_DATA14),
- PINMUX_DATA(DU1_DB5_C3_DATA15_MARK, FN_DU1_DB5_C3_DATA15),
- PINMUX_DATA(DU1_DB6_C4_MARK, FN_DU1_DB6_C4),
- PINMUX_DATA(DU1_DB7_C5_MARK, FN_DU1_DB7_C5),
- PINMUX_DATA(DU1_EXHSYNC_DU1_HSYNC_MARK, FN_DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_DATA(DU1_EXVSYNC_DU1_VSYNC_MARK, FN_DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_DATA(DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_DATA(DU1_DISP_MARK, FN_DU1_DISP),
- PINMUX_DATA(DU1_CDE_MARK, FN_DU1_CDE),
-
- PINMUX_DATA(D0_MARK, FN_D0),
- PINMUX_DATA(D1_MARK, FN_D1),
- PINMUX_DATA(D2_MARK, FN_D2),
- PINMUX_DATA(D3_MARK, FN_D3),
- PINMUX_DATA(D4_MARK, FN_D4),
- PINMUX_DATA(D5_MARK, FN_D5),
- PINMUX_DATA(D6_MARK, FN_D6),
- PINMUX_DATA(D7_MARK, FN_D7),
- PINMUX_DATA(D8_MARK, FN_D8),
- PINMUX_DATA(D9_MARK, FN_D9),
- PINMUX_DATA(D10_MARK, FN_D10),
- PINMUX_DATA(D11_MARK, FN_D11),
- PINMUX_DATA(D12_MARK, FN_D12),
- PINMUX_DATA(D13_MARK, FN_D13),
- PINMUX_DATA(D14_MARK, FN_D14),
- PINMUX_DATA(D15_MARK, FN_D15),
- PINMUX_DATA(A0_MARK, FN_A0),
- PINMUX_DATA(A1_MARK, FN_A1),
- PINMUX_DATA(A2_MARK, FN_A2),
- PINMUX_DATA(A3_MARK, FN_A3),
- PINMUX_DATA(A4_MARK, FN_A4),
- PINMUX_DATA(A5_MARK, FN_A5),
- PINMUX_DATA(A6_MARK, FN_A6),
- PINMUX_DATA(A7_MARK, FN_A7),
- PINMUX_DATA(A8_MARK, FN_A8),
- PINMUX_DATA(A9_MARK, FN_A9),
- PINMUX_DATA(A10_MARK, FN_A10),
- PINMUX_DATA(A11_MARK, FN_A11),
- PINMUX_DATA(A12_MARK, FN_A12),
- PINMUX_DATA(A13_MARK, FN_A13),
- PINMUX_DATA(A14_MARK, FN_A14),
- PINMUX_DATA(A15_MARK, FN_A15),
-
- PINMUX_DATA(A16_MARK, FN_A16),
- PINMUX_DATA(A17_MARK, FN_A17),
- PINMUX_DATA(A18_MARK, FN_A18),
- PINMUX_DATA(A19_MARK, FN_A19),
- PINMUX_DATA(CS1_A26_MARK, FN_CS1_A26),
- PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
- PINMUX_DATA(EX_CS1_MARK, FN_EX_CS1),
- PINMUX_DATA(EX_CS2_MARK, FN_EX_CS2),
- PINMUX_DATA(EX_CS3_MARK, FN_EX_CS3),
- PINMUX_DATA(EX_CS4_MARK, FN_EX_CS4),
- PINMUX_DATA(EX_CS5_MARK, FN_EX_CS5),
- PINMUX_DATA(BS_MARK, FN_BS),
- PINMUX_DATA(RD_MARK, FN_RD),
- PINMUX_DATA(RD_WR_MARK, FN_RD_WR),
- PINMUX_DATA(WE0_MARK, FN_WE0),
- PINMUX_DATA(WE1_MARK, FN_WE1),
- PINMUX_DATA(EX_WAIT0_MARK, FN_EX_WAIT0),
- PINMUX_DATA(IRQ0_MARK, FN_IRQ0),
- PINMUX_DATA(IRQ1_MARK, FN_IRQ1),
- PINMUX_DATA(IRQ2_MARK, FN_IRQ2),
- PINMUX_DATA(IRQ3_MARK, FN_IRQ3),
- PINMUX_DATA(CS0_MARK, FN_CS0),
-
- PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
- PINMUX_DATA(VI0_CLKENB_MARK, FN_VI0_CLKENB),
- PINMUX_DATA(VI0_HSYNC_MARK, FN_VI0_HSYNC),
- PINMUX_DATA(VI0_VSYNC_MARK, FN_VI0_VSYNC),
- PINMUX_DATA(VI0_D0_B0_C0_MARK, FN_VI0_D0_B0_C0),
- PINMUX_DATA(VI0_D1_B1_C1_MARK, FN_VI0_D1_B1_C1),
- PINMUX_DATA(VI0_D2_B2_C2_MARK, FN_VI0_D2_B2_C2),
- PINMUX_DATA(VI0_D3_B3_C3_MARK, FN_VI0_D3_B3_C3),
- PINMUX_DATA(VI0_D4_B4_C4_MARK, FN_VI0_D4_B4_C4),
- PINMUX_DATA(VI0_D5_B5_C5_MARK, FN_VI0_D5_B5_C5),
- PINMUX_DATA(VI0_D6_B6_C6_MARK, FN_VI0_D6_B6_C6),
- PINMUX_DATA(VI0_D7_B7_C7_MARK, FN_VI0_D7_B7_C7),
- PINMUX_DATA(VI0_D8_G0_Y0_MARK, FN_VI0_D8_G0_Y0),
- PINMUX_DATA(VI0_D9_G1_Y1_MARK, FN_VI0_D9_G1_Y1),
- PINMUX_DATA(VI0_D10_G2_Y2_MARK, FN_VI0_D10_G2_Y2),
- PINMUX_DATA(VI0_D11_G3_Y3_MARK, FN_VI0_D11_G3_Y3),
- PINMUX_DATA(VI0_FIELD_MARK, FN_VI0_FIELD),
-
- PINMUX_DATA(VI1_CLK_MARK, FN_VI1_CLK),
- PINMUX_DATA(VI1_CLKENB_MARK, FN_VI1_CLKENB),
- PINMUX_DATA(VI1_HSYNC_MARK, FN_VI1_HSYNC),
- PINMUX_DATA(VI1_VSYNC_MARK, FN_VI1_VSYNC),
- PINMUX_DATA(VI1_D0_B0_C0_MARK, FN_VI1_D0_B0_C0),
- PINMUX_DATA(VI1_D1_B1_C1_MARK, FN_VI1_D1_B1_C1),
- PINMUX_DATA(VI1_D2_B2_C2_MARK, FN_VI1_D2_B2_C2),
- PINMUX_DATA(VI1_D3_B3_C3_MARK, FN_VI1_D3_B3_C3),
- PINMUX_DATA(VI1_D4_B4_C4_MARK, FN_VI1_D4_B4_C4),
- PINMUX_DATA(VI1_D5_B5_C5_MARK, FN_VI1_D5_B5_C5),
- PINMUX_DATA(VI1_D6_B6_C6_MARK, FN_VI1_D6_B6_C6),
- PINMUX_DATA(VI1_D7_B7_C7_MARK, FN_VI1_D7_B7_C7),
- PINMUX_DATA(VI1_D8_G0_Y0_MARK, FN_VI1_D8_G0_Y0),
- PINMUX_DATA(VI1_D9_G1_Y1_MARK, FN_VI1_D9_G1_Y1),
- PINMUX_DATA(VI1_D10_G2_Y2_MARK, FN_VI1_D10_G2_Y2),
- PINMUX_DATA(VI1_D11_G3_Y3_MARK, FN_VI1_D11_G3_Y3),
- PINMUX_DATA(VI1_FIELD_MARK, FN_VI1_FIELD),
-
- PINMUX_DATA(VI3_D10_Y2_MARK, FN_VI3_D10_Y2),
- PINMUX_DATA(VI3_FIELD_MARK, FN_VI3_FIELD),
-
- PINMUX_DATA(VI4_CLK_MARK, FN_VI4_CLK),
-
- PINMUX_DATA(VI5_CLK_MARK, FN_VI5_CLK),
- PINMUX_DATA(VI5_D9_Y1_MARK, FN_VI5_D9_Y1),
- PINMUX_DATA(VI5_D10_Y2_MARK, FN_VI5_D10_Y2),
- PINMUX_DATA(VI5_D11_Y3_MARK, FN_VI5_D11_Y3),
- PINMUX_DATA(VI5_FIELD_MARK, FN_VI5_FIELD),
-
- PINMUX_DATA(HRTS0_MARK, FN_HRTS0),
- PINMUX_DATA(HCTS1_MARK, FN_HCTS1),
- PINMUX_DATA(SCK0_MARK, FN_SCK0),
- PINMUX_DATA(CTS0_MARK, FN_CTS0),
- PINMUX_DATA(RTS0_MARK, FN_RTS0),
- PINMUX_DATA(TX0_MARK, FN_TX0),
- PINMUX_DATA(RX0_MARK, FN_RX0),
- PINMUX_DATA(SCK1_MARK, FN_SCK1),
- PINMUX_DATA(CTS1_MARK, FN_CTS1),
- PINMUX_DATA(RTS1_MARK, FN_RTS1),
- PINMUX_DATA(TX1_MARK, FN_TX1),
- PINMUX_DATA(RX1_MARK, FN_RX1),
- PINMUX_DATA(SCIF_CLK_MARK, FN_SCIF_CLK),
- PINMUX_DATA(CAN0_TX_MARK, FN_CAN0_TX),
- PINMUX_DATA(CAN0_RX_MARK, FN_CAN0_RX),
- PINMUX_DATA(CAN_CLK_MARK, FN_CAN_CLK),
- PINMUX_DATA(CAN1_TX_MARK, FN_CAN1_TX),
- PINMUX_DATA(CAN1_RX_MARK, FN_CAN1_RX),
-
- PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
- PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
- PINMUX_DATA(SD0_DAT0_MARK, FN_SD0_DAT0),
- PINMUX_DATA(SD0_DAT1_MARK, FN_SD0_DAT1),
- PINMUX_DATA(SD0_DAT2_MARK, FN_SD0_DAT2),
- PINMUX_DATA(SD0_DAT3_MARK, FN_SD0_DAT3),
- PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
- PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
- PINMUX_DATA(ADICLK_MARK, FN_ADICLK),
- PINMUX_DATA(ADICS_SAMP_MARK, FN_ADICS_SAMP),
- PINMUX_DATA(ADIDATA_MARK, FN_ADIDATA),
- PINMUX_DATA(ADICHS0_MARK, FN_ADICHS0),
- PINMUX_DATA(ADICHS1_MARK, FN_ADICHS1),
- PINMUX_DATA(ADICHS2_MARK, FN_ADICHS2),
- PINMUX_DATA(AVS1_MARK, FN_AVS1),
- PINMUX_DATA(AVS2_MARK, FN_AVS2),
-
- PINMUX_IPSR_DATA(IP0_0, DU0_DR0_DATA0),
- PINMUX_IPSR_DATA(IP0_1, DU0_DR1_DATA1),
- PINMUX_IPSR_DATA(IP0_2, DU0_DR2_Y4_DATA2),
- PINMUX_IPSR_DATA(IP0_3, DU0_DR3_Y5_DATA3),
- PINMUX_IPSR_DATA(IP0_4, DU0_DR4_Y6_DATA4),
- PINMUX_IPSR_DATA(IP0_5, DU0_DR5_Y7_DATA5),
- PINMUX_IPSR_DATA(IP0_6, DU0_DR6_Y8_DATA6),
- PINMUX_IPSR_DATA(IP0_7, DU0_DR7_Y9_DATA7),
- PINMUX_IPSR_DATA(IP0_8, DU0_DG0_DATA8),
- PINMUX_IPSR_DATA(IP0_9, DU0_DG1_DATA9),
- PINMUX_IPSR_DATA(IP0_10, DU0_DG2_C6_DATA10),
- PINMUX_IPSR_DATA(IP0_11, DU0_DG3_C7_DATA11),
- PINMUX_IPSR_DATA(IP0_12, DU0_DG4_Y0_DATA12),
- PINMUX_IPSR_DATA(IP0_13, DU0_DG5_Y1_DATA13),
- PINMUX_IPSR_DATA(IP0_14, DU0_DG6_Y2_DATA14),
- PINMUX_IPSR_DATA(IP0_15, DU0_DG7_Y3_DATA15),
- PINMUX_IPSR_DATA(IP0_16, DU0_DB0),
- PINMUX_IPSR_DATA(IP0_17, DU0_DB1),
- PINMUX_IPSR_DATA(IP0_18, DU0_DB2_C0),
- PINMUX_IPSR_DATA(IP0_19, DU0_DB3_C1),
- PINMUX_IPSR_DATA(IP0_20, DU0_DB4_C2),
- PINMUX_IPSR_DATA(IP0_21, DU0_DB5_C3),
- PINMUX_IPSR_DATA(IP0_22, DU0_DB6_C4),
- PINMUX_IPSR_DATA(IP0_23, DU0_DB7_C5),
-
- PINMUX_IPSR_DATA(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
- PINMUX_IPSR_DATA(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP1_3, DU0_DISP),
- PINMUX_IPSR_DATA(IP1_4, DU0_CDE),
- PINMUX_IPSR_DATA(IP1_5, DU1_DR2_Y4_DATA0),
- PINMUX_IPSR_DATA(IP1_6, DU1_DR3_Y5_DATA1),
- PINMUX_IPSR_DATA(IP1_7, DU1_DR4_Y6_DATA2),
- PINMUX_IPSR_DATA(IP1_8, DU1_DR5_Y7_DATA3),
- PINMUX_IPSR_DATA(IP1_9, DU1_DR6_DATA4),
- PINMUX_IPSR_DATA(IP1_10, DU1_DR7_DATA5),
- PINMUX_IPSR_DATA(IP1_11, DU1_DG2_C6_DATA6),
- PINMUX_IPSR_DATA(IP1_12, DU1_DG3_C7_DATA7),
- PINMUX_IPSR_DATA(IP1_13, DU1_DG4_Y0_DATA8),
- PINMUX_IPSR_DATA(IP1_14, DU1_DG5_Y1_DATA9),
- PINMUX_IPSR_DATA(IP1_15, DU1_DG6_Y2_DATA10),
- PINMUX_IPSR_DATA(IP1_16, DU1_DG7_Y3_DATA11),
- PINMUX_IPSR_DATA(IP1_17, A20),
- PINMUX_IPSR_DATA(IP1_17, MOSI_IO0),
- PINMUX_IPSR_DATA(IP1_18, A21),
- PINMUX_IPSR_DATA(IP1_18, MISO_IO1),
- PINMUX_IPSR_DATA(IP1_19, A22),
- PINMUX_IPSR_DATA(IP1_19, IO2),
- PINMUX_IPSR_DATA(IP1_20, A23),
- PINMUX_IPSR_DATA(IP1_20, IO3),
- PINMUX_IPSR_DATA(IP1_21, A24),
- PINMUX_IPSR_DATA(IP1_21, SPCLK),
- PINMUX_IPSR_DATA(IP1_22, A25),
- PINMUX_IPSR_DATA(IP1_22, SSL),
-
- PINMUX_IPSR_DATA(IP2_0, VI2_CLK),
- PINMUX_IPSR_DATA(IP2_0, AVB_RX_CLK),
- PINMUX_IPSR_DATA(IP2_1, VI2_CLKENB),
- PINMUX_IPSR_DATA(IP2_1, AVB_RX_DV),
- PINMUX_IPSR_DATA(IP2_2, VI2_HSYNC),
- PINMUX_IPSR_DATA(IP2_2, AVB_RXD0),
- PINMUX_IPSR_DATA(IP2_3, VI2_VSYNC),
- PINMUX_IPSR_DATA(IP2_3, AVB_RXD1),
- PINMUX_IPSR_DATA(IP2_4, VI2_D0_C0),
- PINMUX_IPSR_DATA(IP2_4, AVB_RXD2),
- PINMUX_IPSR_DATA(IP2_5, VI2_D1_C1),
- PINMUX_IPSR_DATA(IP2_5, AVB_RXD3),
- PINMUX_IPSR_DATA(IP2_6, VI2_D2_C2),
- PINMUX_IPSR_DATA(IP2_6, AVB_RXD4),
- PINMUX_IPSR_DATA(IP2_7, VI2_D3_C3),
- PINMUX_IPSR_DATA(IP2_7, AVB_RXD5),
- PINMUX_IPSR_DATA(IP2_8, VI2_D4_C4),
- PINMUX_IPSR_DATA(IP2_8, AVB_RXD6),
- PINMUX_IPSR_DATA(IP2_9, VI2_D5_C5),
- PINMUX_IPSR_DATA(IP2_9, AVB_RXD7),
- PINMUX_IPSR_DATA(IP2_10, VI2_D6_C6),
- PINMUX_IPSR_DATA(IP2_10, AVB_RX_ER),
- PINMUX_IPSR_DATA(IP2_11, VI2_D7_C7),
- PINMUX_IPSR_DATA(IP2_11, AVB_COL),
- PINMUX_IPSR_DATA(IP2_12, VI2_D8_Y0),
- PINMUX_IPSR_DATA(IP2_12, AVB_TXD3),
- PINMUX_IPSR_DATA(IP2_13, VI2_D9_Y1),
- PINMUX_IPSR_DATA(IP2_13, AVB_TX_EN),
- PINMUX_IPSR_DATA(IP2_14, VI2_D10_Y2),
- PINMUX_IPSR_DATA(IP2_14, AVB_TXD0),
- PINMUX_IPSR_DATA(IP2_15, VI2_D11_Y3),
- PINMUX_IPSR_DATA(IP2_15, AVB_TXD1),
- PINMUX_IPSR_DATA(IP2_16, VI2_FIELD),
- PINMUX_IPSR_DATA(IP2_16, AVB_TXD2),
-
- PINMUX_IPSR_DATA(IP3_0, VI3_CLK),
- PINMUX_IPSR_DATA(IP3_0, AVB_TX_CLK),
- PINMUX_IPSR_DATA(IP3_1, VI3_CLKENB),
- PINMUX_IPSR_DATA(IP3_1, AVB_TXD4),
- PINMUX_IPSR_DATA(IP3_2, VI3_HSYNC),
- PINMUX_IPSR_DATA(IP3_2, AVB_TXD5),
- PINMUX_IPSR_DATA(IP3_3, VI3_VSYNC),
- PINMUX_IPSR_DATA(IP3_3, AVB_TXD6),
- PINMUX_IPSR_DATA(IP3_4, VI3_D0_C0),
- PINMUX_IPSR_DATA(IP3_4, AVB_TXD7),
- PINMUX_IPSR_DATA(IP3_5, VI3_D1_C1),
- PINMUX_IPSR_DATA(IP3_5, AVB_TX_ER),
- PINMUX_IPSR_DATA(IP3_6, VI3_D2_C2),
- PINMUX_IPSR_DATA(IP3_6, AVB_GTX_CLK),
- PINMUX_IPSR_DATA(IP3_7, VI3_D3_C3),
- PINMUX_IPSR_DATA(IP3_7, AVB_MDC),
- PINMUX_IPSR_DATA(IP3_8, VI3_D4_C4),
- PINMUX_IPSR_DATA(IP3_8, AVB_MDIO),
- PINMUX_IPSR_DATA(IP3_9, VI3_D5_C5),
- PINMUX_IPSR_DATA(IP3_9, AVB_LINK),
- PINMUX_IPSR_DATA(IP3_10, VI3_D6_C6),
- PINMUX_IPSR_DATA(IP3_10, AVB_MAGIC),
- PINMUX_IPSR_DATA(IP3_11, VI3_D7_C7),
- PINMUX_IPSR_DATA(IP3_11, AVB_PHY_INT),
- PINMUX_IPSR_DATA(IP3_12, VI3_D8_Y0),
- PINMUX_IPSR_DATA(IP3_12, AVB_CRS),
- PINMUX_IPSR_DATA(IP3_13, VI3_D9_Y1),
- PINMUX_IPSR_DATA(IP3_13, AVB_GTXREFCLK),
- PINMUX_IPSR_DATA(IP3_14, VI3_D11_Y3),
-
- PINMUX_IPSR_DATA(IP4_0, VI4_CLKENB),
- PINMUX_IPSR_DATA(IP4_0, VI0_D12_G4_Y4),
- PINMUX_IPSR_DATA(IP4_1, VI4_HSYNC),
- PINMUX_IPSR_DATA(IP4_1, VI0_D13_G5_Y5),
- PINMUX_IPSR_DATA(IP4_3_2, VI4_VSYNC),
- PINMUX_IPSR_DATA(IP4_3_2, VI0_D14_G6_Y6),
- PINMUX_IPSR_DATA(IP4_4, VI4_D0_C0),
- PINMUX_IPSR_DATA(IP4_4, VI0_D15_G7_Y7),
- PINMUX_IPSR_DATA(IP4_6_5, VI4_D1_C1),
- PINMUX_IPSR_DATA(IP4_6_5, VI0_D16_R0),
- PINMUX_IPSR_MODSEL_DATA(IP4_6_5, VI1_D12_G4_Y4_0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP4_8_7, VI4_D2_C2),
- PINMUX_IPSR_DATA(IP4_8_7, VI0_D17_R1),
- PINMUX_IPSR_MODSEL_DATA(IP4_8_7, VI1_D13_G5_Y5_0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP4_10_9, VI4_D3_C3),
- PINMUX_IPSR_DATA(IP4_10_9, VI0_D18_R2),
- PINMUX_IPSR_MODSEL_DATA(IP4_10_9, VI1_D14_G6_Y6_0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP4_12_11, VI4_D4_C4),
- PINMUX_IPSR_DATA(IP4_12_11, VI0_D19_R3),
- PINMUX_IPSR_MODSEL_DATA(IP4_12_11, VI1_D15_G7_Y7_0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP4_14_13, VI4_D5_C5),
- PINMUX_IPSR_DATA(IP4_14_13, VI0_D20_R4),
- PINMUX_IPSR_DATA(IP4_14_13, VI2_D12_Y4),
- PINMUX_IPSR_DATA(IP4_16_15, VI4_D6_C6),
- PINMUX_IPSR_DATA(IP4_16_15, VI0_D21_R5),
- PINMUX_IPSR_DATA(IP4_16_15, VI2_D13_Y5),
- PINMUX_IPSR_DATA(IP4_18_17, VI4_D7_C7),
- PINMUX_IPSR_DATA(IP4_18_17, VI0_D22_R6),
- PINMUX_IPSR_DATA(IP4_18_17, VI2_D14_Y6),
- PINMUX_IPSR_DATA(IP4_20_19, VI4_D8_Y0),
- PINMUX_IPSR_DATA(IP4_20_19, VI0_D23_R7),
- PINMUX_IPSR_DATA(IP4_20_19, VI2_D15_Y7),
- PINMUX_IPSR_DATA(IP4_21, VI4_D9_Y1),
- PINMUX_IPSR_DATA(IP4_21, VI3_D12_Y4),
- PINMUX_IPSR_DATA(IP4_22, VI4_D10_Y2),
- PINMUX_IPSR_DATA(IP4_22, VI3_D13_Y5),
- PINMUX_IPSR_DATA(IP4_23, VI4_D11_Y3),
- PINMUX_IPSR_DATA(IP4_23, VI3_D14_Y6),
- PINMUX_IPSR_DATA(IP4_24, VI4_FIELD),
- PINMUX_IPSR_DATA(IP4_24, VI3_D15_Y7),
-
- PINMUX_IPSR_DATA(IP5_0, VI5_CLKENB),
- PINMUX_IPSR_MODSEL_DATA(IP5_0, VI1_D12_G4_Y4_1, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_1, VI5_HSYNC),
- PINMUX_IPSR_MODSEL_DATA(IP5_1, VI1_D13_G5_Y5_1, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_2, VI5_VSYNC),
- PINMUX_IPSR_MODSEL_DATA(IP5_2, VI1_D14_G6_Y6_1, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_3, VI5_D0_C0),
- PINMUX_IPSR_MODSEL_DATA(IP5_3, VI1_D15_G7_Y7_1, SEL_VI1_1),
- PINMUX_IPSR_DATA(IP5_4, VI5_D1_C1),
- PINMUX_IPSR_DATA(IP5_4, VI1_D16_R0),
- PINMUX_IPSR_DATA(IP5_5, VI5_D2_C2),
- PINMUX_IPSR_DATA(IP5_5, VI1_D17_R1),
- PINMUX_IPSR_DATA(IP5_6, VI5_D3_C3),
- PINMUX_IPSR_DATA(IP5_6, VI1_D18_R2),
- PINMUX_IPSR_DATA(IP5_7, VI5_D4_C4),
- PINMUX_IPSR_DATA(IP5_7, VI1_D19_R3),
- PINMUX_IPSR_DATA(IP5_8, VI5_D5_C5),
- PINMUX_IPSR_DATA(IP5_8, VI1_D20_R4),
- PINMUX_IPSR_DATA(IP5_9, VI5_D6_C6),
- PINMUX_IPSR_DATA(IP5_9, VI1_D21_R5),
- PINMUX_IPSR_DATA(IP5_10, VI5_D7_C7),
- PINMUX_IPSR_DATA(IP5_10, VI1_D22_R6),
- PINMUX_IPSR_DATA(IP5_11, VI5_D8_Y0),
- PINMUX_IPSR_DATA(IP5_11, VI1_D23_R7),
-
- PINMUX_IPSR_DATA(IP6_0, MSIOF0_SCK),
- PINMUX_IPSR_DATA(IP6_0, HSCK0),
- PINMUX_IPSR_DATA(IP6_1, MSIOF0_SYNC),
- PINMUX_IPSR_DATA(IP6_1, HCTS0),
- PINMUX_IPSR_DATA(IP6_2, MSIOF0_TXD),
- PINMUX_IPSR_DATA(IP6_2, HTX0),
- PINMUX_IPSR_DATA(IP6_3, MSIOF0_RXD),
- PINMUX_IPSR_DATA(IP6_3, HRX0),
- PINMUX_IPSR_DATA(IP6_4, MSIOF1_SCK),
- PINMUX_IPSR_DATA(IP6_4, HSCK1),
- PINMUX_IPSR_DATA(IP6_5, MSIOF1_SYNC),
- PINMUX_IPSR_DATA(IP6_5, HRTS1),
- PINMUX_IPSR_DATA(IP6_6, MSIOF1_TXD),
- PINMUX_IPSR_DATA(IP6_6, HTX1),
- PINMUX_IPSR_DATA(IP6_7, MSIOF1_RXD),
- PINMUX_IPSR_DATA(IP6_7, HRX1),
- PINMUX_IPSR_DATA(IP6_9_8, DRACK0),
- PINMUX_IPSR_DATA(IP6_9_8, SCK2),
- PINMUX_IPSR_DATA(IP6_11_10, DACK0),
- PINMUX_IPSR_DATA(IP6_11_10, TX2),
- PINMUX_IPSR_DATA(IP6_13_12, DREQ0),
- PINMUX_IPSR_DATA(IP6_13_12, RX2),
- PINMUX_IPSR_DATA(IP6_15_14, DACK1),
- PINMUX_IPSR_DATA(IP6_15_14, SCK3),
- PINMUX_IPSR_DATA(IP6_16, TX3),
- PINMUX_IPSR_DATA(IP6_18_17, DREQ1),
- PINMUX_IPSR_DATA(IP6_18_17, RX3),
-
- PINMUX_IPSR_DATA(IP7_1_0, PWM0),
- PINMUX_IPSR_DATA(IP7_1_0, TCLK1),
- PINMUX_IPSR_DATA(IP7_1_0, FSO_CFE_0),
- PINMUX_IPSR_DATA(IP7_3_2, PWM1),
- PINMUX_IPSR_DATA(IP7_3_2, TCLK2),
- PINMUX_IPSR_DATA(IP7_3_2, FSO_CFE_1),
- PINMUX_IPSR_DATA(IP7_5_4, PWM2),
- PINMUX_IPSR_DATA(IP7_5_4, TCLK3),
- PINMUX_IPSR_DATA(IP7_5_4, FSO_TOE),
- PINMUX_IPSR_DATA(IP7_6, PWM3),
- PINMUX_IPSR_DATA(IP7_7, PWM4),
- PINMUX_IPSR_DATA(IP7_9_8, SSI_SCK3),
- PINMUX_IPSR_DATA(IP7_9_8, TPU0TO0),
- PINMUX_IPSR_DATA(IP7_11_10, SSI_WS3),
- PINMUX_IPSR_DATA(IP7_11_10, TPU0TO1),
- PINMUX_IPSR_DATA(IP7_13_12, SSI_SDATA3),
- PINMUX_IPSR_DATA(IP7_13_12, TPU0TO2),
- PINMUX_IPSR_DATA(IP7_15_14, SSI_SCK4),
- PINMUX_IPSR_DATA(IP7_15_14, TPU0TO3),
- PINMUX_IPSR_DATA(IP7_16, SSI_WS4),
- PINMUX_IPSR_DATA(IP7_17, SSI_SDATA4),
- PINMUX_IPSR_DATA(IP7_18, AUDIO_CLKOUT),
- PINMUX_IPSR_DATA(IP7_19, AUDIO_CLKA),
- PINMUX_IPSR_DATA(IP7_20, AUDIO_CLKB),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(DU1_DB2_C0_DATA12), GPIO_FN(DU1_DB3_C1_DATA13),
- GPIO_FN(DU1_DB4_C2_DATA14), GPIO_FN(DU1_DB5_C3_DATA15),
- GPIO_FN(DU1_DB6_C4), GPIO_FN(DU1_DB7_C5),
- GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC),
- GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(DU1_DISP), GPIO_FN(DU1_CDE),
-
- GPIO_FN(D0), GPIO_FN(D1), GPIO_FN(D2), GPIO_FN(D3),
- GPIO_FN(D4), GPIO_FN(D5), GPIO_FN(D6), GPIO_FN(D7),
- GPIO_FN(D8), GPIO_FN(D9), GPIO_FN(D10), GPIO_FN(D11),
- GPIO_FN(D12), GPIO_FN(D13), GPIO_FN(D14), GPIO_FN(D15),
- GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
- GPIO_FN(A4), GPIO_FN(A5), GPIO_FN(A6), GPIO_FN(A7),
- GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), GPIO_FN(A11),
- GPIO_FN(A12), GPIO_FN(A13), GPIO_FN(A14), GPIO_FN(A15),
-
- GPIO_FN(A16), GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19),
- GPIO_FN(CS1_A26), GPIO_FN(EX_CS0), GPIO_FN(EX_CS1), GPIO_FN(EX_CS2),
- GPIO_FN(EX_CS3), GPIO_FN(EX_CS4), GPIO_FN(EX_CS5), GPIO_FN(BS),
- GPIO_FN(RD), GPIO_FN(RD_WR), GPIO_FN(WE0), GPIO_FN(WE1),
- GPIO_FN(EX_WAIT0), GPIO_FN(IRQ0), GPIO_FN(IRQ1), GPIO_FN(IRQ2),
- GPIO_FN(IRQ3), GPIO_FN(CS0),
-
- GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_HSYNC),
- GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_D0_B0_C0), GPIO_FN(VI0_D1_B1_C1),
- GPIO_FN(VI0_D2_B2_C2), GPIO_FN(VI0_D3_B3_C3), GPIO_FN(VI0_D4_B4_C4),
- GPIO_FN(VI0_D5_B5_C5), GPIO_FN(VI0_D6_B6_C6), GPIO_FN(VI0_D7_B7_C7),
- GPIO_FN(VI0_D8_G0_Y0), GPIO_FN(VI0_D9_G1_Y1), GPIO_FN(VI0_D10_G2_Y2),
- GPIO_FN(VI0_D11_G3_Y3), GPIO_FN(VI0_FIELD),
-
- GPIO_FN(VI1_CLK), GPIO_FN(VI1_CLKENB), GPIO_FN(VI1_HSYNC),
- GPIO_FN(VI1_VSYNC), GPIO_FN(VI1_D0_B0_C0), GPIO_FN(VI1_D1_B1_C1),
- GPIO_FN(VI1_D2_B2_C2), GPIO_FN(VI1_D3_B3_C3), GPIO_FN(VI1_D4_B4_C4),
- GPIO_FN(VI1_D5_B5_C5), GPIO_FN(VI1_D6_B6_C6), GPIO_FN(VI1_D7_B7_C7),
- GPIO_FN(VI1_D8_G0_Y0), GPIO_FN(VI1_D9_G1_Y1), GPIO_FN(VI1_D10_G2_Y2),
- GPIO_FN(VI1_D11_G3_Y3), GPIO_FN(VI1_FIELD),
-
- GPIO_FN(VI3_D10_Y2), GPIO_FN(VI3_FIELD),
-
- GPIO_FN(VI4_CLK),
-
- GPIO_FN(VI5_CLK), GPIO_FN(VI5_D9_Y1), GPIO_FN(VI5_D10_Y2),
- GPIO_FN(VI5_D11_Y3), GPIO_FN(VI5_FIELD),
-
- GPIO_FN(HRTS0), GPIO_FN(HCTS1), GPIO_FN(SCK0), GPIO_FN(CTS0),
- GPIO_FN(RTS0), GPIO_FN(TX0), GPIO_FN(RX0), GPIO_FN(SCK1),
- GPIO_FN(CTS1), GPIO_FN(RTS1), GPIO_FN(TX1), GPIO_FN(RX1),
- GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_TX), GPIO_FN(CAN0_RX), GPIO_FN(CAN_CLK),
- GPIO_FN(CAN1_TX), GPIO_FN(CAN1_RX),
-
- GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), GPIO_FN(SD0_DAT0),
- GPIO_FN(SD0_DAT1), GPIO_FN(SD0_DAT2), GPIO_FN(SD0_DAT3),
- GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), GPIO_FN(ADICLK),
- GPIO_FN(ADICS_SAMP), GPIO_FN(ADIDATA), GPIO_FN(ADICHS0),
- GPIO_FN(ADICHS1), GPIO_FN(ADICHS2), GPIO_FN(AVS1),
- GPIO_FN(AVS2),
-
- GPIO_FN(DU0_DR0_DATA0), GPIO_FN(DU0_DR1_DATA1),
- GPIO_FN(DU0_DR2_Y4_DATA2), GPIO_FN(DU0_DR3_Y5_DATA3),
- GPIO_FN(DU0_DR4_Y6_DATA4), GPIO_FN(DU0_DR5_Y7_DATA5),
- GPIO_FN(DU0_DR6_Y8_DATA6), GPIO_FN(DU0_DR7_Y9_DATA7),
- GPIO_FN(DU0_DG0_DATA8), GPIO_FN(DU0_DG1_DATA9),
- GPIO_FN(DU0_DG2_C6_DATA10), GPIO_FN(DU0_DG3_C7_DATA11),
- GPIO_FN(DU0_DG4_Y0_DATA12), GPIO_FN(DU0_DG5_Y1_DATA13),
- GPIO_FN(DU0_DG6_Y2_DATA14), GPIO_FN(DU0_DG7_Y3_DATA15),
- GPIO_FN(DU0_DB0), GPIO_FN(DU0_DB1),
- GPIO_FN(DU0_DB2_C0), GPIO_FN(DU0_DB3_C1), GPIO_FN(DU0_DB4_C2),
- GPIO_FN(DU0_DB5_C3), GPIO_FN(DU0_DB6_C4), GPIO_FN(DU0_DB7_C5),
-
- GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(DU0_EXVSYNC_DU0_VSYNC),
- GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(DU0_DISP),
- GPIO_FN(DU0_CDE), GPIO_FN(DU1_DR2_Y4_DATA0), GPIO_FN(DU1_DR3_Y5_DATA1),
- GPIO_FN(DU1_DR4_Y6_DATA2), GPIO_FN(DU1_DR5_Y7_DATA3),
- GPIO_FN(DU1_DR6_DATA4), GPIO_FN(DU1_DR7_DATA5),
- GPIO_FN(DU1_DG2_C6_DATA6), GPIO_FN(DU1_DG3_C7_DATA7),
- GPIO_FN(DU1_DG4_Y0_DATA8), GPIO_FN(DU1_DG5_Y1_DATA9),
- GPIO_FN(DU1_DG6_Y2_DATA10), GPIO_FN(DU1_DG7_Y3_DATA11),
- GPIO_FN(A20), GPIO_FN(MOSI_IO0), GPIO_FN(A21), GPIO_FN(MISO_IO1),
- GPIO_FN(A22), GPIO_FN(IO2), GPIO_FN(A23), GPIO_FN(IO3),
- GPIO_FN(A24), GPIO_FN(SPCLK), GPIO_FN(A25), GPIO_FN(SSL),
-
- GPIO_FN(VI2_CLK), GPIO_FN(AVB_RX_CLK), GPIO_FN(VI2_CLKENB),
- GPIO_FN(AVB_RX_DV), GPIO_FN(VI2_HSYNC), GPIO_FN(AVB_RXD0),
- GPIO_FN(VI2_VSYNC), GPIO_FN(AVB_RXD1), GPIO_FN(VI2_D0_C0),
- GPIO_FN(AVB_RXD2), GPIO_FN(VI2_D1_C1), GPIO_FN(AVB_RXD3),
- GPIO_FN(VI2_D2_C2), GPIO_FN(AVB_RXD4), GPIO_FN(VI2_D3_C3),
- GPIO_FN(AVB_RXD5), GPIO_FN(VI2_D4_C4), GPIO_FN(AVB_RXD6),
- GPIO_FN(VI2_D5_C5), GPIO_FN(AVB_RXD7), GPIO_FN(VI2_D6_C6),
- GPIO_FN(AVB_RX_ER), GPIO_FN(VI2_D7_C7), GPIO_FN(AVB_COL),
- GPIO_FN(VI2_D8_Y0), GPIO_FN(AVB_TXD3), GPIO_FN(VI2_D9_Y1),
- GPIO_FN(AVB_TX_EN), GPIO_FN(VI2_D10_Y2), GPIO_FN(AVB_TXD0),
- GPIO_FN(VI2_D11_Y3), GPIO_FN(AVB_TXD1), GPIO_FN(VI2_FIELD),
- GPIO_FN(AVB_TXD2),
-
- GPIO_FN(VI3_CLK), GPIO_FN(AVB_TX_CLK), GPIO_FN(VI3_CLKENB),
- GPIO_FN(AVB_TXD4), GPIO_FN(VI3_HSYNC), GPIO_FN(AVB_TXD5),
- GPIO_FN(VI3_VSYNC), GPIO_FN(AVB_TXD6), GPIO_FN(VI3_D0_C0),
- GPIO_FN(AVB_TXD7), GPIO_FN(VI3_D1_C1), GPIO_FN(AVB_TX_ER),
- GPIO_FN(VI3_D2_C2), GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI3_D3_C3),
- GPIO_FN(AVB_MDC), GPIO_FN(VI3_D4_C4), GPIO_FN(AVB_MDIO),
- GPIO_FN(VI3_D5_C5), GPIO_FN(AVB_LINK), GPIO_FN(VI3_D6_C6),
- GPIO_FN(AVB_MAGIC), GPIO_FN(VI3_D7_C7), GPIO_FN(AVB_PHY_INT),
- GPIO_FN(VI3_D8_Y0), GPIO_FN(AVB_CRS), GPIO_FN(VI3_D9_Y1),
- GPIO_FN(AVB_GTXREFCLK), GPIO_FN(VI3_D11_Y3),
-
- GPIO_FN(VI4_CLKENB), GPIO_FN(VI0_D12_G4_Y4), GPIO_FN(VI4_HSYNC),
- GPIO_FN(VI0_D13_G5_Y5), GPIO_FN(VI4_VSYNC), GPIO_FN(VI0_D14_G6_Y6),
- GPIO_FN(VI4_D0_C0), GPIO_FN(VI0_D15_G7_Y7), GPIO_FN(VI4_D1_C1),
- GPIO_FN(VI0_D16_R0), GPIO_FN(VI1_D12_G4_Y4_0), GPIO_FN(VI4_D2_C2),
- GPIO_FN(VI0_D17_R1), GPIO_FN(VI1_D13_G5_Y5_0), GPIO_FN(VI4_D3_C3),
- GPIO_FN(VI0_D18_R2), GPIO_FN(VI1_D14_G6_Y6_0), GPIO_FN(VI4_D4_C4),
- GPIO_FN(VI0_D19_R3), GPIO_FN(VI1_D15_G7_Y7_0), GPIO_FN(VI4_D5_C5),
- GPIO_FN(VI0_D20_R4), GPIO_FN(VI2_D12_Y4), GPIO_FN(VI4_D6_C6),
- GPIO_FN(VI0_D21_R5), GPIO_FN(VI2_D13_Y5), GPIO_FN(VI4_D7_C7),
- GPIO_FN(VI0_D22_R6), GPIO_FN(VI2_D14_Y6), GPIO_FN(VI4_D8_Y0),
- GPIO_FN(VI0_D23_R7), GPIO_FN(VI2_D15_Y7), GPIO_FN(VI4_D9_Y1),
- GPIO_FN(VI3_D12_Y4), GPIO_FN(VI4_D10_Y2), GPIO_FN(VI3_D13_Y5),
- GPIO_FN(VI4_D11_Y3), GPIO_FN(VI3_D14_Y6), GPIO_FN(VI4_FIELD),
- GPIO_FN(VI3_D15_Y7),
-
- GPIO_FN(VI5_CLKENB), GPIO_FN(VI1_D12_G4_Y4_1), GPIO_FN(VI5_HSYNC),
- GPIO_FN(VI1_D13_G5_Y5_1), GPIO_FN(VI5_VSYNC), GPIO_FN(VI1_D14_G6_Y6_1),
- GPIO_FN(VI5_D0_C0), GPIO_FN(VI1_D15_G7_Y7_1), GPIO_FN(VI5_D1_C1),
- GPIO_FN(VI1_D16_R0), GPIO_FN(VI5_D2_C2), GPIO_FN(VI1_D17_R1),
- GPIO_FN(VI5_D3_C3), GPIO_FN(VI1_D18_R2), GPIO_FN(VI5_D4_C4),
- GPIO_FN(VI1_D19_R3), GPIO_FN(VI5_D5_C5), GPIO_FN(VI1_D20_R4),
- GPIO_FN(VI5_D6_C6), GPIO_FN(VI1_D21_R5), GPIO_FN(VI5_D7_C7),
- GPIO_FN(VI1_D22_R6), GPIO_FN(VI5_D8_Y0), GPIO_FN(VI1_D23_R7),
-
- GPIO_FN(MSIOF0_SCK), GPIO_FN(HSCK0), GPIO_FN(MSIOF0_SYNC),
- GPIO_FN(HCTS0), GPIO_FN(MSIOF0_TXD), GPIO_FN(HTX0),
- GPIO_FN(MSIOF0_RXD), GPIO_FN(HRX0), GPIO_FN(MSIOF1_SCK),
- GPIO_FN(HSCK1), GPIO_FN(MSIOF1_SYNC), GPIO_FN(HRTS1),
- GPIO_FN(MSIOF1_TXD), GPIO_FN(HTX1), GPIO_FN(MSIOF1_RXD),
- GPIO_FN(HRX1), GPIO_FN(DRACK0), GPIO_FN(SCK2),
- GPIO_FN(DACK0), GPIO_FN(TX2), GPIO_FN(DREQ0),
- GPIO_FN(RX2), GPIO_FN(DACK1), GPIO_FN(SCK3),
- GPIO_FN(TX3), GPIO_FN(DREQ1), GPIO_FN(RX3),
-
- GPIO_FN(PWM0), GPIO_FN(TCLK1), GPIO_FN(FSO_CFE_0),
- GPIO_FN(PWM1), GPIO_FN(TCLK2), GPIO_FN(FSO_CFE_1),
- GPIO_FN(PWM2), GPIO_FN(TCLK3), GPIO_FN(FSO_TOE),
- GPIO_FN(PWM3), GPIO_FN(PWM4),
- GPIO_FN(SSI_SCK3), GPIO_FN(TPU0TO0),
- GPIO_FN(SSI_WS3), GPIO_FN(TPU0TO1),
- GPIO_FN(SSI_SDATA3), GPIO_FN(TPU0TO2),
- GPIO_FN(SSI_SCK4), GPIO_FN(TPU0TO3),
- GPIO_FN(SSI_WS4), GPIO_FN(SSI_SDATA4),
- GPIO_FN(AUDIO_CLKOUT), GPIO_FN(AUDIO_CLKA), GPIO_FN(AUDIO_CLKB),
-
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_0_28_FN, FN_IP1_4,
- GP_0_27_FN, FN_IP1_3,
- GP_0_26_FN, FN_IP1_2,
- GP_0_25_FN, FN_IP1_1,
- GP_0_24_FN, FN_IP1_0,
- GP_0_23_FN, FN_IP0_23,
- GP_0_22_FN, FN_IP0_22,
- GP_0_21_FN, FN_IP0_21,
- GP_0_20_FN, FN_IP0_20,
- GP_0_19_FN, FN_IP0_19,
- GP_0_18_FN, FN_IP0_18,
- GP_0_17_FN, FN_IP0_17,
- GP_0_16_FN, FN_IP0_16,
- GP_0_15_FN, FN_IP0_15,
- GP_0_14_FN, FN_IP0_14,
- GP_0_13_FN, FN_IP0_13,
- GP_0_12_FN, FN_IP0_12,
- GP_0_11_FN, FN_IP0_11,
- GP_0_10_FN, FN_IP0_10,
- GP_0_9_FN, FN_IP0_9,
- GP_0_8_FN, FN_IP0_8,
- GP_0_7_FN, FN_IP0_7,
- GP_0_6_FN, FN_IP0_6,
- GP_0_5_FN, FN_IP0_5,
- GP_0_4_FN, FN_IP0_4,
- GP_0_3_FN, FN_IP0_3,
- GP_0_2_FN, FN_IP0_2,
- GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0 }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_22_FN, FN_DU1_CDE,
- GP_1_21_FN, FN_DU1_DISP,
- GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
- GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
- GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
- GP_1_17_FN, FN_DU1_DB7_C5,
- GP_1_16_FN, FN_DU1_DB6_C4,
- GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
- GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
- GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
- GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
- GP_1_11_FN, FN_IP1_16,
- GP_1_10_FN, FN_IP1_15,
- GP_1_9_FN, FN_IP1_14,
- GP_1_8_FN, FN_IP1_13,
- GP_1_7_FN, FN_IP1_12,
- GP_1_6_FN, FN_IP1_11,
- GP_1_5_FN, FN_IP1_10,
- GP_1_4_FN, FN_IP1_9,
- GP_1_3_FN, FN_IP1_8,
- GP_1_2_FN, FN_IP1_7,
- GP_1_1_FN, FN_IP1_6,
- GP_1_0_FN, FN_IP1_5, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_A15,
- GP_2_30_FN, FN_A14,
- GP_2_29_FN, FN_A13,
- GP_2_28_FN, FN_A12,
- GP_2_27_FN, FN_A11,
- GP_2_26_FN, FN_A10,
- GP_2_25_FN, FN_A9,
- GP_2_24_FN, FN_A8,
- GP_2_23_FN, FN_A7,
- GP_2_22_FN, FN_A6,
- GP_2_21_FN, FN_A5,
- GP_2_20_FN, FN_A4,
- GP_2_19_FN, FN_A3,
- GP_2_18_FN, FN_A2,
- GP_2_17_FN, FN_A1,
- GP_2_16_FN, FN_A0,
- GP_2_15_FN, FN_D15,
- GP_2_14_FN, FN_D14,
- GP_2_13_FN, FN_D13,
- GP_2_12_FN, FN_D12,
- GP_2_11_FN, FN_D11,
- GP_2_10_FN, FN_D10,
- GP_2_9_FN, FN_D9,
- GP_2_8_FN, FN_D8,
- GP_2_7_FN, FN_D7,
- GP_2_6_FN, FN_D6,
- GP_2_5_FN, FN_D5,
- GP_2_4_FN, FN_D4,
- GP_2_3_FN, FN_D3,
- GP_2_2_FN, FN_D2,
- GP_2_1_FN, FN_D1,
- GP_2_0_FN, FN_D0 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_3_27_FN, FN_CS0,
- GP_3_26_FN, FN_IP1_22,
- GP_3_25_FN, FN_IP1_21,
- GP_3_24_FN, FN_IP1_20,
- GP_3_23_FN, FN_IP1_19,
- GP_3_22_FN, FN_IRQ3,
- GP_3_21_FN, FN_IRQ2,
- GP_3_20_FN, FN_IRQ1,
- GP_3_19_FN, FN_IRQ0,
- GP_3_18_FN, FN_EX_WAIT0,
- GP_3_17_FN, FN_WE1,
- GP_3_16_FN, FN_WE0,
- GP_3_15_FN, FN_RD_WR,
- GP_3_14_FN, FN_RD,
- GP_3_13_FN, FN_BS,
- GP_3_12_FN, FN_EX_CS5,
- GP_3_11_FN, FN_EX_CS4,
- GP_3_10_FN, FN_EX_CS3,
- GP_3_9_FN, FN_EX_CS2,
- GP_3_8_FN, FN_EX_CS1,
- GP_3_7_FN, FN_EX_CS0,
- GP_3_6_FN, FN_CS1_A26,
- GP_3_5_FN, FN_IP1_18,
- GP_3_4_FN, FN_IP1_17,
- GP_3_3_FN, FN_A19,
- GP_3_2_FN, FN_A18,
- GP_3_1_FN, FN_A17,
- GP_3_0_FN, FN_A16 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_16_FN, FN_VI0_FIELD,
- GP_4_15_FN, FN_VI0_D11_G3_Y3,
- GP_4_14_FN, FN_VI0_D10_G2_Y2,
- GP_4_13_FN, FN_VI0_D9_G1_Y1,
- GP_4_12_FN, FN_VI0_D8_G0_Y0,
- GP_4_11_FN, FN_VI0_D7_B7_C7,
- GP_4_10_FN, FN_VI0_D6_B6_C6,
- GP_4_9_FN, FN_VI0_D5_B5_C5,
- GP_4_8_FN, FN_VI0_D4_B4_C4,
- GP_4_7_FN, FN_VI0_D3_B3_C3,
- GP_4_6_FN, FN_VI0_D2_B2_C2,
- GP_4_5_FN, FN_VI0_D1_B1_C1,
- GP_4_4_FN, FN_VI0_D0_B0_C0,
- GP_4_3_FN, FN_VI0_VSYNC,
- GP_4_2_FN, FN_VI0_HSYNC,
- GP_4_1_FN, FN_VI0_CLKENB,
- GP_4_0_FN, FN_VI0_CLK }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_16_FN, FN_VI1_FIELD,
- GP_5_15_FN, FN_VI1_D11_G3_Y3,
- GP_5_14_FN, FN_VI1_D10_G2_Y2,
- GP_5_13_FN, FN_VI1_D9_G1_Y1,
- GP_5_12_FN, FN_VI1_D8_G0_Y0,
- GP_5_11_FN, FN_VI1_D7_B7_C7,
- GP_5_10_FN, FN_VI1_D6_B6_C6,
- GP_5_9_FN, FN_VI1_D5_B5_C5,
- GP_5_8_FN, FN_VI1_D4_B4_C4,
- GP_5_7_FN, FN_VI1_D3_B3_C3,
- GP_5_6_FN, FN_VI1_D2_B2_C2,
- GP_5_5_FN, FN_VI1_D1_B1_C1,
- GP_5_4_FN, FN_VI1_D0_B0_C0,
- GP_5_3_FN, FN_VI1_VSYNC,
- GP_5_2_FN, FN_VI1_HSYNC,
- GP_5_1_FN, FN_VI1_CLKENB,
- GP_5_0_FN, FN_VI1_CLK }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_16_FN, FN_IP2_16,
- GP_6_15_FN, FN_IP2_15,
- GP_6_14_FN, FN_IP2_14,
- GP_6_13_FN, FN_IP2_13,
- GP_6_12_FN, FN_IP2_12,
- GP_6_11_FN, FN_IP2_11,
- GP_6_10_FN, FN_IP2_10,
- GP_6_9_FN, FN_IP2_9,
- GP_6_8_FN, FN_IP2_8,
- GP_6_7_FN, FN_IP2_7,
- GP_6_6_FN, FN_IP2_6,
- GP_6_5_FN, FN_IP2_5,
- GP_6_4_FN, FN_IP2_4,
- GP_6_3_FN, FN_IP2_3,
- GP_6_2_FN, FN_IP2_2,
- GP_6_1_FN, FN_IP2_1,
- GP_6_0_FN, FN_IP2_0 }
- },
- { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_16_FN, FN_VI3_FIELD,
- GP_7_15_FN, FN_IP3_14,
- GP_7_14_FN, FN_VI3_D10_Y2,
- GP_7_13_FN, FN_IP3_13,
- GP_7_12_FN, FN_IP3_12,
- GP_7_11_FN, FN_IP3_11,
- GP_7_10_FN, FN_IP3_10,
- GP_7_9_FN, FN_IP3_9,
- GP_7_8_FN, FN_IP3_8,
- GP_7_7_FN, FN_IP3_7,
- GP_7_6_FN, FN_IP3_6,
- GP_7_5_FN, FN_IP3_5,
- GP_7_4_FN, FN_IP3_4,
- GP_7_3_FN, FN_IP3_3,
- GP_7_2_FN, FN_IP3_2,
- GP_7_1_FN, FN_IP3_1,
- GP_7_0_FN, FN_IP3_0 }
- },
- { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_8_16_FN, FN_IP4_24,
- GP_8_15_FN, FN_IP4_23,
- GP_8_14_FN, FN_IP4_22,
- GP_8_13_FN, FN_IP4_21,
- GP_8_12_FN, FN_IP4_20_19,
- GP_8_11_FN, FN_IP4_18_17,
- GP_8_10_FN, FN_IP4_16_15,
- GP_8_9_FN, FN_IP4_14_13,
- GP_8_8_FN, FN_IP4_12_11,
- GP_8_7_FN, FN_IP4_10_9,
- GP_8_6_FN, FN_IP4_8_7,
- GP_8_5_FN, FN_IP4_6_5,
- GP_8_4_FN, FN_IP4_4,
- GP_8_3_FN, FN_IP4_3_2,
- GP_8_2_FN, FN_IP4_1,
- GP_8_1_FN, FN_IP4_0,
- GP_8_0_FN, FN_VI4_CLK }
- },
- { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_9_16_FN, FN_VI5_FIELD,
- GP_9_15_FN, FN_VI5_D11_Y3,
- GP_9_14_FN, FN_VI5_D10_Y2,
- GP_9_13_FN, FN_VI5_D9_Y1,
- GP_9_12_FN, FN_IP5_11,
- GP_9_11_FN, FN_IP5_10,
- GP_9_10_FN, FN_IP5_9,
- GP_9_9_FN, FN_IP5_8,
- GP_9_8_FN, FN_IP5_7,
- GP_9_7_FN, FN_IP5_6,
- GP_9_6_FN, FN_IP5_5,
- GP_9_5_FN, FN_IP5_4,
- GP_9_4_FN, FN_IP5_3,
- GP_9_3_FN, FN_IP5_2,
- GP_9_2_FN, FN_IP5_1,
- GP_9_1_FN, FN_IP5_0,
- GP_9_0_FN, FN_VI5_CLK }
- },
- { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
- GP_10_31_FN, FN_CAN1_RX,
- GP_10_30_FN, FN_CAN1_TX,
- GP_10_29_FN, FN_CAN_CLK,
- GP_10_28_FN, FN_CAN0_RX,
- GP_10_27_FN, FN_CAN0_TX,
- GP_10_26_FN, FN_SCIF_CLK,
- GP_10_25_FN, FN_IP6_18_17,
- GP_10_24_FN, FN_IP6_16,
- GP_10_23_FN, FN_IP6_15_14,
- GP_10_22_FN, FN_IP6_13_12,
- GP_10_21_FN, FN_IP6_11_10,
- GP_10_20_FN, FN_IP6_9_8,
- GP_10_19_FN, FN_RX1,
- GP_10_18_FN, FN_TX1,
- GP_10_17_FN, FN_RTS1,
- GP_10_16_FN, FN_CTS1,
- GP_10_15_FN, FN_SCK1,
- GP_10_14_FN, FN_RX0,
- GP_10_13_FN, FN_TX0,
- GP_10_12_FN, FN_RTS0,
- GP_10_11_FN, FN_CTS0,
- GP_10_10_FN, FN_SCK0,
- GP_10_9_FN, FN_IP6_7,
- GP_10_8_FN, FN_IP6_6,
- GP_10_7_FN, FN_HCTS1,
- GP_10_6_FN, FN_IP6_5,
- GP_10_5_FN, FN_IP6_4,
- GP_10_4_FN, FN_IP6_3,
- GP_10_3_FN, FN_IP6_2,
- GP_10_2_FN, FN_HRTS0,
- GP_10_1_FN, FN_IP6_1,
- GP_10_0_FN, FN_IP6_0 }
- },
- { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
- 0, 0,
- 0, 0,
- GP_11_29_FN, FN_AVS2,
- GP_11_28_FN, FN_AVS1,
- GP_11_27_FN, FN_ADICHS2,
- GP_11_26_FN, FN_ADICHS1,
- GP_11_25_FN, FN_ADICHS0,
- GP_11_24_FN, FN_ADIDATA,
- GP_11_23_FN, FN_ADICS_SAMP,
- GP_11_22_FN, FN_ADICLK,
- GP_11_21_FN, FN_IP7_20,
- GP_11_20_FN, FN_IP7_19,
- GP_11_19_FN, FN_IP7_18,
- GP_11_18_FN, FN_IP7_17,
- GP_11_17_FN, FN_IP7_16,
- GP_11_16_FN, FN_IP7_15_14,
- GP_11_15_FN, FN_IP7_13_12,
- GP_11_14_FN, FN_IP7_11_10,
- GP_11_13_FN, FN_IP7_9_8,
- GP_11_12_FN, FN_SD0_WP,
- GP_11_11_FN, FN_SD0_CD,
- GP_11_10_FN, FN_SD0_DAT3,
- GP_11_9_FN, FN_SD0_DAT2,
- GP_11_8_FN, FN_SD0_DAT1,
- GP_11_7_FN, FN_SD0_DAT0,
- GP_11_6_FN, FN_SD0_CMD,
- GP_11_5_FN, FN_SD0_CLK,
- GP_11_4_FN, FN_IP7_7,
- GP_11_3_FN, FN_IP7_6,
- GP_11_2_FN, FN_IP7_5_4,
- GP_11_1_FN, FN_IP7_3_2,
- GP_11_0_FN, FN_IP7_1_0 }
- },
- /* IPSR0 */
- { PINMUX_CFG_REG("IPSR0", 0xE6060040, 32 ,1) {
- /* IP0_31 [1] */
- 0, 0,
- /* IP0_30 [1] */
- 0, 0,
- /* IP0_29 [1] */
- 0, 0,
- /* IP0_28 [1] */
- 0, 0,
- /* IP0_27 [1] */
- 0, 0,
- /* IP0_26 [1] */
- 0, 0,
- /* IP0_25 [1] */
- 0, 0,
- /* IP0_24 [1] */
- 0, 0,
- /* IP0_23 [1] */
- FN_DU0_DB7_C5, 0,
- /* IP0_22 [1] */
- FN_DU0_DB6_C4, 0,
- /* IP0_21 [1] */
- FN_DU0_DB5_C3, 0,
- /* IP0_20 [1] */
- FN_DU0_DB4_C2, 0,
- /* IP0_19 [1] */
- FN_DU0_DB3_C1, 0,
- /* IP0_18 [1] */
- FN_DU0_DB2_C0, 0,
- /* IP0_17 [1] */
- FN_DU0_DB1, 0,
- /* IP0_16 [1] */
- FN_DU0_DB0, 0,
- /* IP0_15 [1] */
- FN_DU0_DG7_Y3_DATA15, 0,
- /* IP0_14 [1] */
- FN_DU0_DG6_Y2_DATA14, 0,
- /* IP0_13 [1] */
- FN_DU0_DG5_Y1_DATA13, 0,
- /* IP0_12 [1] */
- FN_DU0_DG4_Y0_DATA12, 0,
- /* IP0_11 [1] */
- FN_DU0_DG3_C7_DATA11, 0,
- /* IP0_10 [1] */
- FN_DU0_DG2_C6_DATA10, 0,
- /* IP0_9 [1] */
- FN_DU0_DG1_DATA9, 0,
- /* IP0_8 [1] */
- FN_DU0_DG0_DATA8, 0,
- /* IP0_7 [1] */
- FN_DU0_DR7_Y9_DATA7, 0,
- /* IP0_6 [1] */
- FN_DU0_DR6_Y8_DATA6, 0,
- /* IP0_5 [1] */
- FN_DU0_DR5_Y7_DATA5, 0,
- /* IP0_4 [1] */
- FN_DU0_DR4_Y6_DATA4, 0,
- /* IP0_3 [1] */
- FN_DU0_DR3_Y5_DATA3, 0,
- /* IP0_2 [1] */
- FN_DU0_DR2_Y4_DATA2, 0,
- /* IP0_1 [1] */
- FN_DU0_DR1_DATA1, 0,
- /* IP0_0 [1] */
- FN_DU0_DR0_DATA0, 0, }
- },
- /* IPSR1 */
- { PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 1) {
- /* IP1_31 [1] */
- 0, 0,
- /* IP1_30 [1] */
- 0, 0,
- /* IP1_29 [1] */
- 0, 0,
- /* IP1_28 [1] */
- 0, 0,
- /* IP1_27 [1] */
- 0, 0,
- /* IP1_26 [1] */
- 0, 0,
- /* IP1_25 [1] */
- 0, 0,
- /* IP1_24 [1] */
- 0, 0,
- /* IP1_23 [1] */
- 0, 0,
- /* IP1_22 [1] */
- FN_A25, FN_SSL,
- /* IP1_21 [1] */
- FN_A24, FN_SPCLK,
- /* IP1_20 [1] */
- FN_A23, FN_IO3,
- /* IP1_19 [1] */
- FN_A22, FN_IO2,
- /* IP1_18 [1] */
- FN_A21, FN_MISO_IO1,
- /* IP1_17 [1] */
- FN_A20, FN_MOSI_IO0,
- /* IP1_16 [1] */
- FN_DU1_DG7_Y3_DATA11, 0,
- /* IP1_15 [1] */
- FN_DU1_DG6_Y2_DATA10, 0,
- /* IP1_14 [1] */
- FN_DU1_DG5_Y1_DATA9, 0,
- /* IP1_13 [1] */
- FN_DU1_DG4_Y0_DATA8, 0,
- /* IP1_12 [1] */
- FN_DU1_DG3_C7_DATA7, 0,
- /* IP1_11 [1] */
- FN_DU1_DG2_C6_DATA6, 0,
- /* IP1_10 [1] */
- FN_DU1_DR7_DATA5, 0,
- /* IP1_9 [1] */
- FN_DU1_DR6_DATA4, 0,
- /* IP1_8 [1] */
- FN_DU1_DR5_Y7_DATA3, 0,
- /* IP1_7 [1] */
- FN_DU1_DR4_Y6_DATA2, 0,
- /* IP1_6 [1] */
- FN_DU1_DR3_Y5_DATA1, 0,
- /* IP1_5 [1] */
- FN_DU1_DR2_Y4_DATA0, 0,
- /* IP1_4 [1] */
- FN_DU0_CDE, 0,
- /* IP1_3 [1] */
- FN_DU0_DISP, 0,
- /* IP1_2 [1] */
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
- /* IP1_1 [1] */
- FN_DU0_EXVSYNC_DU0_VSYNC, 0,
- /* IP1_0 [1] */
- FN_DU0_EXHSYNC_DU0_HSYNC, 0, }
- },
- /* IPSR2 */
- { PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 1) {
- /* IP2_31 [1] */
- 0, 0,
- /* IP2_30 [1] */
- 0, 0,
- /* IP2_29 [1] */
- 0, 0,
- /* IP2_28 [1] */
- 0, 0,
- /* IP2_27 [1] */
- 0, 0,
- /* IP2_26 [1] */
- 0, 0,
- /* IP2_25 [1] */
- 0, 0,
- /* IP2_24 [1] */
- 0, 0,
- /* IP2_23 [1] */
- 0, 0,
- /* IP2_22 [1] */
- 0, 0,
- /* IP2_21 [1] */
- 0, 0,
- /* IP2_20 [1] */
- 0, 0,
- /* IP2_19 [1] */
- 0, 0,
- /* IP2_18 [1] */
- 0, 0,
- /* IP2_17 [1] */
- 0, 0,
- /* IP2_16 [1] */
- FN_VI2_FIELD, FN_AVB_TXD2,
- /* IP2_15 [1] */
- FN_VI2_D11_Y3, FN_AVB_TXD1,
- /* IP2_14 [1] */
- FN_VI2_D10_Y2, FN_AVB_TXD0,
- /* IP2_13 [1] */
- FN_VI2_D9_Y1, FN_AVB_TX_EN,
- /* IP2_12 [1] */
- FN_VI2_D8_Y0, FN_AVB_TXD3,
- /* IP2_11 [1] */
- FN_VI2_D7_C7, FN_AVB_COL,
- /* IP2_10 [1] */
- FN_VI2_D6_C6, FN_AVB_RX_ER,
- /* IP2_9 [1] */
- FN_VI2_D5_C5, FN_AVB_RXD7,
- /* IP2_8 [1] */
- FN_VI2_D4_C4, FN_AVB_RXD6,
- /* IP2_7 [1] */
- FN_VI2_D3_C3, FN_AVB_RXD5,
- /* IP2_6 [1] */
- FN_VI2_D2_C2, FN_AVB_RXD4,
- /* IP2_5 [1] */
- FN_VI2_D1_C1, FN_AVB_RXD3,
- /* IP2_4 [1] */
- FN_VI2_D0_C0, FN_AVB_RXD2,
- /* IP2_3 [1] */
- FN_VI2_VSYNC, FN_AVB_RXD1,
- /* IP2_2 [1] */
- FN_VI2_HSYNC, FN_AVB_RXD0,
- /* IP2_1 [1] */
- FN_VI2_CLKENB, FN_AVB_RX_DV,
- /* IP2_0 [1] */
- FN_VI2_CLK, FN_AVB_RX_CLK, }
- },
- /* IPSR3 */
- { PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 1) {
- /* IP3_31 [1] */
- 0, 0,
- /* IP3_30 [1] */
- 0, 0,
- /* IP3_29 [1] */
- 0, 0,
- /* IP3_28 [1] */
- 0, 0,
- /* IP3_27 [1] */
- 0, 0,
- /* IP3_26 [1] */
- 0, 0,
- /* IP3_25 [1] */
- 0, 0,
- /* IP3_24 [1] */
- 0, 0,
- /* IP3_23 [1] */
- 0, 0,
- /* IP3_22 [1] */
- 0, 0,
- /* IP3_21 [1] */
- 0, 0,
- /* IP3_20 [1] */
- 0, 0,
- /* IP3_19 [1] */
- 0, 0,
- /* IP3_18 [1] */
- 0, 0,
- /* IP3_17 [1] */
- 0, 0,
- /* IP3_16 [1] */
- 0, 0,
- /* IP3_15 [1] */
- 0, 0,
- /* IP3_14 [1] */
- FN_VI3_D11_Y3, 0,
- /* IP3_13 [1] */
- FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
- /* IP3_12 [1] */
- FN_VI3_D8_Y0, FN_AVB_CRS,
- /* IP3_11 [1] */
- FN_VI3_D7_C7, FN_AVB_PHY_INT,
- /* IP3_10 [1] */
- FN_VI3_D6_C6, FN_AVB_MAGIC,
- /* IP3_9 [1] */
- FN_VI3_D5_C5, FN_AVB_LINK,
- /* IP3_8 [1] */
- FN_VI3_D4_C4, FN_AVB_MDIO,
- /* IP3_7 [1] */
- FN_VI3_D3_C3, FN_AVB_MDC,
- /* IP3_6 [1] */
- FN_VI3_D2_C2, FN_AVB_GTX_CLK,
- /* IP3_5 [1] */
- FN_VI3_D1_C1, FN_AVB_TX_ER,
- /* IP3_4 [1] */
- FN_VI3_D0_C0, FN_AVB_TXD7,
- /* IP3_3 [1] */
- FN_VI3_VSYNC, FN_AVB_TXD6,
- /* IP3_2 [1] */
- FN_VI3_HSYNC, FN_AVB_TXD5,
- /* IP3_1 [1] */
- FN_VI3_CLKENB, FN_AVB_TXD4,
- /* IP3_0 [1] */
- FN_VI3_CLK, FN_AVB_TX_CLK,}
- },
- /* IPSR4 */
- { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
- 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 1) {
- /* IP4_31 [1] */
- 0, 0,
- /* IP4_30 [1] */
- 0, 0,
- /* IP4_29 [1] */
- 0, 0,
- /* IP4_28 [1] */
- 0, 0,
- /* IP4_27 [1] */
- 0, 0,
- /* IP4_26 [1] */
- 0, 0,
- /* IP4_25 [1] */
- 0, 0,
- /* IP4_24 [1] */
- FN_VI4_FIELD, FN_VI3_D15_Y7,
- /* IP4_23 [1] */
- FN_VI4_D11_Y3, FN_VI3_D14_Y6,
- /* IP4_22 [1] */
- FN_VI4_D10_Y2, FN_VI3_D13_Y5,
- /* IP4_21 [1] */
- FN_VI4_D9_Y1, FN_VI3_D12_Y4,
- /* IP4_20_19 [2] */
- FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
- /* IP4_18_17 [2] */
- FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
- /* IP4_16_15 [2] */
- FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
- /* IP4_14_13 [2] */
- FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
- /* IP4_12_11 [2] */
- FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0, 0,
- /* IP4_10_9 [2] */
- FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, 0,
- /* IP4_8_7 [2] */
- FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0, 0,
- /* IP4_6_5 [2] */
- FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, 0,
- /* IP4_4 [1] */
- FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
- /* IP4_3_2 [2] */
- FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, 0, 0,
- /* IP4_1 [1] */
- FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
- /* IP4_0 [1] */
- FN_VI4_CLKENB, FN_VI0_D12_G4_Y4,}
- },
- /* IPSR5 */
- { PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 1) {
- /* IP5_31 [1] */
- 0, 0,
- /* IP5_30 [1] */
- 0, 0,
- /* IP5_29 [1] */
- 0, 0,
- /* IP5_28 [1] */
- 0, 0,
- /* IP5_27 [1] */
- 0, 0,
- /* IP5_26 [1] */
- 0, 0,
- /* IP5_25 [1] */
- 0, 0,
- /* IP5_24 [1] */
- 0, 0,
- /* IP5_23 [1] */
- 0, 0,
- /* IP5_22 [1] */
- 0, 0,
- /* IP5_21 [1] */
- 0, 0,
- /* IP5_20 [1] */
- 0, 0,
- /* IP5_19 [1] */
- 0, 0,
- /* IP5_18 [1] */
- 0, 0,
- /* IP5_17 [1] */
- 0, 0,
- /* IP5_16 [1] */
- 0, 0,
- /* IP5_15 [1] */
- 0, 0,
- /* IP5_14 [1] */
- 0, 0,
- /* IP5_13 [1] */
- 0, 0,
- /* IP5_12 [1] */
- 0, 0,
- /* IP5_11 [1] */
- FN_VI5_D8_Y0, FN_VI1_D23_R7,
- /* IP5_10 [1] */
- FN_VI5_D7_C7, FN_VI1_D22_R6,
- /* IP5_9 [1] */
- FN_VI5_D6_C6, FN_VI1_D21_R5,
- /* IP5_8 [1] */
- FN_VI5_D5_C5, FN_VI1_D20_R4,
- /* IP5_7 [1] */
- FN_VI5_D4_C4, FN_VI1_D19_R3,
- /* IP5_6 [1] */
- FN_VI5_D3_C3, FN_VI1_D18_R2,
- /* IP5_5 [1] */
- FN_VI5_D2_C2, FN_VI1_D17_R1,
- /* IP5_4 [1] */
- FN_VI5_D1_C1, FN_VI1_D16_R0,
- /* IP5_3 [1] */
- FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
- /* IP5_2 [1] */
- FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1,
- /* IP5_1 [1] */
- FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
- /* IP5_0 [1] */
- FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1,}
- },
- /* IPSR6 */
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 2, 1, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1) {
- /* IP6_31 [1] */
- 0, 0,
- /* IP6_30 [1] */
- 0, 0,
- /* IP6_29 [1] */
- 0, 0,
- /* IP6_28 [1] */
- 0, 0,
- /* IP6_27 [1] */
- 0, 0,
- /* IP6_26 [1] */
- 0, 0,
- /* IP6_25 [1] */
- 0, 0,
- /* IP6_24 [1] */
- 0, 0,
- /* IP6_23 [1] */
- 0, 0,
- /* IP6_22 [1] */
- 0, 0,
- /* IP6_21 [1] */
- 0, 0,
- /* IP6_20 [1] */
- 0, 0,
- /* IP6_19 [1] */
- 0, 0,
- /* IP6_18_17 [2] */
- FN_DREQ1, FN_RX3, 0, 0,
- /* IP6_16 [1] */
- FN_TX3, 0,
- /* IP6_15_14 [2] */
- FN_DACK1, FN_SCK3, 0, 0,
- /* IP6_13_12 [2] */
- FN_DREQ0, FN_RX2, 0, 0,
- /* IP6_11_10 [2] */
- FN_DACK0, FN_TX2, 0, 0,
- /* IP6_9_8 [2] */
- FN_DRACK0, FN_SCK2, 0, 0,
- /* IP6_7 [1] */
- FN_MSIOF1_RXD, FN_HRX1,
- /* IP6_6 [1] */
- FN_MSIOF1_TXD, FN_HTX1,
- /* IP6_5 [1] */
- FN_MSIOF1_SYNC, FN_HRTS1,
- /* IP6_4 [1] */
- FN_MSIOF1_SCK, FN_HSCK1,
- /* IP6_3 [1] */
- FN_MSIOF0_RXD, FN_HRX0,
- /* IP6_2 [1] */
- FN_MSIOF0_TXD, FN_HTX0,
- /* IP6_1 [1] */
- FN_MSIOF0_SYNC, FN_HCTS0,
- /* IP6_0 [1] */
- FN_MSIOF0_SCK, FN_HSCK0, }
- },
- /* IPSR7 */
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 2, 2, 2) {
- /* IP7_31 [1] */
- 0, 0,
- /* IP7_30 [1] */
- 0, 0,
- /* IP7_29 [1] */
- 0, 0,
- /* IP7_28 [1] */
- 0, 0,
- /* IP7_27 [1] */
- 0, 0,
- /* IP7_26 [1] */
- 0, 0,
- /* IP7_25 [1] */
- 0, 0,
- /* IP7_24 [1] */
- 0, 0,
- /* IP7_23 [1] */
- 0, 0,
- /* IP7_22 [1] */
- 0, 0,
- /* IP7_21 [1] */
- 0, 0,
- /* IP7_20 [1] */
- FN_AUDIO_CLKB, 0,
- /* IP7_19 [1] */
- FN_AUDIO_CLKA, 0,
- /* IP7_18 [1] */
- FN_AUDIO_CLKOUT, 0,
- /* IP7_17 [1] */
- FN_SSI_SDATA4, 0,
- /* IP7_16 [1] */
- FN_SSI_WS4, 0,
- /* IP7_15_14 [2] */
- FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
- /* IP7_13_12 [2] */
- FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
- /* IP7_11_10 [2] */
- FN_SSI_WS3, FN_TPU0TO1, 0, 0,
- /* IP7_9_8 [2] */
- FN_SSI_SCK3, FN_TPU0TO0, 0, 0,
- /* IP7_7 [1] */
- FN_PWM4, 0,
- /* IP7_6 [1] */
- FN_PWM3, 0,
- /* IP7_5_4 [2] */
- FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
- /* IP7_3_2 [2] */
- FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
- /* IP7_1_0 [2] */
- FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0, }
- },
- /* MOD SEL */
- { PINMUX_CFG_REG("MOD_SEL", 0xE6060140, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- /* MOD_SEL [1] */
- FN_SEL_VI1_0, FN_SEL_VI1_1, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- GP_0_28_IN, GP_0_28_OUT,
- GP_0_27_IN, GP_0_27_OUT,
- GP_0_26_IN, GP_0_26_OUT,
- GP_0_25_IN, GP_0_25_OUT,
- GP_0_24_IN, GP_0_24_OUT,
- GP_0_23_IN, GP_0_23_OUT,
- GP_0_22_IN, GP_0_22_OUT,
- GP_0_21_IN, GP_0_21_OUT,
- GP_0_20_IN, GP_0_20_OUT,
- GP_0_19_IN, GP_0_19_OUT,
- GP_0_18_IN, GP_0_18_OUT,
- GP_0_17_IN, GP_0_17_OUT,
- GP_0_16_IN, GP_0_16_OUT,
- GP_0_15_IN, GP_0_15_OUT,
- GP_0_14_IN, GP_0_14_OUT,
- GP_0_13_IN, GP_0_13_OUT,
- GP_0_12_IN, GP_0_12_OUT,
- GP_0_11_IN, GP_0_11_OUT,
- GP_0_10_IN, GP_0_10_OUT,
- GP_0_9_IN, GP_0_9_OUT,
- GP_0_8_IN, GP_0_8_OUT,
- GP_0_7_IN, GP_0_7_OUT,
- GP_0_6_IN, GP_0_6_OUT,
- GP_0_5_IN, GP_0_5_OUT,
- GP_0_4_IN, GP_0_4_OUT,
- GP_0_3_IN, GP_0_3_OUT,
- GP_0_2_IN, GP_0_2_OUT,
- GP_0_1_IN, GP_0_1_OUT,
- GP_0_0_IN, GP_0_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_3_27_IN, GP_3_27_OUT,
- GP_3_26_IN, GP_3_26_OUT,
- GP_3_25_IN, GP_3_25_OUT,
- GP_3_24_IN, GP_3_24_OUT,
- GP_3_23_IN, GP_3_23_OUT,
- GP_3_22_IN, GP_3_22_OUT,
- GP_3_21_IN, GP_3_21_OUT,
- GP_3_20_IN, GP_3_20_OUT,
- GP_3_19_IN, GP_3_19_OUT,
- GP_3_18_IN, GP_3_18_OUT,
- GP_3_17_IN, GP_3_17_OUT,
- GP_3_16_IN, GP_3_16_OUT,
- GP_3_15_IN, GP_3_15_OUT,
- GP_3_14_IN, GP_3_14_OUT,
- GP_3_13_IN, GP_3_13_OUT,
- GP_3_12_IN, GP_3_12_OUT,
- GP_3_11_IN, GP_3_11_OUT,
- GP_3_10_IN, GP_3_10_OUT,
- GP_3_9_IN, GP_3_9_OUT,
- GP_3_8_IN, GP_3_8_OUT,
- GP_3_7_IN, GP_3_7_OUT,
- GP_3_6_IN, GP_3_6_OUT,
- GP_3_5_IN, GP_3_5_OUT,
- GP_3_4_IN, GP_3_4_OUT,
- GP_3_3_IN, GP_3_3_OUT,
- GP_3_2_IN, GP_3_2_OUT,
- GP_3_1_IN, GP_3_1_OUT,
- GP_3_0_IN, GP_3_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_4_16_IN, GP_4_16_OUT,
- GP_4_15_IN, GP_4_15_OUT,
- GP_4_14_IN, GP_4_14_OUT,
- GP_4_13_IN, GP_4_13_OUT,
- GP_4_12_IN, GP_4_12_OUT,
- GP_4_11_IN, GP_4_11_OUT,
- GP_4_10_IN, GP_4_10_OUT,
- GP_4_9_IN, GP_4_9_OUT,
- GP_4_8_IN, GP_4_8_OUT,
- GP_4_7_IN, GP_4_7_OUT,
- GP_4_6_IN, GP_4_6_OUT,
- GP_4_5_IN, GP_4_5_OUT,
- GP_4_4_IN, GP_4_4_OUT,
- GP_4_3_IN, GP_4_3_OUT,
- GP_4_2_IN, GP_4_2_OUT,
- GP_4_1_IN, GP_4_1_OUT,
- GP_4_0_IN, GP_4_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_16_IN, GP_5_16_OUT,
- GP_5_15_IN, GP_5_15_OUT,
- GP_5_14_IN, GP_5_14_OUT,
- GP_5_13_IN, GP_5_13_OUT,
- GP_5_12_IN, GP_5_12_OUT,
- GP_5_11_IN, GP_5_11_OUT,
- GP_5_10_IN, GP_5_10_OUT,
- GP_5_9_IN, GP_5_9_OUT,
- GP_5_8_IN, GP_5_8_OUT,
- GP_5_7_IN, GP_5_7_OUT,
- GP_5_6_IN, GP_5_6_OUT,
- GP_5_5_IN, GP_5_5_OUT,
- GP_5_4_IN, GP_5_4_OUT,
- GP_5_3_IN, GP_5_3_OUT,
- GP_5_2_IN, GP_5_2_OUT,
- GP_5_1_IN, GP_5_1_OUT,
- GP_5_0_IN, GP_5_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055104, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_16_IN, GP_6_16_OUT,
- GP_6_15_IN, GP_6_15_OUT,
- GP_6_14_IN, GP_6_14_OUT,
- GP_6_13_IN, GP_6_13_OUT,
- GP_6_12_IN, GP_6_12_OUT,
- GP_6_11_IN, GP_6_11_OUT,
- GP_6_10_IN, GP_6_10_OUT,
- GP_6_9_IN, GP_6_9_OUT,
- GP_6_8_IN, GP_6_8_OUT,
- GP_6_7_IN, GP_6_7_OUT,
- GP_6_6_IN, GP_6_6_OUT,
- GP_6_5_IN, GP_6_5_OUT,
- GP_6_4_IN, GP_6_4_OUT,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055204, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_16_IN, GP_7_16_OUT,
- GP_7_15_IN, GP_7_15_OUT,
- GP_7_14_IN, GP_7_14_OUT,
- GP_7_13_IN, GP_7_13_OUT,
- GP_7_12_IN, GP_7_12_OUT,
- GP_7_11_IN, GP_7_11_OUT,
- GP_7_10_IN, GP_7_10_OUT,
- GP_7_9_IN, GP_7_9_OUT,
- GP_7_8_IN, GP_7_8_OUT,
- GP_7_7_IN, GP_7_7_OUT,
- GP_7_6_IN, GP_7_6_OUT,
- GP_7_5_IN, GP_7_5_OUT,
- GP_7_4_IN, GP_7_4_OUT,
- GP_7_3_IN, GP_7_3_OUT,
- GP_7_2_IN, GP_7_2_OUT,
- GP_7_1_IN, GP_7_1_OUT,
- GP_7_0_IN, GP_7_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL8", 0xE6055304, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_8_16_IN, GP_8_16_OUT,
- GP_8_15_IN, GP_8_15_OUT,
- GP_8_14_IN, GP_8_14_OUT,
- GP_8_13_IN, GP_8_13_OUT,
- GP_8_12_IN, GP_8_12_OUT,
- GP_8_11_IN, GP_8_11_OUT,
- GP_8_10_IN, GP_8_10_OUT,
- GP_8_9_IN, GP_8_9_OUT,
- GP_8_8_IN, GP_8_8_OUT,
- GP_8_7_IN, GP_8_7_OUT,
- GP_8_6_IN, GP_8_6_OUT,
- GP_8_5_IN, GP_8_5_OUT,
- GP_8_4_IN, GP_8_4_OUT,
- GP_8_3_IN, GP_8_3_OUT,
- GP_8_2_IN, GP_8_2_OUT,
- GP_8_1_IN, GP_8_1_OUT,
- GP_8_0_IN, GP_8_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL9", 0xE6055404, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_9_16_IN, GP_9_16_OUT,
- GP_9_15_IN, GP_9_15_OUT,
- GP_9_14_IN, GP_9_14_OUT,
- GP_9_13_IN, GP_9_13_OUT,
- GP_9_12_IN, GP_9_12_OUT,
- GP_9_11_IN, GP_9_11_OUT,
- GP_9_10_IN, GP_9_10_OUT,
- GP_9_9_IN, GP_9_9_OUT,
- GP_9_8_IN, GP_9_8_OUT,
- GP_9_7_IN, GP_9_7_OUT,
- GP_9_6_IN, GP_9_6_OUT,
- GP_9_5_IN, GP_9_5_OUT,
- GP_9_4_IN, GP_9_4_OUT,
- GP_9_3_IN, GP_9_3_OUT,
- GP_9_2_IN, GP_9_2_OUT,
- GP_9_1_IN, GP_9_1_OUT,
- GP_9_0_IN, GP_9_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL10", 0xE6055504, 32, 1) { GP_INOUTSEL(10) } },
- { PINMUX_CFG_REG("INOUTSEL11", 0xE6055604, 32, 1) {
- 0, 0,
- 0, 0,
- GP_11_29_IN, GP_11_29_OUT,
- GP_11_28_IN, GP_11_28_OUT,
- GP_11_27_IN, GP_11_27_OUT,
- GP_11_26_IN, GP_11_26_OUT,
- GP_11_25_IN, GP_11_25_OUT,
- GP_11_24_IN, GP_11_24_OUT,
- GP_11_23_IN, GP_11_23_OUT,
- GP_11_22_IN, GP_11_22_OUT,
- GP_11_21_IN, GP_11_21_OUT,
- GP_11_20_IN, GP_11_20_OUT,
- GP_11_19_IN, GP_11_19_OUT,
- GP_11_18_IN, GP_11_18_OUT,
- GP_11_17_IN, GP_11_17_OUT,
- GP_11_16_IN, GP_11_16_OUT,
- GP_11_15_IN, GP_11_15_OUT,
- GP_11_14_IN, GP_11_14_OUT,
- GP_11_13_IN, GP_11_13_OUT,
- GP_11_12_IN, GP_11_12_OUT,
- GP_11_11_IN, GP_11_11_OUT,
- GP_11_10_IN, GP_11_10_OUT,
- GP_11_9_IN, GP_11_9_OUT,
- GP_11_8_IN, GP_11_8_OUT,
- GP_11_7_IN, GP_11_7_OUT,
- GP_11_6_IN, GP_11_6_OUT,
- GP_11_5_IN, GP_11_5_OUT,
- GP_11_4_IN, GP_11_4_OUT,
- GP_11_3_IN, GP_11_3_OUT,
- GP_11_2_IN, GP_11_2_OUT,
- GP_11_1_IN, GP_11_1_OUT,
- GP_11_0_IN, GP_11_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
- 0, 0, 0, GP_0_28_DATA,
- GP_0_27_DATA, GP_0_26_DATA, GP_0_25_DATA, GP_0_24_DATA,
- GP_0_23_DATA, GP_0_22_DATA, GP_0_21_DATA, GP_0_20_DATA,
- GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA,
- GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
- GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
- GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
- GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
- },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
- 0, 0, 0, 0,
- GP_3_27_DATA, GP_3_26_DATA, GP_3_25_DATA, GP_3_24_DATA,
- GP_3_23_DATA, GP_3_22_DATA, GP_3_21_DATA, GP_3_20_DATA,
- GP_3_19_DATA, GP_3_18_DATA, GP_3_17_DATA, GP_3_16_DATA,
- GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
- GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
- GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
- GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
- },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_4_16_DATA,
- GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
- GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
- GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
- GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
- },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_5_16_DATA,
- GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
- GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
- GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
- GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
- },
- { PINMUX_DATA_REG("INDT6", 0xE6055108, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_6_16_DATA,
- GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
- GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
- GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
- GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
- },
- { PINMUX_DATA_REG("INDT7", 0xE6055208, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_7_16_DATA,
- GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
- GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
- GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { PINMUX_DATA_REG("INDT8", 0xE6055308, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_8_16_DATA,
- GP_8_15_DATA, GP_8_14_DATA, GP_8_13_DATA, GP_8_12_DATA,
- GP_8_11_DATA, GP_8_10_DATA, GP_8_9_DATA, GP_8_8_DATA,
- GP_8_7_DATA, GP_8_6_DATA, GP_8_5_DATA, GP_8_4_DATA,
- GP_8_3_DATA, GP_8_2_DATA, GP_8_1_DATA, GP_8_0_DATA }
- },
- { PINMUX_DATA_REG("INDT9", 0xE6055408, 32) {
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- 0, 0, 0, GP_9_16_DATA,
- GP_9_15_DATA, GP_9_14_DATA, GP_9_13_DATA, GP_9_12_DATA,
- GP_9_11_DATA, GP_9_10_DATA, GP_9_9_DATA, GP_9_8_DATA,
- GP_9_7_DATA, GP_9_6_DATA, GP_9_5_DATA, GP_9_4_DATA,
- GP_9_3_DATA, GP_9_2_DATA, GP_9_1_DATA, GP_9_0_DATA }
- },
- { PINMUX_DATA_REG("INDT10", 0xE6055508, 32) { GP_INDT(10) } },
- { PINMUX_DATA_REG("INDT11", 0xE6055608, 32) {
- 0, 0, GP_11_29_DATA, GP_11_28_DATA,
- GP_11_27_DATA, GP_11_26_DATA, GP_11_25_DATA, GP_11_24_DATA,
- GP_11_23_DATA, GP_11_22_DATA, GP_11_21_DATA, GP_11_20_DATA,
- GP_11_19_DATA, GP_11_18_DATA, GP_11_17_DATA, GP_11_16_DATA,
- GP_11_15_DATA, GP_11_14_DATA, GP_11_13_DATA, GP_11_12_DATA,
- GP_11_11_DATA, GP_11_10_DATA, GP_11_9_DATA, GP_11_8_DATA,
- GP_11_7_DATA, GP_11_6_DATA, GP_11_5_DATA, GP_11_4_DATA,
- GP_11_3_DATA, GP_11_2_DATA, GP_11_1_DATA, GP_11_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7792_pinmux_info = {
- .name = "r8a7792_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_AUDIO_CLKB,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7792_pinmux_init(void)
-{
- register_pinmux(&r8a7792_pinmux_info);
-}
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT1(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-/*
- * GP_0_0_DATA -> GP_7_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
- * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT1(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx), \
- CPU_32_PORT(fn, pfx##_6_, sfx), \
- CPU_32_PORT1(fn, pfx##_7_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
- FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
- FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
- FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
- FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
- FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
-
- /* GPSR1 */
- FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
- FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
- FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
- FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
- FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
- FN_IP3_21_20,
-
- /* GPSR2 */
- FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
- FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
- FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
- FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
- FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
- FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
- FN_IP6_5_3, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
- FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
- FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
- FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
- FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
- FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
- FN_IP9_18_17,
-
- /* GPSR4 */
- FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
- FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
- FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
- FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
- FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
- FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
- FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
-
- /* GPSR5 */
- FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
- FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
- FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
- FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
- FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
- FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
- FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
-
- /* GPSR6 */
- FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
- FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
- FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
- FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
- FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
- FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
-
- /* GPSR7 */
- FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
- FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
- FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
- FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
- FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
- FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
-
- /* IPSR 0 -5 */
-
- /* IPSR6 */
- FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
- FN_SCIF_CLK, FN_BPFCLK_E,
- FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
- FN_SCIFA2_RXD, FN_FMIN_E,
- FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
- FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
- FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
- FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
- FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
- FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
- FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
- FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
- FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
- FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
-
- /* IPSR7 - IPSR10 */
-
- /* IPSR11 */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
- FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
- FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
- FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
- FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
- FN_VI1_DATA7, FN_AVB_MDC,
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
-
- /* IPSR12 */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
-
- /* IPSR13 */
- FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
- FN_ADICLK_B, FN_MSIOF0_SS1_C,
- FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
- FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
- FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
- FN_ADICHS2_B, FN_MSIOF0_TXD_C,
- FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
- FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
- FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
- FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
- FN_SCIFA5_TXD_B, FN_TX3_C,
- FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
- FN_SCIFA5_RXD_B, FN_RX3_C,
- FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
- FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
- FN_SD1_DATA3, FN_IERX_B,
- FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
-
- /* IPSR14 */
- FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
- FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
- FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
- FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
- FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
- FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
- FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
- FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
- FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
- FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
- FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
- FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
- FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
- FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
-
- /* IPSR15 */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
- FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
- FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
- FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
- FN_PWM5_B, FN_SCIFA3_TXD_C,
- FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
- FN_VI1_G6_B, FN_SCIFA3_RXD_C,
- FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
- FN_VI1_G7_B, FN_SCIFA3_SCK_C,
- FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
- FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
- FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
- FN_TCLK2, FN_VI1_DATA3_C,
- FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
- FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
-
- /* IPSR16 */
- FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
- FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
- FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
- FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
-
- /* MOD_SEL */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
- FN_SEL_HSCIF1_4,
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
-
- /* MOD_SEL2 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF0_4,
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
-
- /* MOD_SEL3 */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
-
- /* MOD_SEL4 */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
- FN_SEL_SCIF2_4,
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
- FN_SEL_SOF2_4,
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
-
- EX_CS0_N_MARK, RD_N_MARK,
-
- AUDIO_CLKA_MARK,
-
- VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
- VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
- VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
- SCIF_CLK_MARK, BPFCLK_E_MARK,
- AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
- SCIFA2_RXD_MARK, FMIN_E_MARK,
- AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
- IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
- IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
- IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
- IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
- IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
- MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
- IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
- IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
- SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
- IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
- GPS_CLK_C_MARK, GPS_CLK_D_MARK,
- IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
- GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
- VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
- VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
- SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
- VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
- TX4_B_MARK, SCIFA4_TXD_B_MARK,
- VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
- RX4_B_MARK, SCIFA4_RXD_B_MARK,
- VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
- VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
- VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
- VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
- VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
- VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
- VI1_DATA7_MARK, AVB_MDC_MARK,
- ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
- ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
-
- /* IPSR12 */
- ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
- ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
- ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
- SCL2_D_MARK, MSIOF1_RXD_E_MARK,
- ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
- SDA2_D_MARK, MSIOF1_SCK_E_MARK,
- ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
- CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
- ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
- CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
- ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
- ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
- ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
- ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
- STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
- ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
- STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
- ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
-
- /* IPSR13 */
- STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
- ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
- STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
- STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
- STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
- ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
- SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
- SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
- SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
- SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
- SCIFA5_TXD_B_MARK, TX3_C_MARK,
- SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
- SCIFA5_RXD_B_MARK, RX3_C_MARK,
- SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
- SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
- SD1_DATA3_MARK, IERX_B_MARK,
- SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
-
- /* IPSR14 */
- SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
- SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
- SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
- SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
- SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
- SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
- MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
- VI1_CLK_C_MARK, VI1_G0_B_MARK,
- MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
- VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
- MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
- MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
- MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
- VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
- MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
- VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
-
- /* IPSR15 */
- SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
- SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
- SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
- GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
- PWM5_B_MARK, SCIFA3_TXD_C_MARK,
- GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
- VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
- GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
- VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
- HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
- TCLK1_MARK, VI1_DATA1_C_MARK,
- HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
- HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
- TCLK2_MARK, VI1_DATA3_C_MARK,
- HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
- CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
- HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
- CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
-
- /* IPSR16 */
- HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
- GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
- HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
- GLO_SS_C_MARK, VI1_DATA7_C_MARK,
- HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
- HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
- HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
- PINMUX_DATA(RD_N_MARK, FN_RD_N),
- PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
- PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
- PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
- PINMUX_DATA(VI0_DATA0_VI0_B1_MARK, FN_VI0_DATA0_VI0_B1),
- PINMUX_DATA(VI0_DATA0_VI0_B2_MARK, FN_VI0_DATA0_VI0_B2),
- PINMUX_DATA(VI0_DATA0_VI0_B4_MARK, FN_VI0_DATA0_VI0_B4),
- PINMUX_DATA(VI0_DATA0_VI0_B5_MARK, FN_VI0_DATA0_VI0_B5),
- PINMUX_DATA(VI0_DATA0_VI0_B6_MARK, FN_VI0_DATA0_VI0_B6),
- PINMUX_DATA(VI0_DATA0_VI0_B7_MARK, FN_VI0_DATA0_VI0_B7),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
- PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
- PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
- PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
- PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
- PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
- PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
- PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
- PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
- PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
- PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
- PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
- PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
- PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
- PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
- PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
- PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
- PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
- PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
- PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
- PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
- PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
- PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
- PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
- PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
- PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
- PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
- PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
- PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
- PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
- PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
- PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
- PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
- PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
-
- /* IPSR12 */
- PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
- PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
- PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
- PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
- PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
- PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
- PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
- PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
- PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
- PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
- PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
- PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
- PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
- PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
-
- /* IPSR13 */
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
- PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
- PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
- PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
- PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
- PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
- PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
- PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
- PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
- PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
- PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
- PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
- PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
- PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
- PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
- PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
- PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
- PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
- PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
- PINMUX_IPSR_DATA(IP13_30_28, PWM0),
- PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
- PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
-
- /* IPSR14 */
- PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
- PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
- PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
- PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
- PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
- PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
- PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
- PINMUX_IPSR_DATA(IP14_4, MMC_D0),
- PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
- PINMUX_IPSR_DATA(IP14_5, MMC_D1),
- PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
- PINMUX_IPSR_DATA(IP14_6, MMC_D2),
- PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
- PINMUX_IPSR_DATA(IP14_7, MMC_D3),
- PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
- PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
- PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
- PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
- PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
- PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
- PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
-
- /* IPSR15 */
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_11_9, PWM5),
- PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
- PINMUX_IPSR_DATA(IP15_14_12, PWM6),
- PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
- PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
- PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
- PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
-
- /* IPSR16 */
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
- PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
- PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
- PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
- PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
- PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
- PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
- PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
- PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
- PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(EX_CS0_N), GPIO_FN(RD_N), GPIO_FN(AUDIO_CLKA),
- GPIO_FN(VI0_CLK), GPIO_FN(VI0_DATA0_VI0_B0),
- GPIO_FN(VI0_DATA0_VI0_B1), GPIO_FN(VI0_DATA0_VI0_B2),
- GPIO_FN(VI0_DATA0_VI0_B4), GPIO_FN(VI0_DATA0_VI0_B5),
- GPIO_FN(VI0_DATA0_VI0_B6), GPIO_FN(VI0_DATA0_VI0_B7),
- GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
-
- /* IPSR0 - 5 */
-
- /* IPSR6 */
- GPIO_FN(AUDIO_CLKB), GPIO_FN(STP_OPWM_0_B), GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(SCIF_CLK), GPIO_FN(BPFCLK_E),
- GPIO_FN(AUDIO_CLKC), GPIO_FN(SCIFB0_SCK_C),
- GPIO_FN(MSIOF1_SYNC_B), GPIO_FN(RX2),
- GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN_E),
- GPIO_FN(AUDIO_CLKOUT), GPIO_FN(MSIOF1_SS1_B),
- GPIO_FN(TX2), GPIO_FN(SCIFA2_TXD),
- GPIO_FN(IRQ0), GPIO_FN(SCIFB1_RXD_D), GPIO_FN(INTC_IRQ0_N),
- GPIO_FN(IRQ1), GPIO_FN(SCIFB1_SCK_C), GPIO_FN(INTC_IRQ1_N),
- GPIO_FN(IRQ2), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(INTC_IRQ2_N),
- GPIO_FN(IRQ3), GPIO_FN(SCL4_C),
- GPIO_FN(MSIOF2_TXD_E), GPIO_FN(INTC_IRQ3_N),
- GPIO_FN(IRQ4), GPIO_FN(HRX1_C), GPIO_FN(SDA4_C),
- GPIO_FN(MSIOF2_RXD_E), GPIO_FN(INTC_IRQ4_N),
- GPIO_FN(IRQ5), GPIO_FN(HTX1_C), GPIO_FN(SCL1_E), GPIO_FN(MSIOF2_SCK_E),
- GPIO_FN(IRQ6), GPIO_FN(HSCK1_C), GPIO_FN(MSIOF1_SS2_B),
- GPIO_FN(SDA1_E), GPIO_FN(MSIOF2_SYNC_E),
- GPIO_FN(IRQ7), GPIO_FN(HCTS1_N_C), GPIO_FN(MSIOF1_TXD_B),
- GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D),
- GPIO_FN(IRQ8), GPIO_FN(HRTS1_N_C), GPIO_FN(MSIOF1_RXD_B),
- GPIO_FN(GPS_SIGN_C), GPIO_FN(GPS_SIGN_D),
-
- /* IPSR7 - 10 */
-
- /* IPSR11 */
- GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
- GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
- GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
- GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
- GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
- GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
- GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
- GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
- GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
- GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
- GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
- GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
- GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
- GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
- GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
- GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
- GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
- GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
- GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
- GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
- GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
-
- /* IPSR12 */
- GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
- GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
- GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
- GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
- GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
- GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
- GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
- GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
- GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
- GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
- GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
- GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
- GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
- GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
- GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
- GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
- GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
- GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
-
- /* IPSR13 */
- GPIO_FN(STP_ISD_0), GPIO_FN(AVB_TX_ER), GPIO_FN(SCIFB2_SCK_C),
- GPIO_FN(ADICLK_B), GPIO_FN(MSIOF0_SS1_C),
- GPIO_FN(STP_ISEN_0), GPIO_FN(AVB_TX_CLK),
- GPIO_FN(ADICHS0_B), GPIO_FN(MSIOF0_SS2_C),
- GPIO_FN(STP_ISSYNC_0), GPIO_FN(AVB_COL),
- GPIO_FN(ADICHS1_B), GPIO_FN(MSIOF0_RXD_C),
- GPIO_FN(STP_OPWM_0), GPIO_FN(AVB_GTX_CLK), GPIO_FN(PWM0_B),
- GPIO_FN(ADICHS2_B), GPIO_FN(MSIOF0_TXD_C),
- GPIO_FN(SD0_CLK), GPIO_FN(SPCLK_B),
- GPIO_FN(SD0_CMD), GPIO_FN(MOSI_IO0_B),
- GPIO_FN(SD0_DATA0), GPIO_FN(MISO_IO1_B),
- GPIO_FN(SD0_DATA1), GPIO_FN(IO2_B),
- GPIO_FN(SD0_DATA2), GPIO_FN(IO3_B), GPIO_FN(SD0_DATA3), GPIO_FN(SSL_B),
- GPIO_FN(SD0_CD), GPIO_FN(MMC_D6_B),
- GPIO_FN(SIM0_RST_B), GPIO_FN(CAN0_RX_F),
- GPIO_FN(SCIFA5_TXD_B), GPIO_FN(TX3_C),
- GPIO_FN(SD0_WP), GPIO_FN(MMC_D7_B),
- GPIO_FN(SIM0_D_B), GPIO_FN(CAN0_TX_F),
- GPIO_FN(SCIFA5_RXD_B), GPIO_FN(RX3_C),
- GPIO_FN(SD1_CMD), GPIO_FN(REMOCON_B),
- GPIO_FN(SD1_DATA0), GPIO_FN(SPEEDIN_B),
- GPIO_FN(SD1_DATA1), GPIO_FN(IETX_B),
- GPIO_FN(SD1_DATA2), GPIO_FN(IECLK_B),
- GPIO_FN(SD1_DATA3), GPIO_FN(IERX_B),
- GPIO_FN(SD1_CD), GPIO_FN(PWM0), GPIO_FN(TPU_TO0), GPIO_FN(SCL1_C),
-
- /* IPSR14 */
- GPIO_FN(SD1_WP), GPIO_FN(PWM1_B), GPIO_FN(SDA1_C),
- GPIO_FN(SD2_CLK), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CMD), GPIO_FN(MMC_CMD),
- GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D0),
- GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D1),
- GPIO_FN(SD2_DATA2), GPIO_FN(MMC_D2),
- GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D3),
- GPIO_FN(SD2_CD), GPIO_FN(MMC_D4), GPIO_FN(SCL8_C),
- GPIO_FN(TX5_B), GPIO_FN(SCIFA5_TXD_C),
- GPIO_FN(SD2_WP), GPIO_FN(MMC_D5), GPIO_FN(SDA8_C),
- GPIO_FN(RX5_B), GPIO_FN(SCIFA5_RXD_C),
- GPIO_FN(MSIOF0_SCK), GPIO_FN(RX2_C), GPIO_FN(ADIDATA),
- GPIO_FN(VI1_CLK_C), GPIO_FN(VI1_G0_B),
- GPIO_FN(MSIOF0_SYNC), GPIO_FN(TX2_C), GPIO_FN(ADICS_SAMP),
- GPIO_FN(VI1_CLKENB_C), GPIO_FN(VI1_G1_B),
- GPIO_FN(MSIOF0_TXD), GPIO_FN(ADICLK),
- GPIO_FN(VI1_FIELD_C), GPIO_FN(VI1_G2_B),
- GPIO_FN(MSIOF0_RXD), GPIO_FN(ADICHS0),
- GPIO_FN(VI1_DATA0_C), GPIO_FN(VI1_G3_B),
- GPIO_FN(MSIOF0_SS1), GPIO_FN(MMC_D6), GPIO_FN(ADICHS1), GPIO_FN(TX0_E),
- GPIO_FN(VI1_HSYNC_N_C), GPIO_FN(SCL7_C), GPIO_FN(VI1_G4_B),
- GPIO_FN(MSIOF0_SS2), GPIO_FN(MMC_D7), GPIO_FN(ADICHS2), GPIO_FN(RX0_E),
- GPIO_FN(VI1_VSYNC_N_C), GPIO_FN(SDA7_C), GPIO_FN(VI1_G5_B),
-
- /* IPSR15 */
- GPIO_FN(SIM0_RST), GPIO_FN(IETX), GPIO_FN(CAN1_TX_D),
- GPIO_FN(SIM0_CLK), GPIO_FN(IECLK), GPIO_FN(CAN_CLK_C),
- GPIO_FN(SIM0_D), GPIO_FN(IERX), GPIO_FN(CAN1_RX_D),
- GPIO_FN(GPS_CLK), GPIO_FN(DU1_DOTCLKIN_C), GPIO_FN(AUDIO_CLKB_B),
- GPIO_FN(PWM5_B), GPIO_FN(SCIFA3_TXD_C),
- GPIO_FN(GPS_SIGN), GPIO_FN(TX4_C),
- GPIO_FN(SCIFA4_TXD_C), GPIO_FN(PWM5),
- GPIO_FN(VI1_G6_B), GPIO_FN(SCIFA3_RXD_C),
- GPIO_FN(GPS_MAG), GPIO_FN(RX4_C), GPIO_FN(SCIFA4_RXD_C), GPIO_FN(PWM6),
- GPIO_FN(VI1_G7_B), GPIO_FN(SCIFA3_SCK_C),
- GPIO_FN(HCTS0_N), GPIO_FN(SCIFB0_CTS_N), GPIO_FN(GLO_I0_C),
- GPIO_FN(TCLK1), GPIO_FN(VI1_DATA1_C),
- GPIO_FN(HRTS0_N), GPIO_FN(SCIFB0_RTS_N),
- GPIO_FN(GLO_I1_C), GPIO_FN(VI1_DATA2_C),
- GPIO_FN(HSCK0), GPIO_FN(SCIFB0_SCK),
- GPIO_FN(GLO_Q0_C), GPIO_FN(CAN_CLK),
- GPIO_FN(TCLK2), GPIO_FN(VI1_DATA3_C),
- GPIO_FN(HRX0), GPIO_FN(SCIFB0_RXD), GPIO_FN(GLO_Q1_C),
- GPIO_FN(CAN0_RX_B), GPIO_FN(VI1_DATA4_C),
- GPIO_FN(HTX0), GPIO_FN(SCIFB0_TXD), GPIO_FN(GLO_SCLK_C),
- GPIO_FN(CAN0_TX_B), GPIO_FN(VI1_DATA5_C),
-
- /* IPSR16 */
- GPIO_FN(HRX1), GPIO_FN(SCIFB1_RXD), GPIO_FN(VI1_R0_B),
- GPIO_FN(GLO_SDATA_C), GPIO_FN(VI1_DATA6_C),
- GPIO_FN(HTX1), GPIO_FN(SCIFB1_TXD), GPIO_FN(VI1_R1_B),
- GPIO_FN(GLO_SS_C), GPIO_FN(VI1_DATA7_C),
- GPIO_FN(HSCK1), GPIO_FN(SCIFB1_SCK),
- GPIO_FN(MLB_CK), GPIO_FN(GLO_RFON_C),
- GPIO_FN(HCTS1_N), GPIO_FN(SCIFB1_CTS_N),
- GPIO_FN(MLB_SIG), GPIO_FN(CAN1_TX_B),
- GPIO_FN(HRTS1_N), GPIO_FN(SCIFB1_RTS_N),
- GPIO_FN(MLB_DAT), GPIO_FN(CAN1_RX_B),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP1_22_20,
- GP_0_30_FN, FN_IP1_19_17,
- GP_0_29_FN, FN_IP1_16_14,
- GP_0_28_FN, FN_IP1_13_11,
- GP_0_27_FN, FN_IP1_10_8,
- GP_0_26_FN, FN_IP1_7_6,
- GP_0_25_FN, FN_IP1_5_4,
- GP_0_24_FN, FN_IP1_3_2,
- GP_0_23_FN, FN_IP1_1_0,
- GP_0_22_FN, FN_IP0_30_29,
- GP_0_21_FN, FN_IP0_28_27,
- GP_0_20_FN, FN_IP0_26_25,
- GP_0_19_FN, FN_IP0_24_23,
- GP_0_18_FN, FN_IP0_22_21,
- GP_0_17_FN, FN_IP0_20_19,
- GP_0_16_FN, FN_IP0_18_16,
- GP_0_15_FN, FN_IP0_15,
- GP_0_14_FN, FN_IP0_14,
- GP_0_13_FN, FN_IP0_13,
- GP_0_12_FN, FN_IP0_12,
- GP_0_11_FN, FN_IP0_11,
- GP_0_10_FN, FN_IP0_10,
- GP_0_9_FN, FN_IP0_9,
- GP_0_8_FN, FN_IP0_8,
- GP_0_7_FN, FN_IP0_7,
- GP_0_6_FN, FN_IP0_6,
- GP_0_5_FN, FN_IP0_5,
- GP_0_4_FN, FN_IP0_4,
- GP_0_3_FN, FN_IP0_3,
- GP_0_2_FN, FN_IP0_2,
- GP_0_1_FN, FN_IP0_1,
- GP_0_0_FN, FN_IP0_0, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_IP3_21_20,
- GP_1_24_FN, FN_IP3_19_18,
- GP_1_23_FN, FN_IP3_17_16,
- GP_1_22_FN, FN_IP3_15_14,
- GP_1_21_FN, FN_IP3_13_12,
- GP_1_20_FN, FN_IP3_11_9,
- GP_1_19_FN, FN_RD_N,
- GP_1_18_FN, FN_IP3_8_6,
- GP_1_17_FN, FN_IP3_5_3,
- GP_1_16_FN, FN_IP3_2_0,
- GP_1_15_FN, FN_IP2_29_27,
- GP_1_14_FN, FN_IP2_26_25,
- GP_1_13_FN, FN_IP2_24_23,
- GP_1_12_FN, FN_EX_CS0_N,
- GP_1_11_FN, FN_IP2_22_21,
- GP_1_10_FN, FN_IP2_20_19,
- GP_1_9_FN, FN_IP2_18_16,
- GP_1_8_FN, FN_IP2_15_13,
- GP_1_7_FN, FN_IP2_12_10,
- GP_1_6_FN, FN_IP2_9_7,
- GP_1_5_FN, FN_IP2_6_5,
- GP_1_4_FN, FN_IP2_4_3,
- GP_1_3_FN, FN_IP2_2_0,
- GP_1_2_FN, FN_IP1_31_29,
- GP_1_1_FN, FN_IP1_28_26,
- GP_1_0_FN, FN_IP1_25_23, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_3,
- GP_2_29_FN, FN_IP6_2_0,
- GP_2_28_FN, FN_AUDIO_CLKA,
- GP_2_27_FN, FN_IP5_31_29,
- GP_2_26_FN, FN_IP5_28_26,
- GP_2_25_FN, FN_IP5_25_24,
- GP_2_24_FN, FN_IP5_23_22,
- GP_2_23_FN, FN_IP5_21_20,
- GP_2_22_FN, FN_IP5_19_17,
- GP_2_21_FN, FN_IP5_16_15,
- GP_2_20_FN, FN_IP5_14_12,
- GP_2_19_FN, FN_IP5_11_9,
- GP_2_18_FN, FN_IP5_8_6,
- GP_2_17_FN, FN_IP5_5_3,
- GP_2_16_FN, FN_IP5_2_0,
- GP_2_15_FN, FN_IP4_30_28,
- GP_2_14_FN, FN_IP4_27_26,
- GP_2_13_FN, FN_IP4_25_24,
- GP_2_12_FN, FN_IP4_23_22,
- GP_2_11_FN, FN_IP4_21,
- GP_2_10_FN, FN_IP4_20,
- GP_2_9_FN, FN_IP4_19,
- GP_2_8_FN, FN_IP4_18_16,
- GP_2_7_FN, FN_IP4_15_13,
- GP_2_6_FN, FN_IP4_12_10,
- GP_2_5_FN, FN_IP4_9_8,
- GP_2_4_FN, FN_IP4_7_5,
- GP_2_3_FN, FN_IP4_4_2,
- GP_2_2_FN, FN_IP4_1_0,
- GP_2_1_FN, FN_IP3_30_28,
- GP_2_0_FN, FN_IP3_27_25 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP9_18_17,
- GP_3_30_FN, FN_IP9_16,
- GP_3_29_FN, FN_IP9_15_13,
- GP_3_28_FN, FN_IP9_12,
- GP_3_27_FN, FN_IP9_11,
- GP_3_26_FN, FN_IP9_10_8,
- GP_3_25_FN, FN_IP9_7,
- GP_3_24_FN, FN_IP9_6,
- GP_3_23_FN, FN_IP9_5_3,
- GP_3_22_FN, FN_IP9_2_0,
- GP_3_21_FN, FN_IP8_30_28,
- GP_3_20_FN, FN_IP8_27_26,
- GP_3_19_FN, FN_IP8_25_24,
- GP_3_18_FN, FN_IP8_23_21,
- GP_3_17_FN, FN_IP8_20_18,
- GP_3_16_FN, FN_IP8_17_15,
- GP_3_15_FN, FN_IP8_14_12,
- GP_3_14_FN, FN_IP8_11_9,
- GP_3_13_FN, FN_IP8_8_6,
- GP_3_12_FN, FN_IP8_5_3,
- GP_3_11_FN, FN_IP8_2_0,
- GP_3_10_FN, FN_IP7_29_27,
- GP_3_9_FN, FN_IP7_26_24,
- GP_3_8_FN, FN_IP7_23_21,
- GP_3_7_FN, FN_IP7_20_19,
- GP_3_6_FN, FN_IP7_18_17,
- GP_3_5_FN, FN_IP7_16_15,
- GP_3_4_FN, FN_IP7_14_13,
- GP_3_3_FN, FN_IP7_12_11,
- GP_3_2_FN, FN_IP7_10_9,
- GP_3_1_FN, FN_IP7_8_6,
- GP_3_0_FN, FN_IP7_5_3 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP15_5_4,
- GP_4_30_FN, FN_IP15_3_2,
- GP_4_29_FN, FN_IP15_1_0,
- GP_4_28_FN, FN_IP11_8_6,
- GP_4_27_FN, FN_IP11_5_3,
- GP_4_26_FN, FN_IP11_2_0,
- GP_4_25_FN, FN_IP10_31_29,
- GP_4_24_FN, FN_IP10_28_27,
- GP_4_23_FN, FN_IP10_26_25,
- GP_4_22_FN, FN_IP10_24_22,
- GP_4_21_FN, FN_IP10_21_19,
- GP_4_20_FN, FN_IP10_18_17,
- GP_4_19_FN, FN_IP10_16_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_31_29,
- GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
- GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
- GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
- GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
- GP_4_8_FN, FN_IP9_28_27,
- GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
- GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
- GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
- GP_4_4_FN, FN_IP9_26_25,
- GP_4_3_FN, FN_IP9_24_23,
- GP_4_2_FN, FN_IP9_22_21,
- GP_4_1_FN, FN_IP9_20_19,
- GP_4_0_FN, FN_VI0_CLK }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- GP_5_31_FN, FN_IP3_24_22,
- GP_5_30_FN, FN_IP13_9_7,
- GP_5_29_FN, FN_IP13_6_5,
- GP_5_28_FN, FN_IP13_4_3,
- GP_5_27_FN, FN_IP13_2_0,
- GP_5_26_FN, FN_IP12_29_27,
- GP_5_25_FN, FN_IP12_26_24,
- GP_5_24_FN, FN_IP12_23_22,
- GP_5_23_FN, FN_IP12_21_20,
- GP_5_22_FN, FN_IP12_19_18,
- GP_5_21_FN, FN_IP12_17_16,
- GP_5_20_FN, FN_IP12_15_13,
- GP_5_19_FN, FN_IP12_12_10,
- GP_5_18_FN, FN_IP12_9_7,
- GP_5_17_FN, FN_IP12_6_4,
- GP_5_16_FN, FN_IP12_3_2,
- GP_5_15_FN, FN_IP12_1_0,
- GP_5_14_FN, FN_IP11_31_30,
- GP_5_13_FN, FN_IP11_29_28,
- GP_5_12_FN, FN_IP11_27,
- GP_5_11_FN, FN_IP11_26,
- GP_5_10_FN, FN_IP11_25,
- GP_5_9_FN, FN_IP11_24,
- GP_5_8_FN, FN_IP11_23,
- GP_5_7_FN, FN_IP11_22,
- GP_5_6_FN, FN_IP11_21,
- GP_5_5_FN, FN_IP11_20,
- GP_5_4_FN, FN_IP11_19,
- GP_5_3_FN, FN_IP11_18_17,
- GP_5_2_FN, FN_IP11_16_15,
- GP_5_1_FN, FN_IP11_14_12,
- GP_5_0_FN, FN_IP11_11_9 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- GP_6_29_FN, FN_IP14_31_29,
- GP_6_28_FN, FN_IP14_28_26,
- GP_6_27_FN, FN_IP14_25_23,
- GP_6_26_FN, FN_IP14_22_20,
- GP_6_25_FN, FN_IP14_19_17,
- GP_6_24_FN, FN_IP14_16_14,
- GP_6_23_FN, FN_IP14_13_11,
- GP_6_22_FN, FN_IP14_10_8,
- GP_6_21_FN, FN_IP14_7,
- GP_6_20_FN, FN_IP14_6,
- GP_6_19_FN, FN_IP14_5,
- GP_6_18_FN, FN_IP14_4,
- GP_6_17_FN, FN_IP14_3,
- GP_6_16_FN, FN_IP14_2,
- GP_6_15_FN, FN_IP14_1_0,
- GP_6_14_FN, FN_IP13_30_28,
- GP_6_13_FN, FN_IP13_27,
- GP_6_12_FN, FN_IP13_26,
- GP_6_11_FN, FN_IP13_25,
- GP_6_10_FN, FN_IP13_24_23,
- GP_6_9_FN, FN_IP13_22,
- 0, 0,
- GP_6_7_FN, FN_IP13_21_19,
- GP_6_6_FN, FN_IP13_18_16,
- GP_6_5_FN, FN_IP13_15,
- GP_6_4_FN, FN_IP13_14,
- GP_6_3_FN, FN_IP13_13,
- GP_6_2_FN, FN_IP13_12,
- GP_6_1_FN, FN_IP13_11,
- GP_6_0_FN, FN_IP13_10 }
- },
- { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_FN, FN_USB1_PWEN,
- GP_7_24_FN, FN_USB0_OVC,
- GP_7_23_FN, FN_USB0_PWEN,
- GP_7_22_FN, FN_IP15_14_12,
- GP_7_21_FN, FN_IP15_11_9,
- GP_7_20_FN, FN_IP15_8_6,
- GP_7_19_FN, FN_IP7_2_0,
- GP_7_18_FN, FN_IP6_29_27,
- GP_7_17_FN, FN_IP6_26_24,
- GP_7_16_FN, FN_IP6_23_21,
- GP_7_15_FN, FN_IP6_20_19,
- GP_7_14_FN, FN_IP6_18_16,
- GP_7_13_FN, FN_IP6_15_14,
- GP_7_12_FN, FN_IP6_13_12,
- GP_7_11_FN, FN_IP6_11_10,
- GP_7_10_FN, FN_IP6_9_8,
- GP_7_9_FN, FN_IP16_11_10,
- GP_7_8_FN, FN_IP16_9_8,
- GP_7_7_FN, FN_IP16_7_6,
- GP_7_6_FN, FN_IP16_5_3,
- GP_7_5_FN, FN_IP16_2_0,
- GP_7_4_FN, FN_IP15_29_27,
- GP_7_3_FN, FN_IP15_26_24,
- GP_7_2_FN, FN_IP15_23_21,
- GP_7_1_FN, FN_IP15_20_18,
- GP_7_0_FN, FN_IP15_17_15 }
- },
-
- /* IPSR0 - 5 */
-
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
- /* IP6_31_30 [2] */
- 0, 0, 0, 0,
- /* IP6_29_27 [3] */
- FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
- FN_GPS_SIGN_C, FN_GPS_SIGN_D,
- 0, 0, 0,
- /* IP6_26_24 [3] */
- FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
- FN_GPS_CLK_C, FN_GPS_CLK_D,
- 0, 0, 0,
- /* IP6_23_21 [3] */
- FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
- FN_SDA1_E, FN_MSIOF2_SYNC_E,
- 0, 0, 0,
- /* IP6_20_19 [2] */
- FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
- /* IP6_18_16 [3] */
- FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
- 0, 0, 0,
- /* IP6_15_14 [2] */
- FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
- /* IP6_13_12 [2] */
- FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
- /* IP6_11_10 [2] */
- FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
- /* IP6_9_8 [2] */
- FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
- /* IP6_7_6 [2] */
- FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
- /* IP6_5_3 [3] */
- FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
- FN_SCIFA2_RXD, FN_FMIN_E,
- 0, 0,
- /* IP6_2_0 [3] */
- FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
- FN_SCIF_CLK, 0, FN_BPFCLK_E,
- 0, 0, }
- },
-
- /* IPSR7 - 10 */
-
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 3, 3, 3, 3, 3) {
- /* IP11_31_30 [2] */
- FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
- /* IP11_29_28 [2] */
- FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
- /* IP11_27 [1] */
- FN_VI1_DATA7, FN_AVB_MDC,
- /* IP11_26 [1] */
- FN_VI1_DATA6, FN_AVB_MAGIC,
- /* IP11_25 [1] */
- FN_VI1_DATA5, FN_AVB_RX_DV,
- /* IP11_24 [1] */
- FN_VI1_DATA4, FN_AVB_MDIO,
- /* IP11_23 [1] */
- FN_VI1_DATA3, FN_AVB_RX_ER,
- /* IP11_22 [1] */
- FN_VI1_DATA2, FN_AVB_RXD7,
- /* IP11_21 [1] */
- FN_VI1_DATA1, FN_AVB_RXD6,
- /* IP11_20 [1] */
- FN_VI1_DATA0, FN_AVB_RXD5,
- /* IP11_19 [1] */
- FN_VI1_CLK, FN_AVB_RXD4,
- /* IP11_18_17 [2] */
- FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
- /* IP11_16_15 [2] */
- FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
- /* IP11_14_12 [3] */
- FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
- FN_RX4_B, FN_SCIFA4_RXD_B,
- 0, 0, 0,
- /* IP11_11_9 [3] */
- FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
- FN_TX4_B, FN_SCIFA4_TXD_B,
- 0, 0, 0,
- /* IP11_8_6 [3] */
- FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
- FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
- /* IP11_5_3 [3] */
- FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
- 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
- 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
- /* IP12_31_30 [2] */
- 0, 0, 0, 0,
- /* IP12_29_27 [3] */
- FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
- FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
- 0, 0, 0,
- /* IP12_26_24 [3] */
- FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
- FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
- 0, 0, 0,
- /* IP12_23_22 [2] */
- FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
- /* IP12_21_20 [2] */
- FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
- /* IP12_19_18 [2] */
- FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
- /* IP12_17_16 [2] */
- FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
- /* IP12_15_13 [3] */
- FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
- FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
- 0, 0, 0,
- /* IP12_12_10 [3] */
- FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
- FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
- 0, 0, 0,
- /* IP12_9_7 [3] */
- FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
- FN_SDA2_D, FN_MSIOF1_SCK_E,
- 0, 0, 0,
- /* IP12_6_4 [3] */
- FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
- FN_SCL2_D, FN_MSIOF1_RXD_E,
- 0, 0, 0,
- /* IP12_3_2 [2] */
- FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
- /* IP12_1_0 [2] */
- FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
- },
- { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
- 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
- 3, 2, 2, 3) {
- /* IP13_31 [1] */
- 0, 0,
- /* IP13_30_28 [3] */
- FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
- 0, 0, 0, 0,
- /* IP13_27 [1] */
- FN_SD1_DATA3, FN_IERX_B,
- /* IP13_26 [1] */
- FN_SD1_DATA2, FN_IECLK_B,
- /* IP13_25 [1] */
- FN_SD1_DATA1, FN_IETX_B,
- /* IP13_24_23 [2] */
- FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
- /* IP13_22 [1] */
- FN_SD1_CMD, FN_REMOCON_B,
- /* IP13_21_19 [3] */
- FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
- FN_SCIFA5_RXD_B, FN_RX3_C,
- 0, 0,
- /* IP13_18_16 [3] */
- FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
- FN_SCIFA5_TXD_B, FN_TX3_C,
- 0, 0,
- /* IP13_15 [1] */
- FN_SD0_DATA3, FN_SSL_B,
- /* IP13_14 [1] */
- FN_SD0_DATA2, FN_IO3_B,
- /* IP13_13 [1] */
- FN_SD0_DATA1, FN_IO2_B,
- /* IP13_12 [1] */
- FN_SD0_DATA0, FN_MISO_IO1_B,
- /* IP13_11 [1] */
- FN_SD0_CMD, FN_MOSI_IO0_B,
- /* IP13_10 [1] */
- FN_SD0_CLK, FN_SPCLK_B,
- /* IP13_9_7 [3] */
- FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
- FN_ADICHS2_B, FN_MSIOF0_TXD_C,
- 0, 0, 0,
- /* IP13_6_5 [2] */
- FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
- /* IP13_4_3 [2] */
- FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
- /* IP13_2_0 [3] */
- FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
- FN_ADICLK_B, FN_MSIOF0_SS1_C,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
- 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
- /* IP14_31_29 [3] */
- FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
- FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
- /* IP14_28_26 [3] */
- FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
- FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
- /* IP14_25_23 [3] */
- FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
- 0, 0, 0,
- /* IP14_22_20 [3] */
- FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
- 0, 0, 0,
- /* IP14_19_17 [3] */
- FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
- FN_VI1_CLKENB_C, FN_VI1_G1_B,
- 0, 0,
- /* IP14_16_14 [3] */
- FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
- FN_VI1_CLK_C, FN_VI1_G0_B,
- 0, 0,
- /* IP14_13_11 [3] */
- FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
- 0, 0, 0,
- /* IP14_10_8 [3] */
- FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
- 0, 0, 0,
- /* IP14_7 [1] */
- FN_SD2_DATA3, FN_MMC_D3,
- /* IP14_6 [1] */
- FN_SD2_DATA2, FN_MMC_D2,
- /* IP14_5 [1] */
- FN_SD2_DATA1, FN_MMC_D1,
- /* IP14_4 [1] */
- FN_SD2_DATA0, FN_MMC_D0,
- /* IP14_3 [1] */
- FN_SD2_CMD, FN_MMC_CMD,
- /* IP14_2 [1] */
- FN_SD2_CLK, FN_MMC_CLK,
- /* IP14_1_0 [2] */
- FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
- 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
- /* IP15_31_30 [2] */
- 0, 0, 0, 0,
- /* IP15_29_27 [3] */
- FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
- FN_CAN0_TX_B, FN_VI1_DATA5_C,
- 0, 0,
- /* IP15_26_24 [3] */
- FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
- FN_CAN0_RX_B, FN_VI1_DATA4_C,
- 0, 0,
- /* IP15_23_21 [3] */
- FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
- FN_TCLK2, FN_VI1_DATA3_C, 0,
- /* IP15_20_18 [3] */
- FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
- 0, 0, 0,
- /* IP15_17_15 [3] */
- FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
- FN_TCLK1, FN_VI1_DATA1_C,
- 0, 0,
- /* IP15_14_12 [3] */
- FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
- FN_VI1_G7_B, FN_SCIFA3_SCK_C,
- 0, 0,
- /* IP15_11_9 [3] */
- FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
- FN_VI1_G6_B, FN_SCIFA3_RXD_C,
- 0, 0,
- /* IP15_8_6 [3] */
- FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
- FN_PWM5_B, FN_SCIFA3_TXD_C,
- 0, 0, 0,
- /* IP15_5_4 [2] */
- FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
- /* IP15_3_2 [2] */
- FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
- /* IP15_1_0 [2] */
- FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
- 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
- /* IP16_31_28 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_27_24 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_23_20 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_19_16 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_15_12 [4] */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP16_11_10 [2] */
- FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
- /* IP16_9_8 [2] */
- FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
- /* IP16_7_6 [2] */
- FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
- /* IP16_5_3 [3] */
- FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
- FN_GLO_SS_C, FN_VI1_DATA7_C,
- 0, 0, 0,
- /* IP16_2_0 [3] */
- FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
- FN_GLO_SDATA_C, FN_VI1_DATA6_C,
- 0, 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
- 3, 2, 2, 2, 1, 2, 2, 2) {
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
- /* SEL_SCIFB [2] */
- FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
- /* SEL_SCIFB2 [2] */
- FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
- FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
- /* SEL_SCIFB1 [3] */
- FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
- FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
- 0, 0, 0, 0,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* SEL_SCFA [1] */
- FN_SEL_SCFA_0, FN_SEL_SCFA_1,
- /* SEL_QSP [1] */
- FN_SEL_QSP_0, FN_SEL_QSP_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_HSCIF1 [3] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
- FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_VI1 [2] */
- FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_TMU [1] */
- FN_SEL_TMU1_0, FN_SEL_TMU1_1,
- /* SEL_LBS [2] */
- FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_SOF0 [2] */
- FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 3, 1, 1, 3, 2, 1, 1, 2, 2,
- 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
- /* SEL_SCIF0 [3] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
- FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIF [1] */
- FN_SEL_SCIF_0, FN_SEL_SCIF_1,
- /* SEL_CAN0 [3] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- FN_SEL_CAN0_4, FN_SEL_CAN0_5,
- 0, 0,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIF4 [2] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_ADG [1] */
- FN_SEL_ADG_0, FN_SEL_ADG_1,
- /* SEL_FM [3] */
- FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
- FN_SEL_FM_3, FN_SEL_FM_4,
- 0, 0, 0,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_GPS [2] */
- FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
- /* SEL_SCIFA3 [2] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
- /* SEL_SIM [1] */
- FN_SEL_SIM_0, FN_SEL_SIM_1,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 2, 2, 3, 2, 2, 2, 1) {
- /* SEL_HSCIF2 [2] */
- FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
- FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
- /* SEL_CANCLK [2] */
- FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
- FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
- /* SEL_IIC8 [2] */
- FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
- /* SEL_IIC7 [2] */
- FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
- /* SEL_IIC4 [2] */
- FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
- /* SEL_IIC3 [2] */
- FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
- /* SEL_SCIF3 [2] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_MMC [1] */
- FN_SEL_MMC_0, FN_SEL_MMC_1,
- /* SEL_SCIF5 [1] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_IIC2 [2] */
- FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
- /* SEL_IIC1 [3] */
- FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
- FN_SEL_IIC1_4,
- 0, 0, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
- 3, 2, 2, 1, 1, 1, 1, 3, 2,
- 2, 3, 1, 1, 1, 2, 2, 2, 2) {
- /* SEL_SOF1 [3] */
- FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
- FN_SEL_SOF1_4,
- 0, 0, 0,
- /* SEL_HSCIF0 [2] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
- /* SEL_DIS [2] */
- FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIF2 [3] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
- FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
- 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* SEL_SOF2 [3] */
- FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
- FN_SEL_SOF2_3, FN_SEL_SOF2_4,
- 0, 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI0 [1] */
- FN_SEL_SSI0_0, FN_SEL_SSI0_1,
- /* SEL_SSP [2] */
- FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0,
- /* RESEVED [2] */
- 0, 0, 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
- { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_7_25_IN, GP_7_25_OUT,
- GP_7_24_IN, GP_7_24_OUT,
- GP_7_23_IN, GP_7_23_OUT,
- GP_7_22_IN, GP_7_22_OUT,
- GP_7_21_IN, GP_7_21_OUT,
- GP_7_20_IN, GP_7_20_OUT,
- GP_7_19_IN, GP_7_19_OUT,
- GP_7_18_IN, GP_7_18_OUT,
- GP_7_17_IN, GP_7_17_OUT,
- GP_7_16_IN, GP_7_16_OUT,
- GP_7_15_IN, GP_7_15_OUT,
- GP_7_14_IN, GP_7_14_OUT,
- GP_7_13_IN, GP_7_13_OUT,
- GP_7_12_IN, GP_7_12_OUT,
- GP_7_11_IN, GP_7_11_OUT,
- GP_7_10_IN, GP_7_10_OUT,
- GP_7_9_IN, GP_7_9_OUT,
- GP_7_8_IN, GP_7_8_OUT,
- GP_7_7_IN, GP_7_7_OUT,
- GP_7_6_IN, GP_7_6_OUT,
- GP_7_5_IN, GP_7_5_OUT,
- GP_7_4_IN, GP_7_4_OUT,
- GP_7_3_IN, GP_7_3_OUT,
- GP_7_2_IN, GP_7_2_OUT,
- GP_7_1_IN, GP_7_1_OUT,
- GP_7_0_IN, GP_7_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
- { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_7_25_DATA, GP_7_24_DATA,
- GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
- GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
- GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
- GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
- GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
- GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7793_pinmux_info = {
- .name = "r8a7793_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_CAN1_RX_B,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7793_pinmux_init(void)
-{
- register_pinmux(&r8a7793_pinmux_info);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
- * This file is r8a7794 processor support - PFC hardware block.
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- */
-
-#include <common.h>
-#include <sh_pfc.h>
-#include <asm/gpio.h>
-
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_26_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
-
-#define CPU_28_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
- PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
- PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
- PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
-
-/*
- * GP_0_0_DATA -> GP_6_25_DATA
- * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
- * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
- * GP6[29]),GP6[30],GP6[31])
- */
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_26_PORT(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_28_PORT(fn, pfx##_5_, sfx), \
- CPU_26_PORT(fn, pfx##_6_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
-#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
-#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
- FN_##ipsr, FN_##fn)
-
-enum {
- PINMUX_RESERVED = 0,
-
- PINMUX_DATA_BEGIN,
- GP_ALL(DATA),
- PINMUX_DATA_END,
-
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN),
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT),
- PINMUX_OUTPUT_END,
-
- PINMUX_FUNCTION_BEGIN,
- GP_ALL(FN),
-
- /* GPSR0 */
- FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
- FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
- FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
- FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
- FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
- FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
- FN_IP2_17_16,
-
- /* GPSR1 */
- FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
- FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
- FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
- FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
- FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
-
- /* GPSR2 */
- FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
- FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
- FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
- FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
- FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
- FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
- FN_IP6_5_4, FN_IP6_7_6,
-
- /* GPSR3 */
- FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
- FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
- FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
- FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
- FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
- FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
- FN_IP8_22_20,
-
- /* GPSR4 */
- FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
- FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
- FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
- FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
- FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
- FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
- FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
-
- /* GPSR5 */
- FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
- FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
- FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
- FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
- FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
- FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
-
- /* GPSR6 */
- FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
- FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
- FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
- FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
- FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
-
- /* IPSR0 */
- FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
- FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
- FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
- FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
- FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
- FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
- FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
- FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
- FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
- FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
- FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
- FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
- FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
- FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
- FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
- FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
- FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
- FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
- FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
- FN_ADIDATA, FN_AD_DI,
-
- /* IPSR7 */
- FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
- FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
- FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
- FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
- FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
- FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
- FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
- FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
- FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
- FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
- FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
- FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
- FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
-
- /* IPSR8 */
- FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
- FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
- FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
- FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
- FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
- FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
- FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
- FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
- FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
- FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
- FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
- FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
- FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
- FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
- FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
- FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
- FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
- FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
- FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
- FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
- FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
- FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
- FN_ADICLK_B, FN_AD_CLK_B,
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- /* MOD_SEL */
- FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
- FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
- FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
- FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
- FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
- FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
- FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
- FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
- FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
- FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
- FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
- FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
- FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
-
- /* MOD_SEL2 */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
- FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
- FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
- FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
- FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
- FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
- FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
- FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
- FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
- FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
- FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
- FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
- FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
- FN_SEL_RDS_2, FN_SEL_RDS_3,
-
- /* MOD_SEL3 */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
- FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
- FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
- FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
- FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
- FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
- FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
- FN_SEL_SSI9_1,
- PINMUX_FUNCTION_END,
-
- PINMUX_MARK_BEGIN,
- A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
-
- USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
-
- SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
- SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
-
- SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
- SD1_DATA2_MARK, SD1_DATA3_MARK,
-
- /* IPSR0 */
- SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
- MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
- SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
- SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
- MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
- CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
- CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
- SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
- SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
- SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
- DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
- DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
- CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
- AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
- VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
- AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
- VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
- AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
- I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
- VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
- AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
- IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
- I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
- VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
- ADIDATA_MARK, AD_DI_MARK,
-
- /* IPSR7 */
- ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
- AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
- MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
- AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
- CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
- ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
- AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
- MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
- ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
- SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
- IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
- VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
- SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
- AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
- SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
- DREQ0_N_MARK, SCIFB1_RXD_MARK,
-
- /* IPSR8 */
- ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
- AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
- I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
- HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
- AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
- SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
- HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
- AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
- HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
- I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
- AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
- SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
- CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
- DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
- I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
- TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
- I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
- FMCLK_C_MARK, RDS_CLK_MARK,
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
- CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
- DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
- SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
- SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
- DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
- SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
- CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
- DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
- DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
- AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
- MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
- PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
- ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
- PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
- PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
-
- PINMUX_DATA(A2_MARK, FN_A2),
- PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
- PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
- PINMUX_DATA(DACK0_MARK, FN_DACK0),
- PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
- PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
- PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
- PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
- PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
- PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
- PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
- PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
- PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
- PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
- PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
- PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
- PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
- PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
- PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
- PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
- PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
- PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
-
- /* IPSR0 */
- PINMUX_IPSR_DATA(IP0_0, SD1_CD),
- PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
- PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
- PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
- PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
- PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
- PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
- PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
- PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
- PINMUX_IPSR_DATA(IP0_12, MMC_D0),
- PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
- PINMUX_IPSR_DATA(IP0_13, MMC_D1),
- PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
- PINMUX_IPSR_DATA(IP0_14, MMC_D2),
- PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
- PINMUX_IPSR_DATA(IP0_15, MMC_D3),
- PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
- PINMUX_IPSR_DATA(IP0_16, MMC_D4),
- PINMUX_IPSR_DATA(IP0_16, SD2_CD),
- PINMUX_IPSR_DATA(IP0_17, MMC_D5),
- PINMUX_IPSR_DATA(IP0_17, SD2_WP),
- PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
- PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
- PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
- PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
- PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
- PINMUX_IPSR_DATA(IP0_23_22, D0),
- PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
- PINMUX_IPSR_DATA(IP0_24, D1),
- PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_25, D2),
- PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
- PINMUX_IPSR_DATA(IP0_27_26, D3),
- PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
- PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
- PINMUX_IPSR_DATA(IP0_29_28, D4),
- PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
- PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
- PINMUX_IPSR_DATA(IP0_31_30, D5),
- PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
- PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
- PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
- PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
- PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
- PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
- PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
- PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
- PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
- PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
- PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
- PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
- PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
- PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
- PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
- PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
- PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
- PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
- PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
- PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
- PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
- PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
- PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
- PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
- PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
- PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
- PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
- PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
- PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
- PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
- PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
- PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
- PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
- PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
- PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
- PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
-
- /* IPSR7 */
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
- PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
- PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
- PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
- PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
- PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
- PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
- PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
- PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
- PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
- PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
- PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
- PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
- PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
- PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
- PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
-
- /* IPSR8 */
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
- PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
- PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
- PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
- PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
- PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
- PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
- PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
- PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
- PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
- PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
- PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
- PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
- PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
- PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
- PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_19_17, PWM5),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
- PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
- PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
- PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
- PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
- PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
- PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
- PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
- PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
- PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
- PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
- PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
- PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
- PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
- PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
- PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
- PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
- PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
- PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
- PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
- PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
- PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
- PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
- PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
- PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
- PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
- PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
- PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
- PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
- PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
- PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
- PINMUX_GPIO_GP_ALL(),
-
- GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
- GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
- GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
- GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
- GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
- GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
- GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
-
- /* IPSR0 */
- GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
- GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
- GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
- GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
- GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
- GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
- GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
- GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
- GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
- GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
- GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
- GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
- GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- /* IPSR6 */
- GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
- GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
- GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
- GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
- GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
- GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
- GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
- GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
- GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
- GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
- GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
- GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
- GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
- GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
- GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
- GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
- GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
- GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
- GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
- GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
-
- /* IPSR7 */
- GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
- GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
- GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
- GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
- GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
- GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
- GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
- GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
- GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
- GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
- GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
- GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
- GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
- GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
- GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
- GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
- GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
- GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
- GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
- GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
- GPIO_FN(SCIFB1_RXD),
-
- /* IPSR8 */
- GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
- GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
- GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
- GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
- GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
- GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
- GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
- GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
- GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
- GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
- GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
- GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
- GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
- GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
- GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
- GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
- GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
- GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
- GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
- GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
- GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
- GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
- GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- /* IPSR11 */
- GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
- GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
- GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
- GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
- GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
- GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
- GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
- GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
- GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
- GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
- GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
- GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
- GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
- GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
- GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
- GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
- GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
- GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
- GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
- { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
- GP_0_31_FN, FN_IP2_17_16,
- GP_0_30_FN, FN_IP2_15_14,
- GP_0_29_FN, FN_IP2_13_12,
- GP_0_28_FN, FN_IP2_11_10,
- GP_0_27_FN, FN_IP2_9_8,
- GP_0_26_FN, FN_IP2_7_6,
- GP_0_25_FN, FN_IP2_5_4,
- GP_0_24_FN, FN_IP2_3_2,
- GP_0_23_FN, FN_IP2_1_0,
- GP_0_22_FN, FN_IP1_31_30,
- GP_0_21_FN, FN_IP1_29_28,
- GP_0_20_FN, FN_IP1_27,
- GP_0_19_FN, FN_IP1_26,
- GP_0_18_FN, FN_A2,
- GP_0_17_FN, FN_IP1_24,
- GP_0_16_FN, FN_IP1_23_22,
- GP_0_15_FN, FN_IP1_21_20,
- GP_0_14_FN, FN_IP1_19_18,
- GP_0_13_FN, FN_IP1_17_15,
- GP_0_12_FN, FN_IP1_14_13,
- GP_0_11_FN, FN_IP1_12_11,
- GP_0_10_FN, FN_IP1_10_8,
- GP_0_9_FN, FN_IP1_7_6,
- GP_0_8_FN, FN_IP1_5_4,
- GP_0_7_FN, FN_IP1_3_2,
- GP_0_6_FN, FN_IP1_1_0,
- GP_0_5_FN, FN_IP0_31_30,
- GP_0_4_FN, FN_IP0_29_28,
- GP_0_3_FN, FN_IP0_27_26,
- GP_0_2_FN, FN_IP0_25,
- GP_0_1_FN, FN_IP0_24,
- GP_0_0_FN, FN_IP0_23_22, }
- },
- { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_FN, FN_DACK0,
- GP_1_24_FN, FN_IP7_31,
- GP_1_23_FN, FN_IP4_1_0,
- GP_1_22_FN, FN_WE1_N,
- GP_1_21_FN, FN_WE0_N,
- GP_1_20_FN, FN_IP3_31,
- GP_1_19_FN, FN_IP3_30,
- GP_1_18_FN, FN_IP3_29_27,
- GP_1_17_FN, FN_IP3_26_24,
- GP_1_16_FN, FN_IP3_23_21,
- GP_1_15_FN, FN_IP3_20_18,
- GP_1_14_FN, FN_IP3_17_15,
- GP_1_13_FN, FN_IP3_14_13,
- GP_1_12_FN, FN_IP3_12,
- GP_1_11_FN, FN_IP3_11,
- GP_1_10_FN, FN_IP3_10,
- GP_1_9_FN, FN_IP3_9_8,
- GP_1_8_FN, FN_IP3_7_6,
- GP_1_7_FN, FN_IP3_5_4,
- GP_1_6_FN, FN_IP3_3_2,
- GP_1_5_FN, FN_IP3_1_0,
- GP_1_4_FN, FN_IP2_31_30,
- GP_1_3_FN, FN_IP2_29_27,
- GP_1_2_FN, FN_IP2_26_24,
- GP_1_1_FN, FN_IP2_23_21,
- GP_1_0_FN, FN_IP2_20_18, }
- },
- { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
- GP_2_31_FN, FN_IP6_7_6,
- GP_2_30_FN, FN_IP6_5_4,
- GP_2_29_FN, FN_IP6_3_2,
- GP_2_28_FN, FN_IP6_1_0,
- GP_2_27_FN, FN_IP5_31_30,
- GP_2_26_FN, FN_IP5_29_28,
- GP_2_25_FN, FN_IP5_27_26,
- GP_2_24_FN, FN_IP5_25_24,
- GP_2_23_FN, FN_IP5_23_22,
- GP_2_22_FN, FN_IP5_21_20,
- GP_2_21_FN, FN_IP5_19_18,
- GP_2_20_FN, FN_IP5_17_16,
- GP_2_19_FN, FN_IP5_15_14,
- GP_2_18_FN, FN_IP5_13_12,
- GP_2_17_FN, FN_IP5_11_9,
- GP_2_16_FN, FN_IP5_8_6,
- GP_2_15_FN, FN_IP5_5_4,
- GP_2_14_FN, FN_IP5_3_2,
- GP_2_13_FN, FN_IP5_1_0,
- GP_2_12_FN, FN_IP4_31_30,
- GP_2_11_FN, FN_IP4_29_28,
- GP_2_10_FN, FN_IP4_27_26,
- GP_2_9_FN, FN_IP4_25_23,
- GP_2_8_FN, FN_IP4_22_20,
- GP_2_7_FN, FN_IP4_19_18,
- GP_2_6_FN, FN_IP4_17_16,
- GP_2_5_FN, FN_IP4_15_14,
- GP_2_4_FN, FN_IP4_13_12,
- GP_2_3_FN, FN_IP4_11_10,
- GP_2_2_FN, FN_IP4_9_8,
- GP_2_1_FN, FN_IP4_7_5,
- GP_2_0_FN, FN_IP4_4_2 }
- },
- { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
- GP_3_31_FN, FN_IP8_22_20,
- GP_3_30_FN, FN_IP8_19_17,
- GP_3_29_FN, FN_IP8_16_15,
- GP_3_28_FN, FN_IP8_14_12,
- GP_3_27_FN, FN_IP8_11_9,
- GP_3_26_FN, FN_IP8_8_6,
- GP_3_25_FN, FN_IP8_5_3,
- GP_3_24_FN, FN_IP8_2_0,
- GP_3_23_FN, FN_IP7_29_27,
- GP_3_22_FN, FN_IP7_26_24,
- GP_3_21_FN, FN_IP7_23_21,
- GP_3_20_FN, FN_IP7_20_18,
- GP_3_19_FN, FN_IP7_17_15,
- GP_3_18_FN, FN_IP7_14_12,
- GP_3_17_FN, FN_IP7_11_9,
- GP_3_16_FN, FN_IP7_8_6,
- GP_3_15_FN, FN_IP7_5_3,
- GP_3_14_FN, FN_IP7_2_0,
- GP_3_13_FN, FN_IP6_31_29,
- GP_3_12_FN, FN_IP6_28_26,
- GP_3_11_FN, FN_IP6_25_23,
- GP_3_10_FN, FN_IP6_22_20,
- GP_3_9_FN, FN_IP6_19_17,
- GP_3_8_FN, FN_IP6_16,
- GP_3_7_FN, FN_IP6_15,
- GP_3_6_FN, FN_IP6_14,
- GP_3_5_FN, FN_IP6_13,
- GP_3_4_FN, FN_IP6_12,
- GP_3_3_FN, FN_IP6_11,
- GP_3_2_FN, FN_IP6_10,
- GP_3_1_FN, FN_IP6_9,
- GP_3_0_FN, FN_IP6_8 }
- },
- { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
- GP_4_31_FN, FN_IP11_17_16,
- GP_4_30_FN, FN_IP11_15_14,
- GP_4_29_FN, FN_IP11_13_11,
- GP_4_28_FN, FN_IP11_10_8,
- GP_4_27_FN, FN_IP11_7_6,
- GP_4_26_FN, FN_IP11_5_3,
- GP_4_25_FN, FN_IP11_2_0,
- GP_4_24_FN, FN_IP10_31_30,
- GP_4_23_FN, FN_IP10_29_27,
- GP_4_22_FN, FN_IP10_26_24,
- GP_4_21_FN, FN_IP10_23_21,
- GP_4_20_FN, FN_IP10_20_18,
- GP_4_19_FN, FN_IP10_17_15,
- GP_4_18_FN, FN_IP10_14_12,
- GP_4_17_FN, FN_IP10_11_9,
- GP_4_16_FN, FN_IP10_8_6,
- GP_4_15_FN, FN_IP10_5_3,
- GP_4_14_FN, FN_IP10_2_0,
- GP_4_13_FN, FN_IP9_30_28,
- GP_4_12_FN, FN_IP9_27_25,
- GP_4_11_FN, FN_IP9_24_22,
- GP_4_10_FN, FN_IP9_21_19,
- GP_4_9_FN, FN_IP9_18_17,
- GP_4_8_FN, FN_IP9_16_15,
- GP_4_7_FN, FN_IP9_14_12,
- GP_4_6_FN, FN_IP9_11_9,
- GP_4_5_FN, FN_IP9_8_6,
- GP_4_4_FN, FN_IP9_5_3,
- GP_4_3_FN, FN_IP9_2_0,
- GP_4_2_FN, FN_IP8_31_29,
- GP_4_1_FN, FN_IP8_28_26,
- GP_4_0_FN, FN_IP8_25_23 }
- },
- { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_27_FN, FN_USB1_OVC,
- GP_5_26_FN, FN_USB1_PWEN,
- GP_5_25_FN, FN_USB0_OVC,
- GP_5_24_FN, FN_USB0_PWEN,
- GP_5_23_FN, FN_IP13_26_24,
- GP_5_22_FN, FN_IP13_23_21,
- GP_5_21_FN, FN_IP13_20_18,
- GP_5_20_FN, FN_IP13_17_15,
- GP_5_19_FN, FN_IP13_14_12,
- GP_5_18_FN, FN_IP13_11_9,
- GP_5_17_FN, FN_IP13_8_6,
- GP_5_16_FN, FN_IP13_5_3,
- GP_5_15_FN, FN_IP13_2_0,
- GP_5_14_FN, FN_IP12_29_27,
- GP_5_13_FN, FN_IP12_26_24,
- GP_5_12_FN, FN_IP12_23_21,
- GP_5_11_FN, FN_IP12_20_18,
- GP_5_10_FN, FN_IP12_17_15,
- GP_5_9_FN, FN_IP12_14_13,
- GP_5_8_FN, FN_IP12_12_11,
- GP_5_7_FN, FN_IP12_10_9,
- GP_5_6_FN, FN_IP12_8_6,
- GP_5_5_FN, FN_IP12_5_3,
- GP_5_4_FN, FN_IP12_2_0,
- GP_5_3_FN, FN_IP11_29_27,
- GP_5_2_FN, FN_IP11_26_24,
- GP_5_1_FN, FN_IP11_23_21,
- GP_5_0_FN, FN_IP11_20_18 }
- },
- { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_25_FN, FN_IP0_21_20,
- GP_6_24_FN, FN_IP0_19_18,
- GP_6_23_FN, FN_IP0_17,
- GP_6_22_FN, FN_IP0_16,
- GP_6_21_FN, FN_IP0_15,
- GP_6_20_FN, FN_IP0_14,
- GP_6_19_FN, FN_IP0_13,
- GP_6_18_FN, FN_IP0_12,
- GP_6_17_FN, FN_IP0_11,
- GP_6_16_FN, FN_IP0_10,
- GP_6_15_FN, FN_IP0_9_8,
- GP_6_14_FN, FN_IP0_0,
- GP_6_13_FN, FN_SD1_DATA3,
- GP_6_12_FN, FN_SD1_DATA2,
- GP_6_11_FN, FN_SD1_DATA1,
- GP_6_10_FN, FN_SD1_DATA0,
- GP_6_9_FN, FN_SD1_CMD,
- GP_6_8_FN, FN_SD1_CLK,
- GP_6_7_FN, FN_SD0_WP,
- GP_6_6_FN, FN_SD0_CD,
- GP_6_5_FN, FN_SD0_DATA3,
- GP_6_4_FN, FN_SD0_DATA2,
- GP_6_3_FN, FN_SD0_DATA1,
- GP_6_2_FN, FN_SD0_DATA0,
- GP_6_1_FN, FN_SD0_CMD,
- GP_6_0_FN, FN_SD0_CLK }
- },
- { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
- 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 2, 1, 1, 1, 1, 1, 1, 1, 1) {
- /* IP0_31_30 [2] */
- FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
- /* IP0_29_28 [2] */
- FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
- /* IP0_27_26 [2] */
- FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
- /* IP0_25 [1] */
- FN_D2, FN_SCIFA3_TXD_B,
- /* IP0_24 [1] */
- FN_D1, FN_SCIFA3_RXD_B,
- /* IP0_23_22 [2] */
- FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
- /* IP0_21_20 [2] */
- FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
- /* IP0_19_18 [2] */
- FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
- /* IP0_17 [1] */
- FN_MMC_D5, FN_SD2_WP,
- /* IP0_16 [1] */
- FN_MMC_D4, FN_SD2_CD,
- /* IP0_15 [1] */
- FN_MMC_D3, FN_SD2_DATA3,
- /* IP0_14 [1] */
- FN_MMC_D2, FN_SD2_DATA2,
- /* IP0_13 [1] */
- FN_MMC_D1, FN_SD2_DATA1,
- /* IP0_12 [1] */
- FN_MMC_D0, FN_SD2_DATA0,
- /* IP0_11 [1] */
- FN_MMC_CMD, FN_SD2_CMD,
- /* IP0_10 [1] */
- FN_MMC_CLK, FN_SD2_CLK,
- /* IP0_9_8 [2] */
- FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
- /* IP0_7 [1] */
- 0, 0,
- /* IP0_6 [1] */
- 0, 0,
- /* IP0_5 [1] */
- 0, 0,
- /* IP0_4 [1] */
- 0, 0,
- /* IP0_3 [1] */
- 0, 0,
- /* IP0_2 [1] */
- 0, 0,
- /* IP0_1 [1] */
- 0, 0,
- /* IP0_0 [1] */
- FN_SD1_CD, FN_CAN0_RX, }
- },
-
- /*
- * From IPSR1 to IPSR5 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
- 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
- 2, 2) {
- /* IP6_31_29 [3] */
- FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
- FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
- /* IP6_28_26 [3] */
- FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
- FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
- /* IP6_25_23 [3] */
- FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
- FN_AVB_COL, 0, 0, 0,
- /* IP6_22_20 [3] */
- FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
- FN_AVB_RX_ER, 0, 0, 0,
- /* IP6_19_17 [3] */
- FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
- FN_AVB_RXD7, 0, 0, 0,
- /* IP6_16 [1] */
- FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
- /* IP6_15 [1] */
- FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
- /* IP6_14 [1] */
- FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
- /* IP6_13 [1] */
- FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
- /* IP6_12 [1] */
- FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
- /* IP6_11 [1] */
- FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
- /* IP6_10 [1] */
- FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
- /* IP6_9 [1] */
- FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
- /* IP6_8 [1] */
- FN_VI0_CLK, FN_AVB_RX_CLK,
- /* IP6_7_6 [2] */
- FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
- /* IP6_5_4 [2] */
- FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
- /* IP6_3_2 [2] */
- FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
- /* IP6_1_0 [2] */
- FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
- 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
- /* IP7_31 [1] */
- FN_DREQ0_N, FN_SCIFB1_RXD,
- /* IP7_30 [1] */
- 0, 0,
- /* IP7_29_27 [3] */
- FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
- FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
- /* IP7_26_24 [3] */
- FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
- FN_SSI_SCK6_B, 0, 0, 0,
- /* IP7_23_21 [3] */
- FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
- FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
- /* IP7_20_18 [3] */
- FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
- FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
- /* IP7_17_15 [3] */
- FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
- FN_SSI_SCK5_B, 0, 0, 0,
- /* IP7_14_12 [3] */
- FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
- FN_AVB_TXD4, FN_ADICHS2, 0, 0,
- /* IP7_11_9 [3] */
- FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
- FN_AVB_TXD3, FN_ADICHS1, 0, 0,
- /* IP7_8_6 [3] */
- FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
- FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
- /* IP7_5_3 [3] */
- FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
- FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
- /* IP7_2_0 [3] */
- FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
- FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
- },
- { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
- 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
- /* IP8_31_29 [3] */
- FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
- FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
- /* IP8_28_26 [3] */
- FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
- FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
- /* IP8_25_23 [3] */
- FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
- FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
- /* IP8_22_20 [3] */
- FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
- FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
- /* IP8_19_17 [3] */
- FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
- FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
- /* IP8_16_15 [2] */
- FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
- /* IP8_14_12 [3] */
- FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
- FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
- /* IP8_11_9 [3] */
- FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
- FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
- /* IP8_8_6 [3] */
- FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
- FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
- /* IP8_5_3 [3] */
- FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
- FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
- /* IP8_2_0 [3] */
- FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
- FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
- },
-
- /*
- * From IPSR9 to IPSR10 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
- 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
- /* IP11_31_30 [2] */
- 0, 0, 0, 0,
- /* IP11_29_27 [3] */
- FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
- FN_AD_CLK_B, 0, 0, 0,
- /* IP11_26_24 [3] */
- FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
- FN_AD_DO_B, 0, 0, 0,
- /* IP11_23_21 [3] */
- FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
- FN_AD_DI_B, FN_PCMWE_N, 0, 0,
- /* IP11_20_18 [3] */
- FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
- FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
- /* IP11_17_16 [2] */
- FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
- /* IP11_15_14 [2] */
- FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
- /* IP11_13_11 [3] */
- FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
- FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
- /* IP11_10_8 [3] */
- FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
- FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
- /* IP11_7_6 [2] */
- FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
- FN_CAN_DEBUGOUT13,
- /* IP11_5_3 [3] */
- FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
- FN_CAN_DEBUGOUT12, 0, 0, 0,
- /* IP11_2_0 [3] */
- FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
- FN_CAN_DEBUGOUT11, 0, 0, 0, }
- },
-
- /*
- * From IPSR12 to IPSR13 have been removed because they does not use.
- */
-
- { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
- 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
- 2, 1) {
- /* SEL_ADG [2] */
- FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
- /* SEL_ADI [1] */
- FN_SEL_ADI_0, FN_SEL_ADI_1,
- /* SEL_CAN [2] */
- FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
- /* SEL_DARC [3] */
- FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
- FN_SEL_DARC_4, 0, 0, 0,
- /* SEL_DR0 [1] */
- FN_SEL_DR0_0, FN_SEL_DR0_1,
- /* SEL_DR1 [1] */
- FN_SEL_DR1_0, FN_SEL_DR1_1,
- /* SEL_DR2 [1] */
- FN_SEL_DR2_0, FN_SEL_DR2_1,
- /* SEL_DR3 [1] */
- FN_SEL_DR3_0, FN_SEL_DR3_1,
- /* SEL_ETH [1] */
- FN_SEL_ETH_0, FN_SEL_ETH_1,
- /* SLE_FSN [1] */
- FN_SEL_FSN_0, FN_SEL_FSN_1,
- /* SEL_IC200 [3] */
- FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
- FN_SEL_I2C00_4, 0, 0, 0,
- /* SEL_I2C01 [3] */
- FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
- FN_SEL_I2C01_4, 0, 0, 0,
- /* SEL_I2C02 [3] */
- FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
- FN_SEL_I2C02_4, 0, 0, 0,
- /* SEL_I2C03 [3] */
- FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
- FN_SEL_I2C03_4, 0, 0, 0,
- /* SEL_I2C04 [3] */
- FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
- FN_SEL_I2C04_4, 0, 0, 0,
- /* SEL_IIC00 [2] */
- FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
- /* SEL_AVB [1] */
- FN_SEL_AVB_0, FN_SEL_AVB_1, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
- 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
- 2, 2, 2, 1, 1, 2) {
- /* SEL_IEB [2] */
- FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
- /* SEL_IIC0 [2] */
- FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
- /* SEL_LBS [1] */
- FN_SEL_LBS_0, FN_SEL_LBS_1,
- /* SEL_MSI1 [1] */
- FN_SEL_MSI1_0, FN_SEL_MSI1_1,
- /* SEL_MSI2 [1] */
- FN_SEL_MSI2_0, FN_SEL_MSI2_1,
- /* SEL_RAD [1] */
- FN_SEL_RAD_0, FN_SEL_RAD_1,
- /* SEL_RCN [1] */
- FN_SEL_RCN_0, FN_SEL_RCN_1,
- /* SEL_RSP [1] */
- FN_SEL_RSP_0, FN_SEL_RSP_1,
- /* SEL_SCIFA0 [2] */
- FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
- FN_SEL_SCIFA0_3,
- /* SEL_SCIFA1 [2] */
- FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
- /* SEL_SCIFA2 [1] */
- FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
- /* SEL_SCIFA3 [1] */
- FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
- /* SEL_SCIFA4 [2] */
- FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
- FN_SEL_SCIFA4_3,
- /* SEL_SCIFA5 [2] */
- FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
- FN_SEL_SCIFA5_3,
- /* SEL_SPDM [1] */
- FN_SEL_SPDM_0, FN_SEL_SPDM_1,
- /* SEL_TMU [1] */
- FN_SEL_TMU_0, FN_SEL_TMU_1,
- /* SEL_TSIF0 [2] */
- FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
- /* SEL_CAN0 [2] */
- FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
- /* SEL_CAN1 [2] */
- FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
- /* SEL_HSCIF0 [1] */
- FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
- /* SEL_HSCIF1 [1] */
- FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
- /* SEL_RDS [2] */
- FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
- },
- { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
- 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
- /* SEL_SCIF0 [2] */
- FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
- /* SEL_SCIF1 [2] */
- FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
- /* SEL_SCIF2 [2] */
- FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
- /* SEL_SCIF3 [1] */
- FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
- /* SEL_SCIF4 [3] */
- FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
- FN_SEL_SCIF4_4, 0, 0, 0,
- /* SEL_SCIF5 [2] */
- FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
- /* SEL_SSI1 [1] */
- FN_SEL_SSI1_0, FN_SEL_SSI1_1,
- /* SEL_SSI2 [1] */
- FN_SEL_SSI2_0, FN_SEL_SSI2_1,
- /* SEL_SSI4 [1] */
- FN_SEL_SSI4_0, FN_SEL_SSI4_1,
- /* SEL_SSI5 [1] */
- FN_SEL_SSI5_0, FN_SEL_SSI5_1,
- /* SEL_SSI6 [1] */
- FN_SEL_SSI6_0, FN_SEL_SSI6_1,
- /* SEL_SSI7 [1] */
- FN_SEL_SSI7_0, FN_SEL_SSI7_1,
- /* SEL_SSI8 [1] */
- FN_SEL_SSI8_0, FN_SEL_SSI8_1,
- /* SEL_SSI9 [1] */
- FN_SEL_SSI9_0, FN_SEL_SSI9_1,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0,
- /* RESEVED [1] */
- 0, 0, }
- },
- { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_1_25_IN, GP_1_25_OUT,
- GP_1_24_IN, GP_1_24_OUT,
- GP_1_23_IN, GP_1_23_OUT,
- GP_1_22_IN, GP_1_22_OUT,
- GP_1_21_IN, GP_1_21_OUT,
- GP_1_20_IN, GP_1_20_OUT,
- GP_1_19_IN, GP_1_19_OUT,
- GP_1_18_IN, GP_1_18_OUT,
- GP_1_17_IN, GP_1_17_OUT,
- GP_1_16_IN, GP_1_16_OUT,
- GP_1_15_IN, GP_1_15_OUT,
- GP_1_14_IN, GP_1_14_OUT,
- GP_1_13_IN, GP_1_13_OUT,
- GP_1_12_IN, GP_1_12_OUT,
- GP_1_11_IN, GP_1_11_OUT,
- GP_1_10_IN, GP_1_10_OUT,
- GP_1_9_IN, GP_1_9_OUT,
- GP_1_8_IN, GP_1_8_OUT,
- GP_1_7_IN, GP_1_7_OUT,
- GP_1_6_IN, GP_1_6_OUT,
- GP_1_5_IN, GP_1_5_OUT,
- GP_1_4_IN, GP_1_4_OUT,
- GP_1_3_IN, GP_1_3_OUT,
- GP_1_2_IN, GP_1_2_OUT,
- GP_1_1_IN, GP_1_1_OUT,
- GP_1_0_IN, GP_1_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_5_27_IN, GP_5_27_OUT,
- GP_5_26_IN, GP_5_26_OUT,
- GP_5_25_IN, GP_5_25_OUT,
- GP_5_24_IN, GP_5_24_OUT,
- GP_5_23_IN, GP_5_23_OUT,
- GP_5_22_IN, GP_5_22_OUT,
- GP_5_21_IN, GP_5_21_OUT,
- GP_5_20_IN, GP_5_20_OUT,
- GP_5_19_IN, GP_5_19_OUT,
- GP_5_18_IN, GP_5_18_OUT,
- GP_5_17_IN, GP_5_17_OUT,
- GP_5_16_IN, GP_5_16_OUT,
- GP_5_15_IN, GP_5_15_OUT,
- GP_5_14_IN, GP_5_14_OUT,
- GP_5_13_IN, GP_5_13_OUT,
- GP_5_12_IN, GP_5_12_OUT,
- GP_5_11_IN, GP_5_11_OUT,
- GP_5_10_IN, GP_5_10_OUT,
- GP_5_9_IN, GP_5_9_OUT,
- GP_5_8_IN, GP_5_8_OUT,
- GP_5_7_IN, GP_5_7_OUT,
- GP_5_6_IN, GP_5_6_OUT,
- GP_5_5_IN, GP_5_5_OUT,
- GP_5_4_IN, GP_5_4_OUT,
- GP_5_3_IN, GP_5_3_OUT,
- GP_5_2_IN, GP_5_2_OUT,
- GP_5_1_IN, GP_5_1_OUT,
- GP_5_0_IN, GP_5_0_OUT, }
- },
- { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_25_IN, GP_6_25_OUT,
- GP_6_24_IN, GP_6_24_OUT,
- GP_6_23_IN, GP_6_23_OUT,
- GP_6_22_IN, GP_6_22_OUT,
- GP_6_21_IN, GP_6_21_OUT,
- GP_6_20_IN, GP_6_20_OUT,
- GP_6_19_IN, GP_6_19_OUT,
- GP_6_18_IN, GP_6_18_OUT,
- GP_6_17_IN, GP_6_17_OUT,
- GP_6_16_IN, GP_6_16_OUT,
- GP_6_15_IN, GP_6_15_OUT,
- GP_6_14_IN, GP_6_14_OUT,
- GP_6_13_IN, GP_6_13_OUT,
- GP_6_12_IN, GP_6_12_OUT,
- GP_6_11_IN, GP_6_11_OUT,
- GP_6_10_IN, GP_6_10_OUT,
- GP_6_9_IN, GP_6_9_OUT,
- GP_6_8_IN, GP_6_8_OUT,
- GP_6_7_IN, GP_6_7_OUT,
- GP_6_6_IN, GP_6_6_OUT,
- GP_6_5_IN, GP_6_5_OUT,
- GP_6_4_IN, GP_6_4_OUT,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_1_25_DATA, GP_1_24_DATA,
- GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
- GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
- GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
- GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
- GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
- GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
- },
- { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
- 0, 0, 0, 0,
- GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
- GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
- GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
- GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
- GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
- GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
- GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
- },
- { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
- 0, 0, 0, 0,
- 0, 0, GP_6_25_DATA, GP_6_24_DATA,
- GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
- GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
- GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
- GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
- GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
- GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
- },
- { },
-};
-
-static struct pinmux_info r8a7794_pinmux_info = {
- .name = "r8a7794_pfc",
-
- .unlock_reg = 0xe6060000, /* PMMR */
-
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
- .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_AD_CLK_B,
-
- .gpios = pinmux_gpios,
- .cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
-
- .gpio_data = pinmux_data,
- .gpio_data_size = ARRAY_SIZE(pinmux_data),
-};
-
-void r8a7794_pinmux_init(void)
-{
- register_pinmux(&r8a7794_pinmux_info);
-}
config SYS_SOC
default "snapdragon"
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
+config SPL_SYS_MALLOC_F_LEN
+ default 0x2000
+
choice
prompt "Snapdragon board select"
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
obj-y += clock-snapdragon.o
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(17)
-#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
static const struct bcr_regs sdc_regs[] = {
{
}
};
-static struct gpll0_ctrl gpll0_ctrl = {
+static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
- .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
+ .vote_bit = BIT(0),
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = BLSP1_AHB_CBCR,
+ .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+ .vote_bit = BIT(10),
};
/* SDHCI */
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
CFG_CLK_SRC_GPLL0);
- clk_enable_gpll0(priv->base, &gpll0_ctrl);
+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
return rate;
/* UART: 115200 */
static int clk_init_uart(struct msm_clk_priv *priv)
{
- /* Enable iface clk */
- clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
+ /* Enable AHB clock */
+ clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0);
- clk_enable_gpll0(priv->base, &gpll0_ctrl);
+
+ /* Vote for gpll0 clock */
+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
.D = SDCC2_D,
};
-static const struct gpll0_ctrl gpll0_ctrl = {
+static const struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
CFG_CLK_SRC_GPLL0);
- clk_enable_gpll0(priv->base, &gpll0_ctrl);
+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
return rate;
;
}
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
{
if (readl(base + gpll0->status) & gpll0->status_bit)
return; /* clock already enabled */
;
}
+#define BRANCH_ON_VAL (0)
+#define BRANCH_NOC_FSM_ON_VAL BIT(29)
+#define BRANCH_CHECK_MASK GENMASK(31, 28)
+
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
+{
+ u32 val;
+
+ setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
+ do {
+ val = readl(base + vclk->cbcr_reg);
+ val &= BRANCH_CHECK_MASK;
+ } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
+}
+
#define APPS_CMD_RGCR_UPDATE BIT(0)
/* Update clock command via CMD_RGCR */
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
-struct gpll0_ctrl {
+struct pll_vote_clk {
uintptr_t status;
int status_bit;
uintptr_t ena_vote;
int vote_bit;
};
+struct vote_clk {
+ uintptr_t cbcr_reg;
+ uintptr_t ena_vote;
+ int vote_bit;
+};
struct bcr_regs {
uintptr_t cfg_rcgr;
uintptr_t cmd_rcgr;
phys_addr_t base;
};
-void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
+void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
void clk_enable_cbc(phys_addr_t cbcr);
+void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source);
/* Clocks: (from CLK_CTL_BASE) */
#define GPLL0_STATUS (0x2101C)
#define APCS_GPLL_ENA_VOTE (0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8016 pinctrl
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN];
+static const char * const msm_pinctrl_pins[] = {
+ "SDC1_CLK",
+ "SDC1_CMD",
+ "SDC1_DATA",
+ "SDC2_CLK",
+ "SDC2_CMD",
+ "SDC2_DATA",
+ "QDSD_CLK",
+ "QDSD_CMD",
+ "QDSD_DATA0",
+ "QDSD_DATA1",
+ "QDSD_DATA2",
+ "QDSD_DATA3",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp1_uart", 2},
+};
+
+static const char *apq8016_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8016_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector < 130) {
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ return pin_name;
+ } else {
+ return msm_pinctrl_pins[selector - 130];
+ }
+}
+
+static unsigned int apq8016_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data apq8016_data = {
+ .pin_count = 140,
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = apq8016_get_function_name,
+ .get_function_mux = apq8016_get_function_mux,
+ .get_pin_name = apq8016_get_pin_name,
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TLMM driver for Qualcomm APQ8016, APQ8096
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include "pinctrl-snapdragon.h"
+
+struct msm_pinctrl_priv {
+ phys_addr_t base;
+ struct msm_pinctrl_data *data;
+};
+
+#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
+#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
+#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
+#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
+#define TLMM_GPIO_ENABLE BIT(9)
+
+static const struct pinconf_param msm_conf_params[] = {
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+};
+
+static int msm_get_functions_count(struct udevice *dev)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->data->functions_count;
+}
+
+static int msm_get_pins_count(struct udevice *dev)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->data->pin_count;
+}
+
+static const char *msm_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->data->get_function_name(dev, selector);
+}
+
+static int msm_pinctrl_probe(struct udevice *dev)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->base = devfdt_get_addr(dev);
+ priv->data = (struct msm_pinctrl_data *)dev->driver_data;
+
+ return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
+}
+
+static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->data->get_pin_name(dev, selector);
+}
+
+static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int func_selector)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+ priv->data->get_function_mux(func_selector) << 2);
+ return 0;
+}
+
+static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int param, unsigned int argument)
+{
+ struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_DRV_STRENGTH_MASK, argument << 6);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
+ TLMM_GPIO_PULL_MASK);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops msm_pinctrl_ops = {
+ .get_pins_count = msm_get_pins_count,
+ .get_pin_name = msm_get_pin_name,
+ .set_state = pinctrl_generic_set_state,
+ .pinmux_set = msm_pinmux_set,
+ .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
+ .pinconf_params = msm_conf_params,
+ .pinconf_set = msm_pinconf_set,
+ .get_functions_count = msm_get_functions_count,
+ .get_function_name = msm_get_function_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
+ { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_snapdraon) = {
+ .name = "pinctrl_msm",
+ .id = UCLASS_PINCTRL,
+ .of_match = msm_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
+ .ops = &msm_pinctrl_ops,
+ .probe = msm_pinctrl_probe,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm Pin control
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+#ifndef _PINCTRL_SNAPDRAGON_H
+#define _PINCTRL_SNAPDRAGON_H
+
+#include <common.h>
+
+struct msm_pinctrl_data {
+ int pin_count;
+ int functions_count;
+ const char *(*get_function_name)(struct udevice *dev,
+ unsigned int selector);
+ unsigned int (*get_function_mux)(unsigned int selector);
+ const char *(*get_pin_name)(struct udevice *dev,
+ unsigned int selector);
+};
+
+struct pinctrl_function {
+ const char *name;
+ int val;
+};
+
+extern struct msm_pinctrl_data apq8016_data;
+
+#endif
if ARCH_SOCFPGA
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y if DM_MMC
-
-config SPL_NAND_SUPPORT
- default y if SPL_NAND_DENALI
-
-config SPL_SERIAL_SUPPORT
- default y
-
-config SPL_SPI_FLASH_SUPPORT
- default y if SPL_SPI_SUPPORT
-
-config SPL_SPI_SUPPORT
- default y if DM_SPI
-
-config SPL_WATCHDOG_SUPPORT
- default y
-
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
- default y
-
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+ select ALTERA_SDRAM
config TARGET_SOCFPGA_CYCLONE5
bool
obj-y += reset_manager_arria10.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y += clock_manager_s10.o
+obj-y += reset_manager_s10.o
+obj-y += system_manager_s10.o
+obj-y += wrap_pinmux_config_s10.o
+obj-y += wrap_pll_config_s10.o
+endif
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
#include <common.h>
#include <errno.h>
+#include <fdtdec.h>
#include <asm/arch/reset_manager.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
#include <asm/io.h>
#include <usb.h>
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+ /* configuring the clock based on handoff */
+ cm_basic_init(gd->fdt_blob);
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
+#endif
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
return 0;
}
do {
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
inter_val = readl(&clock_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
inter_val = readl(&clock_manager_base->stat) & mask;
#endif
/* Wait for stable lock */
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
gd->bd->bi_ddr_freq = 0;
#endif
#include <dm.h>
#include <asm/arch/clock_manager.h>
+static const struct socfpga_clock_manager *clock_manager_base =
+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
u32 cntr8clk_cnt;
u32 cntr8clk_src;
u32 cntr9clk_cnt;
+ u32 cntr9clk_src;
u32 emacctl_emac0sel;
u32 emacctl_emac1sel;
u32 emacctl_emac2sel;
u32 gpiodiv_gpiodbclk;
};
-struct alteragrp_cfg {
- u32 nocclk;
- u32 mpuclk;
+struct strtou32 {
+ const char *str;
+ const u32 val;
};
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+static const struct strtou32 mainpll_cfg_tab[] = {
+ { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
+ { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
+ { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
+ { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
+ { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
+ { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
+ { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
+ { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
+ { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
+ { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
+ { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
+ { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
+ { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
+ { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
+ { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
+ { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
+ { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
+ { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
+ { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
+ { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
+ { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
+ { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
+ { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) },
+ { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
+};
+
+static const struct strtou32 perpll_cfg_tab[] = {
+ { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
+ { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
+ { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
+ { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
+ { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
+ { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
+ { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
+ { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
+ { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
+ { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
+ { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
+ { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
+ { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
+ { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
+ { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
+ { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
+ { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
+ { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
+ { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
+ { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
+ { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
+};
+
+static const struct strtou32 alteragrp_cfg_tab[] = {
+ { "nocclk", offsetof(struct mainpll_cfg, nocclk) },
+ { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
+};
+
+struct strtopu32 {
+ const char *str;
+ u32 *p;
+};
+
+const struct strtopu32 dt_to_val[] = {
+ { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
+ { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz},
+ { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
+};
-static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
+static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
+ int cfg_tab_len, void *cfg)
{
- if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
- (u32 *)cfg, cfg_len)) {
- /* could not find required property */
- return -EINVAL;
+ int i;
+ u32 val;
+
+ for (i = 0; i < cfg_tab_len; i++) {
+ if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) {
+ /* could not find required property */
+ return -EINVAL;
+ }
+ *(u32 *)(cfg + cfg_tab[i].val) = val;
}
return 0;
}
-static int of_get_input_clks(const void *blob, int node, u32 *val)
+static void of_get_input_clks(const void *blob)
{
- *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
- if (!*val)
- return -EINVAL;
+ int node, i;
- return 0;
+ for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
+ node = fdt_path_offset(blob, dt_to_val[i].str);
+
+ if (node < 0)
+ continue;
+
+ fdtdec_get_int_array(blob, node, "clock-frequency",
+ dt_to_val[i].p, 1);
+ }
}
static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
- struct perpll_cfg *per_cfg,
- struct alteragrp_cfg *altrgrp_cfg)
+ struct perpll_cfg *per_cfg)
{
int node, child, len;
const char *node_name;
- node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK);
+ of_get_input_clks(blob);
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
+
if (node < 0)
return -EINVAL;
child = fdt_first_subnode(blob, node);
- if (child < 0)
- return -EINVAL;
- child = fdt_first_subnode(blob, child);
if (child < 0)
return -EINVAL;
node_name = fdt_get_name(blob, child, &len);
while (node_name) {
- if (!strcmp(node_name, "osc1")) {
- if (of_get_input_clks(blob, child, &eosc1_hz))
+ if (!strcmp(node_name, "mainpll")) {
+ if (of_to_struct(blob, child, mainpll_cfg_tab,
+ ARRAY_SIZE(mainpll_cfg_tab), main_cfg))
return -EINVAL;
- } else if (!strcmp(node_name, "cb_intosc_ls_clk")) {
- if (of_get_input_clks(blob, child, &cb_intosc_hz))
+ } else if (!strcmp(node_name, "perpll")) {
+ if (of_to_struct(blob, child, perpll_cfg_tab,
+ ARRAY_SIZE(perpll_cfg_tab), per_cfg))
return -EINVAL;
- } else if (!strcmp(node_name, "f2s_free_clk")) {
- if (of_get_input_clks(blob, child, &f2s_free_hz))
+ } else if (!strcmp(node_name, "alteragrp")) {
+ if (of_to_struct(blob, child, alteragrp_cfg_tab,
+ ARRAY_SIZE(alteragrp_cfg_tab), main_cfg))
return -EINVAL;
- } else if (!strcmp(node_name, "main_pll")) {
- if (of_to_struct(blob, child,
- sizeof(*main_cfg)/sizeof(u32),
- main_cfg))
- return -EINVAL;
- } else if (!strcmp(node_name, "periph_pll")) {
- if (of_to_struct(blob, child,
- sizeof(*per_cfg)/sizeof(u32),
- per_cfg))
- return -EINVAL;
- } else if (!strcmp(node_name, "altera")) {
- if (of_to_struct(blob, child,
- sizeof(*altrgrp_cfg)/sizeof(u32),
- altrgrp_cfg))
- return -EINVAL;
-
- main_cfg->mpuclk = altrgrp_cfg->mpuclk;
- main_cfg->nocclk = altrgrp_cfg->nocclk;
}
child = fdt_next_subnode(blob, child);
{
struct mainpll_cfg main_cfg;
struct perpll_cfg per_cfg;
- struct alteragrp_cfg altrgrp_cfg;
int rval;
/* initialize to zero for use case of optional node */
memset(&main_cfg, 0, sizeof(main_cfg));
memset(&per_cfg, 0, sizeof(per_cfg));
- memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg));
- rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg);
+ rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
if (rval)
return rval;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_s10.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+static const struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void cm_write_bypass_mainpll(u32 val)
+{
+ writel(val, &clock_manager_base->main_pll.bypass);
+ cm_wait_for_fsm();
+}
+
+static void cm_write_bypass_perpll(u32 val)
+{
+ writel(val, &clock_manager_base->per_pll.bypass);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void cm_write_ctrl(u32 val)
+{
+ writel(val, &clock_manager_base->ctrl);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+ u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
+
+ if (cfg == 0)
+ return;
+
+ /* Put all plls in bypass */
+ cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+ cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* setup main PLL dividers where calculate the vcocalib value */
+ mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+ CLKMGR_FDBCK_MDIV_MASK;
+ refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+ mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+ hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+ CLKMGR_HSCNT_CONST;
+ vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+ ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+ CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+ writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+ ~CLKMGR_PLLGLOB_RST_MASK),
+ &clock_manager_base->main_pll.pllglob);
+ writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
+ writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
+ writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
+ writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
+ writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+
+ /* setup peripheral PLL dividers */
+ /* calculate the vcocalib value */
+ mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
+ CLKMGR_FDBCK_MDIV_MASK;
+ refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+ mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
+ hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
+ CLKMGR_HSCNT_CONST;
+ vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+ ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+ CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+ writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+ ~CLKMGR_PLLGLOB_RST_MASK),
+ &clock_manager_base->per_pll.pllglob);
+ writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
+ writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
+ writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
+ writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
+ writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
+ writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+ /* Take both PLL out of reset and power up */
+ setbits_le32(&clock_manager_base->main_pll.pllglob,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+ setbits_le32(&clock_manager_base->per_pll.pllglob,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+#define LOCKED_MASK \
+ (CLKMGR_STAT_MAINPLL_LOCKED | \
+ CLKMGR_STAT_PERPLL_LOCKED)
+
+ cm_wait_for_lock(LOCKED_MASK);
+
+ /*
+ * Dividers for C2 to C9 only init after PLLs are lock. As dividers
+ * only take effect upon value change, we shall set a maximum value as
+ * default value.
+ */
+ writel(0xff, &clock_manager_base->main_pll.mpuclk);
+ writel(0xff, &clock_manager_base->main_pll.nocclk);
+ writel(0xff, &clock_manager_base->main_pll.cntr2clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr3clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr4clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr5clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr6clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr7clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr8clk);
+ writel(0xff, &clock_manager_base->main_pll.cntr9clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr2clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr3clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr4clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr5clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr6clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr7clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr8clk);
+ writel(0xff, &clock_manager_base->per_pll.cntr9clk);
+
+ writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
+ writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
+ writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
+ writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
+ writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
+ writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
+ writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
+ writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
+ writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
+ writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
+ writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
+ writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
+ writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
+ writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
+ writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
+ writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
+ writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
+ writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+
+ /* Take all PLLs out of bypass */
+ cm_write_bypass_mainpll(0);
+ cm_write_bypass_perpll(0);
+
+ /* clear safe mode / out of boot mode */
+ cm_write_ctrl(readl(&clock_manager_base->ctrl)
+ & ~(CLKMGR_CTRL_SAFEMODE));
+
+ /* Now ungate non-hw-managed clocks */
+ writel(~0, &clock_manager_base->main_pll.en);
+ writel(~0, &clock_manager_base->per_pll.en);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
+ &clock_manager_base->intrclr);
+}
+
+static unsigned long cm_get_main_vco_clk_hz(void)
+{
+ unsigned long fref, refdiv, mdiv, reg, vco;
+
+ reg = readl(&clock_manager_base->main_pll.pllglob);
+
+ fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+ CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+ switch (fref) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ fref = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_INTOSC:
+ fref = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_F2S:
+ fref = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+ reg = readl(&clock_manager_base->main_pll.fdbck);
+ mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+ vco = fref / refdiv;
+ vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+ return vco;
+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+ unsigned long fref, refdiv, mdiv, reg, vco;
+
+ reg = readl(&clock_manager_base->per_pll.pllglob);
+
+ fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+ CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+ switch (fref) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ fref = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_INTOSC:
+ fref = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_F2S:
+ fref = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+ CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+ reg = readl(&clock_manager_base->per_pll.fdbck);
+ mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+ vco = fref / refdiv;
+ vco = vco * (CLKMGR_MDIV_CONST + mdiv);
+ return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+
+ clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+ switch (clock) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = cm_get_main_vco_clk_hz();
+ clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+ CLKMGR_PLLC0_DIV_MASK);
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = cm_get_per_vco_clk_hz();
+ clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
+ CLKMGR_CLKCNT_MSK);
+ return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+ u32 clock = readl(&clock_manager_base->main_pll.nocclk);
+
+ clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+ switch (clock) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = cm_get_main_vco_clk_hz();
+ clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+ CLKMGR_PLLC0_DIV_MASK);
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = cm_get_per_vco_clk_hz();
+ clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+ CLKMGR_CLKCNT_MSK);
+ return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+ u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
+
+ clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+ switch (clock) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = cm_get_l3_main_clk_hz();
+ clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = cm_get_l3_main_clk_hz();
+ clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+ return clock / 4;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+ u32 clock = cm_get_l3_main_clk_hz();
+
+ clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+ CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+ return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(&sysmgr_regs->boot_scratch_cold0);
+}
+
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+ u32 clock = cm_get_l3_main_clk_hz();
+
+ clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+ CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+ return clock;
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_l3_main_clk_hz() / 4;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
+ printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+ printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+ printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+ printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000);
+ printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+ printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#define SOCFPGA_CCU_ADDRESS 0xf7000000
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
#define SOCFPGA_SDR_ADDRESS 0xf8011000
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER 0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300
+#define SOCFPGA_FIREWALL_TCU 0xffd21400
#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
#include <asm/arch/clock_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
#endif
#endif /* _CLOCK_MANAGER_H_ */
#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
-#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
+#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
/* value */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_S10_
+#define _CLOCK_MANAGER_S10_
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ 25000000
+#define CLKMGR_INTOSC_HZ 460000000
+#define CLKMGR_FPGA_CLK_HZ 50000000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+struct cm_config {
+ /* main group */
+ u32 main_pll_mpuclk;
+ u32 main_pll_nocclk;
+ u32 main_pll_cntr2clk;
+ u32 main_pll_cntr3clk;
+ u32 main_pll_cntr4clk;
+ u32 main_pll_cntr5clk;
+ u32 main_pll_cntr6clk;
+ u32 main_pll_cntr7clk;
+ u32 main_pll_cntr8clk;
+ u32 main_pll_cntr9clk;
+ u32 main_pll_nocdiv;
+ u32 main_pll_pllglob;
+ u32 main_pll_fdbck;
+ u32 main_pll_pllc0;
+ u32 main_pll_pllc1;
+ u32 spare;
+
+ /* peripheral group */
+ u32 per_pll_cntr2clk;
+ u32 per_pll_cntr3clk;
+ u32 per_pll_cntr4clk;
+ u32 per_pll_cntr5clk;
+ u32 per_pll_cntr6clk;
+ u32 per_pll_cntr7clk;
+ u32 per_pll_cntr8clk;
+ u32 per_pll_cntr9clk;
+ u32 per_pll_emacctl;
+ u32 per_pll_gpiodiv;
+ u32 per_pll_pllglob;
+ u32 per_pll_fdbck;
+ u32 per_pll_pllc0;
+ u32 per_pll_pllc1;
+
+ /* incoming clock */
+ u32 hps_osc_clk_hz;
+ u32 fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+ u32 en;
+ u32 ens;
+ u32 enr;
+ u32 bypass;
+ u32 bypasss;
+ u32 bypassr;
+ u32 mpuclk;
+ u32 nocclk;
+ u32 cntr2clk;
+ u32 cntr3clk;
+ u32 cntr4clk;
+ u32 cntr5clk;
+ u32 cntr6clk;
+ u32 cntr7clk;
+ u32 cntr8clk;
+ u32 cntr9clk;
+ u32 nocdiv;
+ u32 pllglob;
+ u32 fdbck;
+ u32 mem;
+ u32 memstat;
+ u32 pllc0;
+ u32 pllc1;
+ u32 vcocalib;
+ u32 _pad_0x90_0xA0[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+ u32 en;
+ u32 ens;
+ u32 enr;
+ u32 bypass;
+ u32 bypasss;
+ u32 bypassr;
+ u32 cntr2clk;
+ u32 cntr3clk;
+ u32 cntr4clk;
+ u32 cntr5clk;
+ u32 cntr6clk;
+ u32 cntr7clk;
+ u32 cntr8clk;
+ u32 cntr9clk;
+ u32 emacctl;
+ u32 gpiodiv;
+ u32 pllglob;
+ u32 fdbck;
+ u32 mem;
+ u32 memstat;
+ u32 pllc0;
+ u32 pllc1;
+ u32 vcocalib;
+ u32 _pad_0x100_0x124[10];
+};
+
+struct socfpga_clock_manager {
+ u32 ctrl;
+ u32 stat;
+ u32 testioctrl;
+ u32 intrgen;
+ u32 intrmsk;
+ u32 intrclr;
+ u32 intrsts;
+ u32 intrstk;
+ u32 intrraw;
+ u32 _pad_0x24_0x2c[3];
+ struct socfpga_clock_manager_main_pll main_pll;
+ struct socfpga_clock_manager_per_pll per_pll;
+};
+
+#define CLKMGR_CTRL_SAFEMODE BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
+#define CLKMGR_STAT_BUSY BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
+#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
+
+#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
+#define CLKMGR_VCO_PSRC_EOSC1 0
+#define CLKMGR_VCO_PSRC_INTOSC 1
+#define CLKMGR_VCO_PSRC_F2S 2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
+
+#define CLKMGR_CLKSRC_MASK 0x7
+#define CLKMGR_CLKSRC_OFFSET 16
+#define CLKMGR_CLKSRC_MAIN 0
+#define CLKMGR_CLKSRC_PER 1
+#define CLKMGR_CLKSRC_OSC1 2
+#define CLKMGR_CLKSRC_INTOSC 3
+#define CLKMGR_CLKSRC_FPGA 4
+#define CLKMGR_CLKCNT_MSK 0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK 0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET 24
+
+#define CLKMGR_PLLC0_DIV_MASK 0xff
+#define CLKMGR_PLLC1_DIV_MASK 0xff
+#define CLKMGR_PLLC0_EN_OFFSET 27
+#define CLKMGR_PLLC1_EN_OFFSET 24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
+#define CLKMGR_NOCDIV_DIV1 0
+#define CLKMGR_NOCDIV_DIV2 1
+#define CLKMGR_NOCDIV_DIV4 2
+#define CLKMGR_NOCDIV_DIV8 3
+#define CLKMGR_CSPDBGCLK_DIV1 0
+#define CLKMGR_CSPDBGCLK_DIV4 1
+
+#define CLKMGR_MSCNT_CONST 200
+#define CLKMGR_MDIV_CONST 6
+#define CLKMGR_HSCNT_CONST 9
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
+#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _HANDOFF_S10_H_
+#define _HANDOFF_S10_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define S10_HANDOFF_BASE 0xFFE3F000
+#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10)
+#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
+#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
+#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
+#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
+#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
+#define S10_HANDOFF_MAGIC_MUX 0x504D5558
+#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354
+#define S10_HANDOFF_MAGIC_FPGA 0x46504741
+#define S10_HANDOFF_MAGIC_DELAY 0x444C4159
+#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#define S10_HANDOFF_MAGIC_MISC 0x4D495343
+#define S10_HANDOFF_OFFSET_LENGTH 0x4
+#define S10_HANDOFF_OFFSET_DATA 0x10
+
+#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
+#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
+
+#define S10_HANDOFF_SIZE 4096
+
+#endif /* _HANDOFF_S10_H_ */
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+ const u8 phymode));
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
-#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
-#endif
/*
* Define a reset identifier, from which a permodrst bank ID
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
#endif
#endif /* _RESET_MANAGER_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _RESET_MANAGER_S10_
+#define _RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+ u32 status;
+ u32 mpu_rst_stat;
+ u32 misc_stat;
+ u32 padding1;
+ u32 hdsk_en;
+ u32 hdsk_req;
+ u32 hdsk_ack;
+ u32 hdsk_stall;
+ u32 mpumodrst;
+ u32 per0modrst;
+ u32 per1modrst;
+ u32 brgmodrst;
+ u32 padding2;
+ u32 cold_mod_reset;
+ u32 padding3;
+ u32 dbg_mod_reset;
+ u32 tap_mod_reset;
+ u32 padding4;
+ u32 padding5;
+ u32 brg_warm_mask;
+ u32 padding6[3];
+ u32 tst_stat;
+ u32 padding7;
+ u32 hdsk_timeout;
+ u32 mpul2flushtimeout;
+ u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK 0x7
+#define RSTMGR_RESET_OFFSET 0
+#define RSTMGR_RESET_MASK 0x1f
+#define RSTMGR_DEFINE(_bank, _offset) \
+ ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset) \
+ (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset) \
+ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
+#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
+#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
+#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
+#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
+#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
+#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
+#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
+
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name) RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_S10_ */
u32 _pad_0x10_0x3c[12]; /* 0x10 */
u32 fsar; /* 0x40 */
u32 fear;
- u32 _pad_0x48_0x50[2];
- u32 acr; /* 0x54 */
+ u32 _pad_0x48_0x4c[2];
+ u32 acr; /* 0x50 */
u32 sacr;
};
#ifndef __ASSEMBLY__
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4; /* 0x10 */
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 __padding0[3];
- u32 dram_addrw; /* 0x2c */
- u32 dram_if_width; /* 0x30 */
- u32 dram_dev_width;
- u32 dram_sts;
- u32 dram_intr;
- u32 sbe_count; /* 0x40 */
- u32 dbe_count;
- u32 err_addr;
- u32 drop_count;
- u32 drop_addr; /* 0x50 */
- u32 lowpwr_eq;
- u32 lowpwr_ack;
- u32 static_cfg;
- u32 ctrl_width; /* 0x60 */
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap; /* 0x70 */
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst; /* 0x80 */
- u32 __padding1;
- u32 fifo_cfg;
- u32 protport_default;
- u32 prot_rule_addr; /* 0x90 */
- u32 prot_rule_id;
- u32 prot_rule_data;
- u32 prot_rule_rdwr;
- u32 __padding2[3];
- u32 mp_priority; /* 0xac */
- u32 mp_weight0; /* 0xb0 */
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0; /* 0xc0 */
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0; /* 0xd0 */
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 __padding3[29];
- u32 phy_ctrl0; /* 0x150 */
- u32 phy_ctrl1;
- u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4;
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 dram_addrw;
- u32 dram_if_width;
- u32 dram_dev_width;
- u32 dram_intr;
- u32 lowpwr_eq;
- u32 static_cfg;
- u32 ctrl_width;
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap;
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst;
- u32 fifo_cfg;
- u32 mp_priority;
- u32 mp_weight0;
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0;
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0;
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
- u8 activate_0_and_1;
- u8 activate_0_and_1_wait1;
- u8 activate_0_and_1_wait2;
- u8 activate_1;
- u8 clear_dqs_enable;
- u8 guaranteed_read;
- u8 guaranteed_read_cont;
- u8 guaranteed_write;
- u8 guaranteed_write_wait0;
- u8 guaranteed_write_wait1;
- u8 guaranteed_write_wait2;
- u8 guaranteed_write_wait3;
- u8 idle;
- u8 idle_loop1;
- u8 idle_loop2;
- u8 init_reset_0_cke_0;
- u8 init_reset_1_cke_0;
- u8 lfsr_wr_rd_bank_0;
- u8 lfsr_wr_rd_bank_0_data;
- u8 lfsr_wr_rd_bank_0_dqs;
- u8 lfsr_wr_rd_bank_0_nop;
- u8 lfsr_wr_rd_bank_0_wait;
- u8 lfsr_wr_rd_bank_0_wl_1;
- u8 lfsr_wr_rd_dm_bank_0;
- u8 lfsr_wr_rd_dm_bank_0_data;
- u8 lfsr_wr_rd_dm_bank_0_dqs;
- u8 lfsr_wr_rd_dm_bank_0_nop;
- u8 lfsr_wr_rd_dm_bank_0_wait;
- u8 lfsr_wr_rd_dm_bank_0_wl_1;
- u8 mrs0_dll_reset;
- u8 mrs0_dll_reset_mirr;
- u8 mrs0_user;
- u8 mrs0_user_mirr;
- u8 mrs1;
- u8 mrs1_mirr;
- u8 mrs2;
- u8 mrs2_mirr;
- u8 mrs3;
- u8 mrs3_mirr;
- u8 precharge_all;
- u8 read_b2b;
- u8 read_b2b_wait1;
- u8 read_b2b_wait2;
- u8 refresh_all;
- u8 rreturn;
- u8 sgle_read;
- u8 zqcl;
-
- u8 true_mem_data_mask_width;
- u8 mem_address_mirroring;
- u8 mem_data_mask_width;
- u8 mem_data_width;
- u8 mem_dq_per_read_dqs;
- u8 mem_dq_per_write_dqs;
- u8 mem_if_read_dqs_width;
- u8 mem_if_write_dqs_width;
- u8 mem_number_of_cs_per_dimm;
- u8 mem_number_of_ranks;
- u8 mem_virtual_groups_per_read_dqs;
- u8 mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
- u16 delay_per_opa_tap;
- u8 delay_per_dchain_tap;
- u8 delay_per_dqs_en_dchain_tap;
- u8 dll_chain_length;
- u8 dqdqs_out_phase_max;
- u8 dqs_en_delay_max;
- u8 dqs_en_delay_offset;
- u8 dqs_en_phase_max;
- u8 dqs_in_delay_max;
- u8 dqs_in_reserve;
- u8 dqs_out_reserve;
- u8 io_in_delay_max;
- u8 io_out1_delay_max;
- u8 io_out2_delay_max;
- u8 shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
- u32 reg_file_init_seq_signature;
- u8 afi_rate_ratio;
- u8 calib_lfifo_offset;
- u8 calib_vfifo_offset;
- u8 enable_super_quick_calibration;
- u8 max_latency_count_width;
- u8 read_valid_fifo_size;
- u8 tinit_cntr0_val;
- u8 tinit_cntr1_val;
- u8 tinit_cntr2_val;
- u8 treset_cntr0_val;
- u8 treset_cntr1_val;
- u8 treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1 */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2 */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3 */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4 */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1 */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC 40
-#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
+#endif
#endif
#endif /* _SDRAM_H_ */
#define _SOCFPGA_SDRAM_ARRIA10_H_
#ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
struct socfpga_ecc_hmc {
u32 ip_rev_id;
u32 niosreserve1;
u32 niosreserve2;
};
+
#endif /*__ASSEMBLY__*/
#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ */
+#ifndef _SOCFPGA_SDRAM_GEN5_H_
+#define _SOCFPGA_SDRAM_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
+
+#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
+
+struct socfpga_sdr_ctrl {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4; /* 0x10 */
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 __padding0[3];
+ u32 dram_addrw; /* 0x2c */
+ u32 dram_if_width; /* 0x30 */
+ u32 dram_dev_width;
+ u32 dram_sts;
+ u32 dram_intr;
+ u32 sbe_count; /* 0x40 */
+ u32 dbe_count;
+ u32 err_addr;
+ u32 drop_count;
+ u32 drop_addr; /* 0x50 */
+ u32 lowpwr_eq;
+ u32 lowpwr_ack;
+ u32 static_cfg;
+ u32 ctrl_width; /* 0x60 */
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap; /* 0x70 */
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst; /* 0x80 */
+ u32 __padding1;
+ u32 fifo_cfg;
+ u32 protport_default;
+ u32 prot_rule_addr; /* 0x90 */
+ u32 prot_rule_id;
+ u32 prot_rule_data;
+ u32 prot_rule_rdwr;
+ u32 __padding2[3];
+ u32 mp_priority; /* 0xac */
+ u32 mp_weight0; /* 0xb0 */
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0; /* 0xc0 */
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0; /* 0xd0 */
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 __padding3[29];
+ u32 phy_ctrl0; /* 0x150 */
+ u32 phy_ctrl1;
+ u32 phy_ctrl2;
+};
+
+/* SDRAM configuration structure for the SPL. */
+struct socfpga_sdram_config {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4;
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 dram_addrw;
+ u32 dram_if_width;
+ u32 dram_dev_width;
+ u32 dram_intr;
+ u32 lowpwr_eq;
+ u32 static_cfg;
+ u32 ctrl_width;
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap;
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst;
+ u32 fifo_cfg;
+ u32 mp_priority;
+ u32 mp_weight0;
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0;
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0;
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 phy_ctrl0;
+};
+
+struct socfpga_sdram_rw_mgr_config {
+ u8 activate_0_and_1;
+ u8 activate_0_and_1_wait1;
+ u8 activate_0_and_1_wait2;
+ u8 activate_1;
+ u8 clear_dqs_enable;
+ u8 guaranteed_read;
+ u8 guaranteed_read_cont;
+ u8 guaranteed_write;
+ u8 guaranteed_write_wait0;
+ u8 guaranteed_write_wait1;
+ u8 guaranteed_write_wait2;
+ u8 guaranteed_write_wait3;
+ u8 idle;
+ u8 idle_loop1;
+ u8 idle_loop2;
+ u8 init_reset_0_cke_0;
+ u8 init_reset_1_cke_0;
+ u8 lfsr_wr_rd_bank_0;
+ u8 lfsr_wr_rd_bank_0_data;
+ u8 lfsr_wr_rd_bank_0_dqs;
+ u8 lfsr_wr_rd_bank_0_nop;
+ u8 lfsr_wr_rd_bank_0_wait;
+ u8 lfsr_wr_rd_bank_0_wl_1;
+ u8 lfsr_wr_rd_dm_bank_0;
+ u8 lfsr_wr_rd_dm_bank_0_data;
+ u8 lfsr_wr_rd_dm_bank_0_dqs;
+ u8 lfsr_wr_rd_dm_bank_0_nop;
+ u8 lfsr_wr_rd_dm_bank_0_wait;
+ u8 lfsr_wr_rd_dm_bank_0_wl_1;
+ u8 mrs0_dll_reset;
+ u8 mrs0_dll_reset_mirr;
+ u8 mrs0_user;
+ u8 mrs0_user_mirr;
+ u8 mrs1;
+ u8 mrs1_mirr;
+ u8 mrs2;
+ u8 mrs2_mirr;
+ u8 mrs3;
+ u8 mrs3_mirr;
+ u8 precharge_all;
+ u8 read_b2b;
+ u8 read_b2b_wait1;
+ u8 read_b2b_wait2;
+ u8 refresh_all;
+ u8 rreturn;
+ u8 sgle_read;
+ u8 zqcl;
+
+ u8 true_mem_data_mask_width;
+ u8 mem_address_mirroring;
+ u8 mem_data_mask_width;
+ u8 mem_data_width;
+ u8 mem_dq_per_read_dqs;
+ u8 mem_dq_per_write_dqs;
+ u8 mem_if_read_dqs_width;
+ u8 mem_if_write_dqs_width;
+ u8 mem_number_of_cs_per_dimm;
+ u8 mem_number_of_ranks;
+ u8 mem_virtual_groups_per_read_dqs;
+ u8 mem_virtual_groups_per_write_dqs;
+};
+
+struct socfpga_sdram_io_config {
+ u16 delay_per_opa_tap;
+ u8 delay_per_dchain_tap;
+ u8 delay_per_dqs_en_dchain_tap;
+ u8 dll_chain_length;
+ u8 dqdqs_out_phase_max;
+ u8 dqs_en_delay_max;
+ u8 dqs_en_delay_offset;
+ u8 dqs_en_phase_max;
+ u8 dqs_in_delay_max;
+ u8 dqs_in_reserve;
+ u8 dqs_out_reserve;
+ u8 io_in_delay_max;
+ u8 io_out1_delay_max;
+ u8 io_out2_delay_max;
+ u8 shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+ u32 reg_file_init_seq_signature;
+ u8 afi_rate_ratio;
+ u8 calib_lfifo_offset;
+ u8 calib_vfifo_offset;
+ u8 enable_super_quick_calibration;
+ u8 max_latency_count_width;
+ u8 read_valid_fifo_size;
+ u8 tinit_cntr0_val;
+ u8 tinit_cntr1_val;
+ u8 tinit_cntr2_val;
+ u8 treset_cntr0_val;
+ u8 treset_cntr1_val;
+ u8 treset_cntr2_val;
+};
+
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1 */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2 */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3 */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4 */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
+
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC 40
+#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+
+#endif
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
#ifndef _SYSTEM_MANAGER_H_
#define _SYSTEM_MANAGER_H_
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/system_manager_s10.h>
+#else
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
#define SYSMGR_ECC_OCRAM_EN BIT(0)
#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
-
+#endif
#endif /* _SYSTEM_MANAGER_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SYSTEM_MANAGER_S10_
+#define _SYSTEM_MANAGER_S10_
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+ /* System Manager Module */
+ u32 siliconid1; /* 0x00 */
+ u32 siliconid2;
+ u32 wddbg;
+ u32 _pad_0xc;
+ u32 mpu_status; /* 0x10 */
+ u32 mpu_ace;
+ u32 _pad_0x18_0x1c[2];
+ u32 dma; /* 0x20 */
+ u32 dma_periph;
+ /* SDMMC Controller Group */
+ u32 sdmmcgrp_ctrl;
+ u32 sdmmcgrp_l3master;
+ /* NAND Flash Controller Register Group */
+ u32 nandgrp_bootstrap; /* 0x30 */
+ u32 nandgrp_l3master;
+ /* USB Controller Group */
+ u32 usb0_l3master;
+ u32 usb1_l3master;
+ /* EMAC Group */
+ u32 emac_gbl; /* 0x40 */
+ u32 emac0;
+ u32 emac1;
+ u32 emac2;
+ u32 emac0_ace; /* 0x50 */
+ u32 emac1_ace;
+ u32 emac2_ace;
+ u32 nand_axuser;
+ u32 _pad_0x60_0x64[2]; /* 0x60 */
+ /* FPGA interface Group */
+ u32 fpgaintf_en_1;
+ u32 fpgaintf_en_2;
+ u32 fpgaintf_en_3; /* 0x70 */
+ u32 dma_l3master;
+ u32 etr_l3master;
+ u32 _pad_0x7c;
+ u32 sec_ctrl_slt; /* 0x80 */
+ u32 osc_trim;
+ u32 _pad_0x88_0x8c[2];
+ /* ECC Group */
+ u32 ecc_intmask_value; /* 0x90 */
+ u32 ecc_intmask_set;
+ u32 ecc_intmask_clr;
+ u32 ecc_intstatus_serr;
+ u32 ecc_intstatus_derr; /* 0xa0 */
+ u32 _pad_0xa4_0xac[3];
+ u32 noc_addr_remap; /* 0xb0 */
+ u32 hmc_clk;
+ u32 io_pa_ctrl;
+ u32 _pad_0xbc;
+ /* NOC Group */
+ u32 noc_timeout; /* 0xc0 */
+ u32 noc_idlereq_set;
+ u32 noc_idlereq_clr;
+ u32 noc_idlereq_value;
+ u32 noc_idleack; /* 0xd0 */
+ u32 noc_idlestatus;
+ u32 fpga2soc_ctrl;
+ u32 fpga_config;
+ u32 iocsrclk_gate; /* 0xe0 */
+ u32 gpo;
+ u32 gpi;
+ u32 _pad_0xec;
+ u32 mpu; /* 0xf0 */
+ u32 sdm_hps_spare;
+ u32 hps_sdm_spare;
+ u32 _pad_0xfc_0x1fc[65];
+ /* Boot scratch register group */
+ u32 boot_scratch_cold0; /* 0x200 */
+ u32 boot_scratch_cold1;
+ u32 boot_scratch_cold2;
+ u32 boot_scratch_cold3;
+ u32 boot_scratch_cold4; /* 0x210 */
+ u32 boot_scratch_cold5;
+ u32 boot_scratch_cold6;
+ u32 boot_scratch_cold7;
+ u32 boot_scratch_cold8; /* 0x220 */
+ u32 boot_scratch_cold9;
+ u32 _pad_0x228_0xffc[886];
+ /* Pin select and pin control group */
+ u32 pinsel0[40]; /* 0x1000 */
+ u32 _pad_0x10a0_0x10fc[24];
+ u32 pinsel40[8];
+ u32 _pad_0x1120_0x112c[4];
+ u32 ioctrl0[28];
+ u32 _pad_0x11a0_0x11fc[24];
+ u32 ioctrl28[20];
+ u32 _pad_0x1250_0x12fc[44];
+ /* Use FPGA mux */
+ u32 rgmii0usefpga; /* 0x1300 */
+ u32 rgmii1usefpga;
+ u32 rgmii2usefpga;
+ u32 i2c0usefpga;
+ u32 i2c1usefpga;
+ u32 i2c_emac0_usefpga;
+ u32 i2c_emac1_usefpga;
+ u32 i2c_emac2_usefpga;
+ u32 nandusefpga;
+ u32 _pad_0x1324;
+ u32 spim0usefpga;
+ u32 spim1usefpga;
+ u32 spis0usefpga;
+ u32 spis1usefpga;
+ u32 uart0usefpga;
+ u32 uart1usefpga;
+ u32 mdio0usefpga;
+ u32 mdio1usefpga;
+ u32 mdio2usefpga;
+ u32 _pad_0x134c;
+ u32 jtagusefpga;
+ u32 sdmmcusefpga;
+ u32 hps_osc_clk;
+ u32 _pad_0x135c_0x13fc[41];
+ u32 iodelay0[40];
+ u32 _pad_0x14a0_0x14fc[24];
+ u32 iodelay40[8];
+
+};
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
+#define SYSMGR_ECC_OCRAM_EN BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR BIT(4)
+#define SYSMGR_FPGAINTF_USEFPGA 0x1
+
+#define SYSMGR_FPGAINTF_NAND BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC BIT(8)
+#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
+#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
+#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0)
+#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8)
+#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+
+#define SYSMGR_NOC_H2F_MSK 0x00000001
+#define SYSMGR_NOC_LWH2F_MSK 0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
+
+#define SYSMGR_DMA_IRQ_NS 0xFF000000
+#define SYSMGR_DMA_MGR_NS 0x00010000
+
+#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
+
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+
+#endif /* _SYSTEM_MANAGER_S10_ */
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+#endif
struct bsel bsel_str[] = {
{ "rsvd", "Reserved", },
#endif
}
+#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
/* Disable the L2 cache */
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
+#endif
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
return 0;
}
+
+#ifdef CONFIG_ETH_DESIGNWARE
+static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+ if (!phymode)
+ return -EINVAL;
+
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rgmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
+ const u8 phymode))
+{
+ const void *fdt = gd->fdt_blob;
+ struct fdtdec_phandle_args args;
+ const char *phy_mode;
+ u32 phy_modereg;
+ int nodes[2]; /* Max. two GMACs */
+ int ret, count;
+ int i, node;
+
+ count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+ COMPAT_ALTERA_SOCFPGA_DWMAC,
+ nodes, ARRAY_SIZE(nodes));
+ for (i = 0; i < count; i++) {
+ node = nodes[i];
+ if (node <= 0)
+ continue;
+
+ ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+ "#reset-cells", 1, 0,
+ &args);
+ if (ret || (args.args_count != 1)) {
+ debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+ continue;
+ }
+
+ phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+ ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+ if (ret) {
+ debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+ continue;
+ }
+
+ resetfn(args.args[0], phy_modereg);
+ }
+
+ return 0;
+}
+#endif
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
+static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
{
u32 reset;
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
+
+static int socfpga_eth_reset(void)
+{
+ /* Put all GMACs into RESET state. */
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
+ return socfpga_eth_reset_common(arria10_dwmac_reset);
+};
+#else
+static int socfpga_eth_reset(void)
+{
+ return 0;
+};
#endif
#if defined(CONFIG_SPL_BUILD)
/* assert reset to all except L4WD0 and L4TIMER0 */
socfpga_per_reset_all();
- /* configuring the clock based on handoff */
- /* TODO: Add call to cm_basic_init() */
-
- /* Add device descriptor to FPGA device table */
- socfpga_fpga_add();
return 0;
}
#else
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
- return 0;
+ return socfpga_eth_reset();
}
#endif
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
+static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
{
u32 physhift, reset;
socfpga_per_reset(reset, 0);
}
-static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- return 0;
- }
-
- if (!strcmp(phymode, "rgmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- return 0;
- }
-
- if (!strcmp(phymode, "rmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- return 0;
- }
-
- return -EINVAL;
-}
-
static int socfpga_eth_reset(void)
{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 phy_modereg;
- int nodes[2]; /* Max. two GMACs */
- int ret, count;
- int i, node;
-
- /* Put both GMACs into RESET state. */
+ /* Put all GMACs into RESET state. */
socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
- "#reset-cells", 1, 0,
- &args);
- if (ret || (args.args_count != 1)) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
-
- dwmac_deassert_reset(args.args[0], phy_modereg);
- }
-
- return 0;
-}
+ return socfpga_eth_reset_common(gen5_dwmac_reset);
+};
#else
static int socfpga_eth_reset(void)
{
setbits_le32(&scu_regs->sacr, 0xfff);
/* Configure the L2 controller to make SDRAM start at 0 */
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
- writel(0x2, &nic301_regs->remap);
-#else
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
-#endif
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#endif
/*
* Write the reset manager register to cause reset
void reset_cpu(ulong addr)
{
/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+ mbox_reset_cold();
+#else
writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
&reset_manager_base->ctrl);
+#endif
/*
* infinite loop here as watchdog will trigger and reset
* the processor
setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
}
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(void)
-{
- /* For SoCFPGA-VT, this is NOP. */
- return 0;
-}
-#else
int socfpga_bridges_reset(void)
{
int ret;
return 0;
}
-#endif
writel(0, &reset_manager_base->per_mod_reset);
}
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
- /* For SoCFPGA-VT, this is NOP. */
- return;
-}
-#else
-
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
}
return;
}
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+ const void *reg;
+
+ if (RSTMGR_BANK(reset) == 0)
+ reg = &reset_manager_base->mpumodrst;
+ else if (RSTMGR_BANK(reset) == 1)
+ reg = &reset_manager_base->per0modrst;
+ else if (RSTMGR_BANK(reset) == 2)
+ reg = &reset_manager_base->per1modrst;
+ else if (RSTMGR_BANK(reset) == 3)
+ reg = &reset_manager_base->brgmodrst;
+ else /* Invalid reset register, do nothing */
+ return;
+
+ if (set)
+ setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ else
+ clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+ const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+ /* disable all except OCP and l4wd0. OCP disable later */
+ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+ &reset_manager_base->per0modrst);
+ writel(~l4wd0, &reset_manager_base->per0modrst);
+ writel(0xffffffff, &reset_manager_base->per1modrst);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+ if (enable) {
+ /* clear idle request to all bridges */
+ setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+
+ /* Release bridges from reset state per handoff value */
+ clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+
+ /* Poll until all idleack to 0 */
+ while (readl(&system_manager_base->noc_idleack))
+ ;
+ } else {
+ /* set idle request to all bridges */
+ writel(~0, &system_manager_base->noc_idlereq_set);
+
+ /* Enable the NOC timeout */
+ writel(1, &system_manager_base->noc_timeout);
+
+ /* Poll until all idleack to 1 */
+ while ((readl(&system_manager_base->noc_idleack) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Poll until all idlestatus to 1 */
+ while ((readl(&system_manager_base->noc_idlestatus) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Put all bridges (except NOR DDR scheduler) into reset */
+ setbits_le32(&reset_manager_base->brgmodrst,
+ ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+
+ /* Disable NOC timeout */
+ writel(0, &system_manager_base->noc_timeout);
+ }
+}
+
+/* of_reset_id: emac reset id
+ * state: 0 - disable reset, !0 - enable reset
+ */
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
+{
+ u32 reset_emac;
+ u32 reset_emacocp;
+
+ /* hardcode this now */
+ switch (of_reset_id) {
+ case EMAC0_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC0);
+ reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
+ break;
+ case EMAC1_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC1);
+ reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
+ break;
+ case EMAC2_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC2);
+ reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
+ break;
+ default:
+ printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+ hang();
+ break;
+ }
+
+ /* Reset ECC OCP first */
+ socfpga_per_reset(reset_emacocp, state);
+
+ /* Release the EMAC controller from reset */
+ socfpga_per_reset(reset_emac, state);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, &reset_manager_base->per1modrst);
+ /* Enable OCP first */
+ writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
+ writel(0, &reset_manager_base->per0modrst);
+}
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/scu.h>
void board_init_f(ulong dummy)
{
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
unsigned long sdram_size;
unsigned long reg;
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
-#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
-#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
-
/* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
socfpga_bridges_reset(0);
/* enable console uart printing */
preloader_console_init();
+
+ WATCHDOG_RESET();
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
}
void board_init_f(ulong dummy)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+ populate_sysmgr_pinmux();
+ populate_sysmgr_fpgaintf_module();
+}
+
+/*
+ * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
+ * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
+ * CONFIG_SYSMGR_ISWGRP_HANDOFF.
+ */
+void populate_sysmgr_fpgaintf_module(void)
+{
+ u32 handoff_val = 0;
+
+ /* Enable the signal for those HPS peripherals that use FPGA. */
+ if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_NAND;
+ if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SDMMC;
+ if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM0;
+ if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_SPIM1;
+ writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+
+ handoff_val = 0;
+ if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC0;
+ if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC1;
+ if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ handoff_val |= SYSMGR_FPGAINTF_EMAC2;
+ writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+}
+
+/*
+ * Configure all the pin muxes
+ */
+void populate_sysmgr_pinmux(void)
+{
+ const u32 *sys_mgr_table_u32;
+ unsigned int len, i;
+
+ /* setup the pin sel */
+ sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
+ for (i = 0; i < len; i = i + 2) {
+ writel(sys_mgr_table_u32[i + 1],
+ sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+ }
+
+ /* setup the pin ctrl */
+ sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
+ for (i = 0; i < len; i = i + 2) {
+ writel(sys_mgr_table_u32[i + 1],
+ sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+ }
+
+ /* setup the fpga use */
+ sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
+ for (i = 0; i < len; i = i + 2) {
+ writel(sys_mgr_table_u32[i + 1],
+ sys_mgr_table_u32[i] +
+ (u8 *)&sysmgr_regs->rgmii0usefpga);
+ }
+
+ /* setup the IO delay */
+ sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
+ for (i = 0; i < len; i = i + 2) {
+ writel(sys_mgr_table_u32[i + 1],
+ sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+ }
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+static void sysmgr_pinmux_handoff_read(void *handoff_address,
+ const u32 **table,
+ unsigned int *table_len)
+{
+ unsigned int handoff_entry = (swab32(readl(handoff_address +
+ S10_HANDOFF_OFFSET_LENGTH)) -
+ S10_HANDOFF_OFFSET_DATA) /
+ sizeof(unsigned int);
+ unsigned int handoff_chunk[handoff_entry], temp, i;
+
+ if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) {
+ /* using handoff from Quartus tools if exists */
+ for (i = 0; i < handoff_entry; i++) {
+ temp = readl(handoff_address +
+ S10_HANDOFF_OFFSET_DATA + (i * 4));
+ handoff_chunk[i] = swab32(temp);
+ }
+ *table = handoff_chunk;
+ *table_len = ARRAY_SIZE(handoff_chunk);
+ }
+}
+
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len)
+{
+ sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table,
+ table_len);
+}
+
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len)
+{
+ sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table,
+ table_len);
+}
+
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len)
+{
+ sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table,
+ table_len);
+}
+
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len)
+{
+ sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table,
+ table_len);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+#include <asm/arch/system_manager.h>
+
+static const struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+const struct cm_config * const cm_get_default_config(void)
+{
+ struct cm_config *cm_handoff_cfg = (struct cm_config *)
+ (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
+ u32 *conversion = (u32 *)cm_handoff_cfg;
+ u32 i;
+ u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
+
+ if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
+ writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
+ for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+ conversion[i] = swab32(conversion[i]);
+ return cm_handoff_cfg;
+ } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
+ return cm_handoff_cfg;
+ }
+
+ return NULL;
+}
+
+const unsigned int cm_get_osc_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
+
+ writel(clock, &sysmgr_regs->boot_scratch_cold1);
+#endif
+ return readl(&sysmgr_regs->boot_scratch_cold1);
+}
+
+const unsigned int cm_get_intosc_clk_hz(void)
+{
+ return CLKMGR_INTOSC_HZ;
+}
+
+const unsigned int cm_get_fpga_clk_hz(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
+
+ writel(clock, &sysmgr_regs->boot_scratch_cold2);
+#endif
+ return readl(&sysmgr_regs->boot_scratch_cold2);
+}
source "board/st/stm32mp1/Kconfig"
+# currently activated for debug / should be deactivated for real product
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+ default y
+
+# debug on UART4 by default
+config DEBUG_UART_BASE
+ default 0x40010000
+
+# clock source is HSI on reset
+config DEBUG_UART_CLOCK
+ default 64000000
+endif
+
endif
-# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
obj-y += dram_init.o
obj-y += syscon.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += bsec.o
+endif
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+
+#define BSEC_OTP_MAX_VALUE 95
+
+#define BSEC_TIMEOUT_US 10000
+
+/* BSEC REGISTER OFFSET (base relative) */
+#define BSEC_OTP_CONF_OFF 0x000
+#define BSEC_OTP_CTRL_OFF 0x004
+#define BSEC_OTP_WRDATA_OFF 0x008
+#define BSEC_OTP_STATUS_OFF 0x00C
+#define BSEC_OTP_LOCK_OFF 0x010
+#define BSEC_DISTURBED_OFF 0x01C
+#define BSEC_ERROR_OFF 0x034
+#define BSEC_SPLOCK_OFF 0x064 /* Program safmem sticky lock */
+#define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */
+#define BSEC_SRLOCK_OFF 0x094 /* shadowing sticky lock */
+#define BSEC_OTP_DATA_OFF 0x200
+
+/* BSEC_CONFIGURATION Register MASK */
+#define BSEC_CONF_POWER_UP 0x001
+
+/* BSEC_CONTROL Register */
+#define BSEC_READ 0x000
+#define BSEC_WRITE 0x100
+
+/* LOCK Register */
+#define OTP_LOCK_MASK 0x1F
+#define OTP_LOCK_BANK_SHIFT 0x05
+#define OTP_LOCK_BIT_MASK 0x01
+
+/* STATUS Register */
+#define BSEC_MODE_BUSY_MASK 0x08
+#define BSEC_MODE_PROGFAIL_MASK 0x10
+#define BSEC_MODE_PWR_MASK 0x20
+
+/*
+ * OTP Lock services definition
+ * Value must corresponding to the bit number in the register
+ */
+#define BSEC_LOCK_PROGRAM 0x04
+
+/**
+ * bsec_check_error() - Check status of one otp
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: 0 if no error, -EAGAIN or -ENOTSUPP
+ */
+static u32 bsec_check_error(u32 base, u32 otp)
+{
+ u32 bit;
+ u32 bank;
+
+ bit = 1 << (otp & OTP_LOCK_MASK);
+ bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
+
+ if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
+ return -EAGAIN;
+ else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
+ return -ENOTSUPP;
+
+ return 0;
+}
+
+/**
+ * bsec_lock() - manage lock for each type SR/SP/SW
+ * @address: address of bsec IP register
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: true if locked else false
+ */
+static bool bsec_read_lock(u32 address, u32 otp)
+{
+ u32 bit;
+ u32 bank;
+
+ bit = 1 << (otp & OTP_LOCK_MASK);
+ bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
+
+ return !!(readl(address + bank) & bit);
+}
+
+/**
+ * bsec_read_SR_lock() - read SR lock (Shadowing)
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: true if locked else false
+ */
+static bool bsec_read_SR_lock(u32 base, u32 otp)
+{
+ return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
+}
+
+/**
+ * bsec_read_SP_lock() - read SP lock (program Lock)
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: true if locked else false
+ */
+static bool bsec_read_SP_lock(u32 base, u32 otp)
+{
+ return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
+}
+
+/**
+ * bsec_SW_lock() - manage SW lock (Write in Shadow)
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: true if locked else false
+ */
+static bool bsec_read_SW_lock(u32 base, u32 otp)
+{
+ return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
+}
+
+/**
+ * bsec_power_safmem() - Activate or deactivate safmem power
+ * @base: base address of bsec IP
+ * @power: true to power up , false to power down
+ * Return: 0 if succeed
+ */
+static int bsec_power_safmem(u32 base, bool power)
+{
+ u32 val;
+ u32 mask;
+
+ if (power) {
+ setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
+ mask = BSEC_MODE_PWR_MASK;
+ } else {
+ clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
+ mask = 0;
+ }
+
+ /* waiting loop */
+ return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
+ val, (val & BSEC_MODE_PWR_MASK) == mask,
+ BSEC_TIMEOUT_US);
+}
+
+/**
+ * bsec_shadow_register() - copy safmen otp to bsec data
+ * @base: base address of bsec IP
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: 0 if no error
+ */
+static int bsec_shadow_register(u32 base, u32 otp)
+{
+ u32 val;
+ int ret;
+ bool power_up = false;
+
+ /* check if shadowing of otp is locked */
+ if (bsec_read_SR_lock(base, otp))
+ pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp);
+
+ /* check if safemem is power up */
+ val = readl(base + BSEC_OTP_STATUS_OFF);
+ if (!(val & BSEC_MODE_PWR_MASK)) {
+ ret = bsec_power_safmem(base, true);
+ if (ret)
+ return ret;
+ power_up = 1;
+ }
+ /* set BSEC_OTP_CTRL_OFF with the otp value*/
+ writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);
+
+ /* check otp status*/
+ ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
+ val, (val & BSEC_MODE_BUSY_MASK) == 0,
+ BSEC_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = bsec_check_error(base, otp);
+
+ if (power_up)
+ bsec_power_safmem(base, false);
+
+ return ret;
+}
+
+/**
+ * bsec_read_shadow() - read an otp data value from shadow
+ * @base: base address of bsec IP
+ * @val: read value
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: 0 if no error
+ */
+static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
+{
+ *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
+
+ return bsec_check_error(base, otp);
+}
+
+/**
+ * bsec_write_shadow() - write value in BSEC data register in shadow
+ * @base: base address of bsec IP
+ * @val: value to write
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * Return: 0 if no error
+ */
+static int bsec_write_shadow(u32 base, u32 val, u32 otp)
+{
+ /* check if programming of otp is locked */
+ if (bsec_read_SW_lock(base, otp))
+ pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp);
+
+ writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
+
+ return bsec_check_error(base, otp);
+}
+
+/**
+ * bsec_program_otp() - program a bit in SAFMEM
+ * @base: base address of bsec IP
+ * @val: value to program
+ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
+ * after the function the otp data is not refreshed in shadow
+ * Return: 0 if no error
+ */
+static int bsec_program_otp(long base, u32 val, u32 otp)
+{
+ u32 ret;
+ bool power_up = false;
+
+ if (bsec_read_SP_lock(base, otp))
+ pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp);
+
+ if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
+ pr_debug("bsec : Global lock, prog will be ignore\n");
+
+ /* check if safemem is power up */
+ if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
+ ret = bsec_power_safmem(base, true);
+ if (ret)
+ return ret;
+
+ power_up = true;
+ }
+ /* set value in write register*/
+ writel(val, base + BSEC_OTP_WRDATA_OFF);
+
+ /* set BSEC_OTP_CTRL_OFF with the otp value */
+ writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
+
+ /* check otp status*/
+ ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
+ val, (val & BSEC_MODE_BUSY_MASK) == 0,
+ BSEC_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ if (val & BSEC_MODE_PROGFAIL_MASK)
+ ret = -EACCES;
+ else
+ ret = bsec_check_error(base, otp);
+
+ if (power_up)
+ bsec_power_safmem(base, false);
+
+ return ret;
+}
+
+/* BSEC MISC driver *******************************************************/
+struct stm32mp_bsec_platdata {
+ u32 base;
+};
+
+static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
+{
+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+ u32 tmp_data = 0;
+ int ret;
+
+ /* read current shadow value */
+ ret = bsec_read_shadow(plat->base, &tmp_data, otp);
+ if (ret)
+ return ret;
+
+ /* copy otp in shadow */
+ ret = bsec_shadow_register(plat->base, otp);
+ if (ret)
+ return ret;
+
+ ret = bsec_read_shadow(plat->base, val, otp);
+ if (ret)
+ return ret;
+
+ /* restore shadow value */
+ ret = bsec_write_shadow(plat->base, tmp_data, otp);
+ return ret;
+}
+
+static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
+{
+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+
+ return bsec_read_shadow(plat->base, val, otp);
+}
+
+static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
+{
+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+
+ return bsec_program_otp(plat->base, val, otp);
+}
+
+static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
+{
+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+
+ return bsec_write_shadow(plat->base, val, otp);
+}
+
+static int stm32mp_bsec_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ int ret;
+ int i;
+ bool shadow = true;
+ int nb_otp = size / sizeof(u32);
+ int otp;
+
+ if (offset >= STM32_BSEC_OTP_OFFSET) {
+ offset -= STM32_BSEC_OTP_OFFSET;
+ shadow = false;
+ }
+ otp = offset / sizeof(u32);
+
+ if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
+ dev_err(dev, "wrong value for otp, max value : %i\n",
+ BSEC_OTP_MAX_VALUE);
+ return -EINVAL;
+ }
+
+ for (i = otp; i < (otp + nb_otp); i++) {
+ u32 *addr = &((u32 *)buf)[i - otp];
+
+ if (shadow)
+ ret = stm32mp_bsec_read_shadow(dev, addr, i);
+ else
+ ret = stm32mp_bsec_read_otp(dev, addr, i);
+
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static int stm32mp_bsec_write(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ int ret = 0;
+ int i;
+ bool shadow = true;
+ int nb_otp = size / sizeof(u32);
+ int otp;
+
+ if (offset >= STM32_BSEC_OTP_OFFSET) {
+ offset -= STM32_BSEC_OTP_OFFSET;
+ shadow = false;
+ }
+ otp = offset / sizeof(u32);
+
+ if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) {
+ dev_err(dev, "wrong value for otp, max value : %d\n",
+ BSEC_OTP_MAX_VALUE);
+ return -EINVAL;
+ }
+
+ for (i = otp; i < otp + nb_otp; i++) {
+ u32 *val = &((u32 *)buf)[i - otp];
+
+ if (shadow)
+ ret = stm32mp_bsec_write_shadow(dev, *val, i);
+ else
+ ret = stm32mp_bsec_write_otp(dev, *val, i);
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static const struct misc_ops stm32mp_bsec_ops = {
+ .read = stm32mp_bsec_read,
+ .write = stm32mp_bsec_write,
+};
+
+static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
+{
+ struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
+
+ plat->base = (u32)dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id stm32mp_bsec_ids[] = {
+ { .compatible = "st,stm32mp-bsec" },
+ {}
+};
+
+U_BOOT_DRIVER(stm32mp_bsec) = {
+ .name = "stm32mp_bsec",
+ .id = UCLASS_MISC,
+ .of_match = stm32mp_bsec_ids,
+ .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
+ .ops = &stm32mp_bsec_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* bsec IP is not present in device tee, manage IP address by platdata */
+static struct stm32mp_bsec_platdata stm32_bsec_platdata = {
+ .base = STM32_BSEC_BASE,
+};
+
+U_BOOT_DEVICE(stm32mp_bsec) = {
+ .name = "stm32mp_bsec",
+ .platdata = &stm32_bsec_platdata,
+};
*/
#include <common.h>
#include <clk.h>
+#include <debug_uart.h>
+#include <environment.h>
+#include <misc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
#include <dm/uclass.h>
/* RCC register */
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
#define BOOTROM_INSTANCE_SHIFT 16
+/* BSEC OTP index */
+#define BSEC_OTP_SERIAL 13
+#define BSEC_OTP_MAC 57
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
static void security_init(void)
{
*/
int arch_cpu_init(void)
{
+ u32 boot_mode;
+
/* early armv7 timer init: needed for polling */
timer_init();
security_init();
#endif
+
/* get bootmode from BootRom context: saved in TAMP register */
- get_bootmode();
+ boot_mode = get_bootmode();
+
+ if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#if defined(CONFIG_DEBUG_UART) && \
+ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ else
+ debug_uart_init();
+#endif
return 0;
}
}
}
+/*
+ * If there is no MAC address in the environment, then it will be initialized
+ * (silently) from the value in the OTP.
+ */
+static int setup_mac_address(void)
+{
+#if defined(CONFIG_NET)
+ int ret;
+ int i;
+ u32 otp[2];
+ uchar enetaddr[6];
+ struct udevice *dev;
+
+ /* MAC already in environment */
+ if (eth_env_get_enetaddr("ethaddr", enetaddr))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+
+ ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
+ otp, sizeof(otp));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 6; i++)
+ enetaddr[i] = ((uint8_t *)&otp)[i];
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ pr_err("invalid MAC address in OTP %pM", enetaddr);
+ return -EINVAL;
+ }
+ pr_debug("OTP MAC address = %pM\n", enetaddr);
+ ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (!ret)
+ pr_err("Failed to set mac address %pM from OTP: %d\n",
+ enetaddr, ret);
+#endif
+
+ return 0;
+}
+
+static int setup_serial_number(void)
+{
+ char serial_string[25];
+ u32 otp[3] = {0, 0, 0 };
+ struct udevice *dev;
+ int ret;
+
+ if (env_get("serial#"))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+
+ ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
+ otp, sizeof(otp));
+ if (ret)
+ return ret;
+
+ sprintf(serial_string, "%08x%08x%08x", otp[0], otp[1], otp[2]);
+ env_set("serial#", serial_string);
+
+ return 0;
+}
+
int arch_misc_init(void)
{
setup_boot_mode();
+ setup_mac_address();
+ setup_serial_number();
return 0;
}
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_DBGMCU_BASE 0x50081000
+#define STM32_BSEC_BASE 0x5C005000
#define STM32_TZC_BASE 0x5C006000
#define STM32_ETZPC_BASE 0x5C007000
#define STM32_TAMP_BASE 0x5C00A000
+#ifdef CONFIG_DEBUG_UART_BASE
+/* hardcoded value can be only used for DEBUG UART */
+#define STM32_USART1_BASE 0x5C000000
+#define STM32_USART2_BASE 0x4000E000
+#define STM32_USART3_BASE 0x4000F000
+#define STM32_UART4_BASE 0x40010000
+#define STM32_UART5_BASE 0x40011000
+#define STM32_USART6_BASE 0x44003000
+#define STM32_UART7_BASE 0x40018000
+#define STM32_UART8_BASE 0x40019000
+#endif
+
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+/* offset used for BSEC driver: misc_read and misc_write */
+#define STM32_BSEC_SHADOW_OFFSET 0x0
+#define STM32_BSEC_OTP_OFFSET 0x80000000
+
#endif /* __ASSEMBLY__*/
#endif /* _MACH_STM32_H_ */
boot_mode = (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
TAMP_BOOT_MODE_SHIFT;
- clrsetbits_le32(TAMP_BOOT_CONTEXT,
- TAMP_BOOT_MODE_MASK,
- boot_mode << TAMP_BOOT_MODE_SHIFT);
switch (boot_mode) {
case BOOT_FLASH_SD_1:
char dtb_name[256];
int buf_len = sizeof(dtb_name);
- if (env_get("fdt_file"))
+ if (env_get("fdtfile"))
return 0; /* do nothing if it is already set */
compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL);
strncat(dtb_name, ".dtb", buf_len);
- return env_set("fdt_file", dtb_name);
+ return env_set("fdtfile", dtb_name);
}
int board_late_init(void)
prompt "Target select"
optional
-config TARGET_NX25_AE250
- bool "Support nx25-ae250"
+config TARGET_AX25_AE350
+ bool "Support ax25-ae350"
endchoice
-source "board/AndesTech/nx25-ae250/Kconfig"
+source "board/AndesTech/ax25-ae350/Kconfig"
choice
prompt "CPU selection"
ifdef CONFIG_32BIT
PLATFORM_LDFLAGS += -m $(32bit-emul)
+EFI_LDS := elf_riscv32_efi.lds
endif
ifdef CONFIG_64BIT
PLATFORM_LDFLAGS += -m $(64bit-emul)
+EFI_LDS := elf_riscv64_efi.lds
endif
CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
-T $(srctree)/examples/standalone/riscv.lds
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 -ffunction-sections
LDFLAGS_u-boot += --gc-sections -static -pie
+
+EFI_CRT0 := crt0_riscv_efi.o
+EFI_RELOC := reloc_riscv_efi.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+extra-y = start.o
+
+obj-y := cpu.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ /* turn off I/D-cache */
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+ panic("ax25-ae350 wdt not support yet.\n");
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Startup Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <elf.h>
+#include <asm/encoding.h>
+
+#ifdef CONFIG_32BIT
+#define LREG lw
+#define SREG sw
+#define REGBYTES 4
+#define RELOC_TYPE R_RISCV_32
+#define SYM_INDEX 0x8
+#define SYM_SIZE 0x10
+#else
+#define LREG ld
+#define SREG sd
+#define REGBYTES 8
+#define RELOC_TYPE R_RISCV_64
+#define SYM_INDEX 0x20
+#define SYM_SIZE 0x18
+#endif
+
+.section .text
+.globl _start
+_start:
+ j handle_reset
+
+nmi_vector:
+ j nmi_vector
+
+trap_vector:
+ j trap_entry
+
+.global trap_entry
+handle_reset:
+ li t0, CONFIG_SYS_SDRAM_BASE
+ SREG a2, 0(t0)
+ la t0, trap_entry
+ csrw mtvec, t0
+ csrwi mstatus, 0
+ csrwi mie, 0
+
+/*
+ * Do CPU critical regs init only at reboot,
+ * not when booting from ram
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ jal cpu_init_crit /* Do CPU critical regs init */
+#endif
+
+/*
+ * Set stackpointer in internal/ex RAM to call board_init_f
+ */
+call_board_init_f:
+ li t0, -16
+ li t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 /* force 16 byte alignment */
+
+#ifdef CONFIG_DEBUG_UART
+ jal debug_uart_init
+#endif
+
+call_board_init_f_0:
+ mv a0, sp
+ jal board_init_f_alloc_reserve
+ mv sp, a0
+ jal board_init_f_init_reserve
+
+ mv a0, zero /* a0 <-- boot_flags = 0 */
+ la t5, board_init_f
+ jr t5 /* jump to board_init_f() */
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl relocate_code
+relocate_code:
+ mv s2, a0 /* save addr_sp */
+ mv s3, a1 /* save addr of gd */
+ mv s4, a2 /* save addr of destination */
+
+/*
+ *Set up the stack
+ */
+stack_setup:
+ mv sp, s2
+ la t0, _start
+ sub t6, s4, t0 /* t6 <- relocation offset */
+ beq t0, s4, clear_bss /* skip relocation */
+
+ mv t1, s4 /* t1 <- scratch for copy_loop */
+ la t3, __bss_start
+ sub t3, t3, t0 /* t3 <- __bss_start_ofs */
+ add t2, t0, t3 /* t2 <- source end address */
+
+copy_loop:
+ LREG t5, 0(t0)
+ addi t0, t0, REGBYTES
+ SREG t5, 0(t1)
+ addi t1, t1, REGBYTES
+ blt t0, t2, copy_loop
+
+/*
+ * Update dynamic relocations after board_init_f
+ */
+fix_rela_dyn:
+ la t1, __rel_dyn_start
+ la t2, __rel_dyn_end
+ beq t1, t2, clear_bss
+ add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
+ add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
+
+/*
+ * skip first reserved entry: address, type, addend
+ */
+ bne t1, t2, 7f
+
+6:
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
+ bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
+ LREG t3, -(REGBYTES*3)(t1)
+ LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
+7:
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 6b
+
+8:
+ la t4, __dyn_sym_start
+ add t4, t4, t6
+
+9:
+ LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
+ andi t5, t5, 0xFF /* t5 <--- relocation type */
+ li t3, RELOC_TYPE
+ bne t5, t3, 10f /* skip non-addned entries */
+
+ LREG t3, -(REGBYTES*3)(t1)
+ li t5, SYM_SIZE
+ mul t0, t0, t5
+ add s1, t4, t0
+ LREG t5, REGBYTES(s1)
+ add t5, t5, t6 /* t5 <-- location to fix up in RAM */
+ add t3, t3, t6 /* t3 <-- location to fix up in RAM */
+ SREG t5, 0(t3)
+10:
+ addi t1, t1, (REGBYTES*3)
+ ble t1, t2, 9b
+
+/*
+ * trap update
+*/
+ la t0, trap_entry
+ add t0, t0, t6
+ csrw mtvec, t0
+
+clear_bss:
+ la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
+ add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
+ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
+ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
+ li t2, 0x00000000 /* clear */
+ beq t0, t1, call_board_init_r
+
+clbss_l:
+ SREG t2, 0(t0) /* clear loop... */
+ addi t0, t0, REGBYTES
+ bne t0, t1, clbss_l
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+ la t0, board_init_r
+ mv t4, t0 /* offset of board_init_r() */
+ add t4, t4, t6 /* real address of board_init_r() */
+/*
+ * setup parameters for board_init_r
+ */
+ mv a0, s3 /* gd_t */
+ mv a1, s4 /* dest_addr */
+
+/*
+ * jump to it ...
+ */
+ jr t4 /* jump to board_init_r() */
+
+/*
+ * trap entry
+ */
+trap_entry:
+ addi sp, sp, -32*REGBYTES
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
+
+/*
+ * Remain in M-mode after mret
+ */
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
+ addi sp, sp, 32*REGBYTES
+ mret
+
+#ifdef CONFIG_INIT_CRITICAL
+cpu_init_crit:
+ ret
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+ . = ALIGN(4);
+ .text :
+ {
+ arch/riscv/cpu/ax25/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ __global_pointer$ = . + 0x800;
+ *(.data*)
+ }
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got.plt) *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(efi_runtime_text)
+ *(efi_runtime_data)
+ __efi_runtime_stop = .;
+ }
+
+ .efi_runtime_rel : {
+ __efi_runtime_rel_start = .;
+ *(.relaefi_runtime_text)
+ *(.relaefi_runtime_data)
+ __efi_runtime_rel_stop = .;
+ }
+
+ . = ALIGN(4);
+
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rela*)
+ __rel_dyn_end = .;
+ }
+
+ . = ALIGN(4);
+
+ .dynsym : {
+ __dyn_sym_start = .;
+ *(.dynsym)
+ __dyn_sym_end = .;
+ }
+
+ . = ALIGN(4);
+
+ _end = .;
+
+ .bss : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017 Andes Technology Corporation
-# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-
-extra-y = start.o
-
-obj-y := cpu.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-/* CPU specific code */
-#include <common.h>
-#include <command.h>
-#include <watchdog.h>
-#include <asm/cache.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
- disable_interrupts();
-
- /* turn off I/D-cache */
-
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- panic("nx25-ae250 wdt not support yet.\n");
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Startup Code for RISC-V Core
- *
- * Copyright (c) 2017 Microsemi Corporation.
- * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
- *
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <common.h>
-#include <elf.h>
-#include <asm/encoding.h>
-
-#ifdef CONFIG_32BIT
-#define LREG lw
-#define SREG sw
-#define REGBYTES 4
-#define RELOC_TYPE R_RISCV_32
-#define SYM_INDEX 0x8
-#define SYM_SIZE 0x10
-#else
-#define LREG ld
-#define SREG sd
-#define REGBYTES 8
-#define RELOC_TYPE R_RISCV_64
-#define SYM_INDEX 0x20
-#define SYM_SIZE 0x18
-#endif
-
-.section .text
-.globl _start
-_start:
- j handle_reset
-
-nmi_vector:
- j nmi_vector
-
-trap_vector:
- j trap_entry
-
-.global trap_entry
-handle_reset:
- li t0, CONFIG_SYS_SDRAM_BASE
- SREG a2, 0(t0)
- la t0, trap_entry
- csrw mtvec, t0
- csrwi mstatus, 0
- csrwi mie, 0
-
-/*
- * Do CPU critical regs init only at reboot,
- * not when booting from ram
- */
-#ifdef CONFIG_INIT_CRITICAL
- jal cpu_init_crit /* Do CPU critical regs init */
-#endif
-
-/*
- * Set stackpointer in internal/ex RAM to call board_init_f
- */
-call_board_init_f:
- li t0, -16
- li t1, CONFIG_SYS_INIT_SP_ADDR
- and sp, t1, t0 /* force 16 byte alignment */
-
-#ifdef CONFIG_DEBUG_UART
- jal debug_uart_init
-#endif
-
-call_board_init_f_0:
- mv a0, sp
- jal board_init_f_alloc_reserve
- mv sp, a0
- jal board_init_f_init_reserve
-
- mv a0, zero /* a0 <-- boot_flags = 0 */
- la t5, board_init_f
- jr t5 /* jump to board_init_f() */
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-.globl relocate_code
-relocate_code:
- mv s2, a0 /* save addr_sp */
- mv s3, a1 /* save addr of gd */
- mv s4, a2 /* save addr of destination */
-
-/*
- *Set up the stack
- */
-stack_setup:
- mv sp, s2
- la t0, _start
- sub t6, s4, t0 /* t6 <- relocation offset */
- beq t0, s4, clear_bss /* skip relocation */
-
- mv t1, s4 /* t1 <- scratch for copy_loop */
- la t3, __bss_start
- sub t3, t3, t0 /* t3 <- __bss_start_ofs */
- add t2, t0, t3 /* t2 <- source end address */
-
-copy_loop:
- LREG t5, 0(t0)
- addi t0, t0, REGBYTES
- SREG t5, 0(t1)
- addi t1, t1, REGBYTES
- blt t0, t2, copy_loop
-
-/*
- * Update dynamic relocations after board_init_f
- */
-fix_rela_dyn:
- la t1, __rel_dyn_start
- la t2, __rel_dyn_end
- beq t1, t2, clear_bss
- add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
- add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
-
-/*
- * skip first reserved entry: address, type, addend
- */
- bne t1, t2, 7f
-
-6:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
- li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
- bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
- LREG t3, -(REGBYTES*3)(t1)
- LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
- add t5, t5, t6 /* t5 <-- location to fix up in RAM */
- add t3, t3, t6 /* t3 <-- location to fix up in RAM */
- SREG t5, 0(t3)
-7:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 6b
-
-8:
- la t4, __dyn_sym_start
- add t4, t4, t6
-
-9:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
- srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
- andi t5, t5, 0xFF /* t5 <--- relocation type */
- li t3, RELOC_TYPE
- bne t5, t3, 10f /* skip non-addned entries */
-
- LREG t3, -(REGBYTES*3)(t1)
- li t5, SYM_SIZE
- mul t0, t0, t5
- add s1, t4, t0
- LREG t5, REGBYTES(s1)
- add t5, t5, t6 /* t5 <-- location to fix up in RAM */
- add t3, t3, t6 /* t3 <-- location to fix up in RAM */
- SREG t5, 0(t3)
-10:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 9b
-
-/*
- * trap update
-*/
- la t0, trap_entry
- add t0, t0, t6
- csrw mtvec, t0
-
-clear_bss:
- la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
- add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
- la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
- add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
- li t2, 0x00000000 /* clear */
- beq t0, t1, call_board_init_r
-
-clbss_l:
- SREG t2, 0(t0) /* clear loop... */
- addi t0, t0, REGBYTES
- bne t0, t1, clbss_l
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-call_board_init_r:
- la t0, board_init_r
- mv t4, t0 /* offset of board_init_r() */
- add t4, t4, t6 /* real address of board_init_r() */
-/*
- * setup parameters for board_init_r
- */
- mv a0, s3 /* gd_t */
- mv a1, s4 /* dest_addr */
-
-/*
- * jump to it ...
- */
- jr t4 /* jump to board_init_r() */
-
-/*
- * trap entry
- */
-trap_entry:
- addi sp, sp, -32*REGBYTES
- SREG x1, 1*REGBYTES(sp)
- SREG x2, 2*REGBYTES(sp)
- SREG x3, 3*REGBYTES(sp)
- SREG x4, 4*REGBYTES(sp)
- SREG x5, 5*REGBYTES(sp)
- SREG x6, 6*REGBYTES(sp)
- SREG x7, 7*REGBYTES(sp)
- SREG x8, 8*REGBYTES(sp)
- SREG x9, 9*REGBYTES(sp)
- SREG x10, 10*REGBYTES(sp)
- SREG x11, 11*REGBYTES(sp)
- SREG x12, 12*REGBYTES(sp)
- SREG x13, 13*REGBYTES(sp)
- SREG x14, 14*REGBYTES(sp)
- SREG x15, 15*REGBYTES(sp)
- SREG x16, 16*REGBYTES(sp)
- SREG x17, 17*REGBYTES(sp)
- SREG x18, 18*REGBYTES(sp)
- SREG x19, 19*REGBYTES(sp)
- SREG x20, 20*REGBYTES(sp)
- SREG x21, 21*REGBYTES(sp)
- SREG x22, 22*REGBYTES(sp)
- SREG x23, 23*REGBYTES(sp)
- SREG x24, 24*REGBYTES(sp)
- SREG x25, 25*REGBYTES(sp)
- SREG x26, 26*REGBYTES(sp)
- SREG x27, 27*REGBYTES(sp)
- SREG x28, 28*REGBYTES(sp)
- SREG x29, 29*REGBYTES(sp)
- SREG x30, 30*REGBYTES(sp)
- SREG x31, 31*REGBYTES(sp)
- csrr a0, mcause
- csrr a1, mepc
- mv a2, sp
- jal handle_trap
- csrw mepc, a0
-
-/*
- * Remain in M-mode after mret
- */
- li t0, MSTATUS_MPP
- csrs mstatus, t0
- LREG x1, 1*REGBYTES(sp)
- LREG x2, 2*REGBYTES(sp)
- LREG x3, 3*REGBYTES(sp)
- LREG x4, 4*REGBYTES(sp)
- LREG x5, 5*REGBYTES(sp)
- LREG x6, 6*REGBYTES(sp)
- LREG x7, 7*REGBYTES(sp)
- LREG x8, 8*REGBYTES(sp)
- LREG x9, 9*REGBYTES(sp)
- LREG x10, 10*REGBYTES(sp)
- LREG x11, 11*REGBYTES(sp)
- LREG x12, 12*REGBYTES(sp)
- LREG x13, 13*REGBYTES(sp)
- LREG x14, 14*REGBYTES(sp)
- LREG x15, 15*REGBYTES(sp)
- LREG x16, 16*REGBYTES(sp)
- LREG x17, 17*REGBYTES(sp)
- LREG x18, 18*REGBYTES(sp)
- LREG x19, 19*REGBYTES(sp)
- LREG x20, 20*REGBYTES(sp)
- LREG x21, 21*REGBYTES(sp)
- LREG x22, 22*REGBYTES(sp)
- LREG x23, 23*REGBYTES(sp)
- LREG x24, 24*REGBYTES(sp)
- LREG x25, 25*REGBYTES(sp)
- LREG x26, 26*REGBYTES(sp)
- LREG x27, 27*REGBYTES(sp)
- LREG x28, 28*REGBYTES(sp)
- LREG x29, 29*REGBYTES(sp)
- LREG x30, 30*REGBYTES(sp)
- LREG x31, 31*REGBYTES(sp)
- addi sp, sp, 32*REGBYTES
- mret
-
-#ifdef CONFIG_INIT_CRITICAL
-cpu_init_crit:
- ret
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-OUTPUT_ARCH("riscv")
-ENTRY(_start)
-
-SECTIONS
-{
- . = ALIGN(4);
- .text :
- {
- arch/riscv/cpu/nx25/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- __global_pointer$ = . + 0x800;
- *(.data*)
- }
- . = ALIGN(4);
-
- .got : {
- __got_start = .;
- *(.got.plt) *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- /DISCARD/ : { *(.rela.plt*) }
- .rela.dyn : {
- __rel_dyn_start = .;
- *(.rela*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(4);
-
- .dynsym : {
- __dyn_sym_start = .;
- *(.dynsym)
- __dyn_sym_end = .;
- }
-
- . = ALIGN(4);
-
- _end = .;
-
- .bss : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
-}
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_NX25_AE250) += ae250.dtb
+dtb-$(CONFIG_TARGET_AX25_AE350) += ae350.dtb
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
+++ /dev/null
-/dts-v1/;
-/ {
- compatible = "riscv32 nx25";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- aliases {
- uart0 = &serial0;
- ethernet0 = &mac0;
- spi0 = &spi;
- } ;
-
- chosen {
- bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- tick-timer = &timer0;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>;
- };
-
- spiclk: virt_100mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "andestech,n13";
- reg = <0>;
- /* FIXME: to fill correct frqeuency */
- clock-frequency = <60000000>;
- };
- };
-
- intc: interrupt-controller {
- compatible = "andestech,atnointc010";
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- serial0: serial@f0300000 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0xf0300000 0x1000>;
- interrupts = <7 4>;
- clock-frequency = <19660800>;
- reg-shift = <2>;
- reg-offset = <32>;
- no-loopback-test = <1>;
- };
-
- timer0: timer@f0400000 {
- compatible = "andestech,atcpit100";
- reg = <0xf0400000 0x1000>;
- interrupts = <2 4>;
- clock-frequency = <40000000>;
- };
-
- mac0: mac@e0100000 {
- compatible = "andestech,atmac100";
- reg = <0xe0100000 0x1000>;
- interrupts = <25 4>;
- };
-
- mmc0: mmc@f0e00000 {
- compatible = "andestech,atsdc010";
- max-frequency = <100000000>;
- fifo-depth = <0x10>;
- reg = <0xf0e00000 0x1000>;
- interrupts = <17 4>;
- cap-sd-highspeed;
- };
-
- spi: spi@f0b00000 {
- compatible = "andestech,atcspi200";
- reg = <0xf0b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- num-cs = <1>;
- clocks = <&spiclk>;
- interrupts = <3 4>;
- flash@0 {
- compatible = "spi-flash";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-cpol;
- spi-cpha;
- };
- };
-
-};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "andestech,ax25";
+ model = "andestech,ax25";
+
+ aliases {
+ uart0 = &serial0;
+ spi0 = &spi;
+ } ;
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <10000000>;
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <60000000>;
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x40000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "andestech,riscv-ae350-soc";
+ ranges;
+ };
+
+ plmt0@e6000000 {
+ compatible = "riscv,plmt0";
+ interrupts-extended = <&CPU0_intc 7>;
+ reg = <0x0 0xe6000000 0x0 0x100000>;
+ };
+
+ plic0: interrupt-controller@e4000000 {
+ compatible = "riscv,plic0";
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x0 0xe4000000 0x0 0x2000000>;
+ riscv,ndev=<31>;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+ };
+
+ plic1: interrupt-controller@e6400000 {
+ compatible = "riscv,plic1";
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x0 0xe6400000 0x0 0x400000>;
+ riscv,ndev=<1>;
+ interrupts-extended = <&CPU0_intc 3>;
+ };
+
+ spiclk: virt_100mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0x0 0xf0400000 0x0 0x1000>;
+ clock-frequency = <40000000>;
+ interrupts = <3 4>;
+ interrupt-parent = <&plic0>;
+ };
+
+ serial0: serial@f0300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x0 0xf0300000 0x0 0x1000>;
+ interrupts = <9 4>;
+ clock-frequency = <19660800>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ interrupt-parent = <&plic0>;
+ };
+
+ mac0: mac@e0100000 {
+ compatible = "andestech,atmac100";
+ reg = <0x0 0xe0100000 0x0 0x1000>;
+ interrupts = <19 4>;
+ interrupt-parent = <&plic0>;
+ };
+
+ mmc0: mmc@f0e00000 {
+ compatible = "andestech,atfsdc010";
+ max-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ fifo-depth = <0x10>;
+ reg = <0x0 0xf0e00000 0x0 0x1000>;
+ interrupts = <18 4>;
+ cap-sd-highspeed;
+ interrupt-parent = <&plic0>;
+ };
+
+ smc0: smc@e0400000 {
+ compatible = "andestech,atfsmc020";
+ reg = <0x0 0xe0400000 0x0 0x1000>;
+ };
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0x0 0x88000000 0x0 0x1000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ spi: spi@f0b00000 {
+ compatible = "andestech,atcspi200";
+ reg = <0x0 0xf0b00000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ clocks = <&spiclk>;
+ interrupts = <3 4>;
+ interrupt-parent = <&plic0>;
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+};
extern unsigned int __machine_arch_type;
#endif
-#define MACH_TYPE_AE250 1
+#define MACH_TYPE_AE350 1
-#ifdef CONFIG_ARCH_AE250
+#ifdef CONFIG_ARCH_AE350
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
-# define machine_arch_type MACH_TYPE_AE250
+# define machine_arch_type MACH_TYPE_AE350
# endif
-# define machine_is_ae250() (machine_arch_type == MACH_TYPE_AE250)
+# define machine_is_ae350() (machine_arch_type == MACH_TYPE_AE350)
#else
-# define machine_is_ae250() (1)
+# define machine_is_ae350() (1)
#endif
#endif /* __ASM_RISCV_MACH_TYPE_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_ 1
+
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
+struct jmp_buf_data {
+ /* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */
+ unsigned long s_regs[12]; /* s0 - s11 */
+ unsigned long ra;
+ unsigned long sp;
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
+
+#endif /* _SETJMP_H_ */
/* board/.../... */
int board_init(void);
+void board_quiesce_devices(void);
#endif /* _U_BOOT_RISCV_H_ */
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-y += interrupts.o
+obj-y += setjmp.o
+
+# For building EFI apps
+CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
+
+CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
+
+extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
DECLARE_GLOBAL_DATA_PTR;
+__weak void board_quiesce_devices(void)
+{
+}
+
int arch_fixup_fdt(void *blob)
{
return 0;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * crt0-efi-riscv.S - PE/COFF header for RISC-V EFI applications
+ *
+ * Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ * Copright (C) 2018 Alexander Graf <agraf@suse.de>
+ *
+ * This file is inspired by arch/arm/lib/crt0_aarch64_efi.S
+ */
+
+#include <asm-generic/pe.h>
+
+#if __riscv_xlen == 64
+#define SIZE_LONG 8
+#define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp)
+#define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp)
+#define PE_MACHINE 0x5064
+#else
+#define SIZE_LONG 4
+#define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp)
+#define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp)
+#define PE_MACHINE 0x5032
+#endif
+
+
+ .section .text.head
+
+ /*
+ * Magic "MZ" signature for PE/COFF
+ */
+ .globl ImageBase
+ImageBase:
+ .ascii "MZ"
+ .skip 58 /* 'MZ' + pad + offset == 64 */
+ .long pe_header - ImageBase /* Offset to the PE header */
+pe_header:
+ .ascii "PE"
+ .short 0
+coff_header:
+ .short PE_MACHINE /* RISC-V 64/32-bit */
+ .short 2 /* nr_sections */
+ .long 0 /* TimeDateStamp */
+ .long 0 /* PointerToSymbolTable */
+ .long 1 /* NumberOfSymbols */
+ .short section_table - optional_header /* SizeOfOptionalHeader */
+ /*
+ * Characteristics: IMAGE_FILE_DEBUG_STRIPPED |
+ * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED
+ */
+ .short 0x206
+optional_header:
+ .short 0x20b /* PE32+ format */
+ .byte 0x02 /* MajorLinkerVersion */
+ .byte 0x14 /* MinorLinkerVersion */
+ .long _edata - _start /* SizeOfCode */
+ .long 0 /* SizeOfInitializedData */
+ .long 0 /* SizeOfUninitializedData */
+ .long _start - ImageBase /* AddressOfEntryPoint */
+ .long _start - ImageBase /* BaseOfCode */
+
+extra_header_fields:
+ .quad 0 /* ImageBase */
+ .long 0x20 /* SectionAlignment */
+ .long 0x8 /* FileAlignment */
+ .short 0 /* MajorOperatingSystemVersion */
+ .short 0 /* MinorOperatingSystemVersion */
+ .short 0 /* MajorImageVersion */
+ .short 0 /* MinorImageVersion */
+ .short 0 /* MajorSubsystemVersion */
+ .short 0 /* MinorSubsystemVersion */
+ .long 0 /* Win32VersionValue */
+
+ .long _edata - ImageBase /* SizeOfImage */
+
+ /*
+ * Everything before the kernel image is considered part of the header
+ */
+ .long _start - ImageBase /* SizeOfHeaders */
+ .long 0 /* CheckSum */
+ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
+ .short 0 /* DllCharacteristics */
+ .quad 0 /* SizeOfStackReserve */
+ .quad 0 /* SizeOfStackCommit */
+ .quad 0 /* SizeOfHeapReserve */
+ .quad 0 /* SizeOfHeapCommit */
+ .long 0 /* LoaderFlags */
+ .long 0x6 /* NumberOfRvaAndSizes */
+
+ .quad 0 /* ExportTable */
+ .quad 0 /* ImportTable */
+ .quad 0 /* ResourceTable */
+ .quad 0 /* ExceptionTable */
+ .quad 0 /* CertificationTable */
+ .quad 0 /* BaseRelocationTable */
+
+ /* Section table */
+section_table:
+
+ /*
+ * The EFI application loader requires a relocation section
+ * because EFI applications must be relocatable. This is a
+ * dummy section as far as we are concerned.
+ */
+ .ascii ".reloc"
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long 0
+ .long 0
+ .long 0 /* SizeOfRawData */
+ .long 0 /* PointerToRawData */
+ .long 0 /* PointerToRelocations */
+ .long 0 /* PointerToLineNumbers */
+ .short 0 /* NumberOfRelocations */
+ .short 0 /* NumberOfLineNumbers */
+ .long 0x42100040 /* Characteristics (section flags) */
+
+
+ .ascii ".text"
+ .byte 0
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long _edata - _start /* VirtualSize */
+ .long _start - ImageBase /* VirtualAddress */
+ .long _edata - _start /* SizeOfRawData */
+ .long _start - ImageBase /* PointerToRawData */
+
+ .long 0 /* PointerToRelocations (0 for executables) */
+ .long 0 /* PointerToLineNumbers (0 for executables) */
+ .short 0 /* NumberOfRelocations (0 for executables) */
+ .short 0 /* NumberOfLineNumbers (0 for executables) */
+ .long 0xe0500020 /* Characteristics (section flags) */
+
+_start:
+ addi sp, sp, -(SIZE_LONG * 3)
+ SAVE_LONG(a0, 0)
+ SAVE_LONG(a1, 1)
+ SAVE_LONG(ra, 2)
+
+ lla a0, ImageBase
+ lla a1, _DYNAMIC
+ call _relocate
+ bne a0, zero, 0f
+
+ LOAD_LONG(a1, 1)
+ LOAD_LONG(a0, 0)
+ call efi_main
+
+ LOAD_LONG(ra, 2)
+
+0: addi sp, sp, (SIZE_LONG * 3)
+ ret
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot riscv32 EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from arch/arm/lib/elf_aarch64_efi.lds
+ */
+
+OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+ .text 0x0 : {
+ _text = .;
+ *(.text.head)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.srodata)
+ *(.rodata*)
+ . = ALIGN(16);
+ }
+ _etext = .;
+ _text_size = . - _text;
+ .dynamic : { *(.dynamic) }
+ .data : {
+ _data = .;
+ *(.sdata)
+ *(.data)
+ *(.data1)
+ *(.data.*)
+ *(.got.plt)
+ *(.got)
+
+ /*
+ * The EFI loader doesn't seem to like a .bss section, so we
+ * stick it all into .data:
+ */
+ . = ALIGN(16);
+ _bss = .;
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(16);
+ _bss_end = .;
+ _edata = .;
+ }
+ .rela.dyn : { *(.rela.dyn) }
+ .rela.plt : { *(.rela.plt) }
+ .rela.got : { *(.rela.got) }
+ .rela.data : { *(.rela.data) *(.rela.data*) }
+ _data_size = . - _etext;
+
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ .note.gnu.build-id : { *(.note.gnu.build-id) }
+ /DISCARD/ : {
+ *(.rel.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+ .comment 0 : { *(.comment) }
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot riscv64 EFI linker script
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Modified from arch/arm/lib/elf_aarch64_efi.lds
+ */
+
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+ .text 0x0 : {
+ _text = .;
+ *(.text.head)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ *(.srodata)
+ *(.rodata*)
+ . = ALIGN(16);
+ }
+ _etext = .;
+ _text_size = . - _text;
+ .dynamic : { *(.dynamic) }
+ .data : {
+ _data = .;
+ *(.sdata)
+ *(.data)
+ *(.data1)
+ *(.data.*)
+ *(.got.plt)
+ *(.got)
+
+ /*
+ * The EFI loader doesn't seem to like a .bss section, so we
+ * stick it all into .data:
+ */
+ . = ALIGN(16);
+ _bss = .;
+ *(.sbss)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(16);
+ _bss_end = .;
+ _edata = .;
+ }
+ .rela.dyn : { *(.rela.dyn) }
+ .rela.plt : { *(.rela.plt) }
+ .rela.got : { *(.rela.got) }
+ .rela.data : { *(.rela.data) *(.rela.data*) }
+ _data_size = . - _etext;
+
+ . = ALIGN(4096);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(4096);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(4096);
+ .note.gnu.build-id : { *(.note.gnu.build-id) }
+ /DISCARD/ : {
+ *(.rel.reloc)
+ *(.eh_frame)
+ *(.note.GNU-stack)
+ }
+ .comment 0 : { *(.comment) }
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/* reloc_riscv.c - position independent ELF shared object relocator
+ Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+ Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ Copyright (C) 1999 Hewlett-Packard Co.
+ Contributed by David Mosberger <davidm@hpl.hp.com>.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials
+ provided with the distribution.
+ * Neither the name of Hewlett-Packard Co. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ SUCH DAMAGE.
+*/
+
+#include <efi.h>
+
+#include <elf.h>
+
+#if __riscv_xlen == 64
+#define Elf_Dyn Elf64_Dyn
+#define Elf_Rela Elf64_Rela
+#define ELF_R_TYPE ELF64_R_TYPE
+#else
+#define Elf_Dyn Elf32_Dyn
+#define Elf_Rela Elf32_Rela
+#define ELF_R_TYPE ELF32_R_TYPE
+#endif
+
+efi_status_t _relocate(long ldbase, Elf_Dyn *dyn, efi_handle_t image,
+ struct efi_system_table *systab)
+{
+ long relsz = 0, relent = 0;
+ Elf_Rela *rel = 0;
+ unsigned long *addr;
+ int i;
+
+ for (i = 0; dyn[i].d_tag != DT_NULL; ++i) {
+ switch (dyn[i].d_tag) {
+ case DT_RELA:
+ rel = (Elf_Rela *)((ulong)dyn[i].d_un.d_ptr + ldbase);
+ break;
+ case DT_RELASZ:
+ relsz = dyn[i].d_un.d_val;
+ break;
+ case DT_RELAENT:
+ relent = dyn[i].d_un.d_val;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (!rel && relent == 0)
+ return EFI_SUCCESS;
+
+ if (!rel || relent == 0)
+ return EFI_LOAD_ERROR;
+
+ while (relsz > 0) {
+ /* apply the relocs */
+ switch (ELF_R_TYPE(rel->r_info)) {
+ case R_RISCV_RELATIVE:
+ addr = (ulong *)(ldbase + rel->r_offset);
+ *addr = ldbase + rel->r_addend;
+ break;
+ default:
+ /* Panic */
+ while (1) ;
+ }
+ rel = (Elf_Rela *)((char *)rel + relent);
+ relsz -= relent;
+ }
+ return EFI_SUCCESS;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) 2018 Alexander Graf <agraf@suse.de>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#ifdef CONFIG_CPU_RISCV_64
+#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
+#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
+#else
+#define STORE_IDX(reg, idx) sw reg, (idx*4)(a0)
+#define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
+#endif
+
+.pushsection .text.setjmp, "ax"
+ENTRY(setjmp)
+ /* Preserve all callee-saved registers and the SP */
+ STORE_IDX(s0, 0)
+ STORE_IDX(s1, 1)
+ STORE_IDX(s2, 2)
+ STORE_IDX(s3, 3)
+ STORE_IDX(s4, 4)
+ STORE_IDX(s5, 5)
+ STORE_IDX(s6, 6)
+ STORE_IDX(s7, 7)
+ STORE_IDX(s8, 8)
+ STORE_IDX(s9, 9)
+ STORE_IDX(s10, 10)
+ STORE_IDX(s11, 11)
+ STORE_IDX(ra, 12)
+ STORE_IDX(sp, 13)
+ li a0, 0
+ ret
+ENDPROC(setjmp)
+.popsection
+
+.pushsection .text.longjmp, "ax"
+ENTRY(longjmp)
+ LOAD_IDX(s0, 0)
+ LOAD_IDX(s1, 1)
+ LOAD_IDX(s2, 2)
+ LOAD_IDX(s3, 3)
+ LOAD_IDX(s4, 4)
+ LOAD_IDX(s5, 5)
+ LOAD_IDX(s6, 6)
+ LOAD_IDX(s7, 7)
+ LOAD_IDX(s8, 8)
+ LOAD_IDX(s9, 9)
+ LOAD_IDX(s10, 10)
+ LOAD_IDX(s11, 11)
+ LOAD_IDX(ra, 12)
+ LOAD_IDX(sp, 13)
+
+ /* Move the return value in place, but return 1 if passed 0. */
+ beq a1, zero, longjmp_1
+ mv a0, a1
+ ret
+
+ longjmp_1:
+ li a0, 1
+ ret
+ENDPROC(longjmp)
+.popsection
sandbox_pmic: sandbox_pmic {
reg = <0x40>;
};
+
+ mc34708: pmic@41 {
+ reg = <0x41>;
+ };
};
lcd {
compatible = "google,sandbox-tpm";
};
+ tpm2 {
+ compatible = "sandbox,tpm2";
+ };
+
triangle {
compatible = "demo-shape";
colour = "cyan";
sandbox_pmic: sandbox_pmic {
reg = <0x40>;
};
+
+ mc34708: pmic@41 {
+ reg = <0x41>;
+ };
};
lcd {
compatible = "google,sandbox-tpm";
};
+ tpm2 {
+ compatible = "sandbox,tpm2";
+ };
+
triangle {
compatible = "demo-shape";
colour = "cyan";
regulator-max-microvolt = <1500000>;
};
};
+
+&mc34708 {
+ compatible = "fsl,mc34708";
+
+ pmic_emul {
+ compatible = "sandbox,i2c-pmic";
+
+ reg-defaults = /bits/ 8 <
+ 0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08
+ 0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18
+ 0x00 0x00 0x0e 0x00 0x00 0x14 0x00 0x00 0x00
+ 0x00 0x00 0x20 0x00 0x01 0x3a 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
+ 0x42 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x5f
+ 0x01 0xff 0xff 0x00 0x00 0x00 0x00 0x7f 0xff
+ 0x92 0x49 0x24 0x59 0x6d 0x34 0x18 0xc1 0x8c
+ 0x00 0x60 0x18 0x51 0x48 0x45 0x14 0x51 0x45
+ 0x00 0x06 0x32 0x00 0x00 0x00 0x06 0x9c 0x99
+ 0x00 0x38 0x0a 0x00 0x38 0x0a 0x00 0x38 0x0a
+ 0x00 0x38 0x0a 0x84 0x00 0x00 0x00 0x00 0x00
+ 0x80 0x90 0x8f 0xf8 0x00 0x04 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x01 0x31 0x7e 0x2b 0x03 0xfd 0xc0 0x36 0x1b
+ 0x60 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00
+ >;
+ };
+};
sandbox_pmic: sandbox_pmic {
reg = <0x40>;
};
+
+ mc34708: pmic@41 {
+ reg = <0x41>;
+ };
};
adc@0 {
clock-frequency = <1000000>;
};
+ tpm2 {
+ compatible = "sandbox,tpm2";
+ };
+
uart0: serial {
compatible = "sandbox,serial";
u-boot,dm-pre-reloc;
--- /dev/null
+if TARGET_AX25_AE350
+
+config SYS_CPU
+ default "ax25"
+
+config SYS_BOARD
+ default "ax25-ae350"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ae350"
+
+config SYS_CONFIG_NAME
+ default "ax25-ae350"
+
+config ENV_SIZE
+ default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x140000 if ENV_IS_IN_SPI_FLASH
+
+endif
--- /dev/null
+AX25-AE350 BOARD
+M: Rick Chen <rick@andestech.com>
+S: Maintained
+F: board/AndesTech/ax25-ae350/
+F: include/configs/ax25-ae350.h
+F: configs/ax25-ae350_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y := ax25-ae350.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <asm/mach-types.h>
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsmc020.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_AE350;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+ void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
+ if (fdt_magic(*ptr) == FDT_MAGIC)
+ return (void *)*ptr;
+
+ return (void *)CONFIG_SYS_FDT_BASE;
+}
+
+int smc_init(void)
+{
+ int node = -1;
+ const char *compat = "andestech,atfsmc020";
+ void *blob = (void *)gd->fdt_blob;
+ fdt_addr_t addr;
+ struct ftsmc020_bank *regs;
+
+ node = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (node < 0)
+ return -FDT_ERR_NOTFOUND;
+
+ addr = fdtdec_get_addr(blob, node, "reg");
+
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ regs = (struct ftsmc020_bank *)addr;
+ regs->cr &= ~FTSMC020_BANK_WPROT;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ smc_init();
+
+ return 0;
+}
+#endif
+++ /dev/null
-if TARGET_NX25_AE250
-
-config SYS_CPU
- default "nx25"
-
-config SYS_BOARD
- default "nx25-ae250"
-
-config SYS_VENDOR
- default "AndesTech"
-
-config SYS_SOC
- default "ae250"
-
-config SYS_CONFIG_NAME
- default "nx25-ae250"
-
-config ENV_SIZE
- default 0x2000 if ENV_IS_IN_SPI_FLASH
-
-config ENV_OFFSET
- default 0x140000 if ENV_IS_IN_SPI_FLASH
-
-endif
+++ /dev/null
-NX25-AE250 BOARD
-M: Rick Chen <rick@andestech.com>
-S: Maintained
-F: board/AndesTech/nx25-ae250/
-F: include/configs/nx25-ae250.h
-F: configs/nx25-ae250_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017 Andes Technology Corporation.
-# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-
-obj-y := nx25-ae250.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-#include <asm/mach-types.h>
-#include <common.h>
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-#include <netdev.h>
-#endif
-#include <linux/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initializations
- */
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_AE250;
- gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
-
- return 0;
-}
-
-int dram_init(void)
-{
- unsigned long sdram_base = PHYS_SDRAM_0;
- unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
- unsigned long actual_size;
-
- actual_size = get_ram_size((void *)sdram_base, expected_size);
- gd->ram_size = actual_size;
-
- if (expected_size != actual_size) {
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-int board_eth_init(bd_t *bd)
-{
- return ftmac100_initialize(bd);
-}
-#endif
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- return 0;
-}
-
-void *board_fdt_blob_setup(void)
-{
- void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
- if (fdt_magic(*ptr) == FDT_MAGIC)
- return (void *)*ptr;
-
- return (void *)CONFIG_SYS_FDT_BASE;
-}
--- /dev/null
+if TARGET_MX6DL_MAMOJ
+
+config SYS_BOARD
+ default "mamoj"
+
+config SYS_VENDOR
+ default "bticino"
+
+config SYS_CONFIG_NAME
+ default "imx6dl-mamoj"
+
+endif
--- /dev/null
+MX6DL_MAMOJ BOARD
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+M: Simone CIANNI <simone.cianni@bticino.it>
+S: Maintained
+F: board/bticino/mamoj
+F: include/configs/imx6dl-mamoj.h
+F: configs/imx6dl_mamoj_defconfig
+F: arch/arm/dts/imx6dl-mamoj.dts
+F: arch/arm/dts/imx6dl-mamoj-u-boot.dtsi
--- /dev/null
+# Copyright (C) 2018 BTicino
+# Copyright (C) 2017 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mamoj.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+BTicino Mamoj board:
+===================
+
+Build:
+
+ $ make mrproper
+ $ make imx6dl_mamoj_defconfig
+ $ make
+
+ This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+The following methods can be used for booting Mamoj boards:
+
+1. USB SDP boot
+
+2. eMMC boot (via DFU)
+
+3. Falcon mode
+
+1. USB SDP boot:
+---------------
+
+ - Build imx_usb_loader
+
+ $ git clone git://github.com/boundarydevices/imx_usb_loader.git
+ $ cd imx_usb_loader
+ $ make
+
+ - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory
+
+ - Put the board in "Serial Download Mode"
+
+ - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host
+
+ - Turn-on board
+
+ - Identify VID/PID using lsusb
+
+ Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode
+
+ - Update the conf files
+
+ imx_usb.conf
+ 0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf
+
+ mx6_usb_rom.conf
+ mx6_usb
+ hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+ SPL:jump header2
+
+ mx6_usb_sdp_spl.conf
+ mx6_spl_sdp
+ hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+ u-boot-dtb.img:jump header2
+
+ - Launch the loader
+
+ $ ./imx_usb
+
+ We can see U-Boot boot from USB SDP on minicom
+
+2. eMMC boot via DFU:
+--------------------
+
+ Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG)
+
+ - Change eMMC partition config
+
+ => mmc partconf 2 1 0 0
+
+ - Partition eMMC on host
+
+ => ums 0 mmc 2
+
+ Host will able to detect the eMMC disk as UMS, partition the same.
+
+ - Program SPL
+
+ => setenv dfu_alt_info $dfu_alt_info_spl
+ => dfu 0 mmc 2
+
+ At Host
+
+ # dfu-util -D SPL -a spl
+
+ - Program u-boot-dtb.img
+
+ => setenv dfu_alt_info $dfu_alt_info_uboot
+ => dfu 0 mmc 2
+
+ At Host
+
+ # dfu-util -D u-boot-dtb.img -a u-boot
+
+ Poweroff and Poweron the board and see U-Boot booting from eMMC.
+
+3. Falcon mode:
+--------------
+
+ - Skip 10M space and create dual partitions for eMMC, start sector is 20480
+
+ Partition Map for MMC device 2 -- Partition Type: DOS
+
+ Part Start Sector Num Sectors UUID Type
+ 1 20480 131072 c52e78be-01 83
+ 2 151552 7581696 c52e78be-02 83
+
+ - Write uImage
+
+ => fatload mmc 2:1 $kernel_addr_r uImage
+ => mmc write $kernel_addr_r 0x1000 0x4000
+
+ - Write dtb and args
+
+ => setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet
+ => fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb
+ => spl export fdt $kernel_addr_r - $fdt_addr_r
+ => mmc write 0x13000000 0x800 0x800
+
+ Poweroff and Poweron the board and see Linux booting directly after SPL.
+
+--
+Jagan Teki <jagan@amarulasolutions.com>
+03/12/18
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif
+
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 32,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0042004b,
+ .p0_mpwldectrl1 = 0x0038003c,
+ .p0_mpdgctrl0 = 0x42340230,
+ .p0_mpdgctrl1 = 0x0228022c,
+ .p0_mprddlctl = 0x42444646,
+ .p0_mpwrdlctl = 0x38382e2e,
+};
+
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 1,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+ .refsel = 1,
+ .refr = 7,
+};
+
+static void spl_dram_init(void)
+{
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
+
+ udelay(100);
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00003f3f, &ccm->CCGR0);
+ writel(0x0030fc00, &ccm->CCGR1);
+ writel(0x000fc000, &ccm->CCGR2);
+ writel(0x3f300000, &ccm->CCGR3);
+ writel(0xff00f300, &ccm->CCGR4);
+ writel(0x0f0000c3, &ccm->CCGR5);
+ writel(0x000003cc, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ SETUP_IOMUX_PADS(uart3_pads);
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
/* RAM */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
- .size = 0xc0000000UL,
+ .size = 255UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
F: configs/imx6qdl_icore_rqs_defconfig
F: configs/imx6qdl_icore_mipi_defconfig
F: configs/imx6qdl_icore_nand_defconfig
+F: arch/arm/dts/imx6qdl.dtsi
+F: arch/arm/dts/imx6qdl-u-boot.dtsi
F: arch/arm/dts/imx6qdl-icore.dtsi
+F: arch/arm/dts/imx6qdl-icore-u-boot.dtsi
F: arch/arm/dts/imx6q-icore.dts
+F: arch/arm/dts/imx6q-icore-u-boot.dtsi
F: arch/arm/dts/imx6dl-icore.dts
+F: arch/arm/dts/imx6dl-icore-u-boot.dtsi
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
+F: arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
+F: arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
F: arch/arm/dts/imx6dl-icore-rqs.dts
+F: arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
F: arch/arm/dts/imx6dl-icore-mipi.dts
+F: arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
F: arch/arm/dts/imx6q-icore-mipi.dts
-F: arch/arm/dts/imx6qdl-icore.dtsi
+F: arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi
F: configs/imx6ul_isiot_emmc_defconfig
F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_isiot_nand_defconfig
+F: arch/arm/dts/imx6ul.dtsi
+F: arch/arm/dts/imx6ul-u-boot.dtsi
F: arch/arm/dts/imx6ul-geam-kit.dts
+F: arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot.dtsi
+F: arch/arm/dts/imx6ul-isiot-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot-emmc.dts
+F: arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
F: arch/arm/dts/imx6ul-isiot-nand.dts
#include <common.h>
#include <dm.h>
#include <miiphy.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm-generic/gpio.h>
#include <fs.h>
#include <i2c.h>
#include <mmc.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
*/
#include <common.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <malloc.h>
#include <linux/ctype.h>
#include <asm/unaligned.h>
#include <fs.h>
#include <i2c.h>
#include <mmc.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
-if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+if TARGET_GE_BX50V3
config IMX_CONFIG
default "board/ge/bx50v3/bx50v3.cfg"
#include "../../../drivers/net/e1000.h"
DECLARE_GLOBAL_DATA_PTR;
+struct vpd_cache;
+
+static int confidx = 3; /* Default to b850v3. */
+static struct vpd_cache vpd;
+
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
return 0;
}
-static int detect_baseboard(struct display_info_t const *dev)
+static int is_b850v3(void)
{
- if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
- IS_ENABLED(CONFIG_TARGET_GE_B650V3))
- return 1;
+ return confidx == 3;
+}
- return 0;
+static int detect_lcd(struct display_info_t const *dev)
+{
+ return !is_b850v3();
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = -1,
.pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_baseboard,
+ .detect = detect_lcd,
.enable = NULL,
.mode = {
.name = "G121X1-L03",
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ enable_videopll();
+
/* When a reset/reboot is performed the display power needs to be turned
* off for atleast 500ms. The boot time is ~300ms, we need to wait for
* an additional 200ms here. Unfortunately we use external PMIC for
switch (vpd->product_id) {
case VPD_PRODUCT_B450:
env_set("confidx", "1");
+ i210_index = 0;
+ fec_index = 1;
break;
case VPD_PRODUCT_B650:
env_set("confidx", "2");
- break;
- case VPD_PRODUCT_B850:
- env_set("confidx", "3");
- break;
- }
-
- switch (vpd->product_id) {
- case VPD_PRODUCT_B450:
- /* fall thru */
- case VPD_PRODUCT_B650:
i210_index = 0;
fec_index = 1;
break;
case VPD_PRODUCT_B850:
+ env_set("confidx", "3");
i210_index = 1;
fec_index = 2;
break;
static int read_vpd(uint eeprom_bus)
{
- struct vpd_cache vpd;
int res;
int size = 1024;
uint8_t *data;
if (res == 0) {
memset(&vpd, 0, sizeof(vpd));
vpd_reader(size, data, &vpd, vpd_callback);
- process_vpd(&vpd);
}
free(data);
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ if (is_b850v3())
/* Set LDB clock to Video PLL */
select_ldb_di_clock_source(MXC_PLL5_CLK);
else
return 0;
}
+static void set_confidx(const struct vpd_cache* vpd)
+{
+ switch (vpd->product_id) {
+ case VPD_PRODUCT_B450:
+ confidx = 1;
+ break;
+ case VPD_PRODUCT_B650:
+ confidx = 2;
+ break;
+ case VPD_PRODUCT_B850:
+ confidx = 3;
+ break;
+ }
+}
+
int board_init(void)
{
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+ read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+
+ set_confidx(&vpd);
+
gpio_direction_output(SUS_S3_OUT, 1);
gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ if (is_b850v3())
setup_display_b850v3();
else
setup_display_bx50v3();
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
return 0;
}
int board_late_init(void)
{
- read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+ process_vpd(&vpd);
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+ if (is_b850v3())
+ env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
+
/* board specific pmic init */
pmic_init();
--- /dev/null
+if TARGET_KP_IMX53
+
+config SYS_BOARD
+ default "kp_imx53"
+
+config SYS_VENDOR
+ default "k+p"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "kp_imx53"
+
+endif
--- /dev/null
+KP_IMX53_HSC BOARD
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+F: board/k+p/kp_imx53/
+F: include/configs/kp_imx53.h
+F: configs/kp_imx53_defconfig
--- /dev/null
+#
+# Copyright (C) 2018, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += kp_imx53.o kp_id_rev.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <i2c.h>
+#include "kp_id_rev.h"
+
+static int eeprom_has_been_read;
+static struct id_eeprom eeprom;
+
+void show_eeprom(void)
+{
+ char safe_string[33];
+ int i;
+ u8 *p;
+
+ puts("Module EEPROM:\n");
+ /* ID */
+ for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i)
+ safe_string[i] = eeprom.id[i];
+ safe_string[i] = '\0';
+
+ if (!strncmp(safe_string, "TQM", 3)) {
+ printf(" ID: %s\n", safe_string);
+ env_set("boardtype", safe_string);
+ } else {
+ puts(" unknown hardware variant\n");
+ }
+
+ /* Serial number */
+ for (i = 0; (sizeof(eeprom.serial) >= i) &&
+ (eeprom.serial[i] >= 0x30) &&
+ (eeprom.serial[i] <= 0x39); ++i)
+ safe_string[i] = eeprom.serial[i];
+ safe_string[i] = '\0';
+
+ if (strlen(safe_string) == 8) {
+ printf(" SN: %s\n", safe_string);
+ env_set("serial#", safe_string);
+ } else {
+ puts(" unknown serial number\n");
+ }
+
+ /* MAC address */
+ p = eeprom.mac;
+ if (!is_valid_ethaddr(p)) {
+ printf(" Not valid ETH EEPROM addr!\n");
+ return;
+ }
+
+ printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ eth_env_set_enetaddr("ethaddr", p);
+}
+
+int read_eeprom(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (eeprom_has_been_read)
+ return 0;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+ if (ret) {
+ printf("Cannot find EEPROM !\n");
+ return ret;
+ }
+
+ ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom));
+
+ eeprom_has_been_read = (ret == 0) ? 1 : 0;
+ return ret;
+}
+
+int read_board_id(void)
+{
+ unsigned char rev_id = 0x42;
+ char rev_str[32], buf[8];
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev);
+ if (ret) {
+ printf("Cannot find pcf8574 IO expander !\n");
+ return ret;
+ }
+
+ dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id));
+
+ sprintf(rev_str, "%02X", rev_id);
+ if (rev_id & 0x80) {
+ printf("BBoard:4x00 Rev:%s\n", rev_str);
+ env_set("boardtype", "ddc");
+ env_set("fit_config", "imx53_kb_conf");
+ } else {
+ printf("BBoard:40x0 Rev:%s\n", rev_str);
+ env_set("boardtype", "hsc");
+ env_set("fit_config", "imx53_kb_40x0_conf");
+ }
+
+ sprintf(buf, "kp-%s", env_get("boardtype"));
+ env_set("boardname", buf);
+ env_set("boardsoc", "imx53");
+ env_set("kb53_rev", rev_str);
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ */
+
+#ifndef __KP_ID_REV_H_
+#define __KP_ID_REV_H_
+
+struct id_eeprom {
+ u8 hrcw_primary[0x20];
+ u8 mac[6]; /* 0x20 ... 0x25 */
+ u8 rsv1[10];
+ u8 serial[8]; /* 0x30 ... 0x37 */
+ u8 rsv2[8];
+ u8 id[0x40]; /* 0x40 ... 0x7f */
+} __packed;
+
+void show_eeprom(void);
+int read_eeprom(void);
+int read_board_id(void);
+#endif /* __KP_ID_REV_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include "kp_id_rev.h"
+
+#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
+#define PHY_nRST IMX_GPIO_NR(7, 6)
+#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ u32 size;
+
+ size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ gd->ram_size = size;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ int rev = readl(&fuse->gp[6]);
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
+ gpio_direction_output(VBUS_PWR_EN, 1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[] = {
+ {MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* eMMC is always present */
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ static const iomux_v3_cfg_t sd3_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ };
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+static int power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("mc34708", &dev);
+ if (ret) {
+ printf("%s: mc34708 not found !\n", __func__);
+ return ret;
+ }
+
+ /* Set VDDGP to 1.110V for 800 MHz on SW1 */
+ pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
+ SWx_1_110V_MC34708);
+
+ /* Set VCC as 1.30V on SW2 */
+ pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
+ SWx_1_300V_MC34708);
+
+ /* Set global reset timer to 4s */
+ pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
+ TIMER_4S_MC34708);
+
+ return ret;
+}
+
+static void setup_clocks(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * CPU clock set to 800MHz and DDR to 400MHz
+ */
+ ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to 800MHZ failed\n");
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+}
+
+static void setup_ups(void)
+{
+ gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
+ gpio_direction_output(BOOSTER_OFF, 0);
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+void eth_phy_reset(void)
+{
+ gpio_request(PHY_nRST, "PHY_nRST");
+ gpio_direction_output(PHY_nRST, 1);
+ udelay(50);
+ gpio_set_value(PHY_nRST, 0);
+ udelay(400);
+ gpio_set_value(PHY_nRST, 1);
+ udelay(50);
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+
+ setup_ups();
+
+ if (!power_init())
+ setup_clocks();
+
+ ret = read_eeprom();
+ if (ret)
+ printf("Error %d reading EEPROM content!\n", ret);
+
+ eth_phy_reset();
+
+ show_eeprom();
+ read_board_id();
+
+ return ret;
+}
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := blanche.o qos.o ../rcar-common/common.o
+obj-y := blanche.o qos.o
*/
#include <common.h>
-#include <malloc.h>
-#include <netdev.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sh_sdhi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <environment.h>
-#include <asm/processor.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
+#include <i2c.h>
#include <linux/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/sh_sdhi.h>
+#include <malloc.h>
#include <miiphy.h>
-#include <i2c.h>
#include <mmc.h>
+#include <netdev.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
-struct pin_db {
- u32 addr; /* register address */
- u32 mask; /* mask value */
- u32 val; /* setting value */
-};
-
-#define PMMR 0xE6060000
-#define GPSR0 0xE6060004
-#define GPSR1 0xE6060008
-#define GPSR4 0xE6060014
-#define GPSR5 0xE6060018
-#define GPSR6 0xE606001C
-#define GPSR7 0xE6060020
-#define GPSR8 0xE6060024
-#define GPSR9 0xE6060028
-#define GPSR10 0xE606002C
-#define GPSR11 0xE6060030
-#define IPSR6 0xE6060058
-#define PUPR2 0xE6060108
-#define PUPR3 0xE606010C
-#define PUPR4 0xE6060110
-#define PUPR5 0xE6060114
-#define PUPR7 0xE606011C
-#define PUPR9 0xE6060124
-#define PUPR10 0xE6060128
-#define PUPR11 0xE606012C
-
#define CPG_PLL1CR 0xE6150028
#define CPG_PLL3CR 0xE61500DC
-#define SetREG(x) \
- writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
-
-#define SetGuardREG(x) \
-{ \
- u32 val; \
- val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
- writel(~val, PMMR); \
- writel(val, (x)->addr); \
-}
-
-struct pin_db pin_guard[] = {
- { GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
- { GPSR1, 0xFFFFFFFF, 0x002FFFFF },
- { GPSR4, 0xFFFFFFFF, 0x00000FFF },
- { GPSR5, 0xFFFFFFFF, 0x00010FFF },
- { GPSR6, 0xFFFFFFFF, 0x00010FFF },
- { GPSR7, 0xFFFFFFFF, 0x00010FFF },
- { GPSR8, 0xFFFFFFFF, 0x00010FFF },
- { GPSR9, 0xFFFFFFFF, 0x00010FFF },
- { GPSR10, 0xFFFFFFFF, 0x04006000 },
- { GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
- { IPSR6, 0xFFFFFFFF, 0x0002000E },
-};
+#define TMU0_MSTP125 BIT(25)
+#define QSPI_MSTP917 BIT(17)
-struct pin_db pin_tbl[] = {
- { PUPR2, 0xFFFFFFFF, 0x00000000 },
- { PUPR3, 0xFFFFFFFF, 0x0803FF40 },
- { PUPR4, 0xFFFFFFFF, 0x0000FFFF },
- { PUPR5, 0xFFFFFFFF, 0x00010FFF },
- { PUPR7, 0xFFFFFFFF, 0x0001AFFF },
- { PUPR9, 0xFFFFFFFF, 0x0001CFFF },
- { PUPR10, 0xFFFFFFFF, 0xC0438001 },
- { PUPR11, 0xFFFFFFFF, 0x0FC00007 },
+struct reg_config {
+ u16 off;
+ u32 val;
};
-void pin_init(void)
-{
- struct pin_db *db;
-
- for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
- SetGuardREG(db);
- }
- for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
- SetREG(db);
- }
-}
-
-#define s_init_wait(cnt) \
- ({ \
- volatile u32 i = 0x10000 * cnt; \
- while (i > 0) \
- i--; \
- })
-
-void s_init(void)
+static void blanche_init_sys(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
+}
- /* QoS(Quality-of-Service) Init */
- qos_init();
+static void blanche_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0004, 0x0bffffff },
+ { 0x0008, 0x002fffff },
+ { 0x0014, 0x00000fff },
+ { 0x0018, 0x00010fff },
+ { 0x001c, 0x00010fff },
+ { 0x0020, 0x00010fff },
+ { 0x0024, 0x00010fff },
+ { 0x0028, 0x00010fff },
+ { 0x002c, 0x04006000 },
+ { 0x0030, 0x303fefe0 },
+ { 0x0058, 0x0002000e },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0108, 0x00000000 },
+ { 0x010c, 0x0803FF40 },
+ { 0x0110, 0x0000FFFF },
+ { 0x0114, 0x00010FFF },
+ { 0x011c, 0x0001AFFF },
+ { 0x0124, 0x0001CFFF },
+ { 0x0128, 0xC0438001 },
+ { 0x012c, 0x0FC00007 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
- /* SCIF Init */
- pin_init();
+static void blanche_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0x19102110 },
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+}
#if defined(CONFIG_MTD_NOR_FLASH)
- struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
- struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
- /* LBSC */
- writel(0x00000020, &lbsc->cs0ctrl);
- writel(0x00000020, &lbsc->cs1ctrl);
- writel(0x00002020, &lbsc->ecs0ctrl);
- writel(0x00002020, &lbsc->ecs1ctrl);
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
- writel(0x2A103320, &lbsc->cswcr0);
- writel(0x2A103320, &lbsc->cswcr1);
- writel(0x19102110, &lbsc->ecswcr0);
- writel(0x19102110, &lbsc->ecswcr1);
+static void blanche_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0280, 0x0000a55a },
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0001c000 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181ee4 },
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000008d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000300 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082004 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c4e1 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcdb60 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000004 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
- /* DBSC3 */
- s_init_wait(10);
+}
- writel(0x0000A55A, &dbsc3_0->dbpdlck);
-
- writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
- writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
- writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
-
- /* Stop Auto-Calibration */
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x80000000, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
-
- /* PLLCR: PLL Control Register */
- writel(0x00000006, &dbsc3_0->dbpdrga);
- writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
-
- /* DXCCR: DATX8 Common Configuration Register */
- writel(0x0000000F, &dbsc3_0->dbpdrga);
- writel(0x00181EE4, &dbsc3_0->dbpdrgd);
-
- /* DSGCR :DDR System General Configuration Register */
- writel(0x00000010, &dbsc3_0->dbpdrga);
- writel(0xF00464DB, &dbsc3_0->dbpdrgd);
-
- writel(0x00000061, &dbsc3_0->dbpdrga);
- writel(0x0000008D, &dbsc3_0->dbpdrgd);
-
- /* Re-Execute ZQ calibration */
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000073, &dbsc3_0->dbpdrgd);
-
- writel(0x00000007, &dbsc3_0->dbkind);
- writel(0x0F030A02, &dbsc3_0->dbconf0);
- writel(0x00000001, &dbsc3_0->dbphytype);
- writel(0x00000000, &dbsc3_0->dbbl);
-
- writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
- writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
- writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
- writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
- writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
- writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
- writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
- writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
- writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
- writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
- writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
- writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
- writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
- writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
- writel(0x00140005, &dbsc3_0->dbtr14);
- writel(0x00050004, &dbsc3_0->dbtr15);
- writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
- writel(0x000C0000, &dbsc3_0->dbtr17);
- writel(0x00000300, &dbsc3_0->dbtr18);
- writel(0x00000040, &dbsc3_0->dbtr19);
- writel(0x00000001, &dbsc3_0->dbrnk0);
- writel(0x00020001, &dbsc3_0->dbadj0);
- writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
- writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
- writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
-
- while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
- writel(0x00000011, &dbsc3_0->dbdficnt);
-
- /* PGCR1 :PHY General Configuration Register 1 */
- writel(0x00000003, &dbsc3_0->dbpdrga);
- writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
-
- /* PGCR2: PHY General Configuration Registers 2 */
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
-
- writel(0x00000011, &dbsc3_0->dbpdrga);
- writel(0x1000040B, &dbsc3_0->dbpdrgd);
-
- /* DTPR0 :DRAM Timing Parameters Register 0 */
- writel(0x00000012, &dbsc3_0->dbpdrga);
- writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
-
- /* DTPR1 :DRAM Timing Parameters Register 1 */
- writel(0x00000013, &dbsc3_0->dbpdrga);
- writel(0x1A868400, &dbsc3_0->dbpdrgd);
-
- /* DTPR2 ::DRAM Timing Parameters Register 2 */
- writel(0x00000014, &dbsc3_0->dbpdrga);
- writel(0x300214D8, &dbsc3_0->dbpdrgd);
-
- /* MR0 :Mode Register 0 */
- writel(0x00000015, &dbsc3_0->dbpdrga);
- writel(0x00000D70, &dbsc3_0->dbpdrgd);
-
- /* MR1 :Mode Register 1 */
- writel(0x00000016, &dbsc3_0->dbpdrga);
- writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
-
- /* MR2 :Mode Register 2 */
- writel(0x00000017, &dbsc3_0->dbpdrga);
- writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
-
- /* VREF(ZQCAL) */
- writel(0x0000001A, &dbsc3_0->dbpdrga);
- writel(0x910035C7, &dbsc3_0->dbpdrgd);
-
- /* PGSR0 :PHY General Status Registers 0 */
- writel(0x00000004, &dbsc3_0->dbpdrga);
- while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
-
- /* DRAM Init (set MRx etc) */
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000181, &dbsc3_0->dbpdrgd);
-
- /* CKE = H */
- writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
-
- /* PGSR0 :PHY General Status Registers 0 */
- writel(0x00000004, &dbsc3_0->dbpdrga);
- while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
-
- /* RAM ACC Training */
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x0000FE01, &dbsc3_0->dbpdrgd);
-
- /* Bus control 0 */
- writel(0x00000000, &dbsc3_0->dbbs0cnt1);
- /* DDR3 Calibration set */
- writel(0x01004C20, &dbsc3_0->dbcalcnf);
- /* DDR3 Calibration timing */
- writel(0x014000AA, &dbsc3_0->dbcaltr);
- /* Refresh */
- writel(0x00000140, &dbsc3_0->dbrfcnf0);
- writel(0x00081860, &dbsc3_0->dbrfcnf1);
- writel(0x00010000, &dbsc3_0->dbrfcnf2);
-
- /* PGSR0 :PHY General Status Registers 0 */
- writel(0x00000004, &dbsc3_0->dbpdrga);
- while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
-
- /* Enable Auto-Refresh */
- writel(0x00000001, &dbsc3_0->dbrfen);
- /* Permit DDR-Access */
- writel(0x00000001, &dbsc3_0->dbacen);
-
- /* This locks the access to the PHY unit registers */
- writel(0x00000000, &dbsc3_0->dbpdlck);
-#endif /* CONFIG_MTD_NOR_FLASH */
+static void s_init_wait(volatile unsigned int cnt)
+{
+ volatile u32 i = cnt * 0x10000;
+ while (i-- > 0)
+ ;
}
+#endif
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define SDHI0_MSTP314 (1 << 14)
-#define QSPI_MSTP917 (1 << 17)
+void s_init(void)
+{
+ blanche_init_sys();
+ qos_init();
+ blanche_init_pfc();
+ blanche_init_lbsc();
+#if defined(CONFIG_MTD_NOR_FLASH)
+ s_init_wait(10);
+ blanche_init_dbsc();
+#endif /* CONFIG_MTD_NOR_FLASH */
+}
int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
- /* SDHI0 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
/* QSPI */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
return 0;
}
-DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7792_pinmux_init();
-
- gpio_request(GPIO_FN_D0, NULL);
- gpio_request(GPIO_FN_D1, NULL);
- gpio_request(GPIO_FN_D2, NULL);
- gpio_request(GPIO_FN_D3, NULL);
- gpio_request(GPIO_FN_D4, NULL);
- gpio_request(GPIO_FN_D5, NULL);
- gpio_request(GPIO_FN_D6, NULL);
- gpio_request(GPIO_FN_D7, NULL);
- gpio_request(GPIO_FN_D8, NULL);
- gpio_request(GPIO_FN_D9, NULL);
- gpio_request(GPIO_FN_D10, NULL);
- gpio_request(GPIO_FN_D11, NULL);
- gpio_request(GPIO_FN_D12, NULL);
- gpio_request(GPIO_FN_D13, NULL);
- gpio_request(GPIO_FN_D14, NULL);
- gpio_request(GPIO_FN_D15, NULL);
- gpio_request(GPIO_FN_A0, NULL);
- gpio_request(GPIO_FN_A1, NULL);
- gpio_request(GPIO_FN_A2, NULL);
- gpio_request(GPIO_FN_A3, NULL);
- gpio_request(GPIO_FN_A4, NULL);
- gpio_request(GPIO_FN_A5, NULL);
- gpio_request(GPIO_FN_A6, NULL);
- gpio_request(GPIO_FN_A7, NULL);
- gpio_request(GPIO_FN_A8, NULL);
- gpio_request(GPIO_FN_A9, NULL);
- gpio_request(GPIO_FN_A10, NULL);
- gpio_request(GPIO_FN_A11, NULL);
- gpio_request(GPIO_FN_A12, NULL);
- gpio_request(GPIO_FN_A13, NULL);
- gpio_request(GPIO_FN_A14, NULL);
- gpio_request(GPIO_FN_A15, NULL);
- gpio_request(GPIO_FN_A16, NULL);
- gpio_request(GPIO_FN_A17, NULL);
- gpio_request(GPIO_FN_A18, NULL);
- gpio_request(GPIO_FN_A19, NULL);
-#if !defined(CONFIG_MTD_NOR_FLASH)
- gpio_request(GPIO_FN_MOSI_IO0, NULL);
- gpio_request(GPIO_FN_MISO_IO1, NULL);
- gpio_request(GPIO_FN_IO2, NULL);
- gpio_request(GPIO_FN_IO3, NULL);
- gpio_request(GPIO_FN_SPCLK, NULL);
- gpio_request(GPIO_FN_SSL, NULL);
-#else /* CONFIG_MTD_NOR_FLASH */
- gpio_request(GPIO_FN_A20, NULL);
- gpio_request(GPIO_FN_A21, NULL);
- gpio_request(GPIO_FN_A22, NULL);
- gpio_request(GPIO_FN_A23, NULL);
- gpio_request(GPIO_FN_A24, NULL);
- gpio_request(GPIO_FN_A25, NULL);
-#endif /* CONFIG_MTD_NOR_FLASH */
-
- gpio_request(GPIO_FN_CS1_A26, NULL);
- gpio_request(GPIO_FN_EX_CS0, NULL);
- gpio_request(GPIO_FN_EX_CS1, NULL);
- gpio_request(GPIO_FN_BS, NULL);
- gpio_request(GPIO_FN_RD, NULL);
- gpio_request(GPIO_FN_WE0, NULL);
- gpio_request(GPIO_FN_WE1, NULL);
- gpio_request(GPIO_FN_EX_WAIT0, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
- gpio_request(GPIO_FN_IRQ2, NULL);
- gpio_request(GPIO_FN_IRQ3, NULL);
- gpio_request(GPIO_FN_CS0, NULL);
-
- /* Init timer */
- timer_init();
-
return 0;
}
-/*
- Added for BLANCHE(R-CarV2H board)
-*/
+/* Added for BLANCHE(R-CarV2H board) */
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
-#define STR_ENV_ETHADDR "ethaddr"
-
struct eth_device *dev;
uchar eth_addr[6];
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
dev = eth_get_dev_by_index(0);
if (dev) {
- eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ eth_env_set_enetaddr("ethaddr", dev->enetaddr);
} else {
printf("blanche: Couldn't get eth device\n");
rc = -1;
return rc;
}
-int board_mmc_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
-
- gpio_request(GPIO_GP_11_12, NULL);
- gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
-
- if (ret)
- return ret;
-#endif
- return ret;
+ return 0;
}
-int dram_init(void)
+int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ fdtdec_setup_memory_banksize();
return 0;
}
void reset_cpu(ulong addr)
{
}
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
-
-U_BOOT_DEVICE(blanche_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
#include <power/pmic.h>
#include <power/stpmu1.h>
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
+
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+
+ /* UART4 clock enable */
+ setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+#define GPIOG_BASE 0x50008000
+ /* GPIOG clock enable */
+ writel(BIT(6), RCC_MP_AHB4ENSETR);
+ /* GPIO configuration for EVAL board
+ * => Uart4 TX = G11
+ */
+ writel(0xffbfffff, GPIOG_BASE + 0x00);
+ writel(0x00006000, GPIOG_BASE + 0x24);
+#else
+
+#error("CONFIG_DEBUG_UART_BASE: not supported value")
+
+#endif
+}
+#endif
+
#ifdef CONFIG_PMIC_STPMU1
int board_ddr_power_init(void)
{
#include <spl.h>
#include <mmc.h>
#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
-#endif
#include "twister.h"
DECLARE_GLOBAL_DATA_PTR;
XR16L2751_GPMC_CONFIG6,
};
-#ifdef CONFIG_USB_EHCI_HCD
+#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_initialize();
-
+#endif
/* init cs for extern lan */
enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
- if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
- printf("\nError initializing SMC911x controlleri\n");
-
+#ifdef CONFIG_SMC911X
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#else
return 0;
+#endif
}
-#if defined(CONFIG_MMC_OMAP_HS) && \
- !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC_OMAP_HS)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
puts("Board: Xilinx ZynqMP\n");
return 0;
}
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data0 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = ZYNQMP_USB0_XHCI_BASEADDR,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 0,
-};
-
-static struct dwc3_device dwc3_device_data1 = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = ZYNQMP_USB1_XHCI_BASEADDR,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 1,
-};
-
-int usb_gadget_handle_interrupts(int index)
-{
- dwc3_uboot_handle_interrupt(index);
- return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- debug("%s: index %x\n", __func__, index);
-
-#if defined(CONFIG_USB_GADGET_DOWNLOAD)
- g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
-#endif
-
- switch (index) {
- case 0:
- return dwc3_uboot_init(&dwc3_device_data0);
- case 1:
- return dwc3_uboot_init(&dwc3_device_data1);
- };
-
- return -1;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- dwc3_uboot_exit(index);
- return 0;
-}
-#endif
config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
- depends on CMD_BOOTEFI && (ARM || X86)
+ depends on CMD_BOOTEFI && (ARM || X86 || RISCV)
default y
help
This compiles a standard EFI hello world application with U-Boot so
help
MMC memory mapped support.
+config CMD_MMC_RPMB
+ bool "Enable support for RPMB in the mmc command"
+ depends on CMD_MMC
+ help
+ Enable the commands for reading, writing and programming the
+ key for the Replay Protection Memory Block partition in eMMC.
+
config CMD_NAND
bool "nand"
default y if NAND_SUNXI
the image into RAM, then using this command to look at it or display
it.
+config CMD_BOOTCOUNT
+ bool "bootcount"
+ depends on BOOTCOUNT_LIMIT
+ help
+ Enable the bootcount command, which allows interrogation and
+ reset of the bootcounter.
+
config CMD_BSP
bool "Enable board-specific commands"
help
help
Add -v option to verify data against a hash.
+config CMD_TPM_V1
+ bool
+
+config CMD_TPM_V2
+ bool
+
config CMD_TPM
bool "Enable the 'tpm' command"
- depends on TPM
+ depends on TPM_V1 || TPM_V2
+ select CMD_TPM_V1 if TPM_V1
+ select CMD_TPM_V2 if TPM_V2
help
This provides a means to talk to a TPM from the command line. A wide
range of commands if provided - see 'tpm help' for details. The
command requires a suitable TPM on your board and the correct driver
must be enabled.
+if CMD_TPM
+
config CMD_TPM_TEST
bool "Enable the 'tpm test' command"
- depends on CMD_TPM
+ depends on TPM_V1
help
- This provides a a series of tests to confirm that the TPM is working
- correctly. The tests cover initialisation, non-volatile RAM, extend,
- global lock and checking that timing is within expectations. The
- tests pass correctly on Infineon TPMs but may need to be adjusted
+ This provides a a series of tests to confirm that the TPMv1.x is
+ working correctly. The tests cover initialisation, non-volatile RAM,
+ extend, global lock and checking that timing is within expectations.
+ The tests pass correctly on Infineon TPMs but may need to be adjusted
for other devices.
+endif
+
endmenu
menu "Firmware commands"
obj-$(CONFIG_CMD_BINOP) += binop.o
obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o
obj-$(CONFIG_CMD_BMP) += bmp.o
+obj-$(CONFIG_CMD_BOOTCOUNT) += bootcount.o
obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o
obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o
obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o
obj-$(CONFIG_CMD_TIME) += time.o
obj-$(CONFIG_CMD_TRACE) += trace.o
obj-$(CONFIG_HUSH_PARSER) += test.o
-obj-$(CONFIG_CMD_TPM) += tpm.o
+obj-$(CONFIG_CMD_TPM) += tpm-common.o
+obj-$(CONFIG_CMD_TPM_V1) += tpm-v1.o
obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
+obj-$(CONFIG_CMD_TPM_V2) += tpm-v2.o
obj-$(CONFIG_CMD_CROS_EC) += cros_ec.o
obj-$(CONFIG_CMD_TSI148) += tsi148.o
obj-$(CONFIG_CMD_UBI) += ubi.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <command.h>
+#include <bootcount.h>
+
+static int do_bootcount_print(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ printf("%lu\n", bootcount_load());
+ return CMD_RET_SUCCESS;
+}
+
+static int do_bootcount_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /*
+ * note that we're explicitly not resetting the environment
+ * variable, so you still have the old bootcounter available
+ */
+ bootcount_store(0);
+ return CMD_RET_SUCCESS;
+}
+
+static cmd_tbl_t bootcount_sub[] = {
+ U_BOOT_CMD_MKENT(print, 1, 1, do_bootcount_print, "", ""),
+ U_BOOT_CMD_MKENT(reset, 1, 1, do_bootcount_reset, "", ""),
+};
+
+static int do_bootcount(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *cp;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* drop initial "bootcount" arg */
+ argc--;
+ argv++;
+
+ cp = find_cmd_tbl(argv[0], bootcount_sub, ARRAY_SIZE(bootcount_sub));
+ if (cp)
+ return cp->cmd(cmdtp, flag, argc, argv);
+
+ return CMD_RET_USAGE;
+}
+
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+static char bootcount_help_text[] =
+ "print - print current bootcounter\n"
+ "reset - reset the bootcounter"
+ ;
+#endif
+
+U_BOOT_CMD(bootcount, 2, 1, do_bootcount,
+ "bootcount",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+ bootcount_help_text
+#endif
+);
return CMD_RET_SUCCESS;
}
-#ifdef CONFIG_SUPPORT_EMMC_RPMB
+#if CONFIG_IS_ENABLED(CMD_MMC_RPMB)
static int confirm_key_prog(void)
{
puts("Warning: Programming authentication key can be done only once !\n"
U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""),
U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""),
#endif
-#ifdef CONFIG_SUPPORT_EMMC_RPMB
+#if CONFIG_IS_ENABLED(CMD_MMC_RPMB)
U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""),
#endif
U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
" - Change the RST_n_FUNCTION field of the specified device\n"
" WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n"
#endif
-#ifdef CONFIG_SUPPORT_EMMC_RPMB
+#if CONFIG_IS_ENABLED(CMD_MMC_RPMB)
"mmc rpmb read addr blk# cnt [address of auth-key] - block size is 256 bytes\n"
"mmc rpmb write addr blk# cnt <address of auth-key> - block size is 256 bytes\n"
"mmc rpmb key <address of auth-key> - program the RPMB authentication key.\n"
static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ struct uc_pmic_priv *priv;
struct udevice *dev;
- uint8_t value;
+ char fmt[16];
uint reg;
int ret;
}
dev = currdev;
-
+ priv = dev_get_uclass_priv(dev);
printf("Dump pmic: %s registers\n", dev->name);
+ sprintf(fmt, "%%%d.%dx ", priv->trans_len * 2,
+ priv->trans_len * 2);
+
for (reg = 0; reg < pmic_reg_count(dev); reg++) {
- ret = pmic_read(dev, reg, &value, 1);
- if (ret) {
+ ret = pmic_reg_read(dev, reg);
+ if (ret < 0) {
printf("Can't read register: %d\n", reg);
return failure(ret);
}
if (!(reg % 16))
printf("\n0x%02x: ", reg);
- printf("%2.2x ", value);
+ printf(fmt, ret);
}
printf("\n");
static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ struct uc_pmic_priv *priv;
struct udevice *dev;
int regs, ret;
- uint8_t value;
+ char fmt[24];
uint reg;
if (!currdev) {
}
dev = currdev;
+ priv = dev_get_uclass_priv(dev);
if (argc != 2)
return CMD_RET_USAGE;
return failure(-EFAULT);
}
- ret = pmic_read(dev, reg, &value, 1);
- if (ret) {
+ ret = pmic_reg_read(dev, reg);
+ if (ret < 0) {
printf("Can't read PMIC register: %d!\n", reg);
return failure(ret);
}
- printf("0x%02x: 0x%2.2x\n", reg, value);
+ sprintf(fmt, "0x%%02x: 0x%%%d.%dx\n", priv->trans_len * 2,
+ priv->trans_len * 2);
+ printf(fmt, reg, ret);
return CMD_RET_SUCCESS;
}
static int do_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
+ uint reg, value;
int regs, ret;
- uint8_t value;
- uint reg;
if (!currdev) {
printf("First, set the PMIC device!\n");
value = simple_strtoul(argv[2], NULL, 0);
- ret = pmic_write(dev, reg, &value, 1);
+ ret = pmic_reg_write(dev, reg, value);
if (ret) {
printf("Can't write PMIC register: %d!\n", reg);
return failure(ret);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <asm/unaligned.h>
+#include <linux/string.h>
+#include <tpm-common.h>
+#include "tpm-user-utils.h"
+
+/**
+ * Print a byte string in hexdecimal format, 16-bytes per line.
+ *
+ * @param data byte string to be printed
+ * @param count number of bytes to be printed
+ */
+void print_byte_string(u8 *data, size_t count)
+{
+ int i, print_newline = 0;
+
+ for (i = 0; i < count; i++) {
+ printf(" %02x", data[i]);
+ print_newline = (i % 16 == 15);
+ if (print_newline)
+ putc('\n');
+ }
+ /* Avoid duplicated newline at the end */
+ if (!print_newline)
+ putc('\n');
+}
+
+/**
+ * Convert a text string of hexdecimal values into a byte string.
+ *
+ * @param bytes text string of hexdecimal values with no space
+ * between them
+ * @param data output buffer for byte string. The caller has to make
+ * sure it is large enough for storing the output. If
+ * NULL is passed, a large enough buffer will be allocated,
+ * and the caller must free it.
+ * @param count_ptr output variable for the length of byte string
+ * @return pointer to output buffer
+ */
+void *parse_byte_string(char *bytes, u8 *data, size_t *count_ptr)
+{
+ char byte[3];
+ size_t count, length;
+ int i;
+
+ if (!bytes)
+ return NULL;
+ length = strlen(bytes);
+ count = length / 2;
+
+ if (!data)
+ data = malloc(count);
+ if (!data)
+ return NULL;
+
+ byte[2] = '\0';
+ for (i = 0; i < length; i += 2) {
+ byte[0] = bytes[i];
+ byte[1] = bytes[i + 1];
+ data[i / 2] = (u8)simple_strtoul(byte, NULL, 16);
+ }
+
+ if (count_ptr)
+ *count_ptr = count;
+
+ return data;
+}
+
+/**
+ * report_return_code() - Report any error and return failure or success
+ *
+ * @param return_code TPM command return code
+ * @return value of enum command_ret_t
+ */
+int report_return_code(int return_code)
+{
+ if (return_code) {
+ printf("Error: %d\n", return_code);
+ return CMD_RET_FAILURE;
+ } else {
+ return CMD_RET_SUCCESS;
+ }
+}
+
+/**
+ * Return number of values defined by a type string.
+ *
+ * @param type_str type string
+ * @return number of values of type string
+ */
+int type_string_get_num_values(const char *type_str)
+{
+ return strlen(type_str);
+}
+
+/**
+ * Return total size of values defined by a type string.
+ *
+ * @param type_str type string
+ * @return total size of values of type string, or 0 if type string
+ * contains illegal type character.
+ */
+size_t type_string_get_space_size(const char *type_str)
+{
+ size_t size;
+
+ for (size = 0; *type_str; type_str++) {
+ switch (*type_str) {
+ case 'b':
+ size += 1;
+ break;
+ case 'w':
+ size += 2;
+ break;
+ case 'd':
+ size += 4;
+ break;
+ default:
+ return 0;
+ }
+ }
+
+ return size;
+}
+
+/**
+ * Allocate a buffer large enough to hold values defined by a type
+ * string. The caller has to free the buffer.
+ *
+ * @param type_str type string
+ * @param count pointer for storing size of buffer
+ * @return pointer to buffer or NULL on error
+ */
+void *type_string_alloc(const char *type_str, u32 *count)
+{
+ void *data;
+ size_t size;
+
+ size = type_string_get_space_size(type_str);
+ if (!size)
+ return NULL;
+ data = malloc(size);
+ if (data)
+ *count = size;
+
+ return data;
+}
+
+/**
+ * Pack values defined by a type string into a buffer. The buffer must have
+ * large enough space.
+ *
+ * @param type_str type string
+ * @param values text strings of values to be packed
+ * @param data output buffer of values
+ * @return 0 on success, non-0 on error
+ */
+int type_string_pack(const char *type_str, char * const values[],
+ u8 *data)
+{
+ size_t offset;
+ u32 value;
+
+ for (offset = 0; *type_str; type_str++, values++) {
+ value = simple_strtoul(values[0], NULL, 0);
+ switch (*type_str) {
+ case 'b':
+ data[offset] = value;
+ offset += 1;
+ break;
+ case 'w':
+ put_unaligned_be16(value, data + offset);
+ offset += 2;
+ break;
+ case 'd':
+ put_unaligned_be32(value, data + offset);
+ offset += 4;
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Read values defined by a type string from a buffer, and write these values
+ * to environment variables.
+ *
+ * @param type_str type string
+ * @param data input buffer of values
+ * @param vars names of environment variables
+ * @return 0 on success, non-0 on error
+ */
+int type_string_write_vars(const char *type_str, u8 *data,
+ char * const vars[])
+{
+ size_t offset;
+ u32 value;
+
+ for (offset = 0; *type_str; type_str++, vars++) {
+ switch (*type_str) {
+ case 'b':
+ value = data[offset];
+ offset += 1;
+ break;
+ case 'w':
+ value = get_unaligned_be16(data + offset);
+ offset += 2;
+ break;
+ case 'd':
+ value = get_unaligned_be32(data + offset);
+ offset += 4;
+ break;
+ default:
+ return -1;
+ }
+ if (env_set_ulong(*vars, value))
+ return -1;
+ }
+
+ return 0;
+}
+
+int get_tpm(struct udevice **devp)
+{
+ int rc;
+
+ rc = uclass_first_device_err(UCLASS_TPM, devp);
+ if (rc) {
+ printf("Could not find TPM (ret=%d)\n", rc);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ char buf[80];
+ int rc;
+
+ rc = get_tpm(&dev);
+ if (rc)
+ return rc;
+ rc = tpm_get_desc(dev, buf, sizeof(buf));
+ if (rc < 0) {
+ printf("Couldn't get TPM info (%d)\n", rc);
+ return CMD_RET_FAILURE;
+ }
+ printf("%s\n", buf);
+
+ return 0;
+}
+
+int do_tpm_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 1)
+ return CMD_RET_USAGE;
+
+ return report_return_code(tpm_init());
+}
+
+int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *tpm_commands, *cmd;
+ unsigned int size;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ tpm_commands = get_tpm_commands(&size);
+
+ cmd = find_cmd_tbl(argv[1], tpm_commands, size);
+ if (!cmd)
+ return CMD_RET_USAGE;
+
+ return cmd->cmd(cmdtp, flag, argc - 1, argv + 1);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_USER_UTILS_H
+#define __TPM_USER_UTILS_H
+
+void print_byte_string(u8 *data, size_t count);
+void *parse_byte_string(char *bytes, u8 *data, size_t *count_ptr);
+int report_return_code(int return_code);
+int type_string_get_num_values(const char *type_str);
+size_t type_string_get_space_size(const char *type_str);
+void *type_string_alloc(const char *type_str, u32 *count);
+int type_string_pack(const char *type_str, char * const values[], u8 *data);
+int type_string_write_vars(const char *type_str, u8 *data, char * const vars[]);
+int get_tpm(struct udevice **devp);
+
+int do_tpm_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+#endif /* __TPM_USER_UTILS_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/unaligned.h>
+#include <tpm-common.h>
+#include <tpm-v1.h>
+#include "tpm-user-utils.h"
+
+static int do_tpm_startup(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ enum tpm_startup_type mode;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if (!strcasecmp("TPM_ST_CLEAR", argv[1])) {
+ mode = TPM_ST_CLEAR;
+ } else if (!strcasecmp("TPM_ST_STATE", argv[1])) {
+ mode = TPM_ST_STATE;
+ } else if (!strcasecmp("TPM_ST_DEACTIVATED", argv[1])) {
+ mode = TPM_ST_DEACTIVATED;
+ } else {
+ printf("Couldn't recognize mode string: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ return report_return_code(tpm_startup(mode));
+}
+
+static int do_tpm_nv_define_space(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, perm, size;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[1], NULL, 0);
+ perm = simple_strtoul(argv[2], NULL, 0);
+ size = simple_strtoul(argv[3], NULL, 0);
+
+ return report_return_code(tpm_nv_define_space(index, perm, size));
+}
+
+static int do_tpm_nv_read_value(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, count, rc;
+ void *data;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[1], NULL, 0);
+ data = (void *)simple_strtoul(argv[2], NULL, 0);
+ count = simple_strtoul(argv[3], NULL, 0);
+
+ rc = tpm_nv_read_value(index, data, count);
+ if (!rc) {
+ puts("area content:\n");
+ print_byte_string(data, count);
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_nv_write_value(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, rc;
+ size_t count;
+ void *data;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[1], NULL, 0);
+ data = parse_byte_string(argv[2], NULL, &count);
+ if (!data) {
+ printf("Couldn't parse byte string %s\n", argv[2]);
+ return CMD_RET_FAILURE;
+ }
+
+ rc = tpm_nv_write_value(index, data, count);
+ free(data);
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_extend(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, rc;
+ u8 in_digest[20], out_digest[20];
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[1], NULL, 0);
+ if (!parse_byte_string(argv[2], in_digest, NULL)) {
+ printf("Couldn't parse byte string %s\n", argv[2]);
+ return CMD_RET_FAILURE;
+ }
+
+ rc = tpm_extend(index, in_digest, out_digest);
+ if (!rc) {
+ puts("PCR value after execution of the command:\n");
+ print_byte_string(out_digest, sizeof(out_digest));
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, count, rc;
+ void *data;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[1], NULL, 0);
+ data = (void *)simple_strtoul(argv[2], NULL, 0);
+ count = simple_strtoul(argv[3], NULL, 0);
+
+ rc = tpm_pcr_read(index, data, count);
+ if (!rc) {
+ puts("Named PCR content:\n");
+ print_byte_string(data, count);
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_tsc_physical_presence(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u16 presence;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ presence = (u16)simple_strtoul(argv[1], NULL, 0);
+
+ return report_return_code(tpm_tsc_physical_presence(presence));
+}
+
+static int do_tpm_read_pubek(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 count, rc;
+ void *data;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+ data = (void *)simple_strtoul(argv[1], NULL, 0);
+ count = simple_strtoul(argv[2], NULL, 0);
+
+ rc = tpm_read_pubek(data, count);
+ if (!rc) {
+ puts("pubek value:\n");
+ print_byte_string(data, count);
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_physical_set_deactivated(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u8 state;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ state = (u8)simple_strtoul(argv[1], NULL, 0);
+
+ return report_return_code(tpm_physical_set_deactivated(state));
+}
+
+static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 cap_area, sub_cap, rc;
+ void *cap;
+ size_t count;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+ cap_area = simple_strtoul(argv[1], NULL, 0);
+ sub_cap = simple_strtoul(argv[2], NULL, 0);
+ cap = (void *)simple_strtoul(argv[3], NULL, 0);
+ count = simple_strtoul(argv[4], NULL, 0);
+
+ rc = tpm_get_capability(cap_area, sub_cap, cap, count);
+ if (!rc) {
+ puts("capability information:\n");
+ print_byte_string(cap, count);
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_raw_transfer(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ void *command;
+ u8 response[1024];
+ size_t count, response_length = sizeof(response);
+ u32 rc;
+
+ command = parse_byte_string(argv[1], NULL, &count);
+ if (!command) {
+ printf("Couldn't parse byte string %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ rc = get_tpm(&dev);
+ if (rc)
+ return rc;
+
+ rc = tpm_xfer(dev, command, count, response, &response_length);
+ free(command);
+ if (!rc) {
+ puts("tpm response:\n");
+ print_byte_string(response, response_length);
+ }
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_nv_define(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, perm, size;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+ size = type_string_get_space_size(argv[1]);
+ if (!size) {
+ printf("Couldn't parse arguments\n");
+ return CMD_RET_USAGE;
+ }
+ index = simple_strtoul(argv[2], NULL, 0);
+ perm = simple_strtoul(argv[3], NULL, 0);
+
+ return report_return_code(tpm_nv_define_space(index, perm, size));
+}
+
+static int do_tpm_nv_read(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, count, err;
+ void *data;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (argc != 3 + type_string_get_num_values(argv[1]))
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[2], NULL, 0);
+ data = type_string_alloc(argv[1], &count);
+ if (!data) {
+ printf("Couldn't parse arguments\n");
+ return CMD_RET_USAGE;
+ }
+
+ err = tpm_nv_read_value(index, data, count);
+ if (!err) {
+ if (type_string_write_vars(argv[1], data, argv + 3)) {
+ printf("Couldn't write to variables\n");
+ err = ~0;
+ }
+ }
+ free(data);
+
+ return report_return_code(err);
+}
+
+static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index, count, err;
+ void *data;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (argc != 3 + type_string_get_num_values(argv[1]))
+ return CMD_RET_USAGE;
+ index = simple_strtoul(argv[2], NULL, 0);
+ data = type_string_alloc(argv[1], &count);
+ if (!data) {
+ printf("Couldn't parse arguments\n");
+ return CMD_RET_USAGE;
+ }
+ if (type_string_pack(argv[1], argv + 3, data)) {
+ printf("Couldn't parse arguments\n");
+ free(data);
+ return CMD_RET_USAGE;
+ }
+
+ err = tpm_nv_write_value(index, data, count);
+ free(data);
+
+ return report_return_code(err);
+}
+
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+
+static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 auth_handle, err;
+
+ err = tpm_oiap(&auth_handle);
+
+ return report_return_code(err);
+}
+
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+static int do_tpm_load_key_by_sha1(cmd_tbl_t *cmdtp, int flag, int argc, char *
+ const argv[])
+{
+ u32 parent_handle = 0;
+ u32 key_len, key_handle, err;
+ u8 usage_auth[DIGEST_LENGTH];
+ u8 parent_hash[DIGEST_LENGTH];
+ void *key;
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ parse_byte_string(argv[1], parent_hash, NULL);
+ key = (void *)simple_strtoul(argv[2], NULL, 0);
+ key_len = simple_strtoul(argv[3], NULL, 0);
+ if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[4], usage_auth, NULL);
+
+ err = tpm_find_key_sha1(usage_auth, parent_hash, &parent_handle);
+ if (err) {
+ printf("Could not find matching parent key (err = %d)\n", err);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Found parent key %08x\n", parent_handle);
+
+ err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+ &key_handle);
+ if (!err) {
+ printf("Key handle is 0x%x\n", key_handle);
+ env_set_hex("key_handle", key_handle);
+ }
+
+ return report_return_code(err);
+}
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
+static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 parent_handle, key_len, key_handle, err;
+ u8 usage_auth[DIGEST_LENGTH];
+ void *key;
+
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ parent_handle = simple_strtoul(argv[1], NULL, 0);
+ key = (void *)simple_strtoul(argv[2], NULL, 0);
+ key_len = simple_strtoul(argv[3], NULL, 0);
+ if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[4], usage_auth, NULL);
+
+ err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
+ &key_handle);
+ if (!err)
+ printf("Key handle is 0x%x\n", key_handle);
+
+ return report_return_code(err);
+}
+
+static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 key_handle, err;
+ u8 usage_auth[DIGEST_LENGTH];
+ u8 pub_key_buffer[TPM_PUBKEY_MAX_LENGTH];
+ size_t pub_key_len = sizeof(pub_key_buffer);
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ key_handle = simple_strtoul(argv[1], NULL, 0);
+ if (strlen(argv[2]) != 2 * DIGEST_LENGTH)
+ return CMD_RET_FAILURE;
+ parse_byte_string(argv[2], usage_auth, NULL);
+
+ err = tpm_get_pub_key_oiap(key_handle, usage_auth, pub_key_buffer,
+ &pub_key_len);
+ if (!err) {
+ printf("dump of received pub key structure:\n");
+ print_byte_string(pub_key_buffer, pub_key_len);
+ }
+ return report_return_code(err);
+}
+
+TPM_COMMAND_NO_ARG(tpm_end_oiap)
+
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int type = 0;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ if (!strcasecmp(argv[1], "key"))
+ type = TPM_RT_KEY;
+ else if (!strcasecmp(argv[1], "auth"))
+ type = TPM_RT_AUTH;
+ else if (!strcasecmp(argv[1], "hash"))
+ type = TPM_RT_HASH;
+ else if (!strcasecmp(argv[1], "trans"))
+ type = TPM_RT_TRANS;
+ else if (!strcasecmp(argv[1], "context"))
+ type = TPM_RT_CONTEXT;
+ else if (!strcasecmp(argv[1], "counter"))
+ type = TPM_RT_COUNTER;
+ else if (!strcasecmp(argv[1], "delegate"))
+ type = TPM_RT_DELEGATE;
+ else if (!strcasecmp(argv[1], "daa_tpm"))
+ type = TPM_RT_DAA_TPM;
+ else if (!strcasecmp(argv[1], "daa_v0"))
+ type = TPM_RT_DAA_V0;
+ else if (!strcasecmp(argv[1], "daa_v1"))
+ type = TPM_RT_DAA_V1;
+
+ if (!type) {
+ printf("Resource type %s unknown.\n", argv[1]);
+ return -1;
+ }
+
+ if (!strcasecmp(argv[2], "all")) {
+ u16 res_count;
+ u8 buf[288];
+ u8 *ptr;
+ int err;
+ uint i;
+
+ /* fetch list of already loaded resources in the TPM */
+ err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
+ sizeof(buf));
+ if (err) {
+ printf("tpm_get_capability returned error %d.\n", err);
+ return -1;
+ }
+ res_count = get_unaligned_be16(buf);
+ ptr = buf + 2;
+ for (i = 0; i < res_count; ++i, ptr += 4)
+ tpm_flush_specific(get_unaligned_be32(ptr), type);
+ } else {
+ u32 handle = simple_strtoul(argv[2], NULL, 0);
+
+ if (!handle) {
+ printf("Illegal resource handle %s\n", argv[2]);
+ return -1;
+ }
+ tpm_flush_specific(cpu_to_be32(handle), type);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+
+#ifdef CONFIG_TPM_LIST_RESOURCES
+static int do_tpm_list(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int type = 0;
+ u16 res_count;
+ u8 buf[288];
+ u8 *ptr;
+ int err;
+ uint i;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (!strcasecmp(argv[1], "key"))
+ type = TPM_RT_KEY;
+ else if (!strcasecmp(argv[1], "auth"))
+ type = TPM_RT_AUTH;
+ else if (!strcasecmp(argv[1], "hash"))
+ type = TPM_RT_HASH;
+ else if (!strcasecmp(argv[1], "trans"))
+ type = TPM_RT_TRANS;
+ else if (!strcasecmp(argv[1], "context"))
+ type = TPM_RT_CONTEXT;
+ else if (!strcasecmp(argv[1], "counter"))
+ type = TPM_RT_COUNTER;
+ else if (!strcasecmp(argv[1], "delegate"))
+ type = TPM_RT_DELEGATE;
+ else if (!strcasecmp(argv[1], "daa_tpm"))
+ type = TPM_RT_DAA_TPM;
+ else if (!strcasecmp(argv[1], "daa_v0"))
+ type = TPM_RT_DAA_V0;
+ else if (!strcasecmp(argv[1], "daa_v1"))
+ type = TPM_RT_DAA_V1;
+
+ if (!type) {
+ printf("Resource type %s unknown.\n", argv[1]);
+ return -1;
+ }
+
+ /* fetch list of already loaded resources in the TPM */
+ err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
+ sizeof(buf));
+ if (err) {
+ printf("tpm_get_capability returned error %d.\n", err);
+ return -1;
+ }
+ res_count = get_unaligned_be16(buf);
+ ptr = buf + 2;
+
+ printf("Resources of type %s (%02x):\n", argv[1], type);
+ if (!res_count) {
+ puts("None\n");
+ } else {
+ for (i = 0; i < res_count; ++i, ptr += 4)
+ printf("Index %d: %08x\n", i, get_unaligned_be32(ptr));
+ }
+
+ return 0;
+}
+#endif /* CONFIG_TPM_LIST_RESOURCES */
+
+TPM_COMMAND_NO_ARG(tpm_self_test_full)
+TPM_COMMAND_NO_ARG(tpm_continue_self_test)
+TPM_COMMAND_NO_ARG(tpm_force_clear)
+TPM_COMMAND_NO_ARG(tpm_physical_enable)
+TPM_COMMAND_NO_ARG(tpm_physical_disable)
+
+static cmd_tbl_t tpm1_commands[] = {
+ U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
+ U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""),
+ U_BOOT_CMD_MKENT(startup, 0, 1,
+ do_tpm_startup, "", ""),
+ U_BOOT_CMD_MKENT(self_test_full, 0, 1,
+ do_tpm_self_test_full, "", ""),
+ U_BOOT_CMD_MKENT(continue_self_test, 0, 1,
+ do_tpm_continue_self_test, "", ""),
+ U_BOOT_CMD_MKENT(force_clear, 0, 1,
+ do_tpm_force_clear, "", ""),
+ U_BOOT_CMD_MKENT(physical_enable, 0, 1,
+ do_tpm_physical_enable, "", ""),
+ U_BOOT_CMD_MKENT(physical_disable, 0, 1,
+ do_tpm_physical_disable, "", ""),
+ U_BOOT_CMD_MKENT(nv_define_space, 0, 1,
+ do_tpm_nv_define_space, "", ""),
+ U_BOOT_CMD_MKENT(nv_read_value, 0, 1,
+ do_tpm_nv_read_value, "", ""),
+ U_BOOT_CMD_MKENT(nv_write_value, 0, 1,
+ do_tpm_nv_write_value, "", ""),
+ U_BOOT_CMD_MKENT(extend, 0, 1,
+ do_tpm_extend, "", ""),
+ U_BOOT_CMD_MKENT(pcr_read, 0, 1,
+ do_tpm_pcr_read, "", ""),
+ U_BOOT_CMD_MKENT(tsc_physical_presence, 0, 1,
+ do_tpm_tsc_physical_presence, "", ""),
+ U_BOOT_CMD_MKENT(read_pubek, 0, 1,
+ do_tpm_read_pubek, "", ""),
+ U_BOOT_CMD_MKENT(physical_set_deactivated, 0, 1,
+ do_tpm_physical_set_deactivated, "", ""),
+ U_BOOT_CMD_MKENT(get_capability, 0, 1,
+ do_tpm_get_capability, "", ""),
+ U_BOOT_CMD_MKENT(raw_transfer, 0, 1,
+ do_tpm_raw_transfer, "", ""),
+ U_BOOT_CMD_MKENT(nv_define, 0, 1,
+ do_tpm_nv_define, "", ""),
+ U_BOOT_CMD_MKENT(nv_read, 0, 1,
+ do_tpm_nv_read, "", ""),
+ U_BOOT_CMD_MKENT(nv_write, 0, 1,
+ do_tpm_nv_write, "", ""),
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+ U_BOOT_CMD_MKENT(oiap, 0, 1,
+ do_tpm_oiap, "", ""),
+ U_BOOT_CMD_MKENT(end_oiap, 0, 1,
+ do_tpm_end_oiap, "", ""),
+ U_BOOT_CMD_MKENT(load_key2_oiap, 0, 1,
+ do_tpm_load_key2_oiap, "", ""),
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+ U_BOOT_CMD_MKENT(load_key_by_sha1, 0, 1,
+ do_tpm_load_key_by_sha1, "", ""),
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+ U_BOOT_CMD_MKENT(get_pub_key_oiap, 0, 1,
+ do_tpm_get_pub_key_oiap, "", ""),
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+ U_BOOT_CMD_MKENT(flush, 0, 1,
+ do_tpm_flush, "", ""),
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+#ifdef CONFIG_TPM_LIST_RESOURCES
+ U_BOOT_CMD_MKENT(list, 0, 1,
+ do_tpm_list, "", ""),
+#endif /* CONFIG_TPM_LIST_RESOURCES */
+};
+
+cmd_tbl_t *get_tpm_commands(unsigned int *size)
+{
+ *size = ARRAY_SIZE(tpm1_commands);
+
+ return tpm1_commands;
+}
+
+U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
+"Issue a TPMv1.x command",
+"cmd args...\n"
+" - Issue TPM command <cmd> with arguments <args...>.\n"
+"Admin Startup and State Commands:\n"
+" info - Show information about the TPM\n"
+" init\n"
+" - Put TPM into a state where it waits for 'startup' command.\n"
+" startup mode\n"
+" - Issue TPM_Starup command. <mode> is one of TPM_ST_CLEAR,\n"
+" TPM_ST_STATE, and TPM_ST_DEACTIVATED.\n"
+"Admin Testing Commands:\n"
+" self_test_full\n"
+" - Test all of the TPM capabilities.\n"
+" continue_self_test\n"
+" - Inform TPM that it should complete the self-test.\n"
+"Admin Opt-in Commands:\n"
+" physical_enable\n"
+" - Set the PERMANENT disable flag to FALSE using physical presence as\n"
+" authorization.\n"
+" physical_disable\n"
+" - Set the PERMANENT disable flag to TRUE using physical presence as\n"
+" authorization.\n"
+" physical_set_deactivated 0|1\n"
+" - Set deactivated flag.\n"
+"Admin Ownership Commands:\n"
+" force_clear\n"
+" - Issue TPM_ForceClear command.\n"
+" tsc_physical_presence flags\n"
+" - Set TPM device's Physical Presence flags to <flags>.\n"
+"The Capability Commands:\n"
+" get_capability cap_area sub_cap addr count\n"
+" - Read <count> bytes of TPM capability indexed by <cap_area> and\n"
+" <sub_cap> to memory address <addr>.\n"
+#if defined(CONFIG_TPM_FLUSH_RESOURCES) || defined(CONFIG_TPM_LIST_RESOURCES)
+"Resource management functions\n"
+#endif
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+" flush resource_type id\n"
+" - flushes a resource of type <resource_type> (may be one of key, auth,\n"
+" hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
+" and id <id> from the TPM. Use an <id> of \"all\" to flush all\n"
+" resources of that type.\n"
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+#ifdef CONFIG_TPM_LIST_RESOURCES
+" list resource_type\n"
+" - lists resources of type <resource_type> (may be one of key, auth,\n"
+" hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
+" contained in the TPM.\n"
+#endif /* CONFIG_TPM_LIST_RESOURCES */
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+"Storage functions\n"
+" loadkey2_oiap parent_handle key_addr key_len usage_auth\n"
+" - loads a key data from memory address <key_addr>, <key_len> bytes\n"
+" into TPM using the parent key <parent_handle> with authorization\n"
+" <usage_auth> (20 bytes hex string).\n"
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+" load_key_by_sha1 parent_hash key_addr key_len usage_auth\n"
+" - loads a key data from memory address <key_addr>, <key_len> bytes\n"
+" into TPM using the parent hash <parent_hash> (20 bytes hex string)\n"
+" with authorization <usage_auth> (20 bytes hex string).\n"
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+" get_pub_key_oiap key_handle usage_auth\n"
+" - get the public key portion of a loaded key <key_handle> using\n"
+" authorization <usage auth> (20 bytes hex string)\n"
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+"Endorsement Key Handling Commands:\n"
+" read_pubek addr count\n"
+" - Read <count> bytes of the public endorsement key to memory\n"
+" address <addr>\n"
+"Integrity Collection and Reporting Commands:\n"
+" extend index digest_hex_string\n"
+" - Add a new measurement to a PCR. Update PCR <index> with the 20-bytes\n"
+" <digest_hex_string>\n"
+" pcr_read index addr count\n"
+" - Read <count> bytes from PCR <index> to memory address <addr>.\n"
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+"Authorization Sessions\n"
+" oiap\n"
+" - setup an OIAP session\n"
+" end_oiap\n"
+" - terminates an active OIAP session\n"
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+"Non-volatile Storage Commands:\n"
+" nv_define_space index permission size\n"
+" - Establish a space at index <index> with <permission> of <size> bytes.\n"
+" nv_read_value index addr count\n"
+" - Read <count> bytes from space <index> to memory address <addr>.\n"
+" nv_write_value index addr count\n"
+" - Write <count> bytes from memory address <addr> to space <index>.\n"
+"Miscellaneous helper functions:\n"
+" raw_transfer byte_string\n"
+" - Send a byte string <byte_string> to TPM and print the response.\n"
+" Non-volatile storage helper functions:\n"
+" These helper functions treat a non-volatile space as a non-padded\n"
+" sequence of integer values. These integer values are defined by a type\n"
+" string, which is a text string of 'bwd' characters: 'b' means a 8-bit\n"
+" value, 'w' 16-bit value, 'd' 32-bit value. All helper functions take\n"
+" a type string as their first argument.\n"
+" nv_define type_string index perm\n"
+" - Define a space <index> with permission <perm>.\n"
+" nv_read types_string index vars...\n"
+" - Read from space <index> to environment variables <vars...>.\n"
+" nv_write types_string index values...\n"
+" - Write to space <index> from values <values...>.\n"
+);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Bootlin
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+#include <tpm-common.h>
+#include <tpm-v2.h>
+#include "tpm-user-utils.h"
+
+static int do_tpm2_startup(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ enum tpm2_startup_types mode;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (!strcasecmp("TPM2_SU_CLEAR", argv[1])) {
+ mode = TPM2_SU_CLEAR;
+ } else if (!strcasecmp("TPM2_SU_STATE", argv[1])) {
+ mode = TPM2_SU_STATE;
+ } else {
+ printf("Couldn't recognize mode string: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ return report_return_code(tpm2_startup(mode));
+}
+
+static int do_tpm2_self_test(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ enum tpm2_yes_no full_test;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (!strcasecmp("full", argv[1])) {
+ full_test = TPMI_YES;
+ } else if (!strcasecmp("continue", argv[1])) {
+ full_test = TPMI_NO;
+ } else {
+ printf("Couldn't recognize test mode: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+
+ return report_return_code(tpm2_self_test(full_test));
+}
+
+static int do_tpm2_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 handle = 0;
+ const char *pw = (argc < 3) ? NULL : argv[2];
+ const ssize_t pw_sz = pw ? strlen(pw) : 0;
+
+ if (argc < 2 || argc > 3)
+ return CMD_RET_USAGE;
+
+ if (pw_sz > TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ if (!strcasecmp("TPM2_RH_LOCKOUT", argv[1]))
+ handle = TPM2_RH_LOCKOUT;
+ else if (!strcasecmp("TPM2_RH_PLATFORM", argv[1]))
+ handle = TPM2_RH_PLATFORM;
+ else
+ return CMD_RET_USAGE;
+
+ return report_return_code(tpm2_clear(handle, pw, pw_sz));
+}
+
+static int do_tpm2_pcr_extend(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ struct tpm_chip_priv *priv;
+ u32 index = simple_strtoul(argv[1], NULL, 0);
+ void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
+ int ret;
+ u32 rc;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ ret = uclass_first_device_err(UCLASS_TPM, &dev);
+ if (ret)
+ return ret;
+
+ priv = dev_get_uclass_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ if (index >= priv->pcr_count)
+ return -EINVAL;
+
+ rc = tpm2_pcr_extend(index, digest);
+
+ unmap_sysmem(digest);
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ struct tpm_chip_priv *priv;
+ u32 index, rc;
+ unsigned int updates;
+ void *data;
+ int ret;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ ret = uclass_first_device_err(UCLASS_TPM, &dev);
+ if (ret)
+ return ret;
+
+ priv = dev_get_uclass_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ index = simple_strtoul(argv[1], NULL, 0);
+ if (index >= priv->pcr_count)
+ return -EINVAL;
+
+ data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0);
+
+ rc = tpm2_pcr_read(index, priv->pcr_select_min, data, &updates);
+ if (!rc) {
+ printf("PCR #%u content (%d known updates):\n", index, updates);
+ print_byte_string(data, TPM2_DIGEST_LEN);
+ }
+
+ unmap_sysmem(data);
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 capability, property, rc;
+ u8 *data;
+ size_t count;
+ int i, j;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ capability = simple_strtoul(argv[1], NULL, 0);
+ property = simple_strtoul(argv[2], NULL, 0);
+ data = map_sysmem(simple_strtoul(argv[3], NULL, 0), 0);
+ count = simple_strtoul(argv[4], NULL, 0);
+
+ rc = tpm2_get_capability(capability, property, data, count);
+ if (rc)
+ goto unmap_data;
+
+ printf("Capabilities read from TPM:\n");
+ for (i = 0; i < count; i++) {
+ printf("Property 0x");
+ for (j = 0; j < 4; j++)
+ printf("%02x", data[(i * 8) + j]);
+ printf(": 0x");
+ for (j = 4; j < 8; j++)
+ printf("%02x", data[(i * 8) + j]);
+ printf("\n");
+ }
+
+unmap_data:
+ unmap_sysmem(data);
+
+ return report_return_code(rc);
+}
+
+static int do_tpm_dam_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *pw = (argc < 2) ? NULL : argv[1];
+ const ssize_t pw_sz = pw ? strlen(pw) : 0;
+
+ if (argc > 2)
+ return CMD_RET_USAGE;
+
+ if (pw_sz > TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ return report_return_code(tpm2_dam_reset(pw, pw_sz));
+}
+
+static int do_tpm_dam_parameters(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *pw = (argc < 5) ? NULL : argv[4];
+ const ssize_t pw_sz = pw ? strlen(pw) : 0;
+ /*
+ * No Dictionary Attack Mitigation (DAM) means:
+ * maxtries = 0xFFFFFFFF, recovery_time = 1, lockout_recovery = 0
+ */
+ unsigned long int max_tries;
+ unsigned long int recovery_time;
+ unsigned long int lockout_recovery;
+
+ if (argc < 4 || argc > 5)
+ return CMD_RET_USAGE;
+
+ if (pw_sz > TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ if (strict_strtoul(argv[1], 0, &max_tries))
+ return CMD_RET_USAGE;
+
+ if (strict_strtoul(argv[2], 0, &recovery_time))
+ return CMD_RET_USAGE;
+
+ if (strict_strtoul(argv[3], 0, &lockout_recovery))
+ return CMD_RET_USAGE;
+
+ log(LOGC_NONE, LOGL_INFO, "Changing dictionary attack parameters:\n");
+ log(LOGC_NONE, LOGL_INFO, "- maxTries: %lu", max_tries);
+ log(LOGC_NONE, LOGL_INFO, "- recoveryTime: %lu\n", recovery_time);
+ log(LOGC_NONE, LOGL_INFO, "- lockoutRecovery: %lu\n", lockout_recovery);
+
+ return report_return_code(tpm2_dam_parameters(pw, pw_sz, max_tries,
+ recovery_time,
+ lockout_recovery));
+}
+
+static int do_tpm_change_auth(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 handle;
+ const char *newpw = argv[2];
+ const char *oldpw = (argc == 3) ? NULL : argv[3];
+ const ssize_t newpw_sz = strlen(newpw);
+ const ssize_t oldpw_sz = oldpw ? strlen(oldpw) : 0;
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ if (newpw_sz > TPM2_DIGEST_LEN || oldpw_sz > TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ if (!strcasecmp("TPM2_RH_LOCKOUT", argv[1]))
+ handle = TPM2_RH_LOCKOUT;
+ else if (!strcasecmp("TPM2_RH_ENDORSEMENT", argv[1]))
+ handle = TPM2_RH_ENDORSEMENT;
+ else if (!strcasecmp("TPM2_RH_OWNER", argv[1]))
+ handle = TPM2_RH_OWNER;
+ else if (!strcasecmp("TPM2_RH_PLATFORM", argv[1]))
+ handle = TPM2_RH_PLATFORM;
+ else
+ return CMD_RET_USAGE;
+
+ return report_return_code(tpm2_change_auth(handle, newpw, newpw_sz,
+ oldpw, oldpw_sz));
+}
+
+static int do_tpm_pcr_setauthpolicy(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 index = simple_strtoul(argv[1], NULL, 0);
+ char *key = argv[2];
+ const char *pw = (argc < 4) ? NULL : argv[3];
+ const ssize_t pw_sz = pw ? strlen(pw) : 0;
+
+ if (strlen(key) != TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ return report_return_code(tpm2_pcr_setauthpolicy(pw, pw_sz, index,
+ key));
+}
+
+static int do_tpm_pcr_setauthvalue(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ u32 index = simple_strtoul(argv[1], NULL, 0);
+ char *key = argv[2];
+ const ssize_t key_sz = strlen(key);
+ const char *pw = (argc < 4) ? NULL : argv[3];
+ const ssize_t pw_sz = pw ? strlen(pw) : 0;
+
+ if (strlen(key) != TPM2_DIGEST_LEN)
+ return -EINVAL;
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ return report_return_code(tpm2_pcr_setauthvalue(pw, pw_sz, index,
+ key, key_sz));
+}
+
+static cmd_tbl_t tpm2_commands[] = {
+ U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
+ U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""),
+ U_BOOT_CMD_MKENT(startup, 0, 1, do_tpm2_startup, "", ""),
+ U_BOOT_CMD_MKENT(self_test, 0, 1, do_tpm2_self_test, "", ""),
+ U_BOOT_CMD_MKENT(clear, 0, 1, do_tpm2_clear, "", ""),
+ U_BOOT_CMD_MKENT(pcr_extend, 0, 1, do_tpm2_pcr_extend, "", ""),
+ U_BOOT_CMD_MKENT(pcr_read, 0, 1, do_tpm_pcr_read, "", ""),
+ U_BOOT_CMD_MKENT(get_capability, 0, 1, do_tpm_get_capability, "", ""),
+ U_BOOT_CMD_MKENT(dam_reset, 0, 1, do_tpm_dam_reset, "", ""),
+ U_BOOT_CMD_MKENT(dam_parameters, 0, 1, do_tpm_dam_parameters, "", ""),
+ U_BOOT_CMD_MKENT(change_auth, 0, 1, do_tpm_change_auth, "", ""),
+ U_BOOT_CMD_MKENT(pcr_setauthpolicy, 0, 1,
+ do_tpm_pcr_setauthpolicy, "", ""),
+ U_BOOT_CMD_MKENT(pcr_setauthvalue, 0, 1,
+ do_tpm_pcr_setauthvalue, "", ""),
+};
+
+cmd_tbl_t *get_tpm_commands(unsigned int *size)
+{
+ *size = ARRAY_SIZE(tpm2_commands);
+
+ return tpm2_commands;
+}
+
+U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
+"<command> [<arguments>]\n"
+"\n"
+"info\n"
+" Show information about the TPM.\n"
+"init\n"
+" Initialize the software stack. Always the first command to issue.\n"
+"startup <mode>\n"
+" Issue a TPM2_Startup command.\n"
+" <mode> is one of:\n"
+" * TPM2_SU_CLEAR (reset state)\n"
+" * TPM2_SU_STATE (preserved state)\n"
+"self_test <type>\n"
+" Test the TPM capabilities.\n"
+" <type> is one of:\n"
+" * full (perform all tests)\n"
+" * continue (only check untested tests)\n"
+"clear <hierarchy>\n"
+" Issue a TPM2_Clear command.\n"
+" <hierarchy> is one of:\n"
+" * TPM2_RH_LOCKOUT\n"
+" * TPM2_RH_PLATFORM\n"
+"pcr_extend <pcr> <digest_addr>\n"
+" Extend PCR #<pcr> with digest at <digest_addr>.\n"
+" <pcr>: index of the PCR\n"
+" <digest_addr>: address of a 32-byte SHA256 digest\n"
+"pcr_read <pcr> <digest_addr>\n"
+" Read PCR #<pcr> to memory address <digest_addr>.\n"
+" <pcr>: index of the PCR\n"
+" <digest_addr>: address to store the a 32-byte SHA256 digest\n"
+"get_capability <capability> <property> <addr> <count>\n"
+" Read and display <count> entries indexed by <capability>/<property>.\n"
+" Values are 4 bytes long and are written at <addr>.\n"
+" <capability>: capability\n"
+" <property>: property\n"
+" <addr>: address to store <count> entries of 4 bytes\n"
+" <count>: number of entries to retrieve\n"
+"dam_reset [<password>]\n"
+" If the TPM is not in a LOCKOUT state, reset the internal error counter.\n"
+" <password>: optional password\n"
+"dam_parameters <max_tries> <recovery_time> <lockout_recovery> [<password>]\n"
+" If the TPM is not in a LOCKOUT state, set the DAM parameters\n"
+" <maxTries>: maximum number of failures before lockout,\n"
+" 0 means always locking\n"
+" <recoveryTime>: time before decrement of the error counter,\n"
+" 0 means no lockout\n"
+" <lockoutRecovery>: time of a lockout (before the next try),\n"
+" 0 means a reboot is needed\n"
+" <password>: optional password of the LOCKOUT hierarchy\n"
+"change_auth <hierarchy> <new_pw> [<old_pw>]\n"
+" <hierarchy>: the hierarchy\n"
+" <new_pw>: new password for <hierarchy>\n"
+" <old_pw>: optional previous password of <hierarchy>\n"
+"pcr_setauthpolicy|pcr_setauthvalue <pcr> <key> [<password>]\n"
+" Change the <key> to access PCR #<pcr>.\n"
+" hierarchy and may be empty.\n"
+" /!\\WARNING: untested function, use at your own risks !\n"
+" <pcr>: index of the PCR\n"
+" <key>: secret to protect the access of PCR #<pcr>\n"
+" <password>: optional password of the PLATFORM hierarchy\n"
+);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2013 The Chromium OS Authors.
- */
-
-#include <common.h>
-#include <command.h>
-#include <dm.h>
-#include <malloc.h>
-#include <tpm.h>
-#include <asm/unaligned.h>
-#include <linux/string.h>
-
-/* Useful constants */
-enum {
- DIGEST_LENGTH = 20,
- /* max lengths, valid for RSA keys <= 2048 bits */
- TPM_PUBKEY_MAX_LENGTH = 288,
-};
-
-/**
- * Print a byte string in hexdecimal format, 16-bytes per line.
- *
- * @param data byte string to be printed
- * @param count number of bytes to be printed
- */
-static void print_byte_string(uint8_t *data, size_t count)
-{
- int i, print_newline = 0;
-
- for (i = 0; i < count; i++) {
- printf(" %02x", data[i]);
- print_newline = (i % 16 == 15);
- if (print_newline)
- putc('\n');
- }
- /* Avoid duplicated newline at the end */
- if (!print_newline)
- putc('\n');
-}
-
-/**
- * Convert a text string of hexdecimal values into a byte string.
- *
- * @param bytes text string of hexdecimal values with no space
- * between them
- * @param data output buffer for byte string. The caller has to make
- * sure it is large enough for storing the output. If
- * NULL is passed, a large enough buffer will be allocated,
- * and the caller must free it.
- * @param count_ptr output variable for the length of byte string
- * @return pointer to output buffer
- */
-static void *parse_byte_string(char *bytes, uint8_t *data, size_t *count_ptr)
-{
- char byte[3];
- size_t count, length;
- int i;
-
- if (!bytes)
- return NULL;
- length = strlen(bytes);
- count = length / 2;
-
- if (!data)
- data = malloc(count);
- if (!data)
- return NULL;
-
- byte[2] = '\0';
- for (i = 0; i < length; i += 2) {
- byte[0] = bytes[i];
- byte[1] = bytes[i + 1];
- data[i / 2] = (uint8_t)simple_strtoul(byte, NULL, 16);
- }
-
- if (count_ptr)
- *count_ptr = count;
-
- return data;
-}
-
-/**
- * report_return_code() - Report any error and return failure or success
- *
- * @param return_code TPM command return code
- * @return value of enum command_ret_t
- */
-static int report_return_code(int return_code)
-{
- if (return_code) {
- printf("Error: %d\n", return_code);
- return CMD_RET_FAILURE;
- } else {
- return CMD_RET_SUCCESS;
- }
-}
-
-/**
- * Return number of values defined by a type string.
- *
- * @param type_str type string
- * @return number of values of type string
- */
-static int type_string_get_num_values(const char *type_str)
-{
- return strlen(type_str);
-}
-
-/**
- * Return total size of values defined by a type string.
- *
- * @param type_str type string
- * @return total size of values of type string, or 0 if type string
- * contains illegal type character.
- */
-static size_t type_string_get_space_size(const char *type_str)
-{
- size_t size;
-
- for (size = 0; *type_str; type_str++) {
- switch (*type_str) {
- case 'b':
- size += 1;
- break;
- case 'w':
- size += 2;
- break;
- case 'd':
- size += 4;
- break;
- default:
- return 0;
- }
- }
-
- return size;
-}
-
-/**
- * Allocate a buffer large enough to hold values defined by a type
- * string. The caller has to free the buffer.
- *
- * @param type_str type string
- * @param count pointer for storing size of buffer
- * @return pointer to buffer or NULL on error
- */
-static void *type_string_alloc(const char *type_str, uint32_t *count)
-{
- void *data;
- size_t size;
-
- size = type_string_get_space_size(type_str);
- if (!size)
- return NULL;
- data = malloc(size);
- if (data)
- *count = size;
-
- return data;
-}
-
-/**
- * Pack values defined by a type string into a buffer. The buffer must have
- * large enough space.
- *
- * @param type_str type string
- * @param values text strings of values to be packed
- * @param data output buffer of values
- * @return 0 on success, non-0 on error
- */
-static int type_string_pack(const char *type_str, char * const values[],
- uint8_t *data)
-{
- size_t offset;
- uint32_t value;
-
- for (offset = 0; *type_str; type_str++, values++) {
- value = simple_strtoul(values[0], NULL, 0);
- switch (*type_str) {
- case 'b':
- data[offset] = value;
- offset += 1;
- break;
- case 'w':
- put_unaligned_be16(value, data + offset);
- offset += 2;
- break;
- case 'd':
- put_unaligned_be32(value, data + offset);
- offset += 4;
- break;
- default:
- return -1;
- }
- }
-
- return 0;
-}
-
-/**
- * Read values defined by a type string from a buffer, and write these values
- * to environment variables.
- *
- * @param type_str type string
- * @param data input buffer of values
- * @param vars names of environment variables
- * @return 0 on success, non-0 on error
- */
-static int type_string_write_vars(const char *type_str, uint8_t *data,
- char * const vars[])
-{
- size_t offset;
- uint32_t value;
-
- for (offset = 0; *type_str; type_str++, vars++) {
- switch (*type_str) {
- case 'b':
- value = data[offset];
- offset += 1;
- break;
- case 'w':
- value = get_unaligned_be16(data + offset);
- offset += 2;
- break;
- case 'd':
- value = get_unaligned_be32(data + offset);
- offset += 4;
- break;
- default:
- return -1;
- }
- if (env_set_ulong(*vars, value))
- return -1;
- }
-
- return 0;
-}
-
-static int do_tpm_startup(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- enum tpm_startup_type mode;
-
- if (argc != 2)
- return CMD_RET_USAGE;
- if (!strcasecmp("TPM_ST_CLEAR", argv[1])) {
- mode = TPM_ST_CLEAR;
- } else if (!strcasecmp("TPM_ST_STATE", argv[1])) {
- mode = TPM_ST_STATE;
- } else if (!strcasecmp("TPM_ST_DEACTIVATED", argv[1])) {
- mode = TPM_ST_DEACTIVATED;
- } else {
- printf("Couldn't recognize mode string: %s\n", argv[1]);
- return CMD_RET_FAILURE;
- }
-
- return report_return_code(tpm_startup(mode));
-}
-
-static int do_tpm_nv_define_space(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, perm, size;
-
- if (argc != 4)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[1], NULL, 0);
- perm = simple_strtoul(argv[2], NULL, 0);
- size = simple_strtoul(argv[3], NULL, 0);
-
- return report_return_code(tpm_nv_define_space(index, perm, size));
-}
-
-static int do_tpm_nv_read_value(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, count, rc;
- void *data;
-
- if (argc != 4)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[1], NULL, 0);
- data = (void *)simple_strtoul(argv[2], NULL, 0);
- count = simple_strtoul(argv[3], NULL, 0);
-
- rc = tpm_nv_read_value(index, data, count);
- if (!rc) {
- puts("area content:\n");
- print_byte_string(data, count);
- }
-
- return report_return_code(rc);
-}
-
-static int do_tpm_nv_write_value(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, rc;
- size_t count;
- void *data;
-
- if (argc != 3)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[1], NULL, 0);
- data = parse_byte_string(argv[2], NULL, &count);
- if (!data) {
- printf("Couldn't parse byte string %s\n", argv[2]);
- return CMD_RET_FAILURE;
- }
-
- rc = tpm_nv_write_value(index, data, count);
- free(data);
-
- return report_return_code(rc);
-}
-
-static int do_tpm_extend(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, rc;
- uint8_t in_digest[20], out_digest[20];
-
- if (argc != 3)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[1], NULL, 0);
- if (!parse_byte_string(argv[2], in_digest, NULL)) {
- printf("Couldn't parse byte string %s\n", argv[2]);
- return CMD_RET_FAILURE;
- }
-
- rc = tpm_extend(index, in_digest, out_digest);
- if (!rc) {
- puts("PCR value after execution of the command:\n");
- print_byte_string(out_digest, sizeof(out_digest));
- }
-
- return report_return_code(rc);
-}
-
-static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, count, rc;
- void *data;
-
- if (argc != 4)
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[1], NULL, 0);
- data = (void *)simple_strtoul(argv[2], NULL, 0);
- count = simple_strtoul(argv[3], NULL, 0);
-
- rc = tpm_pcr_read(index, data, count);
- if (!rc) {
- puts("Named PCR content:\n");
- print_byte_string(data, count);
- }
-
- return report_return_code(rc);
-}
-
-static int do_tpm_tsc_physical_presence(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint16_t presence;
-
- if (argc != 2)
- return CMD_RET_USAGE;
- presence = (uint16_t)simple_strtoul(argv[1], NULL, 0);
-
- return report_return_code(tpm_tsc_physical_presence(presence));
-}
-
-static int do_tpm_read_pubek(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t count, rc;
- void *data;
-
- if (argc != 3)
- return CMD_RET_USAGE;
- data = (void *)simple_strtoul(argv[1], NULL, 0);
- count = simple_strtoul(argv[2], NULL, 0);
-
- rc = tpm_read_pubek(data, count);
- if (!rc) {
- puts("pubek value:\n");
- print_byte_string(data, count);
- }
-
- return report_return_code(rc);
-}
-
-static int do_tpm_physical_set_deactivated(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint8_t state;
-
- if (argc != 2)
- return CMD_RET_USAGE;
- state = (uint8_t)simple_strtoul(argv[1], NULL, 0);
-
- return report_return_code(tpm_physical_set_deactivated(state));
-}
-
-static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t cap_area, sub_cap, rc;
- void *cap;
- size_t count;
-
- if (argc != 5)
- return CMD_RET_USAGE;
- cap_area = simple_strtoul(argv[1], NULL, 0);
- sub_cap = simple_strtoul(argv[2], NULL, 0);
- cap = (void *)simple_strtoul(argv[3], NULL, 0);
- count = simple_strtoul(argv[4], NULL, 0);
-
- rc = tpm_get_capability(cap_area, sub_cap, cap, count);
- if (!rc) {
- puts("capability information:\n");
- print_byte_string(cap, count);
- }
-
- return report_return_code(rc);
-}
-
-#define TPM_COMMAND_NO_ARG(cmd) \
-static int do_##cmd(cmd_tbl_t *cmdtp, int flag, \
- int argc, char * const argv[]) \
-{ \
- if (argc != 1) \
- return CMD_RET_USAGE; \
- return report_return_code(cmd()); \
-}
-
-TPM_COMMAND_NO_ARG(tpm_init)
-TPM_COMMAND_NO_ARG(tpm_self_test_full)
-TPM_COMMAND_NO_ARG(tpm_continue_self_test)
-TPM_COMMAND_NO_ARG(tpm_force_clear)
-TPM_COMMAND_NO_ARG(tpm_physical_enable)
-TPM_COMMAND_NO_ARG(tpm_physical_disable)
-
-static int get_tpm(struct udevice **devp)
-{
- int rc;
-
- rc = uclass_first_device_err(UCLASS_TPM, devp);
- if (rc) {
- printf("Could not find TPM (ret=%d)\n", rc);
- return CMD_RET_FAILURE;
- }
-
- return 0;
-}
-
-static int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct udevice *dev;
- char buf[80];
- int rc;
-
- rc = get_tpm(&dev);
- if (rc)
- return rc;
- rc = tpm_get_desc(dev, buf, sizeof(buf));
- if (rc < 0) {
- printf("Couldn't get TPM info (%d)\n", rc);
- return CMD_RET_FAILURE;
- }
- printf("%s\n", buf);
-
- return 0;
-}
-
-static int do_tpm_raw_transfer(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- struct udevice *dev;
- void *command;
- uint8_t response[1024];
- size_t count, response_length = sizeof(response);
- uint32_t rc;
-
- command = parse_byte_string(argv[1], NULL, &count);
- if (!command) {
- printf("Couldn't parse byte string %s\n", argv[1]);
- return CMD_RET_FAILURE;
- }
-
- rc = get_tpm(&dev);
- if (rc)
- return rc;
-
- rc = tpm_xfer(dev, command, count, response, &response_length);
- free(command);
- if (!rc) {
- puts("tpm response:\n");
- print_byte_string(response, response_length);
- }
-
- return report_return_code(rc);
-}
-
-static int do_tpm_nv_define(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, perm, size;
-
- if (argc != 4)
- return CMD_RET_USAGE;
- size = type_string_get_space_size(argv[1]);
- if (!size) {
- printf("Couldn't parse arguments\n");
- return CMD_RET_USAGE;
- }
- index = simple_strtoul(argv[2], NULL, 0);
- perm = simple_strtoul(argv[3], NULL, 0);
-
- return report_return_code(tpm_nv_define_space(index, perm, size));
-}
-
-static int do_tpm_nv_read(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, count, err;
- void *data;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- if (argc != 3 + type_string_get_num_values(argv[1]))
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[2], NULL, 0);
- data = type_string_alloc(argv[1], &count);
- if (!data) {
- printf("Couldn't parse arguments\n");
- return CMD_RET_USAGE;
- }
-
- err = tpm_nv_read_value(index, data, count);
- if (!err) {
- if (type_string_write_vars(argv[1], data, argv + 3)) {
- printf("Couldn't write to variables\n");
- err = ~0;
- }
- }
- free(data);
-
- return report_return_code(err);
-}
-
-static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t index, count, err;
- void *data;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- if (argc != 3 + type_string_get_num_values(argv[1]))
- return CMD_RET_USAGE;
- index = simple_strtoul(argv[2], NULL, 0);
- data = type_string_alloc(argv[1], &count);
- if (!data) {
- printf("Couldn't parse arguments\n");
- return CMD_RET_USAGE;
- }
- if (type_string_pack(argv[1], argv + 3, data)) {
- printf("Couldn't parse arguments\n");
- free(data);
- return CMD_RET_USAGE;
- }
-
- err = tpm_nv_write_value(index, data, count);
- free(data);
-
- return report_return_code(err);
-}
-
-#ifdef CONFIG_TPM_AUTH_SESSIONS
-
-static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t auth_handle, err;
-
- err = tpm_oiap(&auth_handle);
-
- return report_return_code(err);
-}
-
-#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
-static int do_tpm_load_key_by_sha1(cmd_tbl_t *cmdtp, int flag, int argc, char *
- const argv[])
-{
- uint32_t parent_handle = 0;
- uint32_t key_len, key_handle, err;
- uint8_t usage_auth[DIGEST_LENGTH];
- uint8_t parent_hash[DIGEST_LENGTH];
- void *key;
-
- if (argc < 5)
- return CMD_RET_USAGE;
-
- parse_byte_string(argv[1], parent_hash, NULL);
- key = (void *)simple_strtoul(argv[2], NULL, 0);
- key_len = simple_strtoul(argv[3], NULL, 0);
- if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
- return CMD_RET_FAILURE;
- parse_byte_string(argv[4], usage_auth, NULL);
-
- err = tpm_find_key_sha1(usage_auth, parent_hash, &parent_handle);
- if (err) {
- printf("Could not find matching parent key (err = %d)\n", err);
- return CMD_RET_FAILURE;
- }
-
- printf("Found parent key %08x\n", parent_handle);
-
- err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
- &key_handle);
- if (!err) {
- printf("Key handle is 0x%x\n", key_handle);
- env_set_hex("key_handle", key_handle);
- }
-
- return report_return_code(err);
-}
-#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
-
-static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t parent_handle, key_len, key_handle, err;
- uint8_t usage_auth[DIGEST_LENGTH];
- void *key;
-
- if (argc < 5)
- return CMD_RET_USAGE;
-
- parent_handle = simple_strtoul(argv[1], NULL, 0);
- key = (void *)simple_strtoul(argv[2], NULL, 0);
- key_len = simple_strtoul(argv[3], NULL, 0);
- if (strlen(argv[4]) != 2 * DIGEST_LENGTH)
- return CMD_RET_FAILURE;
- parse_byte_string(argv[4], usage_auth, NULL);
-
- err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth,
- &key_handle);
- if (!err)
- printf("Key handle is 0x%x\n", key_handle);
-
- return report_return_code(err);
-}
-
-static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- uint32_t key_handle, err;
- uint8_t usage_auth[DIGEST_LENGTH];
- uint8_t pub_key_buffer[TPM_PUBKEY_MAX_LENGTH];
- size_t pub_key_len = sizeof(pub_key_buffer);
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- key_handle = simple_strtoul(argv[1], NULL, 0);
- if (strlen(argv[2]) != 2 * DIGEST_LENGTH)
- return CMD_RET_FAILURE;
- parse_byte_string(argv[2], usage_auth, NULL);
-
- err = tpm_get_pub_key_oiap(key_handle, usage_auth,
- pub_key_buffer, &pub_key_len);
- if (!err) {
- printf("dump of received pub key structure:\n");
- print_byte_string(pub_key_buffer, pub_key_len);
- }
- return report_return_code(err);
-}
-
-TPM_COMMAND_NO_ARG(tpm_end_oiap)
-
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-
-#ifdef CONFIG_TPM_FLUSH_RESOURCES
-static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int type = 0;
-
- if (argc != 3)
- return CMD_RET_USAGE;
-
- if (!strcasecmp(argv[1], "key"))
- type = TPM_RT_KEY;
- else if (!strcasecmp(argv[1], "auth"))
- type = TPM_RT_AUTH;
- else if (!strcasecmp(argv[1], "hash"))
- type = TPM_RT_HASH;
- else if (!strcasecmp(argv[1], "trans"))
- type = TPM_RT_TRANS;
- else if (!strcasecmp(argv[1], "context"))
- type = TPM_RT_CONTEXT;
- else if (!strcasecmp(argv[1], "counter"))
- type = TPM_RT_COUNTER;
- else if (!strcasecmp(argv[1], "delegate"))
- type = TPM_RT_DELEGATE;
- else if (!strcasecmp(argv[1], "daa_tpm"))
- type = TPM_RT_DAA_TPM;
- else if (!strcasecmp(argv[1], "daa_v0"))
- type = TPM_RT_DAA_V0;
- else if (!strcasecmp(argv[1], "daa_v1"))
- type = TPM_RT_DAA_V1;
-
- if (!type) {
- printf("Resource type %s unknown.\n", argv[1]);
- return -1;
- }
-
- if (!strcasecmp(argv[2], "all")) {
- uint16_t res_count;
- uint8_t buf[288];
- uint8_t *ptr;
- int err;
- uint i;
-
- /* fetch list of already loaded resources in the TPM */
- err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
- sizeof(buf));
- if (err) {
- printf("tpm_get_capability returned error %d.\n", err);
- return -1;
- }
- res_count = get_unaligned_be16(buf);
- ptr = buf + 2;
- for (i = 0; i < res_count; ++i, ptr += 4)
- tpm_flush_specific(get_unaligned_be32(ptr), type);
- } else {
- uint32_t handle = simple_strtoul(argv[2], NULL, 0);
-
- if (!handle) {
- printf("Illegal resource handle %s\n", argv[2]);
- return -1;
- }
- tpm_flush_specific(cpu_to_be32(handle), type);
- }
-
- return 0;
-}
-#endif /* CONFIG_TPM_FLUSH_RESOURCES */
-
-#ifdef CONFIG_TPM_LIST_RESOURCES
-static int do_tpm_list(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int type = 0;
- uint16_t res_count;
- uint8_t buf[288];
- uint8_t *ptr;
- int err;
- uint i;
-
- if (argc != 2)
- return CMD_RET_USAGE;
-
- if (!strcasecmp(argv[1], "key"))
- type = TPM_RT_KEY;
- else if (!strcasecmp(argv[1], "auth"))
- type = TPM_RT_AUTH;
- else if (!strcasecmp(argv[1], "hash"))
- type = TPM_RT_HASH;
- else if (!strcasecmp(argv[1], "trans"))
- type = TPM_RT_TRANS;
- else if (!strcasecmp(argv[1], "context"))
- type = TPM_RT_CONTEXT;
- else if (!strcasecmp(argv[1], "counter"))
- type = TPM_RT_COUNTER;
- else if (!strcasecmp(argv[1], "delegate"))
- type = TPM_RT_DELEGATE;
- else if (!strcasecmp(argv[1], "daa_tpm"))
- type = TPM_RT_DAA_TPM;
- else if (!strcasecmp(argv[1], "daa_v0"))
- type = TPM_RT_DAA_V0;
- else if (!strcasecmp(argv[1], "daa_v1"))
- type = TPM_RT_DAA_V1;
-
- if (!type) {
- printf("Resource type %s unknown.\n", argv[1]);
- return -1;
- }
-
- /* fetch list of already loaded resources in the TPM */
- err = tpm_get_capability(TPM_CAP_HANDLE, type, buf,
- sizeof(buf));
- if (err) {
- printf("tpm_get_capability returned error %d.\n", err);
- return -1;
- }
- res_count = get_unaligned_be16(buf);
- ptr = buf + 2;
-
- printf("Resources of type %s (%02x):\n", argv[1], type);
- if (!res_count) {
- puts("None\n");
- } else {
- for (i = 0; i < res_count; ++i, ptr += 4)
- printf("Index %d: %08x\n", i, get_unaligned_be32(ptr));
- }
-
- return 0;
-}
-#endif /* CONFIG_TPM_LIST_RESOURCES */
-
-#define MAKE_TPM_CMD_ENTRY(cmd) \
- U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
-
-static cmd_tbl_t tpm_commands[] = {
- U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
- U_BOOT_CMD_MKENT(init, 0, 1,
- do_tpm_init, "", ""),
- U_BOOT_CMD_MKENT(startup, 0, 1,
- do_tpm_startup, "", ""),
- U_BOOT_CMD_MKENT(self_test_full, 0, 1,
- do_tpm_self_test_full, "", ""),
- U_BOOT_CMD_MKENT(continue_self_test, 0, 1,
- do_tpm_continue_self_test, "", ""),
- U_BOOT_CMD_MKENT(force_clear, 0, 1,
- do_tpm_force_clear, "", ""),
- U_BOOT_CMD_MKENT(physical_enable, 0, 1,
- do_tpm_physical_enable, "", ""),
- U_BOOT_CMD_MKENT(physical_disable, 0, 1,
- do_tpm_physical_disable, "", ""),
- U_BOOT_CMD_MKENT(nv_define_space, 0, 1,
- do_tpm_nv_define_space, "", ""),
- U_BOOT_CMD_MKENT(nv_read_value, 0, 1,
- do_tpm_nv_read_value, "", ""),
- U_BOOT_CMD_MKENT(nv_write_value, 0, 1,
- do_tpm_nv_write_value, "", ""),
- U_BOOT_CMD_MKENT(extend, 0, 1,
- do_tpm_extend, "", ""),
- U_BOOT_CMD_MKENT(pcr_read, 0, 1,
- do_tpm_pcr_read, "", ""),
- U_BOOT_CMD_MKENT(tsc_physical_presence, 0, 1,
- do_tpm_tsc_physical_presence, "", ""),
- U_BOOT_CMD_MKENT(read_pubek, 0, 1,
- do_tpm_read_pubek, "", ""),
- U_BOOT_CMD_MKENT(physical_set_deactivated, 0, 1,
- do_tpm_physical_set_deactivated, "", ""),
- U_BOOT_CMD_MKENT(get_capability, 0, 1,
- do_tpm_get_capability, "", ""),
- U_BOOT_CMD_MKENT(raw_transfer, 0, 1,
- do_tpm_raw_transfer, "", ""),
- U_BOOT_CMD_MKENT(nv_define, 0, 1,
- do_tpm_nv_define, "", ""),
- U_BOOT_CMD_MKENT(nv_read, 0, 1,
- do_tpm_nv_read, "", ""),
- U_BOOT_CMD_MKENT(nv_write, 0, 1,
- do_tpm_nv_write, "", ""),
-#ifdef CONFIG_TPM_AUTH_SESSIONS
- U_BOOT_CMD_MKENT(oiap, 0, 1,
- do_tpm_oiap, "", ""),
- U_BOOT_CMD_MKENT(end_oiap, 0, 1,
- do_tpm_end_oiap, "", ""),
- U_BOOT_CMD_MKENT(load_key2_oiap, 0, 1,
- do_tpm_load_key2_oiap, "", ""),
-#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
- U_BOOT_CMD_MKENT(load_key_by_sha1, 0, 1,
- do_tpm_load_key_by_sha1, "", ""),
-#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
- U_BOOT_CMD_MKENT(get_pub_key_oiap, 0, 1,
- do_tpm_get_pub_key_oiap, "", ""),
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-#ifdef CONFIG_TPM_FLUSH_RESOURCES
- U_BOOT_CMD_MKENT(flush, 0, 1,
- do_tpm_flush, "", ""),
-#endif /* CONFIG_TPM_FLUSH_RESOURCES */
-#ifdef CONFIG_TPM_LIST_RESOURCES
- U_BOOT_CMD_MKENT(list, 0, 1,
- do_tpm_list, "", ""),
-#endif /* CONFIG_TPM_LIST_RESOURCES */
-};
-
-static int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cmd_tbl_t *tpm_cmd;
-
- if (argc < 2)
- return CMD_RET_USAGE;
- tpm_cmd = find_cmd_tbl(argv[1], tpm_commands, ARRAY_SIZE(tpm_commands));
- if (!tpm_cmd)
- return CMD_RET_USAGE;
-
- return tpm_cmd->cmd(cmdtp, flag, argc - 1, argv + 1);
-}
-
-U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
-"Issue a TPM command",
-"cmd args...\n"
-" - Issue TPM command <cmd> with arguments <args...>.\n"
-"Admin Startup and State Commands:\n"
-" info - Show information about the TPM\n"
-" init\n"
-" - Put TPM into a state where it waits for 'startup' command.\n"
-" startup mode\n"
-" - Issue TPM_Starup command. <mode> is one of TPM_ST_CLEAR,\n"
-" TPM_ST_STATE, and TPM_ST_DEACTIVATED.\n"
-"Admin Testing Commands:\n"
-" self_test_full\n"
-" - Test all of the TPM capabilities.\n"
-" continue_self_test\n"
-" - Inform TPM that it should complete the self-test.\n"
-"Admin Opt-in Commands:\n"
-" physical_enable\n"
-" - Set the PERMANENT disable flag to FALSE using physical presence as\n"
-" authorization.\n"
-" physical_disable\n"
-" - Set the PERMANENT disable flag to TRUE using physical presence as\n"
-" authorization.\n"
-" physical_set_deactivated 0|1\n"
-" - Set deactivated flag.\n"
-"Admin Ownership Commands:\n"
-" force_clear\n"
-" - Issue TPM_ForceClear command.\n"
-" tsc_physical_presence flags\n"
-" - Set TPM device's Physical Presence flags to <flags>.\n"
-"The Capability Commands:\n"
-" get_capability cap_area sub_cap addr count\n"
-" - Read <count> bytes of TPM capability indexed by <cap_area> and\n"
-" <sub_cap> to memory address <addr>.\n"
-#if defined(CONFIG_TPM_FLUSH_RESOURCES) || defined(CONFIG_TPM_LIST_RESOURCES)
-"Resource management functions\n"
-#endif
-#ifdef CONFIG_TPM_FLUSH_RESOURCES
-" flush resource_type id\n"
-" - flushes a resource of type <resource_type> (may be one of key, auth,\n"
-" hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
-" and id <id> from the TPM. Use an <id> of \"all\" to flush all\n"
-" resources of that type.\n"
-#endif /* CONFIG_TPM_FLUSH_RESOURCES */
-#ifdef CONFIG_TPM_LIST_RESOURCES
-" list resource_type\n"
-" - lists resources of type <resource_type> (may be one of key, auth,\n"
-" hash, trans, context, counter, delegate, daa_tpm, daa_v0, daa_v1),\n"
-" contained in the TPM.\n"
-#endif /* CONFIG_TPM_LIST_RESOURCES */
-#ifdef CONFIG_TPM_AUTH_SESSIONS
-"Storage functions\n"
-" loadkey2_oiap parent_handle key_addr key_len usage_auth\n"
-" - loads a key data from memory address <key_addr>, <key_len> bytes\n"
-" into TPM using the parent key <parent_handle> with authorization\n"
-" <usage_auth> (20 bytes hex string).\n"
-#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
-" load_key_by_sha1 parent_hash key_addr key_len usage_auth\n"
-" - loads a key data from memory address <key_addr>, <key_len> bytes\n"
-" into TPM using the parent hash <parent_hash> (20 bytes hex string)\n"
-" with authorization <usage_auth> (20 bytes hex string).\n"
-#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
-" get_pub_key_oiap key_handle usage_auth\n"
-" - get the public key portion of a loaded key <key_handle> using\n"
-" authorization <usage auth> (20 bytes hex string)\n"
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-"Endorsement Key Handling Commands:\n"
-" read_pubek addr count\n"
-" - Read <count> bytes of the public endorsement key to memory\n"
-" address <addr>\n"
-"Integrity Collection and Reporting Commands:\n"
-" extend index digest_hex_string\n"
-" - Add a new measurement to a PCR. Update PCR <index> with the 20-bytes\n"
-" <digest_hex_string>\n"
-" pcr_read index addr count\n"
-" - Read <count> bytes from PCR <index> to memory address <addr>.\n"
-#ifdef CONFIG_TPM_AUTH_SESSIONS
-"Authorization Sessions\n"
-" oiap\n"
-" - setup an OIAP session\n"
-" end_oiap\n"
-" - terminates an active OIAP session\n"
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-"Non-volatile Storage Commands:\n"
-" nv_define_space index permission size\n"
-" - Establish a space at index <index> with <permission> of <size> bytes.\n"
-" nv_read_value index addr count\n"
-" - Read <count> bytes from space <index> to memory address <addr>.\n"
-" nv_write_value index addr count\n"
-" - Write <count> bytes from memory address <addr> to space <index>.\n"
-"Miscellaneous helper functions:\n"
-" raw_transfer byte_string\n"
-" - Send a byte string <byte_string> to TPM and print the response.\n"
-" Non-volatile storage helper functions:\n"
-" These helper functions treat a non-volatile space as a non-padded\n"
-" sequence of integer values. These integer values are defined by a type\n"
-" string, which is a text string of 'bwd' characters: 'b' means a 8-bit\n"
-" value, 'w' 16-bit value, 'd' 32-bit value. All helper functions take\n"
-" a type string as their first argument.\n"
-" nv_define type_string index perm\n"
-" - Define a space <index> with permission <perm>.\n"
-" nv_read types_string index vars...\n"
-" - Read from space <index> to environment variables <vars...>.\n"
-" nv_write types_string index values...\n"
-" - Write to space <index> from values <values...>.\n"
-);
#include <common.h>
#include <command.h>
#include <environment.h>
-#include <tpm.h>
+#include <tpm-v1.h>
/* Prints error and returns on failure */
#define TPM_CHECK(tpm_command) do { \
if ((long)bytes < 0) return NULL;
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+ if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
+ nb = roundup(bytes, alignment);
+ return malloc_simple(nb);
+ }
+#endif
+
/* If need less alignment than we give anyway, just relay to malloc */
if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes);
return count;
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT)
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT)
+/**
+ * fit_image_print_data() - prints out the hash node details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the hash node
+ * @p: pointer to prefix string
+ * @type: Type of information to print ("hash" or "sign")
+ *
+ * fit_image_print_data() lists properties for the processed hash node
+ *
+ * This function avoid using puts() since it prints a newline on the host
+ * but does not in U-Boot.
+ *
+ * returns:
+ * no returned results
+ */
+static void fit_image_print_data(const void *fit, int noffset, const char *p,
+ const char *type)
+{
+ const char *keyname;
+ uint8_t *value;
+ int value_len;
+ char *algo;
+ int required;
+ int ret, i;
+
+ debug("%s %s node: '%s'\n", p, type,
+ fit_get_name(fit, noffset, NULL));
+ printf("%s %s algo: ", p, type);
+ if (fit_image_hash_get_algo(fit, noffset, &algo)) {
+ printf("invalid/unsupported\n");
+ return;
+ }
+ printf("%s", algo);
+ keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
+ required = fdt_getprop(fit, noffset, "required", NULL) != NULL;
+ if (keyname)
+ printf(":%s", keyname);
+ if (required)
+ printf(" (required)");
+ printf("\n");
+
+ ret = fit_image_hash_get_value(fit, noffset, &value,
+ &value_len);
+ printf("%s %s value: ", p, type);
+ if (ret) {
+ printf("unavailable\n");
+ } else {
+ for (i = 0; i < value_len; i++)
+ printf("%02x", value[i]);
+ printf("\n");
+ }
+
+ debug("%s %s len: %d\n", p, type, value_len);
+
+ /* Signatures have a time stamp */
+ if (IMAGE_ENABLE_TIMESTAMP && keyname) {
+ time_t timestamp;
+
+ printf("%s Timestamp: ", p);
+ if (fit_get_timestamp(fit, noffset, ×tamp))
+ printf("unavailable\n");
+ else
+ genimg_print_time(timestamp);
+ }
+}
+
+/**
+ * fit_image_print_verification_data() - prints out the hash/signature details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the hash or signature node
+ * @p: pointer to prefix string
+ *
+ * This lists properties for the processed hash node
+ *
+ * returns:
+ * no returned results
+ */
+static void fit_image_print_verification_data(const void *fit, int noffset,
+ const char *p)
+{
+ const char *name;
+
+ /*
+ * Check subnode name, must be equal to "hash" or "signature".
+ * Multiple hash/signature nodes require unique unit node
+ * names, e.g. hash-1, hash-2, signature-1, signature-2, etc.
+ */
+ name = fit_get_name(fit, noffset, NULL);
+ if (!strncmp(name, FIT_HASH_NODENAME, strlen(FIT_HASH_NODENAME))) {
+ fit_image_print_data(fit, noffset, p, "Hash");
+ } else if (!strncmp(name, FIT_SIG_NODENAME,
+ strlen(FIT_SIG_NODENAME))) {
+ fit_image_print_data(fit, noffset, p, "Sign");
+ }
+}
+
+/**
+ * fit_conf_print - prints out the FIT configuration details
+ * @fit: pointer to the FIT format image header
+ * @noffset: offset of the configuration node
+ * @p: pointer to prefix string
+ *
+ * fit_conf_print() lists all mandatory properties for the processed
+ * configuration node.
+ *
+ * returns:
+ * no returned results
+ */
+static void fit_conf_print(const void *fit, int noffset, const char *p)
+{
+ char *desc;
+ const char *uname;
+ int ret;
+ int fdt_index, loadables_index;
+ int ndepth;
+
+ /* Mandatory properties */
+ ret = fit_get_desc(fit, noffset, &desc);
+ printf("%s Description: ", p);
+ if (ret)
+ printf("unavailable\n");
+ else
+ printf("%s\n", desc);
+
+ uname = fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
+ printf("%s Kernel: ", p);
+ if (!uname)
+ printf("unavailable\n");
+ else
+ printf("%s\n", uname);
+
+ /* Optional properties */
+ uname = fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
+ if (uname)
+ printf("%s Init Ramdisk: %s\n", p, uname);
+
+ uname = fdt_getprop(fit, noffset, FIT_FIRMWARE_PROP, NULL);
+ if (uname)
+ printf("%s Firmware: %s\n", p, uname);
+
+ for (fdt_index = 0;
+ uname = fdt_stringlist_get(fit, noffset, FIT_FDT_PROP,
+ fdt_index, NULL), uname;
+ fdt_index++) {
+ if (fdt_index == 0)
+ printf("%s FDT: ", p);
+ else
+ printf("%s ", p);
+ printf("%s\n", uname);
+ }
+
+ uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+ if (uname)
+ printf("%s FPGA: %s\n", p, uname);
+
+ /* Print out all of the specified loadables */
+ for (loadables_index = 0;
+ uname = fdt_stringlist_get(fit, noffset, FIT_LOADABLE_PROP,
+ loadables_index, NULL), uname;
+ loadables_index++) {
+ if (loadables_index == 0) {
+ printf("%s Loadables: ", p);
+ } else {
+ printf("%s ", p);
+ }
+ printf("%s\n", uname);
+ }
+
+ /* Process all hash subnodes of the component configuration node */
+ for (ndepth = 0, noffset = fdt_next_node(fit, noffset, &ndepth);
+ (noffset >= 0) && (ndepth > 0);
+ noffset = fdt_next_node(fit, noffset, &ndepth)) {
+ if (ndepth == 1) {
+ /* Direct child node of the component configuration node */
+ fit_image_print_verification_data(fit, noffset, p);
+ }
+ }
+}
+
/**
* fit_print_contents - prints out the contents of the FIT format image
* @fit: pointer to the FIT format image header
}
}
-/**
- * fit_image_print_data() - prints out the hash node details
- * @fit: pointer to the FIT format image header
- * @noffset: offset of the hash node
- * @p: pointer to prefix string
- * @type: Type of information to print ("hash" or "sign")
- *
- * fit_image_print_data() lists properties for the processed hash node
- *
- * This function avoid using puts() since it prints a newline on the host
- * but does not in U-Boot.
- *
- * returns:
- * no returned results
- */
-static void fit_image_print_data(const void *fit, int noffset, const char *p,
- const char *type)
-{
- const char *keyname;
- uint8_t *value;
- int value_len;
- char *algo;
- int required;
- int ret, i;
-
- debug("%s %s node: '%s'\n", p, type,
- fit_get_name(fit, noffset, NULL));
- printf("%s %s algo: ", p, type);
- if (fit_image_hash_get_algo(fit, noffset, &algo)) {
- printf("invalid/unsupported\n");
- return;
- }
- printf("%s", algo);
- keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
- required = fdt_getprop(fit, noffset, "required", NULL) != NULL;
- if (keyname)
- printf(":%s", keyname);
- if (required)
- printf(" (required)");
- printf("\n");
-
- ret = fit_image_hash_get_value(fit, noffset, &value,
- &value_len);
- printf("%s %s value: ", p, type);
- if (ret) {
- printf("unavailable\n");
- } else {
- for (i = 0; i < value_len; i++)
- printf("%02x", value[i]);
- printf("\n");
- }
-
- debug("%s %s len: %d\n", p, type, value_len);
-
- /* Signatures have a time stamp */
- if (IMAGE_ENABLE_TIMESTAMP && keyname) {
- time_t timestamp;
-
- printf("%s Timestamp: ", p);
- if (fit_get_timestamp(fit, noffset, ×tamp))
- printf("unavailable\n");
- else
- genimg_print_time(timestamp);
- }
-}
-
-/**
- * fit_image_print_verification_data() - prints out the hash/signature details
- * @fit: pointer to the FIT format image header
- * @noffset: offset of the hash or signature node
- * @p: pointer to prefix string
- *
- * This lists properties for the processed hash node
- *
- * returns:
- * no returned results
- */
-static void fit_image_print_verification_data(const void *fit, int noffset,
- const char *p)
-{
- const char *name;
-
- /*
- * Check subnode name, must be equal to "hash" or "signature".
- * Multiple hash/signature nodes require unique unit node
- * names, e.g. hash-1, hash-2, signature-1, signature-2, etc.
- */
- name = fit_get_name(fit, noffset, NULL);
- if (!strncmp(name, FIT_HASH_NODENAME, strlen(FIT_HASH_NODENAME))) {
- fit_image_print_data(fit, noffset, p, "Hash");
- } else if (!strncmp(name, FIT_SIG_NODENAME,
- strlen(FIT_SIG_NODENAME))) {
- fit_image_print_data(fit, noffset, p, "Sign");
- }
-}
-
/**
* fit_image_print - prints out the FIT component image details
* @fit: pointer to the FIT format image header
fit_image_get_comp(fit, image_noffset, &comp);
printf("%s Compression: %s\n", p, genimg_get_comp_name(comp));
- ret = fit_image_get_data(fit, image_noffset, &data, &size);
+ ret = fit_image_get_data_and_size(fit, image_noffset, &data, &size);
#ifndef USE_HOSTCC
printf("%s Data Start: ", p);
}
}
}
-
-#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT) */
+#else
+void fit_print_contents(const void *fit) { }
+void fit_image_print(const void *fit, int image_noffset, const char *p) { }
+#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) */
/**
* fit_get_desc - get node description property
return 0;
}
+/**
+ * fit_image_get_data_and_size - get data and its size including
+ * both embedded and external data
+ * @fit: pointer to the FIT format image header
+ * @noffset: component image node offset
+ * @data: double pointer to void, will hold data property's data address
+ * @size: pointer to size_t, will hold data property's data size
+ *
+ * fit_image_get_data_and_size() finds data and its size including
+ * both embedded and external data. If the property is found
+ * its data start address and size are returned to the caller.
+ *
+ * returns:
+ * 0, on success
+ * otherwise, on failure
+ */
+int fit_image_get_data_and_size(const void *fit, int noffset,
+ const void **data, size_t *size)
+{
+ bool external_data = false;
+ int offset;
+ int len;
+ int ret;
+
+ if (!fit_image_get_data_position(fit, noffset, &offset)) {
+ external_data = true;
+ } else if (!fit_image_get_data_offset(fit, noffset, &offset)) {
+ external_data = true;
+ /*
+ * For FIT with external data, figure out where
+ * the external images start. This is the base
+ * for the data-offset properties in each image.
+ */
+ offset += ((fdt_totalsize(fit) + 3) & ~3);
+ }
+
+ if (external_data) {
+ debug("External Data\n");
+ ret = fit_image_get_data_size(fit, noffset, &len);
+ *data = fit + offset;
+ *size = len;
+ } else {
+ ret = fit_image_get_data(fit, noffset, data, size);
+ }
+
+ return ret;
+}
+
/**
* fit_image_hash_get_algo - get hash algorithm name
* @fit: pointer to the FIT format image header
char *err_msg = "";
/* Get image data and data length */
- if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+ if (fit_image_get_data_and_size(fit, image_noffset, &data, &size)) {
err_msg = "Can't get image data/size";
printf("error!\n%s for '%s' hash node in '%s' image node\n",
err_msg, fit_get_name(fit, noffset, NULL),
return fit_conf_get_prop_node_index(fit, noffset, prop_name, 0);
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT)
-/**
- * fit_conf_print - prints out the FIT configuration details
- * @fit: pointer to the FIT format image header
- * @noffset: offset of the configuration node
- * @p: pointer to prefix string
- *
- * fit_conf_print() lists all mandatory properties for the processed
- * configuration node.
- *
- * returns:
- * no returned results
- */
-void fit_conf_print(const void *fit, int noffset, const char *p)
-{
- char *desc;
- const char *uname;
- int ret;
- int fdt_index, loadables_index;
- int ndepth;
-
- /* Mandatory properties */
- ret = fit_get_desc(fit, noffset, &desc);
- printf("%s Description: ", p);
- if (ret)
- printf("unavailable\n");
- else
- printf("%s\n", desc);
-
- uname = fdt_getprop(fit, noffset, FIT_KERNEL_PROP, NULL);
- printf("%s Kernel: ", p);
- if (uname == NULL)
- printf("unavailable\n");
- else
- printf("%s\n", uname);
-
- /* Optional properties */
- uname = fdt_getprop(fit, noffset, FIT_RAMDISK_PROP, NULL);
- if (uname)
- printf("%s Init Ramdisk: %s\n", p, uname);
-
- uname = fdt_getprop(fit, noffset, FIT_FIRMWARE_PROP, NULL);
- if (uname)
- printf("%s Firmware: %s\n", p, uname);
-
- for (fdt_index = 0;
- uname = fdt_stringlist_get(fit, noffset, FIT_FDT_PROP,
- fdt_index, NULL), uname;
- fdt_index++) {
-
- if (fdt_index == 0)
- printf("%s FDT: ", p);
- else
- printf("%s ", p);
- printf("%s\n", uname);
- }
-
- uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
- if (uname)
- printf("%s FPGA: %s\n", p, uname);
-
- /* Print out all of the specified loadables */
- for (loadables_index = 0;
- uname = fdt_stringlist_get(fit, noffset, FIT_LOADABLE_PROP,
- loadables_index, NULL), uname;
- loadables_index++) {
- if (loadables_index == 0) {
- printf("%s Loadables: ", p);
- } else {
- printf("%s ", p);
- }
- printf("%s\n", uname);
- }
-
- /* Process all hash subnodes of the component configuration node */
- for (ndepth = 0, noffset = fdt_next_node(fit, noffset, &ndepth);
- (noffset >= 0) && (ndepth > 0);
- noffset = fdt_next_node(fit, noffset, &ndepth)) {
- if (ndepth == 1) {
- /* Direct child node of the component configuration node */
- fit_image_print_verification_data(fit, noffset, p);
- }
- }
-}
-#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_FIT_SPL_PRINT) */
-
static int fit_image_select(const void *fit, int rd_noffset, int verify)
{
fit_image_print(fit, rd_noffset, " ");
return FIT_LOADABLE_PROP;
case IH_TYPE_FPGA:
return FIT_FPGA_PROP;
+ case IH_TYPE_STANDALONE:
+ return FIT_STANDALONE_PROP;
}
return "unknown";
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL_OK);
/* get image data address and length */
- if (fit_image_get_data(fit, noffset, &buf, &size)) {
+ if (fit_image_get_data_and_size(fit, noffset, &buf, &size)) {
printf("Could not find %s subimage data!\n", prop_name);
bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
return -ENOENT;
spl_image->name = "U-Boot";
}
+#ifdef CONFIG_SPL_LOAD_FIT_FULL
+/* Parse and load full fitImage in SPL */
+static int spl_load_fit_image(struct spl_image_info *spl_image,
+ const struct image_header *header)
+{
+ bootm_headers_t images;
+ const char *fit_uname_config = NULL;
+ const char *fit_uname_fdt = FIT_FDT_PROP;
+ const char *uname;
+ ulong fw_data = 0, dt_data = 0, img_data = 0;
+ ulong fw_len = 0, dt_len = 0, img_len = 0;
+ int idx, conf_noffset;
+ int ret;
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ ret = fit_image_load(&images, (ulong)header,
+ NULL, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_STANDALONE, -1,
+ FIT_LOAD_REQUIRED, &fw_data, &fw_len);
+ if (ret < 0)
+ return ret;
+
+ spl_image->size = fw_len;
+ spl_image->entry_point = fw_data;
+ spl_image->load_addr = fw_data;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+
+ debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
+ (int)sizeof(spl_image->name), spl_image->name,
+ spl_image->load_addr, spl_image->size);
+
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ fit_image_load(&images, (ulong)header,
+ &fit_uname_fdt, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_FLATDT, -1,
+ FIT_LOAD_OPTIONAL, &dt_data, &dt_len);
+
+ conf_noffset = fit_conf_get_node((const void *)header,
+ fit_uname_config);
+ if (conf_noffset <= 0)
+ return 0;
+
+ for (idx = 0;
+ uname = fdt_stringlist_get((const void *)header, conf_noffset,
+ FIT_LOADABLE_PROP, idx,
+ NULL), uname;
+ idx++)
+ {
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ images.verify = 1;
+#endif
+ ret = fit_image_load(&images, (ulong)header,
+ &uname, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_LOADABLE, -1,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
int spl_parse_image_header(struct spl_image_info *spl_image,
const struct image_header *header)
{
+#ifdef CONFIG_SPL_LOAD_FIT_FULL
+ int ret = spl_load_fit_image(spl_image, header);
+
+ if (!ret)
+ return ret;
+#endif
if (image_get_magic(header) == IH_MAGIC) {
#ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT
u32 header_size = sizeof(struct image_header);
return (data_size + info->bl_len - 1) / info->bl_len;
}
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+__weak int spl_load_fpga_image(struct spl_load_info *info, size_t length,
+ int nr_sectors, int sector_offset)
+{
+ return 0;
+}
+#endif
+
/**
* spl_load_fit_image(): load the image described in a certain FIT node
* @info: points to information about the device to load data from
void *fit, ulong base_offset, int node,
struct spl_image_info *image_info)
{
- int offset;
+ int offset, sector_offset;
size_t length;
int len;
ulong size;
overhead = get_aligned_image_overhead(info, offset);
nr_sectors = get_aligned_image_size(info, length, offset);
+ sector_offset = sector + get_aligned_image_offset(info, offset);
- if (info->read(info,
- sector + get_aligned_image_offset(info, offset),
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+ if (type == IH_TYPE_FPGA) {
+ return spl_load_fpga_image(info, length, nr_sectors,
+ sector_offset);
+ }
+#endif
+
+ if (info->read(info, sector_offset,
nr_sectors, (void *)load_ptr) != nr_sectors)
return -EIO;
return -1;
}
+#ifdef CONFIG_SPL_FPGA_SUPPORT
+ node = spl_fit_get_image_node(fit, images, "fpga", 0);
+ if (node >= 0) {
+ /* Load the image and set up the spl_image structure */
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ spl_image);
+ if (ret) {
+ printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
+ return ret;
+ }
+ node = -1;
+ }
+#endif
+
/*
* Find the U-Boot image using the following search order:
* - start at 'firmware' (e.g. an ARM Trusted Firmware)
CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_DEFAULT_DEVICE_TREE="ae350"
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_AUTO_COMPLETE is not set
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_DM_ETH=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATCSPI200_SPI=y
+CONFIG_TIMER=y
+CONFIG_ATCPIT100_TIMER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_CPU_RISCV_64=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_DEFAULT_DEVICE_TREE="axs101"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xe0022000
+CONFIG_DEBUG_UART_CLOCK=33333333
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_DEFAULT_DEVICE_TREE="axs103"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200n8"
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xe0022000
+CONFIG_DEBUG_UART_CLOCK=33333333
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche"
CONFIG_R8A7792=y
CONFIG_TARGET_BLANCHE=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x18000000
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_SH_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_STORAGE=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" D2 v2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net"
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_FULL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_MVGBE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B450V3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b450v3.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_EXT=y
-CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B650V3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b650v3.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_EXT=y
-CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B850V3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b850v3.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_EXT=y
-CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_GE_BX50V3=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_EXT=y
+CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
+CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_CMD_E1000=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
-CONFIG_OF_LIBFDT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_DEFAULT_DEVICE_TREE="hsdk"
+CONFIG_DEBUG_UART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xf0005000
+CONFIG_DEBUG_UART_CLOCK=33333333
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_IB62X0=y
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
CONFIG_IDENT_STRING=" Iomega iConnect"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
-CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6DL_MAMOJ=y
+CONFIG_SPL_OS_BOOT=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_SYS_PROMPT="=> "
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_DFU_MMC=y
+CONFIG_IMX_THERMAL=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SECURE_BOOT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" IS v2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile COGE5UN"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile NUSA"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile SUGP1"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile SUV31"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_TARGET_KP_IMX53=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR=1
+CONFIG_PHY_SMSC=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_MC34708=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=2
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-CHLv2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MVSATA_IDE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-XHL"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_API=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MVSATA_IDE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_IDENT_STRING="\nKeymile COGE3UN"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_EEPROM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_MVEBU=y
CONFIG_BLOCK_CACHE=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_TARGET_MX31PDK=y
+CONFIG_ARCH_MX31=y
CONFIG_SYS_TEXT_BASE=0x87e00000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX31PDK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_EXT=y
CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_NITROGEN6X=y
CONFIG_CMD_HDMIDETECT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
+# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" 2Big v2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big"
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Lite"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS Max v2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Mini"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_CMD_FAT=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_KIRKWOOD_SPI=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_ARC_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xc0fc1000
+CONFIG_DEBUG_UART_CLOCK=70000000
+CONFIG_ARC_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_ARC_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xc0fc1000
+CONFIG_DEBUG_UART_CLOCK=70000000
+CONFIG_ARC_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_ARC_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xc0fc1000
+CONFIG_DEBUG_UART_CLOCK=70000000
+CONFIG_ARC_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
+CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_OF_EMBED=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_ARC_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xc0fc1000
+CONFIG_DEBUG_UART_CLOCK=70000000
+CONFIG_ARC_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_RISCV=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_DEFAULT_DEVICE_TREE="ae250"
-CONFIG_TARGET_NX25_AE250=y
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="RISC-V # "
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SF_TEST=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_BOARD=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM=y
-CONFIG_CLK=y
-CONFIG_MMC=y
-CONFIG_DM_MMC=y
-CONFIG_FTSDC010=y
-CONFIG_FTSDC010_SDIO=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DM_ETH=y
-CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_ATCSPI200_SPI=y
-CONFIG_TIMER=y
-CONFIG_ATCPIT100_TIMER=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Base"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=2
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Client"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=2
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_OPENRD=y
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate"
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
CONFIG_BOOTDELAY=3
CONFIG_LOGLEVEL=2
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
CONFIG_IDENT_STRING="\nPogo E02"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
CONFIG_PMIC_PM8916=y
CONFIG_PMIC_RK8XX=y
CONFIG_PMIC_S2MPS11=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
CONFIG_PMIC_PM8916=y
CONFIG_PMIC_S2MPS11=y
CONFIG_DM_PMIC_SANDBOX=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
CONFIG_PMIC_PM8916=y
CONFIG_PMIC_RK8XX=y
CONFIG_PMIC_S2MPS11=y
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_MVSATA_IDE=y
CONFIG_NETDEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
-CONFIG_OF_LIBFDT=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
--- /dev/null
+AX25 is Andes CPU IP to adopt RISC-V architecture.
+
+Features
+========
+
+CPU Core
+ - 5-stage in-order execution pipeline
+ - Hardware Multiplier
+ - radix-2/radix-4/radix-16/radix-256/fast
+ - Hardware Divider
+ - Optional branch prediction
+ - Machine mode and optional user mode
+ - Optional performance monitoring
+
+ISA
+ - RV64I base integer instructions
+ - RVC for 16-bit compressed instructions
+ - RVM for multiplication and division instructions
+
+Memory subsystem
+ - I & D local memory
+ - Size: 4KB to 16MB
+ - Memory subsyetem soft-error protection
+ - Protection scheme: parity-checking or error-checking-and-correction (ECC)
+ - Automatic hardware error correction
+
+Bus
+ - Interface Protocol
+ - Synchronous AHB (32-bit/64-bit data-width), or
+ - Synchronous AXI4 (64-bit data-width)
+
+Power management
+ - Wait for interrupt (WFI) mode
+
+Debug
+ - Configurable number of breakpoints: 2/4/8
+ - External Debug Module
+ - AHB slave port
+ - External JTAG debug transport module
+
+Platform Level Interrupt Controller (PLIC)
+ - AHB slave port
+ - Configurable number of interrupts: 1-1023
+ - Configurable number of interrupt priorities: 3/7/15/63/127/255
+ - Configurable number of targets: 1-16
+ - Preempted interrupt priority stack
+++ /dev/null
-NX25 is Andes CPU IP to adopt RISC-V architecture.
-
-Features
-========
-
-CPU Core
- - 5-stage in-order execution pipeline
- - Hardware Multiplier
- - radix-2/radix-4/radix-16/radix-256/fast
- - Hardware Divider
- - Optional branch prediction
- - Machine mode and optional user mode
- - Optional performance monitoring
-
-ISA
- - RV64I base integer instructions
- - RVC for 16-bit compressed instructions
- - RVM for multiplication and division instructions
-
-Memory subsystem
- - I & D local memory
- - Size: 4KB to 16MB
- - Memory subsyetem soft-error protection
- - Protection scheme: parity-checking or error-checking-and-correction (ECC)
- - Automatic hardware error correction
-
-Bus
- - Interface Protocol
- - Synchronous AHB (32-bit/64-bit data-width), or
- - Synchronous AXI4 (64-bit data-width)
-
-Power management
- - Wait for interrupt (WFI) mode
-
-Debug
- - Configurable number of breakpoints: 2/4/8
- - External Debug Module
- - AHB slave port
- - External JTAG debug transport module
-
-Platform Level Interrupt Controller (PLIC)
- - AHB slave port
- - Configurable number of interrupts: 1-1023
- - Configurable number of interrupt priorities: 3/7/15/63/127/255
- - Configurable number of targets: 1-16
- - Preempted interrupt priority stack
+++ /dev/null
-Andes Technology SoC AE250
-===========================
-
-AE250 is the mainline SoC produced by Andes Technology using NX25 CPU core
-base on RISC-V architecture.
-
-AE250 has integrated both AHB and APB bus and many periphals for application
-and product development.
-
-NX25-AE250
-=========
-
-NX25-AE250 is the SoC with AE250 hardcore CPU.
-
-Configurations
-==============
-
-CONFIG_SKIP_LOWLEVEL_INIT:
- If you want to boot this system from SPI ROM and bypass e-bios (the
- other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
- in "include/configs/nx25-ae250.h".
-
-Build and boot steps
-====================
-
-build:
-1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
-2. Use `make nx25-ae250_defconfig` in u-boot root to build the image.
-
-Verification
-====================
-
-Target
-====================
-1. startup
-2. relocation
-3. timer driver
-4. uart driver
-5. mac driver
-6. mmc driver
-7. spi driver
-
-Steps
-====================
-1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
-2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
-3. Ping a server by mac driver
-4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
-5. Burn this u-boot image to spi rom by spi driver
-6. Re-boot u-boot from spi flash with power off and power on.
-
-Messages of U-Boot boot on AE250 board
-======================================
-U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
-
-DRAM: 1 GiB
-MMC: mmc@f0e00000: 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
-eth0: mac@e0100000
-
-RISC-V # version
-U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
-
-riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
-GNU ld (GNU Binutils) 2.29
-
-RISC-V # setenv ipaddr 10.0.4.200 ;
-RISC-V # setenv serverip 10.0.4.97 ;
-RISC-V # ping 10.0.4.97 ;
-Using mac@e0100000 device
-host 10.0.4.97 is alive
-
-RISC-V # mmc rescan
-RISC-V # fatls mmc 0:1
- 318907 u-boot-ae250-64.bin
- 1252 hello_world_ae250_32.bin
- 328787 u-boot-ae250-32.bin
-
-3 file(s), 0 dir(s)
-
-RISC-V # sf probe 0:0 50000000 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-
-RISC-V # sf test 0x100000 0x1000
-SPI flash test:
-0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
-1 check: 29 ticks, 137 KiB/s 1.096 Mbps
-2 write: 40 ticks, 100 KiB/s 0.800 Mbps
-3 read: 20 ticks, 200 KiB/s 1.600 Mbps
-Test passed
-0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
-1 check: 29 ticks, 137 KiB/s 1.096 Mbps
-2 write: 40 ticks, 100 KiB/s 0.800 Mbps
-3 read: 20 ticks, 200 KiB/s 1.600 Mbps
-
-RISC-V # fatload mmc 0:1 0x600000 u-boot-ae250-32.bin
-reading u-boot-ae250-32.bin
-328787 bytes read in 324 ms (990.2 KiB/s)
-
-RISC-V # sf erase 0x0 0x51000
-SF: 331776 bytes @ 0x0 Erased: OK
-
-RISC-V # sf write 0x600000 0x0 0x50453
-device 0 offset 0x0, size 0x50453
-SF: 328787 bytes @ 0x0 Written: OK
-
-RISC-V # crc32 0x600000 0x50453
-crc32 for 00600000 ... 00650452 ==> 692dc44a
-
-RISC-V # crc32 0x80000000 0x50453
-crc32 for 80000000 ... 80050452 ==> 692dc44a
-RISC-V #
-
-*** power-off and power-on, this U-Boot is booted from spi flash ***
-
-U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
-
-DRAM: 1 GiB
-MMC: mmc@f0e00000: 0
-SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
-eth0: mac@e0100000
-RISC-V #
-
-
-Boot bbl and riscv-linux via U-Boot on QEMU
-===========================================
-1. Build riscv-linux
-2. Build bbl and riscv-linux with --with-payload
-3. Prepare ae250.dtb
-4. Creating OS-kernel images
- ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
- Image Name:
- Created: Tue Mar 13 10:06:42 2018
- Image Type: RISC-V Linux Kernel Image (uncompressed)
- Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
- Load Address: 00000000
- Entry Point: 00000000
-
-4. Copy bootmImage-bbl.bin and ae250.dtb to qemu sd card image
-5. Message of booting riscv-linux from bbl via u-boot on qemu
-
-U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
-
-DRAM: 1 GiB
-main-loop: WARNING: I/O thread spun for 1000 iterations
-MMC: mmc@f0e00000: 0
-Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
-
-Failed (-22)
-In: serial@f0300000
-Out: serial@f0300000
-Err: serial@f0300000
-Net:
-Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
-eth0: mac@e0100000
-RISC-V # mmc rescan
-RISC-V # mmc part
-
-Partition Map for MMC device 0 -- Partition Type: DOS
-
-Part Start Sector Num Sectors UUID Type
-RISC-V # fatls mmc 0:0
- 17901268 bootmImage-bbl.bin
- 1954 ae2xx.dtb
-
-2 file(s), 0 dir(s)
-
-RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
-17901268 bytes read in 4642 ms (3.7 MiB/s)
-RISC-V # fatload mmc 0:0 0x2000000 ae250.dtb
-1954 bytes read in 1 ms (1.9 MiB/s)
-RISC-V # setenv bootm_size 0x2000000
-RISC-V # setenv fdt_high 0x1f00000
-RISC-V # bootm 0x00600000 - 0x2000000
-## Booting kernel from Legacy Image at 00600000 ...
- Image Name:
- Image Type: RISC-V Linux Kernel Image (uncompressed)
- Data Size: 17901204 Bytes = 17.1 MiB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
-## Flattened Device Tree blob at 02000000
- Booting using the fdt blob at 0x2000000
- Loading Kernel Image ... OK
- Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
-[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
-[ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
-[ 0.000000] bootconsole [early0] enabled
-[ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
-[ 0.000000] Zone ranges:
-[ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] Normal empty
-[ 0.000000] Movable zone start for each node
-[ 0.000000] Early memory node ranges
-[ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
-[ 0.000000] elf_hwcap is 0x112d
-[ 0.000000] random: fast init done
-[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
-[ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
-[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
-[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
-[ 0.000000] Sorting __ex_table...
-[ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
-[ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
-[ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
-[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
-[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
-[ 0.000000] pid_max: default: 32768 minimum: 301
-[ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
-[ 0.056000] devtmpfs: initialized
-[ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
-[ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
-[ 0.068000] NET: Registered protocol family 16
-[ 0.080000] vgaarb: loaded
-[ 0.084000] clocksource: Switched to clocksource riscv_clocksource
-[ 0.088000] NET: Registered protocol family 2
-[ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
-[ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
-[ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
-[ 0.104000] NET: Registered protocol family 1
-[ 0.616000] Unpacking initramfs...
-[ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
-[ 1.244000] io scheduler noop registered
-[ 1.244000] io scheduler cfq registered (default)
-[ 1.244000] io scheduler mq-deadline registered
-[ 1.248000] io scheduler kyber registered
-[ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 1.368000] console [ttyS0] disabled
-[ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
-[ 1.392000] console [ttyS0] enabled
-[ 1.392000] ftmac100: Loading version 0.2 ...
-[ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
-[ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
-[ 1.404000] IR NEC protocol handler initialized
-[ 1.404000] IR RC5(x/sz) protocol handler initialized
-[ 1.404000] IR RC6 protocol handler initialized
-[ 1.404000] IR JVC protocol handler initialized
-[ 1.408000] IR Sony protocol handler initialized
-[ 1.408000] IR SANYO protocol handler initialized
-[ 1.408000] IR Sharp protocol handler initialized
-[ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
-[ 1.412000] IR XMP protocol handler initialized
-[ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
-[ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
-[ 1.464000] bootconsole [early0] disabled
-[ 1.508000] Freeing unused kernel memory: 12076K
-[ 1.512000] This architecture does not have kernel memory protection.
-[ 1.520000] mmc0: new SD card at address 4567
-[ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
-[ 1.844000] mmcblk0:
-Wed Dec 1 10:00:00 CST 2010
-/ #
-
-
-
-TODO
-==================================================
-Boot bbl and riscv-linux via U-Boot on AE250 board
--- /dev/null
+Andes Technology SoC AE350
+===========================
+
+AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
+base on RISC-V architecture.
+
+AE350 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+AX25-AE350
+=========
+
+AX25-AE350 is the SoC with AE350 hardcore CPU.
+
+Configurations
+==============
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from SPI ROM and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/ax25-ae350.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make ax25-ae350_defconfig` in u-boot root to build the image.
+
+Verification
+====================
+
+Target
+====================
+1. startup
+2. relocation
+3. timer driver
+4. uart driver
+5. mac driver
+6. mmc driver
+7. spi driver
+
+Steps
+====================
+1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
+2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
+3. Ping a server by mac driver
+4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
+5. Burn this u-boot image to spi rom by spi driver
+6. Re-boot u-boot from spi flash with power off and power on.
+
+Messages of U-Boot boot on AE350 board
+======================================
+U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800)
+
+DRAM: 1 GiB
+MMC: mmc@f0e00000: 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10
+eth0: mac@e0100000
+
+RISC-V # version
+U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
+
+riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0
+GNU ld (GNU Binutils) 2.29
+
+RISC-V # setenv ipaddr 10.0.4.200 ;
+RISC-V # setenv serverip 10.0.4.97 ;
+RISC-V # ping 10.0.4.97 ;
+Using mac@e0100000 device
+host 10.0.4.97 is alive
+
+RISC-V # mmc rescan
+RISC-V # fatls mmc 0:1
+ 318907 u-boot-ae350-64.bin
+ 1252 hello_world_ae350_32.bin
+ 328787 u-boot-ae350-32.bin
+
+3 file(s), 0 dir(s)
+
+RISC-V # sf probe 0:0 50000000 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+
+RISC-V # sf test 0x100000 0x1000
+SPI flash test:
+0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+Test passed
+0 erase: 36 ticks, 111 KiB/s 0.888 Mbps
+1 check: 29 ticks, 137 KiB/s 1.096 Mbps
+2 write: 40 ticks, 100 KiB/s 0.800 Mbps
+3 read: 20 ticks, 200 KiB/s 1.600 Mbps
+
+RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
+reading u-boot-ae350-32.bin
+328787 bytes read in 324 ms (990.2 KiB/s)
+
+RISC-V # sf erase 0x0 0x51000
+SF: 331776 bytes @ 0x0 Erased: OK
+
+RISC-V # sf write 0x600000 0x0 0x50453
+device 0 offset 0x0, size 0x50453
+SF: 328787 bytes @ 0x0 Written: OK
+
+RISC-V # crc32 0x600000 0x50453
+crc32 for 00600000 ... 00650452 ==> 692dc44a
+
+RISC-V # crc32 0x80000000 0x50453
+crc32 for 80000000 ... 80050452 ==> 692dc44a
+RISC-V #
+
+*** power-off and power-on, this U-Boot is booted from spi flash ***
+
+U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800)
+
+DRAM: 1 GiB
+MMC: mmc@f0e00000: 0
+SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5
+eth0: mac@e0100000
+RISC-V #
+
+
+Boot bbl and riscv-linux via U-Boot on QEMU
+===========================================
+1. Build riscv-linux
+2. Build bbl and riscv-linux with --with-payload
+3. Prepare ae350.dtb
+4. Creating OS-kernel images
+ ./mkimage -A riscv -O linux -T kernel -C none -a 0x0000 -e 0x0000 -d bbl.bin bootmImage-bbl.bin
+ Image Name:
+ Created: Tue Mar 13 10:06:42 2018
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17481.64 KiB = 17.07 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+
+4. Copy bootmImage-bbl.bin and ae350.dtb to qemu sd card image
+5. Message of booting riscv-linux from bbl via u-boot on qemu
+
+U-Boot 2018.03-rc4-00031-g2631273 (Mar 13 2018 - 15:02:55 +0800)
+
+DRAM: 1 GiB
+main-loop: WARNING: I/O thread spun for 1000 iterations
+MMC: mmc@f0e00000: 0
+Loading Environment from SPI Flash... *** Warning - spi_flash_probe_bus_cs() failed, using default environment
+
+Failed (-22)
+In: serial@f0300000
+Out: serial@f0300000
+Err: serial@f0300000
+Net:
+Warning: mac@e0100000 (eth0) using random MAC address - 02:00:00:00:00:00
+eth0: mac@e0100000
+RISC-V # mmc rescan
+RISC-V # mmc part
+
+Partition Map for MMC device 0 -- Partition Type: DOS
+
+Part Start Sector Num Sectors UUID Type
+RISC-V # fatls mmc 0:0
+ 17901268 bootmImage-bbl.bin
+ 1954 ae2xx.dtb
+
+2 file(s), 0 dir(s)
+
+RISC-V # fatload mmc 0:0 0x00600000 bootmImage-bbl.bin
+17901268 bytes read in 4642 ms (3.7 MiB/s)
+RISC-V # fatload mmc 0:0 0x2000000 ae350.dtb
+1954 bytes read in 1 ms (1.9 MiB/s)
+RISC-V # setenv bootm_size 0x2000000
+RISC-V # setenv fdt_high 0x1f00000
+RISC-V # bootm 0x00600000 - 0x2000000
+## Booting kernel from Legacy Image at 00600000 ...
+ Image Name:
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 17901204 Bytes = 17.1 MiB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+## Flattened Device Tree blob at 02000000
+ Booting using the fdt blob at 0x2000000
+ Loading Kernel Image ... OK
+ Loading Device Tree to 0000000001efc000, end 0000000001eff7a1 ... OK
+[ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x200000
+[ 0.000000] Linux version 4.14.0-00046-gf3e439f-dirty (rick@atcsqa06) (gcc version 7.1.1 20170509 (GCC)) #1 Tue Jan 9 16:34:25 CST 2018
+[ 0.000000] bootconsole [early0] enabled
+[ 0.000000] Initial ramdisk at: 0xffffffe000016a98 (12267008 bytes)
+[ 0.000000] Zone ranges:
+[ 0.000000] DMA [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] Normal empty
+[ 0.000000] Movable zone start for each node
+[ 0.000000] Early memory node ranges
+[ 0.000000] node 0: [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x000000007fffffff]
+[ 0.000000] elf_hwcap is 0x112d
+[ 0.000000] random: fast init done
+[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 516615
+[ 0.000000] Kernel command line: console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7
+[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
+[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
+[ 0.000000] Sorting __ex_table...
+[ 0.000000] Memory: 2047832K/2095104K available (1856K kernel code, 204K rwdata, 532K rodata, 12076K init, 756K bss, 47272K reserved, 0K cma-reserved)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+[ 0.000000] riscv,cpu_intc,0: 64 local interrupts mapped
+[ 0.000000] riscv,plic0,e4000000: mapped 31 interrupts to 1/2 handlers
+[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns
+[ 0.000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000)
+[ 0.000000] pid_max: default: 32768 minimum: 301
+[ 0.004000] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.004000] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.056000] devtmpfs: initialized
+[ 0.060000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+[ 0.064000] futex hash table entries: 256 (order: 0, 6144 bytes)
+[ 0.068000] NET: Registered protocol family 16
+[ 0.080000] vgaarb: loaded
+[ 0.084000] clocksource: Switched to clocksource riscv_clocksource
+[ 0.088000] NET: Registered protocol family 2
+[ 0.092000] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.096000] TCP bind hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.096000] TCP: Hash tables configured (established 16384 bind 16384)
+[ 0.100000] UDP hash table entries: 1024 (order: 3, 32768 bytes)
+[ 0.100000] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
+[ 0.104000] NET: Registered protocol family 1
+[ 0.616000] Unpacking initramfs...
+[ 1.220000] workingset: timestamp_bits=62 max_order=19 bucket_order=0
+[ 1.244000] io scheduler noop registered
+[ 1.244000] io scheduler cfq registered (default)
+[ 1.244000] io scheduler mq-deadline registered
+[ 1.248000] io scheduler kyber registered
+[ 1.360000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 1.368000] console [ttyS0] disabled
+[ 1.372000] f0300000.serial: ttyS0 at MMIO 0xf0300020 (irq = 10, base_baud = 1228800) is a 16550A
+[ 1.392000] console [ttyS0] enabled
+[ 1.392000] ftmac100: Loading version 0.2 ...
+[ 1.396000] ftmac100 e0100000.mac eth0: irq 8, mapped at ffffffd002005000
+[ 1.400000] ftmac100 e0100000.mac eth0: generated random MAC address 6e:ac:c3:92:36:c0
+[ 1.404000] IR NEC protocol handler initialized
+[ 1.404000] IR RC5(x/sz) protocol handler initialized
+[ 1.404000] IR RC6 protocol handler initialized
+[ 1.404000] IR JVC protocol handler initialized
+[ 1.408000] IR Sony protocol handler initialized
+[ 1.408000] IR SANYO protocol handler initialized
+[ 1.408000] IR Sharp protocol handler initialized
+[ 1.408000] IR MCE Keyboard/mouse protocol handler initialized
+[ 1.412000] IR XMP protocol handler initialized
+[ 1.456000] ftsdc010 f0e00000.mmc: mmc0 - using hw SDIO IRQ
+[ 1.464000] bootconsole [early0] uses init memory and must be disabled even before the real one is ready
+[ 1.464000] bootconsole [early0] disabled
+[ 1.508000] Freeing unused kernel memory: 12076K
+[ 1.512000] This architecture does not have kernel memory protection.
+[ 1.520000] mmc0: new SD card at address 4567
+[ 1.524000] mmcblk0: mmc0:4567 QEMU! 20.0 MiB
+[ 1.844000] mmcblk0:
+Wed Dec 1 10:00:00 CST 2010
+/ #
+
+
+
+TODO
+==================================================
+Boot bbl and riscv-linux via U-Boot on AE350 board
+Command definition
+------------------
Commands are added to U-Boot by creating a new command structure.
-This is done by first including command.h, then using the U_BOOT_CMD() macro
-to fill in a cmd_tbl_t struct.
+This is done by first including command.h, then using the U_BOOT_CMD() or the
+U_BOOT_CMD_COMPLETE macro to fill in a cmd_tbl_t struct.
-U_BOOT_CMD(name,maxargs,repeatable,command,"usage","help")
+U_BOOT_CMD(name, maxargs, repeatable, command, "usage", "help")
+U_BOOT_CMD_COMPLETE(name, maxargs, repeatable, command, "usage, "help", comp)
-name: is the name of the commad. THIS IS NOT a string.
-maxargs: the maximum number of arguments this function takes
-repeatable: either 0 or 1 to indicate if autorepeat is allowed
-command: Function pointer (*cmd)(struct cmd_tbl_s *, int, int, char *[]);
-usage: Short description. This is a string
-help: Long description. This is a string
+name: The name of the command. THIS IS NOT a string.
+maxargs: The maximum number of arguments this function takes including
+ the command itself.
-**** Behind the scene ******
+repeatable: Either 0 or 1 to indicate if autorepeat is allowed.
+
+command: Pointer to the command function. This is the function that is
+ called when the command is issued.
+
+usage: Short description. This is a string.
+
+help: Long description. This is a string. The long description is
+ only available if CONFIG_SYS_LONGHELP is defined.
+
+comp: Pointer to the completion function. May be NULL.
+ This function is called if the user hits the TAB key while
+ entering the command arguments to complete the entry. Command
+ completion is only available if CONFIG_AUTO_COMPLETE is defined.
+
+Command function
+----------------
+
+The commmand function pointer has to be of type
+int (*cmd)(struct cmd_tbl_s *cmdtp, int flag, int argc, const char *argv[]);
+
+cmdtp: Table entry describing the command (see above).
+
+flag: A bitmap which may contain the following bit:
+ CMD_FLAG_REPEAT - The last command is repeated.
+ CMD_FLAG_BOOTD - The command is called by the bootd command.
+ CMD_FLAG_ENV - The command is called by the run command.
+
+argc: Number of arguments including the command.
+
+argv: Arguments.
+
+Allowable return value are:
+
+CMD_SUCCESS The command was successfully executed.
+
+CMD_FAILURE The command failed.
+
+CMD_RET_USAGE The command was called with invalid parameters. This value
+ leads to the display of the usage string.
+
+Completion function
+-------------------
+
+The completion function pointer has to be of type
+int (*complete)(int argc, char *const argv[], char last_char,
+ int maxv, char *cmdv[]);
+
+argc: Number of arguments including the command.
+
+argv: Arguments.
+
+last_char: The last character in the command line buffer.
+
+maxv: Maximum number of possible completions that may be returned by
+ the function.
+
+cmdv: Used to return possible values for the last argument. The last
+ possible completion must be followed by NULL.
+
+The function returns the number of possible completions (without the terminating
+NULL value).
+
+Behind the scene
+----------------
The structure created is named with a special prefix and placed by
the linker in a special section using the linker lists mechanism
The minimal QEMU command line to get U-Boot up and running is:
- For ARM:
- qemu-system-arm -machine virt,highmem=off -bios u-boot.bin
+ qemu-system-arm -machine virt -bios u-boot.bin
- For AArch64:
- qemu-system-aarch64 -machine virt,highmem=off -cpu cortex-a57 -bios u-boot.bin
+ qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin
-The 'highmem=off' parameter to the 'virt' machine is required for PCI to work
-in U-Boot. Also, for some odd reason qemu-system-aarch64 needs to be explicitly
+Note that for some odd reason qemu-system-aarch64 needs to be explicitly
told to use a 64-bit CPU or it will boot in 32-bit mode.
Additional peripherals that have been tested to work in both U-Boot and Linux
Required properties for the pinctrl driver:
- compatible: "marvell,mvebu-pinctrl",
- "marvell,armada-ap806-pinctrl",
- "marvell,a70x0-pinctrl",
- "marvell,a80x0-cp0-pinctrl",
- "marvell,a80x0-cp1-pinctrl"
+ "marvell,ap806-pinctrl",
+ "marvell,armada-7k-pinctrl",
+ "marvell,armada-8k-cpm-pinctrl",
+ "marvell,armada-8k-cps-pinctrl"
- bank-name: A string defining the pinc controller bank name
- reg: A pair of values defining the pin controller base address
and the address space
config-space {
pinctl: pinctl@6F4000 {
compatible = "marvell,mvebu-pinctrl",
- "marvell,armada-ap806-pinctrl";
+ "marvell,ap806-pinctrl";
bank-name ="apn-806";
reg = <0x6F4000 0x10>;
pin-count = <20>;
config-space {
cpm_pinctl: pinctl@44000 {
compatible = "marvell,mvebu-pinctrl",
- "marvell,a70x0-pinctrl",
- "marvell,a80x0-cp0-pinctrl";
+ "marvell,armada-7k-pinctrl",
+ "marvell,armada-8k-cpm-pinctrl";
bank-name ="cp0-110";
reg = <0x440000 0x20>;
pin-count = <63>;
config-space {
cps_pinctl: pinctl@44000 {
compatible = "marvell,mvebu-pinctrl",
- "marvell,a80x0-cp1-pinctrl";
+ "marvell,armada-8k-cps-pinctrl";
bank-name ="cp1-110";
reg = <0x440000 0x20>;
pin-count = <63>;
--- /dev/null
+Sandbox TPMv2.0 bindings
+------------------------
+
+Required properties:
+- compatible : Should be "sandbox,tpm2"
+
+Example:
+
+ tpm {
+ compatible = "sandbox,tpm2";
+ };
--- /dev/null
+ST33TPHF20 SPI TPMv2.0 bindings
+-------------------------------
+
+Required properties:
+- compatible : Should be "tis,tpm2-spi"
+- reg : SPI Chip select
+
+Optional properties:
+- gpio-reset : Reset GPIO (if not connected to the SoC reset line)
+- spi-max-frequency : See spi-bus.txt
+
+Example:
+
+ tpm@1 {
+ compatible = "tis,tpm2-spi";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
ppc4xx_i2c
rcar_i2c
sh_i2c
- sh_sh7734_i2c
soft_i2c
- tsi108_i2c
zynq_i2c
The deadline for this work is the end of June 2017. If no one steps
help
Enable this driver to support the SIL3114 SATA controllers.
+config AHCI_MVEBU
+ bool "Marvell EBU AHCI SATA support"
+ depends on ARCH_MVEBU
+ depends on AHCI
+ select SCSI_AHCI
+ select DM_SCSI
+ help
+ This option enables support for the Marvell EBU SoC's
+ onboard AHCI SATA.
+
+ If unsure, say N.
endmenu
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_SANDBOX) += sata_sandbox.o
+obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_ahci_enable(void)
+{
+ return 0;
+}
+
+static int mvebu_ahci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+ int ret;
+
+ ret = ahci_bind_scsi(dev, &scsi_dev);
+ if (ret) {
+ debug("%s: Failed to bind (err=%d\n)", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mvebu_ahci_probe(struct udevice *dev)
+{
+ /*
+ * Board specific SATA / AHCI enable code, e.g. enable the
+ * AHCI power or deassert reset
+ */
+ board_ahci_enable();
+
+ ahci_probe_scsi(dev, (ulong)devfdt_get_addr_ptr(dev));
+
+ return 0;
+}
+
+static const struct udevice_id mvebu_ahci_ids[] = {
+ { .compatible = "marvell,armada-3700-ahci" },
+ { .compatible = "marvell,armada-8k-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(ahci_mvebu_drv) = {
+ .name = "ahci_mvebu",
+ .id = UCLASS_AHCI,
+ .of_match = mvebu_ahci_ids,
+ .bind = mvebu_ahci_bind,
+ .probe = mvebu_ahci_probe,
+};
rate /= 2;
if (rate > H32MX_MAX_FREQ)
- dm_warn("H32MX clock is too fast\n");
+ dev_dbg(clk->dev, "H32MX clock is too fast\n");
return rate;
}
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
- depends on TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
# Copyright (C) 2014 Altera Corporation <www.altera.com>
ifdef CONFIG_ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright Altera Corporation (C) 2014-2015
- */
-#include <common.h>
-#include <errno.h>
-#include <div64.h>
-#include <watchdog.h>
-#include <asm/arch/fpga_manager.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/system_manager.h>
-#include <asm/io.h>
-
-struct sdram_prot_rule {
- u32 sdram_start; /* SDRAM start address */
- u32 sdram_end; /* SDRAM end address */
- u32 rule; /* SDRAM protection rule number: 0-19 */
- int valid; /* Rule valid or not? 1 - valid, 0 not*/
-
- u32 security;
- u32 portmask;
- u32 result;
- u32 lo_prot_id;
- u32 hi_prot_id;
-};
-
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-
-/**
- * get_errata_rows() - Up the number of DRAM rows to cover entire address space
- * @cfg: SDRAM controller configuration data
- *
- * SDRAM Failure happens when accessing non-existent memory. Artificially
- * increase the number of rows so that the memory controller thinks it has
- * 4GB of RAM. This function returns such amount of rows.
- */
-static int get_errata_rows(const struct socfpga_sdram_config *cfg)
-{
- /* Define constant for 4G memory - used for SDRAM errata workaround */
-#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
- const unsigned long long memsize = MEMSIZE_4G;
- const unsigned int cs =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- const unsigned int rows =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
- const unsigned int banks =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
- const unsigned int cols =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
- const unsigned int width = 8;
-
- unsigned long long newrows;
- int bits, inewrowslog2;
-
- debug("workaround rows - memsize %lld\n", memsize);
- debug("workaround rows - cs %d\n", cs);
- debug("workaround rows - width %d\n", width);
- debug("workaround rows - rows %d\n", rows);
- debug("workaround rows - banks %d\n", banks);
- debug("workaround rows - cols %d\n", cols);
-
- newrows = lldiv(memsize, cs * (width / 8));
- debug("rows workaround - term1 %lld\n", newrows);
-
- newrows = lldiv(newrows, (1 << banks) * (1 << cols));
- debug("rows workaround - term2 %lld\n", newrows);
-
- /*
- * Compute the hamming weight - same as number of bits set.
- * Need to see if result is ordinal power of 2 before
- * attempting log2 of result.
- */
- bits = generic_hweight32(newrows);
-
- debug("rows workaround - bits %d\n", bits);
-
- if (bits != 1) {
- printf("SDRAM workaround failed, bits set %d\n", bits);
- return rows;
- }
-
- if (newrows > UINT_MAX) {
- printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
- return rows;
- }
-
- inewrowslog2 = __ilog2(newrows);
-
- debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
-
- if (inewrowslog2 == -1) {
- printf("SDRAM workaround failed, newrows %lld\n", newrows);
- return rows;
- }
-
- return inewrowslog2;
-}
-
-/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
-static void sdram_set_rule(struct sdram_prot_rule *prule)
-{
- u32 lo_addr_bits;
- u32 hi_addr_bits;
- int ruleno = prule->rule;
-
- /* Select the rule */
- writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
-
- /* Obtain the address bits */
- lo_addr_bits = prule->sdram_start >> 20ULL;
- hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
-
- debug("sdram set rule start %x, %d\n", lo_addr_bits,
- prule->sdram_start);
- debug("sdram set rule end %x, %d\n", hi_addr_bits,
- prule->sdram_end);
-
- /* Set rule addresses */
- writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
-
- /* Set rule protection ids */
- writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
- &sdr_ctrl->prot_rule_id);
-
- /* Set the rule data */
- writel(prule->security | (prule->valid << 2) |
- (prule->portmask << 3) | (prule->result << 13),
- &sdr_ctrl->prot_rule_data);
-
- /* write the rule */
- writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
-
- /* Set rule number to 0 by default */
- writel(0, &sdr_ctrl->prot_rule_rdwr);
-}
-
-static void sdram_get_rule(struct sdram_prot_rule *prule)
-{
- u32 addr;
- u32 id;
- u32 data;
- int ruleno = prule->rule;
-
- /* Read the rule */
- writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
- writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
-
- /* Get the addresses */
- addr = readl(&sdr_ctrl->prot_rule_addr);
- prule->sdram_start = (addr & 0xFFF) << 20;
- prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
-
- /* Get the configured protection IDs */
- id = readl(&sdr_ctrl->prot_rule_id);
- prule->lo_prot_id = id & 0xFFF;
- prule->hi_prot_id = (id >> 12) & 0xFFF;
-
- /* Get protection data */
- data = readl(&sdr_ctrl->prot_rule_data);
-
- prule->security = data & 0x3;
- prule->valid = (data >> 2) & 0x1;
- prule->portmask = (data >> 3) & 0x3FF;
- prule->result = (data >> 13) & 0x1;
-}
-
-static void
-sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
-{
- struct sdram_prot_rule rule;
- int rules;
-
- /* Start with accepting all SDRAM transaction */
- writel(0x0, &sdr_ctrl->protport_default);
-
- /* Clear all protection rules for warm boot case */
- memset(&rule, 0, sizeof(rule));
-
- for (rules = 0; rules < 20; rules++) {
- rule.rule = rules;
- sdram_set_rule(&rule);
- }
-
- /* new rule: accept SDRAM */
- rule.sdram_start = sdram_start;
- rule.sdram_end = sdram_end;
- rule.lo_prot_id = 0x0;
- rule.hi_prot_id = 0xFFF;
- rule.portmask = 0x3FF;
- rule.security = 0x3;
- rule.result = 0;
- rule.valid = 1;
- rule.rule = 0;
-
- /* set new rule */
- sdram_set_rule(&rule);
-
- /* default rule: reject everything */
- writel(0x3ff, &sdr_ctrl->protport_default);
-}
-
-static void sdram_dump_protection_config(void)
-{
- struct sdram_prot_rule rule;
- int rules;
-
- debug("SDRAM Prot rule, default %x\n",
- readl(&sdr_ctrl->protport_default));
-
- for (rules = 0; rules < 20; rules++) {
- rule.rule = rules;
- sdram_get_rule(&rule);
- debug("Rule %d, rules ...\n", rules);
- debug(" sdram start %x\n", rule.sdram_start);
- debug(" sdram end %x\n", rule.sdram_end);
- debug(" low prot id %d, hi prot id %d\n",
- rule.lo_prot_id,
- rule.hi_prot_id);
- debug(" portmask %x\n", rule.portmask);
- debug(" security %d\n", rule.security);
- debug(" result %d\n", rule.result);
- debug(" valid %d\n", rule.valid);
- }
-}
-
-/**
- * sdram_write_verify() - write to register and verify the write.
- * @addr: Register address
- * @val: Value to be written and verified
- *
- * This function writes to a register, reads back the value and compares
- * the result with the written value to check if the data match.
- */
-static unsigned sdram_write_verify(const u32 *addr, const u32 val)
-{
- u32 rval;
-
- debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
- writel(val, addr);
-
- debug(" Read and verify...");
- rval = readl(addr);
- if (rval != val) {
- debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
- addr, val, rval);
- return -EINVAL;
- }
-
- debug("correct!\n");
- return 0;
-}
-
-/**
- * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
- * @cfg: SDRAM controller configuration data
- *
- * Return the value of DRAM CTRLCFG register.
- */
-static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
-{
- const u32 csbits =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- u32 addrorder =
- (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
- SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
-
- u32 ctrl_cfg = cfg->ctrl_cfg;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Set the addrorder field of the SDRAM control register
- * based on the CSBITs setting.
- */
- if (csbits == 1) {
- if (addrorder != 0)
- debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
- addrorder = 0;
- } else if (csbits == 2) {
- if (addrorder != 2)
- debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
- addrorder = 2;
- }
-
- ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
- ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
-
- return ctrl_cfg;
-}
-
-/**
- * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
- * @cfg: SDRAM controller configuration data
- *
- * Return the value of DRAM ADDRW register.
- */
-static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
-{
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
- * log2(number of chip select bits). Since there's only
- * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
- * which is the same as "chip selects" - 1.
- */
- const int rows = get_errata_rows(cfg);
- u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
-
- return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
-}
-
-/**
- * sdr_load_regs() - Load SDRAM controller registers
- * @cfg: SDRAM controller configuration data
- *
- * This function loads the register values into the SDRAM controller block.
- */
-static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
-{
- const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
- const u32 dram_addrw = sdr_get_addr_rw(cfg);
-
- debug("\nConfiguring CTRLCFG\n");
- writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
-
- debug("Configuring DRAMTIMING1\n");
- writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
-
- debug("Configuring DRAMTIMING2\n");
- writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
-
- debug("Configuring DRAMTIMING3\n");
- writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
-
- debug("Configuring DRAMTIMING4\n");
- writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
-
- debug("Configuring LOWPWRTIMING\n");
- writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
-
- debug("Configuring DRAMADDRW\n");
- writel(dram_addrw, &sdr_ctrl->dram_addrw);
-
- debug("Configuring DRAMIFWIDTH\n");
- writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
-
- debug("Configuring DRAMDEVWIDTH\n");
- writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
-
- debug("Configuring LOWPWREQ\n");
- writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
-
- debug("Configuring DRAMINTR\n");
- writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
-
- debug("Configuring STATICCFG\n");
- writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
-
- debug("Configuring CTRLWIDTH\n");
- writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
-
- debug("Configuring PORTCFG\n");
- writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
-
- debug("Configuring FIFOCFG\n");
- writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
-
- debug("Configuring MPPRIORITY\n");
- writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
-
- debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
- writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
- writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
- writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
- writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
-
- debug("Configuring MPPACING_MPPACING_0\n");
- writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
- writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
- writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
- writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
-
- debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
- writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
- writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
- writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
-
- debug("Configuring PHYCTRL_PHYCTRL_0\n");
- writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
-
- debug("Configuring CPORTWIDTH\n");
- writel(cfg->cport_width, &sdr_ctrl->cport_width);
-
- debug("Configuring CPORTWMAP\n");
- writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
-
- debug("Configuring CPORTRMAP\n");
- writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
-
- debug("Configuring RFIFOCMAP\n");
- writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
-
- debug("Configuring WFIFOCMAP\n");
- writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
-
- debug("Configuring CPORTRDWR\n");
- writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
-
- debug("Configuring DRAMODT\n");
- writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
-
- debug("Configuring EXTRATIME1\n");
- writel(cfg->extratime1, &sdr_ctrl->extratime1);
-}
-
-/**
- * sdram_mmr_init_full() - Function to initialize SDRAM MMR
- * @sdr_phy_reg: Value of the PHY control register 0
- *
- * Initialize the SDRAM MMR.
- */
-int sdram_mmr_init_full(unsigned int sdr_phy_reg)
-{
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
- const unsigned int rows =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
- int ret;
-
- writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
-
- sdr_load_regs(cfg);
-
- /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
- writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
-
- /* only enable if the FPGA is programmed */
- if (fpgamgr_test_fpga_ready()) {
- ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
- cfg->fpgaport_rst);
- if (ret)
- return ret;
- }
-
- /* Restore the SDR PHY Register if valid */
- if (sdr_phy_reg != 0xffffffff)
- writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
-
- /* Final step - apply configuration changes */
- debug("Configuring STATICCFG\n");
- clrsetbits_le32(&sdr_ctrl->static_cfg,
- SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
- 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
-
- sdram_set_protection_config(0, sdram_calculate_size() - 1);
-
- sdram_dump_protection_config();
-
- return 0;
-}
-
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-unsigned long sdram_calculate_size(void)
-{
- unsigned long temp;
- unsigned long row, bank, col, cs, width;
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
- const unsigned int csbits =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- const unsigned int rowbits =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
-
- temp = readl(&sdr_ctrl->dram_addrw);
- col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Use ROWBITS from Quartus/QSys to calculate SDRAM size
- * since the FB specifies we modify ROWBITs to work around SDRAM
- * controller issue.
- */
- row = readl(&sysmgr_regs->iswgrp_handoff[4]);
- if (row == 0)
- row = rowbits;
- /*
- * If the stored handoff value for rows is greater than
- * the field width in the sdr.dramaddrw register then
- * something is very wrong. Revert to using the the #define
- * value handed off by the SOCEDS tool chain instead of
- * using a broken value.
- */
- if (row > 31)
- row = rowbits;
-
- bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Use CSBITs from Quartus/QSys to calculate SDRAM size
- * since the FB specifies we modify CSBITs to work around SDRAM
- * controller issue.
- */
- cs = csbits;
-
- width = readl(&sdr_ctrl->dram_if_width);
-
- /* ECC would not be calculated as its not addressible */
- if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
- width = 32;
- if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
- width = 16;
-
- /* calculate the SDRAM size base on this info */
- temp = 1 << (row + bank + col);
- temp = temp * cs * (width / 8);
-
- debug("%s returns %ld\n", __func__, temp);
-
- return temp;
-}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/sdram.h>
+#include <linux/kernel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static u64 sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+ (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE 0xFFD0507C
+#define DDR_REG_CORE2SEQ 0xFFD05078
+#define DDR_READ_LATENCY_DELAY 40
+#define DDR_SIZE_2GB_HEX 0x80000000
+#define DDR_MAX_TRIES 0x00100000
+
+#define IO48_MMR_DRAMSTS 0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
+
+#define SEQ2CORE_MASK 0xF
+#define CORE2SEQ_INT_REQ 0xF
+#define SEQ2CORE_INT_RESP_BIT 3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+ (void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+ (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+ *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+ (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+ (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+ (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The following are the supported configurations */
+static u32 ddr_config[] = {
+ /* Chip - Row - Bank - Column Style */
+ /* All Types */
+ ARRIA_DDR_CONFIG(0, 3, 10, 12),
+ ARRIA_DDR_CONFIG(0, 3, 10, 13),
+ ARRIA_DDR_CONFIG(0, 3, 10, 14),
+ ARRIA_DDR_CONFIG(0, 3, 10, 15),
+ ARRIA_DDR_CONFIG(0, 3, 10, 16),
+ ARRIA_DDR_CONFIG(0, 3, 10, 17),
+ /* LPDDR x16 */
+ ARRIA_DDR_CONFIG(0, 3, 11, 14),
+ ARRIA_DDR_CONFIG(0, 3, 11, 15),
+ ARRIA_DDR_CONFIG(0, 3, 11, 16),
+ ARRIA_DDR_CONFIG(0, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(0, 4, 10, 14),
+ ARRIA_DDR_CONFIG(0, 4, 10, 15),
+ ARRIA_DDR_CONFIG(0, 4, 10, 16),
+ ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+ /* Chip - Bank - Row - Column Style */
+ ARRIA_DDR_CONFIG(1, 3, 10, 12),
+ ARRIA_DDR_CONFIG(1, 3, 10, 13),
+ ARRIA_DDR_CONFIG(1, 3, 10, 14),
+ ARRIA_DDR_CONFIG(1, 3, 10, 15),
+ ARRIA_DDR_CONFIG(1, 3, 10, 16),
+ ARRIA_DDR_CONFIG(1, 3, 10, 17),
+ ARRIA_DDR_CONFIG(1, 3, 11, 14),
+ ARRIA_DDR_CONFIG(1, 3, 11, 15),
+ ARRIA_DDR_CONFIG(1, 3, 11, 16),
+ ARRIA_DDR_CONFIG(1, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(1, 4, 10, 14),
+ ARRIA_DDR_CONFIG(1, 4, 10, 15),
+ ARRIA_DDR_CONFIG(1, 4, 10, 16),
+ ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(u32 ddr_conf)
+{
+ int i;
+
+ for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+ if (ddr_conf == ddr_config[i])
+ return i;
+ }
+ return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+ return readl(&socfpga_ecc_hmc_base->ddrcalstat);
+}
+
+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
+{
+ u32 reg = readl(ereg);
+
+ return (reg & BIT(bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
+ u32 expected, u32 timeout_usec)
+{
+ u32 tmr;
+
+ for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+ udelay(100);
+ WATCHDOG_RESET();
+ if (ddr_get_bit(ereg, bit) == expected)
+ return 0;
+ }
+
+ return 1;
+}
+
+static int emif_clear(void)
+{
+ u32 i = DDR_MAX_TRIES;
+ u8 ret = 0;
+
+ writel(0, DDR_REG_CORE2SEQ);
+
+ do {
+ ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+ SEQ2CORE_MASK, 1, 50, 0);
+ } while (ret && (--i > 0));
+
+ return !i;
+}
+
+static int emif_reset(void)
+{
+ u32 c2s, s2c;
+
+ c2s = readl(DDR_REG_CORE2SEQ);
+ s2c = readl(DDR_REG_SEQ2CORE);
+
+ debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+ c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2),
+ readl(IO48_MMR_DRAMSTS));
+
+ if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+ debug("failed emif_clear()\n");
+ return -EPERM;
+ }
+
+ writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+ if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+ debug("emif_reset failed to see interrupt acknowledge\n");
+ return -EPERM;
+ } else {
+ debug("emif_reset interrupt acknowledged\n");
+ }
+
+ if (emif_clear()) {
+ debug("emif_clear() failed\n");
+ return -EPERM;
+ }
+ debug("emif_reset interrupt cleared\n");
+
+ debug("nr0=%08x nr1=%08x nr2=%08x\n",
+ readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2));
+
+ return 0;
+}
+
+static int ddr_setup(void)
+{
+ int i, j, ddr_setup_complete = 0;
+
+ /* Try 3 times to do a calibration */
+ for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+ WATCHDOG_RESET();
+
+ /* A delay to wait for calibration bit to set */
+ for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+ mdelay(500);
+ ddr_setup_complete = is_sdram_cal_success();
+ }
+
+ if (!ddr_setup_complete)
+ if (emif_reset())
+ puts("Error: Failed to reset EMIF\n");
+ }
+
+ /* After 3 times trying calibration */
+ if (!ddr_setup_complete) {
+ puts("Error: Could Not Calibrate SDRAM\n");
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int sdram_startup(void)
+{
+ /* Release NOC ddr scheduler from reset */
+ socfpga_reset_deassert_noc_ddr_scheduler();
+
+ /* Bringup the DDR (calibration and configuration) */
+ return ddr_setup();
+}
+
+static u64 sdram_size_calc(void)
+{
+ u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+
+ u64 size = BIT(((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
+ (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
+
+ size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+ ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
+
+ debug("SDRAM size=%llu", size);
+
+ return size;
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void sdram_mmr_init(void)
+{
+ u32 update_value, io48_value;
+ u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
+ u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
+ u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+ u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
+ u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
+ u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
+ u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
+ u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
+ u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
+ u32 ddrioctl;
+
+ /*
+ * Configure the DDR IO size [0xFFCFB008]
+ * niosreserve0: Used to indicate DDR width &
+ * bit[7:0] = Number of data bits (0x20 for 32bit)
+ * bit[8] = 1 if user-mode OCT is present
+ * bit[9] = 1 if warm reset compiled into EMIF Cal Code
+ * bit[10] = 1 if warm reset is on during generation in EMIF Cal
+ * niosreserve1: IP ADCDS version encoded as 16 bit value
+ * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+ * 3=EAP, 4-6 are reserved)
+ * bit[5:3] = Service Pack # (e.g. 1)
+ * bit[9:6] = Minor Release #
+ * bit[14:10] = Major Release #
+ */
+ if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+ update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+ writel(((update_value & 0xFF) >> 5),
+ &socfpga_ecc_hmc_base->ddrioctrl);
+ }
+
+ ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+ /* Set the DDR Configuration [0xFFD12400] */
+ io48_value = ARRIA_DDR_CONFIG(
+ ((ctrlcfg1 &
+ IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
+ IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
+ (dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
+ ((dramaddrw &
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+ IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
+
+ update_value = match_ddr_conf(io48_value);
+ if (update_value)
+ writel(update_value,
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
+
+ /*
+ * Configure DDR timing [0xFFD1240C]
+ * RDTOMISS = tRTP + tRP + tRCD - BL/2
+ * WRTOMISS = WL + tWR + tRP + tRCD and
+ * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
+ * First part of equation is in memory clock units so divide by 2
+ * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+ * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+ */
+ u32 ctrlcfg0_cfg_ctrl_burst_len =
+ (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
+ IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
+
+ u32 caltim0_cfg_act_to_rdwr = caltim0 &
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
+
+ u32 caltim0_cfg_act_to_act =
+ (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
+
+ u32 caltim0_cfg_act_to_act_db =
+ (caltim0 &
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
+ IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
+
+ u32 caltim1_cfg_rd_to_wr =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
+
+ u32 caltim1_cfg_rd_to_rd_dc =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
+
+ u32 caltim1_cfg_rd_to_wr_dc =
+ (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
+ IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
+
+ u32 caltim2_cfg_rd_to_pch =
+ (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
+ IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
+
+ u32 caltim3_cfg_wr_to_rd =
+ (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
+ IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
+
+ u32 caltim3_cfg_wr_to_rd_dc =
+ (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
+ IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
+
+ u32 caltim4_cfg_pch_to_valid =
+ (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
+ IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
+
+ u32 caltim9_cfg_4_act_to_act = caltim9 &
+ IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
+
+ update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
+ caltim0_cfg_act_to_rdwr -
+ (ctrlcfg0_cfg_ctrl_burst_len >> 2));
+
+ io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+ ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
+ (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
+ /* Up to here was in memory cycles so divide by 2 */
+ caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
+ caltim4_cfg_pch_to_valid);
+
+ writel(((caltim0_cfg_act_to_act <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+ (update_value <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+ (io48_value <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+ ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+ (caltim1_cfg_rd_to_wr <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+ (caltim3_cfg_wr_to_rd <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+ (((ddrioctl == 1) ? 1 : 0) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+ &socfpga_noc_ddr_scheduler_base->
+ ddr_t_main_scheduler_ddrtiming);
+
+ /* Configure DDR mode [0xFFD12410] [precharge = 0] */
+ writel(((ddrioctl ? 0 : 1) <<
+ ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
+
+ /* Configure the read latency [0xFFD12414] */
+ writel(((socfpga_io48_mmr_base->dramtiming0 &
+ ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
+ DDR_READ_LATENCY_DELAY,
+ &socfpga_noc_ddr_scheduler_base->
+ ddr_t_main_scheduler_readlatency);
+
+ /*
+ * Configuring timing values concerning activate commands
+ * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+ */
+ writel(((caltim0_cfg_act_to_act_db <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+ (caltim9_cfg_4_act_to_act <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+ (ARRIA10_SDR_ACTIVATE_FAWBANK <<
+ ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
+
+ /*
+ * Configuring timing values concerning device to device data bus
+ * ownership change [0xFFD1243C]
+ */
+ writel(((caltim1_cfg_rd_to_rd_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+ (caltim1_cfg_rd_to_wr_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+ (caltim3_cfg_wr_to_rd_dc <<
+ ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+ &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
+
+ /* Enable or disable the SDRAM ECC */
+ if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
+ setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
+ setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+ (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+ } else {
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+ (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+ clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+ (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+ ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+ }
+}
+
+struct firewall_entry {
+ const char *prop_name;
+ const u32 cfg_addr;
+ const u32 en_addr;
+ const u32 en_bit;
+};
+#define FW_MPU_FPGA_ADDRESS \
+ ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
+
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
+ (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
+ offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
+
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
+ (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
+ offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
+
+const struct firewall_entry firewall_table[] = {
+ {
+ "mpu0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
+ },
+ {
+ "mpu1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
+ },
+ {
+ "mpu2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
+ },
+ {
+ "mpu3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
+ },
+ {
+ "l3-0",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
+ },
+ {
+ "l3-1",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
+ },
+ {
+ "l3-2",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
+ },
+ {
+ "l3-3",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
+ },
+ {
+ "l3-4",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
+ },
+ {
+ "l3-5",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
+ },
+ {
+ "l3-6",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
+ },
+ {
+ "l3-7",
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
+ SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram0-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram0region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram1-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram1region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-0",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region0addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-1",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region1addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-2",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region2addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
+ },
+ {
+ "fpga2sdram2-3",
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+ (fpga2sdram2region3addr),
+ SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+ ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
+ },
+
+};
+
+static int of_sdram_firewall_setup(const void *blob)
+{
+ int child, i, node, ret;
+ u32 start_end[2];
+ char name[32];
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
+ if (node < 0)
+ return -ENXIO;
+
+ child = fdt_first_subnode(blob, node);
+ if (child < 0)
+ return -ENXIO;
+
+ /* set to default state */
+ writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
+ writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
+
+
+ for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
+ sprintf(name, "%s", firewall_table[i].prop_name);
+ ret = fdtdec_get_int_array(blob, child, name,
+ start_end, 2);
+ if (ret) {
+ sprintf(name, "altr,%s", firewall_table[i].prop_name);
+ ret = fdtdec_get_int_array(blob, child, name,
+ start_end, 2);
+ if (ret)
+ continue;
+ }
+
+ writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
+ (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
+ firewall_table[i].cfg_addr);
+ setbits_le32(firewall_table[i].en_addr,
+ firewall_table[i].en_bit);
+ }
+
+ return 0;
+}
+
+int ddr_calibration_sequence(void)
+{
+ WATCHDOG_RESET();
+
+ /* Check to see if SDRAM cal was success */
+ if (sdram_startup()) {
+ puts("DDRCAL: Failed\n");
+ return -EPERM;
+ }
+
+ puts("DDRCAL: Success\n");
+
+ WATCHDOG_RESET();
+
+ /* initialize the MMR register */
+ sdram_mmr_init();
+
+ /* assigning the SDRAM size */
+ u64 size = sdram_size_calc();
+
+ /*
+ * If size is less than zero, this is invalid/weird value from
+ * calculation, use default Config size.
+ * Up to 2GB is supported, 2GB would be used if more than that.
+ */
+ if (size <= 0)
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ else if (DDR_SIZE_2GB_HEX <= size)
+ gd->ram_size = DDR_SIZE_2GB_HEX;
+ else
+ gd->ram_size = (u32)size;
+
+ /* setup the dram info within bd */
+ dram_init_banksize();
+
+ if (of_sdram_firewall_setup(gd->fdt_blob))
+ puts("FW: Error Configuring Firewall\n");
+
+ return 0;
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = bd->bi_dram[bank].start >> 20;
+ i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+ i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+ }
+
+ /* same as above but just that we would want cacheable for ocram too */
+ i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ */
+#include <common.h>
+#include <errno.h>
+#include <div64.h>
+#include <watchdog.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+
+struct sdram_prot_rule {
+ u32 sdram_start; /* SDRAM start address */
+ u32 sdram_end; /* SDRAM end address */
+ u32 rule; /* SDRAM protection rule number: 0-19 */
+ int valid; /* Rule valid or not? 1 - valid, 0 not*/
+
+ u32 security;
+ u32 portmask;
+ u32 result;
+ u32 lo_prot_id;
+ u32 hi_prot_id;
+};
+
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+/**
+ * get_errata_rows() - Up the number of DRAM rows to cover entire address space
+ * @cfg: SDRAM controller configuration data
+ *
+ * SDRAM Failure happens when accessing non-existent memory. Artificially
+ * increase the number of rows so that the memory controller thinks it has
+ * 4GB of RAM. This function returns such amount of rows.
+ */
+static int get_errata_rows(const struct socfpga_sdram_config *cfg)
+{
+ /* Define constant for 4G memory - used for SDRAM errata workaround */
+#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
+ const unsigned long long memsize = MEMSIZE_4G;
+ const unsigned int cs =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ const unsigned int rows =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+ const unsigned int banks =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+ const unsigned int cols =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+ const unsigned int width = 8;
+
+ unsigned long long newrows;
+ int bits, inewrowslog2;
+
+ debug("workaround rows - memsize %lld\n", memsize);
+ debug("workaround rows - cs %d\n", cs);
+ debug("workaround rows - width %d\n", width);
+ debug("workaround rows - rows %d\n", rows);
+ debug("workaround rows - banks %d\n", banks);
+ debug("workaround rows - cols %d\n", cols);
+
+ newrows = lldiv(memsize, cs * (width / 8));
+ debug("rows workaround - term1 %lld\n", newrows);
+
+ newrows = lldiv(newrows, (1 << banks) * (1 << cols));
+ debug("rows workaround - term2 %lld\n", newrows);
+
+ /*
+ * Compute the hamming weight - same as number of bits set.
+ * Need to see if result is ordinal power of 2 before
+ * attempting log2 of result.
+ */
+ bits = generic_hweight32(newrows);
+
+ debug("rows workaround - bits %d\n", bits);
+
+ if (bits != 1) {
+ printf("SDRAM workaround failed, bits set %d\n", bits);
+ return rows;
+ }
+
+ if (newrows > UINT_MAX) {
+ printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
+ return rows;
+ }
+
+ inewrowslog2 = __ilog2(newrows);
+
+ debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
+
+ if (inewrowslog2 == -1) {
+ printf("SDRAM workaround failed, newrows %lld\n", newrows);
+ return rows;
+ }
+
+ return inewrowslog2;
+}
+
+/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
+static void sdram_set_rule(struct sdram_prot_rule *prule)
+{
+ u32 lo_addr_bits;
+ u32 hi_addr_bits;
+ int ruleno = prule->rule;
+
+ /* Select the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+
+ /* Obtain the address bits */
+ lo_addr_bits = prule->sdram_start >> 20ULL;
+ hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
+
+ debug("sdram set rule start %x, %d\n", lo_addr_bits,
+ prule->sdram_start);
+ debug("sdram set rule end %x, %d\n", hi_addr_bits,
+ prule->sdram_end);
+
+ /* Set rule addresses */
+ writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
+
+ /* Set rule protection ids */
+ writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
+ &sdr_ctrl->prot_rule_id);
+
+ /* Set the rule data */
+ writel(prule->security | (prule->valid << 2) |
+ (prule->portmask << 3) | (prule->result << 13),
+ &sdr_ctrl->prot_rule_data);
+
+ /* write the rule */
+ writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Set rule number to 0 by default */
+ writel(0, &sdr_ctrl->prot_rule_rdwr);
+}
+
+static void sdram_get_rule(struct sdram_prot_rule *prule)
+{
+ u32 addr;
+ u32 id;
+ u32 data;
+ int ruleno = prule->rule;
+
+ /* Read the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+ writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Get the addresses */
+ addr = readl(&sdr_ctrl->prot_rule_addr);
+ prule->sdram_start = (addr & 0xFFF) << 20;
+ prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
+
+ /* Get the configured protection IDs */
+ id = readl(&sdr_ctrl->prot_rule_id);
+ prule->lo_prot_id = id & 0xFFF;
+ prule->hi_prot_id = (id >> 12) & 0xFFF;
+
+ /* Get protection data */
+ data = readl(&sdr_ctrl->prot_rule_data);
+
+ prule->security = data & 0x3;
+ prule->valid = (data >> 2) & 0x1;
+ prule->portmask = (data >> 3) & 0x3FF;
+ prule->result = (data >> 13) & 0x1;
+}
+
+static void
+sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ /* Start with accepting all SDRAM transaction */
+ writel(0x0, &sdr_ctrl->protport_default);
+
+ /* Clear all protection rules for warm boot case */
+ memset(&rule, 0, sizeof(rule));
+
+ for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
+ sdram_set_rule(&rule);
+ }
+
+ /* new rule: accept SDRAM */
+ rule.sdram_start = sdram_start;
+ rule.sdram_end = sdram_end;
+ rule.lo_prot_id = 0x0;
+ rule.hi_prot_id = 0xFFF;
+ rule.portmask = 0x3FF;
+ rule.security = 0x3;
+ rule.result = 0;
+ rule.valid = 1;
+ rule.rule = 0;
+
+ /* set new rule */
+ sdram_set_rule(&rule);
+
+ /* default rule: reject everything */
+ writel(0x3ff, &sdr_ctrl->protport_default);
+}
+
+static void sdram_dump_protection_config(void)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ debug("SDRAM Prot rule, default %x\n",
+ readl(&sdr_ctrl->protport_default));
+
+ for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
+ sdram_get_rule(&rule);
+ debug("Rule %d, rules ...\n", rules);
+ debug(" sdram start %x\n", rule.sdram_start);
+ debug(" sdram end %x\n", rule.sdram_end);
+ debug(" low prot id %d, hi prot id %d\n",
+ rule.lo_prot_id,
+ rule.hi_prot_id);
+ debug(" portmask %x\n", rule.portmask);
+ debug(" security %d\n", rule.security);
+ debug(" result %d\n", rule.result);
+ debug(" valid %d\n", rule.valid);
+ }
+}
+
+/**
+ * sdram_write_verify() - write to register and verify the write.
+ * @addr: Register address
+ * @val: Value to be written and verified
+ *
+ * This function writes to a register, reads back the value and compares
+ * the result with the written value to check if the data match.
+ */
+static unsigned sdram_write_verify(const u32 *addr, const u32 val)
+{
+ u32 rval;
+
+ debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
+ writel(val, addr);
+
+ debug(" Read and verify...");
+ rval = readl(addr);
+ if (rval != val) {
+ debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
+ addr, val, rval);
+ return -EINVAL;
+ }
+
+ debug("correct!\n");
+ return 0;
+}
+
+/**
+ * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
+ * @cfg: SDRAM controller configuration data
+ *
+ * Return the value of DRAM CTRLCFG register.
+ */
+static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
+{
+ const u32 csbits =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ u32 addrorder =
+ (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
+ SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+ u32 ctrl_cfg = cfg->ctrl_cfg;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Set the addrorder field of the SDRAM control register
+ * based on the CSBITs setting.
+ */
+ if (csbits == 1) {
+ if (addrorder != 0)
+ debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
+ addrorder = 0;
+ } else if (csbits == 2) {
+ if (addrorder != 2)
+ debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
+ addrorder = 2;
+ }
+
+ ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
+ ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+ return ctrl_cfg;
+}
+
+/**
+ * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
+ * @cfg: SDRAM controller configuration data
+ *
+ * Return the value of DRAM ADDRW register.
+ */
+static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
+{
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
+ * log2(number of chip select bits). Since there's only
+ * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
+ * which is the same as "chip selects" - 1.
+ */
+ const int rows = get_errata_rows(cfg);
+ u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
+
+ return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
+}
+
+/**
+ * sdr_load_regs() - Load SDRAM controller registers
+ * @cfg: SDRAM controller configuration data
+ *
+ * This function loads the register values into the SDRAM controller block.
+ */
+static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
+{
+ const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
+ const u32 dram_addrw = sdr_get_addr_rw(cfg);
+
+ debug("\nConfiguring CTRLCFG\n");
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
+
+ debug("Configuring DRAMTIMING1\n");
+ writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
+
+ debug("Configuring DRAMTIMING2\n");
+ writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
+
+ debug("Configuring DRAMTIMING3\n");
+ writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
+
+ debug("Configuring DRAMTIMING4\n");
+ writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
+
+ debug("Configuring LOWPWRTIMING\n");
+ writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
+
+ debug("Configuring DRAMADDRW\n");
+ writel(dram_addrw, &sdr_ctrl->dram_addrw);
+
+ debug("Configuring DRAMIFWIDTH\n");
+ writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
+
+ debug("Configuring DRAMDEVWIDTH\n");
+ writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
+
+ debug("Configuring LOWPWREQ\n");
+ writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
+
+ debug("Configuring DRAMINTR\n");
+ writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
+
+ debug("Configuring STATICCFG\n");
+ writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
+
+ debug("Configuring CTRLWIDTH\n");
+ writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
+
+ debug("Configuring PORTCFG\n");
+ writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
+
+ debug("Configuring FIFOCFG\n");
+ writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
+
+ debug("Configuring MPPRIORITY\n");
+ writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
+
+ debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+ writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
+ writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
+ writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
+ writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
+
+ debug("Configuring MPPACING_MPPACING_0\n");
+ writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
+ writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
+ writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
+ writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
+
+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+ writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
+ writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
+ writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
+
+ debug("Configuring PHYCTRL_PHYCTRL_0\n");
+ writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
+
+ debug("Configuring CPORTWIDTH\n");
+ writel(cfg->cport_width, &sdr_ctrl->cport_width);
+
+ debug("Configuring CPORTWMAP\n");
+ writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
+
+ debug("Configuring CPORTRMAP\n");
+ writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
+
+ debug("Configuring RFIFOCMAP\n");
+ writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
+
+ debug("Configuring WFIFOCMAP\n");
+ writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
+
+ debug("Configuring CPORTRDWR\n");
+ writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
+
+ debug("Configuring DRAMODT\n");
+ writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
+}
+
+/**
+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR
+ * @sdr_phy_reg: Value of the PHY control register 0
+ *
+ * Initialize the SDRAM MMR.
+ */
+int sdram_mmr_init_full(unsigned int sdr_phy_reg)
+{
+ const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+ const unsigned int rows =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+ int ret;
+
+ writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+
+ sdr_load_regs(cfg);
+
+ /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
+ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+
+ /* only enable if the FPGA is programmed */
+ if (fpgamgr_test_fpga_ready()) {
+ ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
+ cfg->fpgaport_rst);
+ if (ret)
+ return ret;
+ }
+
+ /* Restore the SDR PHY Register if valid */
+ if (sdr_phy_reg != 0xffffffff)
+ writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
+
+ /* Final step - apply configuration changes */
+ debug("Configuring STATICCFG\n");
+ clrsetbits_le32(&sdr_ctrl->static_cfg,
+ SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
+ 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
+
+ sdram_set_protection_config(0, sdram_calculate_size() - 1);
+
+ sdram_dump_protection_config();
+
+ return 0;
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+unsigned long sdram_calculate_size(void)
+{
+ unsigned long temp;
+ unsigned long row, bank, col, cs, width;
+ const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+ const unsigned int csbits =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ const unsigned int rowbits =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+
+ temp = readl(&sdr_ctrl->dram_addrw);
+ col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify ROWBITs to work around SDRAM
+ * controller issue.
+ */
+ row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+ if (row == 0)
+ row = rowbits;
+ /*
+ * If the stored handoff value for rows is greater than
+ * the field width in the sdr.dramaddrw register then
+ * something is very wrong. Revert to using the the #define
+ * value handed off by the SOCEDS tool chain instead of
+ * using a broken value.
+ */
+ if (row > 31)
+ row = rowbits;
+
+ bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Use CSBITs from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify CSBITs to work around SDRAM
+ * controller issue.
+ */
+ cs = csbits;
+
+ width = readl(&sdr_ctrl->dram_if_width);
+
+ /* ECC would not be calculated as its not addressible */
+ if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
+ width = 32;
+ if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
+ width = 16;
+
+ /* calculate the SDRAM size base on this info */
+ temp = 1 << (row + bank + col);
+ temp = temp * cs * (width / 8);
+
+ debug("%s returns %ld\n", __func__, temp);
+
+ return temp;
+}
OMAP24xx Slave speed channel 0
endif
+config SYS_I2C_RCAR_I2C
+ bool "Renesas RCar I2C driver"
+ depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
+ help
+ Support for Renesas RCar I2C controller.
+
config SYS_I2C_RCAR_IIC
bool "Renesas RCar Gen3 IIC driver"
depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
-obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
-obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/i2c/rcar_i2c.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
+ * Clock configuration based on Linux i2c-rcar.c:
+ * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
+ * Copyright (C) 2011-2015 Renesas Electronics Corporation
+ * Copyright (C) 2012-14 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*/
#include <common.h>
+#include <clk.h>
+#include <dm.h>
#include <i2c.h>
#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rcar_i2c {
- u32 icscr;
- u32 icmcr;
- u32 icssr;
- u32 icmsr;
- u32 icsier;
- u32 icmier;
- u32 icccr;
- u32 icsar;
- u32 icmar;
- u32 icrxdtxd;
- u32 icccr2;
- u32 icmpr;
- u32 ichpr;
- u32 iclpr;
-};
-
-#define MCR_MDBS 0x80 /* non-fifo mode switch */
-#define MCR_FSCL 0x40 /* override SCL pin */
-#define MCR_FSDA 0x20 /* override SDA pin */
-#define MCR_OBPC 0x10 /* override pins */
-#define MCR_MIE 0x08 /* master if enable */
-#define MCR_TSBE 0x04
-#define MCR_FSB 0x02 /* force stop bit */
-#define MCR_ESG 0x01 /* en startbit gen. */
-
-#define MSR_MASK 0x7f
-#define MSR_MNR 0x40 /* nack received */
-#define MSR_MAL 0x20 /* arbitration lost */
-#define MSR_MST 0x10 /* sent a stop */
-#define MSR_MDE 0x08
-#define MSR_MDT 0x04
-#define MSR_MDR 0x02
-#define MSR_MAT 0x01 /* slave addr xfer done */
-
-static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
- (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
- (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
- (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
- (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
+#include <wait_bit.h>
+
+#define RCAR_I2C_ICSCR 0x00
+#define RCAR_I2C_ICMCR 0x04
+#define RCAR_I2C_ICMCR_MDBS BIT(7)
+#define RCAR_I2C_ICMCR_FSCL BIT(6)
+#define RCAR_I2C_ICMCR_FSDA BIT(5)
+#define RCAR_I2C_ICMCR_OBPC BIT(4)
+#define RCAR_I2C_ICMCR_MIE BIT(3)
+#define RCAR_I2C_ICMCR_TSBE BIT(2)
+#define RCAR_I2C_ICMCR_FSB BIT(1)
+#define RCAR_I2C_ICMCR_ESG BIT(0)
+#define RCAR_I2C_ICSSR 0x08
+#define RCAR_I2C_ICMSR 0x0c
+#define RCAR_I2C_ICMSR_MASK 0x7f
+#define RCAR_I2C_ICMSR_MNR BIT(6)
+#define RCAR_I2C_ICMSR_MAL BIT(5)
+#define RCAR_I2C_ICMSR_MST BIT(4)
+#define RCAR_I2C_ICMSR_MDE BIT(3)
+#define RCAR_I2C_ICMSR_MDT BIT(2)
+#define RCAR_I2C_ICMSR_MDR BIT(1)
+#define RCAR_I2C_ICMSR_MAT BIT(0)
+#define RCAR_I2C_ICSIER 0x10
+#define RCAR_I2C_ICMIER 0x14
+#define RCAR_I2C_ICCCR 0x18
+#define RCAR_I2C_ICCCR_SCGD_OFF 3
+#define RCAR_I2C_ICSAR 0x1c
+#define RCAR_I2C_ICMAR 0x20
+#define RCAR_I2C_ICRXD_ICTXD 0x24
+
+struct rcar_i2c_priv {
+ void __iomem *base;
+ struct clk clk;
+ u32 intdelay;
+ u32 icccr;
};
-static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
+static int rcar_i2c_finish(struct udevice *dev)
{
- /* set slave address */
- writel(chip << 1, &dev->icmar);
- /* set register address */
- writel(addr, &dev->icrxdtxd);
- /* clear status */
- writel(0, &dev->icmsr);
- /* start master send */
- writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
-
- while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
- != (MSR_MAT | MSR_MDE))
- udelay(10);
-
- /* clear ESG */
- writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
- /* start SCLclk */
- writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
-
- while (!(readl(&dev->icmsr) & MSR_MDE))
- udelay(10);
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
+ true, 10, true);
+
+ writel(0, priv->base + RCAR_I2C_ICSSR);
+ writel(0, priv->base + RCAR_I2C_ICMSR);
+ writel(0, priv->base + RCAR_I2C_ICMCR);
+
+ return ret;
}
-static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
+static void rcar_i2c_recover(struct udevice *dev)
{
- while (!(readl(&dev->icmsr) & MSR_MST))
- udelay(10);
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
+ u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
+ int i;
- writel(0, &dev->icmcr);
+ /* Send 9 SCL pulses */
+ for (i = 0; i < 9; i++) {
+ writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
+ writel(mcra, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
+ }
+
+ /* Send stop condition */
+ udelay(5);
+ writel(mcra, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
+ writel(mcr, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
+ writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
+ writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
+ udelay(5);
}
-static int
-rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
+static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
{
- rcar_i2c_raw_rw_common(dev, chip, addr);
-
- /* set send date */
- writel(*val, &dev->icrxdtxd);
- /* start SCLclk */
- writel(~MSR_MDE, &dev->icmsr);
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ u32 mask = RCAR_I2C_ICMSR_MAT |
+ (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
+ u32 val;
+ int ret;
+
+ writel(0, priv->base + RCAR_I2C_ICMIER);
+ writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
+ writel(0, priv->base + RCAR_I2C_ICMSR);
+ writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
+
+ ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
+ RCAR_I2C_ICMCR_FSDA, false, 2, true);
+ if (ret) {
+ rcar_i2c_recover(dev);
+ val = readl(priv->base + RCAR_I2C_ICMSR);
+ if (val & RCAR_I2C_ICMCR_FSDA) {
+ dev_err(dev, "Bus busy, aborting\n");
+ return ret;
+ }
+ }
- while (!(readl(&dev->icmsr) & MSR_MDE))
- udelay(10);
+ writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
+ writel(0, priv->base + RCAR_I2C_ICMSR);
+ writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
+ priv->base + RCAR_I2C_ICMCR);
- /* set stop condition */
- writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
- /* start SCLclk */
- writel(~MSR_MDE, &dev->icmsr);
+ ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
+ true, 100, true);
+ if (ret)
+ return ret;
- rcar_i2c_raw_rw_finish(dev);
+ /* Check NAK */
+ if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
+ return -EREMOTEIO;
return 0;
}
-static u8
-rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
+static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
{
- u8 ret;
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
+ int i, ret = -EREMOTEIO;
- rcar_i2c_raw_rw_common(dev, chip, addr);
+ ret = rcar_i2c_set_addr(dev, msg->addr, 1);
+ if (ret)
+ return ret;
- /* set slave address, receive */
- writel((chip << 1) | 1, &dev->icmar);
- /* start master receive */
- writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
- /* clear status */
- writel(0, &dev->icmsr);
+ for (i = 0; i < msg->len; i++) {
+ if (msg->len - 1 == i)
+ icmcr |= RCAR_I2C_ICMCR_FSB;
- while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
- != (MSR_MAT | MSR_MDR))
- udelay(10);
+ writel(icmcr, priv->base + RCAR_I2C_ICMCR);
+ writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
- /* clear ESG */
- writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
- /* prepare stop condition */
- writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
- /* start SCLclk */
- writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
+ ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
+ RCAR_I2C_ICMSR_MDR, true, 100, true);
+ if (ret)
+ return ret;
- while (!(readl(&dev->icmsr) & MSR_MDR))
- udelay(10);
-
- /* get receive data */
- ret = (u8)readl(&dev->icrxdtxd);
- /* start SCLclk */
- writel(~MSR_MDR, &dev->icmsr);
+ msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
+ }
- rcar_i2c_raw_rw_finish(dev);
+ writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
- return ret;
+ return rcar_i2c_finish(dev);
}
-/*
- * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
- * iicck : I2C internal clock < 20 MHz
- * ticf : I2C SCL falling time: 35 ns
- * tr : I2C SCL rising time: 200 ns
- * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
- * F[n] : n rounded up to an integer
- */
-static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
+static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
{
- u32 iicck, f, scl, scgd;
- u32 intd = 5;
-
- int bit = 0, cdf_width = 3;
- for (bit = 0; bit < (1 << cdf_width); bit++) {
- iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
- if (iicck < 20000000)
- break;
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
+ int i, ret = -EREMOTEIO;
+
+ ret = rcar_i2c_set_addr(dev, msg->addr, 0);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < msg->len; i++) {
+ writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
+ writel(icmcr, priv->base + RCAR_I2C_ICMCR);
+ writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
+
+ ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
+ RCAR_I2C_ICMSR_MDE, true, 100, true);
+ if (ret)
+ return ret;
}
- if (bit > (1 << cdf_width)) {
- puts("rcar-i2c: Can not get CDF\n");
- return 0;
- }
+ writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
+ icmcr |= RCAR_I2C_ICMCR_FSB;
+ writel(icmcr, priv->base + RCAR_I2C_ICMCR);
- if (i2c_no == 0)
- intd = 50;
+ return rcar_i2c_finish(dev);
+}
- f = (35 + 200 + intd) * (iicck / 1000000000);
+static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
+{
+ int ret;
- for (scgd = 0; scgd < 0x40; scgd++) {
- scl = iicck / (20 + (scgd * 8) + f);
- if (scl <= bus_speed)
- break;
- }
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD)
+ ret = rcar_i2c_read_common(dev, msg);
+ else
+ ret = rcar_i2c_write_common(dev, msg);
- if (scgd > 0x40) {
- puts("rcar-i2c: Can not get SDGB\n");
- return 0;
+ if (ret)
+ return -EREMOTEIO;
}
- debug("%s: scl: %d\n", __func__, scl);
- debug("%s: bit %x\n", __func__, bit);
- debug("%s: scgd %x\n", __func__, scgd);
- debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
+ return ret;
+}
+
+static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
+{
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
- return scgd << (cdf_width) | bit;
+ /* Ignore address 0, slave address */
+ if (addr == 0)
+ return -EINVAL;
+
+ ret = rcar_i2c_set_addr(dev, addr, 1);
+ writel(0, priv->base + RCAR_I2C_ICMSR);
+ return ret;
}
-static void
-rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
{
- struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
- u32 icccr = 0;
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ u32 scgd, cdf, round, ick, sum, scl;
+ unsigned long rate;
- /* No i2c support prior to relocation */
- if (!(gd->flags & GD_FLG_RELOC))
- return;
+ /*
+ * calculate SCL clock
+ * see
+ * ICCCR
+ *
+ * ick = clkp / (1 + CDF)
+ * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
+ *
+ * ick : I2C internal clock < 20 MHz
+ * ticf : I2C SCL falling time
+ * tr : I2C SCL rising time
+ * intd : LSI internal delay
+ * clkp : peripheral_clk
+ * F[] : integer up-valuation
+ */
+ rate = clk_get_rate(&priv->clk);
+ cdf = rate / 20000000;
+ if (cdf >= 8) {
+ dev_err(dev, "Input clock %lu too high\n", rate);
+ return -EIO;
+ }
+ ick = rate / (cdf + 1);
/*
- * reset slave mode.
- * slave mode is not used on this driver
+ * it is impossible to calculate large scale
+ * number on u32. separate it
+ *
+ * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
+ * = F[sum * ick / 1000000000]
+ * = F[(ick / 1000000) * sum / 1000]
*/
- writel(0, &dev->icsier);
- writel(0, &dev->icsar);
- writel(0, &dev->icscr);
- writel(0, &dev->icssr);
+ sum = 35 + 200 + priv->intdelay;
+ round = (ick + 500000) / 1000000 * sum;
+ round = (round + 500) / 1000;
- /* reset master mode */
- writel(0, &dev->icmier);
- writel(0, &dev->icmcr);
- writel(0, &dev->icmsr);
- writel(0, &dev->icmar);
-
- icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
- if (icccr == 0)
- puts("I2C: Init failed\n");
- else
- writel(icccr, &dev->icccr);
-}
+ /*
+ * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
+ *
+ * Calculation result (= SCL) should be less than
+ * bus_speed for hardware safety
+ *
+ * We could use something along the lines of
+ * div = ick / (bus_speed + 1) + 1;
+ * scgd = (div - 20 - round + 7) / 8;
+ * scl = ick / (20 + (scgd * 8) + round);
+ * (not fully verified) but that would get pretty involved
+ */
+ for (scgd = 0; scgd < 0x40; scgd++) {
+ scl = ick / (20 + (scgd * 8) + round);
+ if (scl <= bus_freq_hz)
+ goto scgd_find;
+ }
+ dev_err(dev, "it is impossible to calculate best SCL\n");
+ return -EIO;
-static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
- uint addr, int alen, u8 *data, int len)
-{
- struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
- int i;
+scgd_find:
+ dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
+ scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
- for (i = 0; i < len; i++)
- data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
+ priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
+ writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
return 0;
}
-static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
- int alen, u8 *data, int len)
+static int rcar_i2c_probe(struct udevice *dev)
{
- struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
- return rcar_i2c_raw_write(dev, chip, addr, data, len);
-}
+ struct rcar_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
-static int
-rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
-{
- return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
-}
+ priv->base = dev_read_addr_ptr(dev);
+ priv->intdelay = dev_read_u32_default(dev,
+ "i2c-scl-internal-delay-ns", 5);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
+
+ /* reset slave mode */
+ writel(0, priv->base + RCAR_I2C_ICSIER);
+ writel(0, priv->base + RCAR_I2C_ICSAR);
+ writel(0, priv->base + RCAR_I2C_ICSCR);
+ writel(0, priv->base + RCAR_I2C_ICSSR);
+
+ /* reset master mode */
+ writel(0, priv->base + RCAR_I2C_ICMIER);
+ writel(0, priv->base + RCAR_I2C_ICMCR);
+ writel(0, priv->base + RCAR_I2C_ICMSR);
+ writel(0, priv->base + RCAR_I2C_ICMAR);
+
+ ret = rcar_i2c_set_speed(dev, 100000);
+ if (ret)
+ clk_disable(&priv->clk);
-static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
- u32 icccr;
- int ret = 0;
-
- rcar_i2c_raw_rw_finish(dev);
-
- icccr = rcar_clock_gen(adap->hwadapnr, speed);
- if (icccr == 0) {
- puts("I2C: Init failed\n");
- ret = -1;
- } else {
- writel(icccr, &dev->icccr);
- }
return ret;
}
-/*
- * Register RCAR i2c adapters
- */
-U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
- rcar_i2c_write, rcar_i2c_set_bus_speed,
- CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
-U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
- rcar_i2c_write, rcar_i2c_set_bus_speed,
- CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
-U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
- rcar_i2c_write, rcar_i2c_set_bus_speed,
- CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
-U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
- rcar_i2c_write, rcar_i2c_set_bus_speed,
- CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)
+static const struct dm_i2c_ops rcar_i2c_ops = {
+ .xfer = rcar_i2c_xfer,
+ .probe_chip = rcar_i2c_probe_chip,
+ .set_bus_speed = rcar_i2c_set_speed,
+};
+
+static const struct udevice_id rcar_i2c_ids[] = {
+ { .compatible = "renesas,rcar-gen2-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_rcar) = {
+ .name = "i2c_rcar",
+ .id = UCLASS_I2C,
+ .of_match = rcar_i2c_ids,
+ .probe = rcar_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
+ .ops = &rcar_i2c_ops,
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-struct sh_i2c {
- u8 iccr1;
- u8 iccr2;
- u8 icmr;
- u8 icier;
- u8 icsr;
- u8 sar;
- u8 icdrt;
- u8 icdrr;
- u8 nf2cyc;
- u8 __pad0;
- u8 __pad1;
-};
-
-static struct sh_i2c *base;
-static u8 iccr1_cks, nf2cyc;
-
-/* ICCR1 */
-#define SH_I2C_ICCR1_ICE (1 << 7)
-#define SH_I2C_ICCR1_RCVD (1 << 6)
-#define SH_I2C_ICCR1_MST (1 << 5)
-#define SH_I2C_ICCR1_TRS (1 << 4)
-#define SH_I2C_ICCR1_MTRS \
- (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
-
-/* ICCR1 */
-#define SH_I2C_ICCR2_BBSY (1 << 7)
-#define SH_I2C_ICCR2_SCP (1 << 6)
-#define SH_I2C_ICCR2_SDAO (1 << 5)
-#define SH_I2C_ICCR2_SDAOP (1 << 4)
-#define SH_I2C_ICCR2_SCLO (1 << 3)
-#define SH_I2C_ICCR2_IICRST (1 << 1)
-
-#define SH_I2C_ICIER_TIE (1 << 7)
-#define SH_I2C_ICIER_TEIE (1 << 6)
-#define SH_I2C_ICIER_RIE (1 << 5)
-#define SH_I2C_ICIER_NAKIE (1 << 4)
-#define SH_I2C_ICIER_STIE (1 << 3)
-#define SH_I2C_ICIER_ACKE (1 << 2)
-#define SH_I2C_ICIER_ACKBR (1 << 1)
-#define SH_I2C_ICIER_ACKBT (1 << 0)
-
-#define SH_I2C_ICSR_TDRE (1 << 7)
-#define SH_I2C_ICSR_TEND (1 << 6)
-#define SH_I2C_ICSR_RDRF (1 << 5)
-#define SH_I2C_ICSR_NACKF (1 << 4)
-#define SH_I2C_ICSR_STOP (1 << 3)
-#define SH_I2C_ICSR_ALOVE (1 << 2)
-#define SH_I2C_ICSR_AAS (1 << 1)
-#define SH_I2C_ICSR_ADZ (1 << 0)
-
-#define IRQ_WAIT 1000
-
-static void sh_i2c_send_stop(struct sh_i2c *base)
-{
- clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP);
-}
-
-static int check_icsr_bits(struct sh_i2c *base, u8 bits)
-{
- int i;
-
- for (i = 0; i < IRQ_WAIT; i++) {
- if (bits & readb(&base->icsr))
- return 0;
- udelay(10);
- }
-
- return 1;
-}
-
-static int check_stop(struct sh_i2c *base)
-{
- int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
-
- return ret;
-}
-
-static int check_tend(struct sh_i2c *base, int stop)
-{
- int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
-
- if (stop) {
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
- sh_i2c_send_stop(base);
- }
-
- clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
- return ret;
-}
-
-static int check_tdre(struct sh_i2c *base)
-{
- return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
-}
-
-static int check_rdrf(struct sh_i2c *base)
-{
- return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
-}
-
-static int check_bbsy(struct sh_i2c *base)
-{
- int i;
-
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
- return 0;
- udelay(10);
- }
- return 1;
-}
-
-static int check_ackbr(struct sh_i2c *base)
-{
- int i;
-
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
- return 0;
- udelay(10);
- }
-
- return 1;
-}
-
-static void sh_i2c_reset(struct sh_i2c *base)
-{
- setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
-
- udelay(100);
-
- clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
-}
-
-static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
-{
- if (check_bbsy(base)) {
- puts("i2c bus busy\n");
- goto fail;
- }
-
- setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
-
- writeb((id << 1), &base->icdrt);
-
- if (check_tend(base, 0)) {
- puts("TEND check fail...\n");
- goto fail;
- }
-
- if (check_ackbr(base)) {
- check_tend(base, 0);
- sh_i2c_send_stop(base);
- goto fail;
- }
-
- writeb(reg, &base->icdrt);
-
- if (check_tdre(base)) {
- puts("TDRE check fail...\n");
- goto fail;
- }
-
- if (check_tend(base, 0)) {
- puts("TEND check fail...\n");
- goto fail;
- }
-
- return 0;
-fail:
-
- return 1;
-}
-
-static int
-i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
-{
- int i;
-
- if (i2c_set_addr(base, id, reg)) {
- puts("Fail set slave address\n");
- return 1;
- }
-
- for (i = 0; i < size; i++) {
- writeb(val[i], &base->icdrt);
- check_tdre(base);
- }
-
- check_tend(base, 1);
- check_stop(base);
-
- udelay(100);
-
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
- sh_i2c_reset(base);
-
- return 0;
-}
-
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
-{
- u8 ret = 0;
-
- if (i2c_set_addr(base, id, reg)) {
- puts("Fail set slave address\n");
- goto fail;
- }
-
- clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
- writeb((id << 1) | 1, &base->icdrt);
-
- if (check_tend(base, 0))
- puts("TDRE check fail...\n");
-
- clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
- setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
- setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
-
- /* read data (dummy) */
- ret = readb(&base->icdrr);
-
- if (check_rdrf(base)) {
- puts("check RDRF error\n");
- goto fail;
- }
-
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
- udelay(1000);
-
- sh_i2c_send_stop(base);
-
- if (check_stop(base)) {
- puts("check STOP error\n");
- goto fail;
- }
-
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
-
- /* data read */
- ret = readb(&base->icdrr);
-
-fail:
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
-
- return ret;
-}
-
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int current_bus;
-
-/**
- * i2c_set_bus_num - change active I2C bus
- * @bus: bus index, zero based
- * @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- switch (bus) {
- case 0:
- base = (void *)CONFIG_SH_I2C_BASE0;
- break;
- case 1:
- base = (void *)CONFIG_SH_I2C_BASE1;
- break;
- default:
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- current_bus = bus;
-
- return 0;
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveaddr)
-{
-#ifdef CONFIG_I2C_MULTI_BUS
- current_bus = 0;
-#endif
- base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
-
- if (speed == 400000)
- iccr1_cks = 0x07;
- else
- iccr1_cks = 0x0F;
-
- nf2cyc = 1;
-
- /* Reset */
- sh_i2c_reset(base);
-
- /* ICE enable and set clock */
- writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1);
- writeb(nf2cyc, &base->nf2cyc);
-}
-
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
-{
- int i = 0;
- for (i = 0; i < len; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
- return 0;
-}
-
-/*
- * i2c_write: - Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be written
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
-{
- return i2c_raw_write(base, chip, addr, buffer, len);
-}
-
-/*
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip: address of the chip which is searched for
- * @return: 0 if a chip was found, -1 otherwhise
- */
-int i2c_probe(u8 chip)
-{
- u8 byte;
- return i2c_read(chip, 0, 0, &byte, 1);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Author: Alex Bounine
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <config.h>
-#include <common.h>
-
-#include <tsi108.h>
-
-#if defined(CONFIG_CMD_I2C)
-
-#define I2C_DELAY 100000
-#undef DEBUG_I2C
-
-#ifdef DEBUG_I2C
-#define DPRINT(x) printf (x)
-#else
-#define DPRINT(x)
-#endif
-
-/* All functions assume that Tsi108 I2C block is the only master on the bus */
-/* I2C read helper function */
-
-void i2c_init(int speed, int slaveaddr)
-{
- /*
- * The TSI108 has a fixed I2C clock rate and doesn't support slave
- * operation. This function only exists as a stub to fit into the
- * U-Boot I2C API.
- */
-}
-
-static int i2c_read_byte (
- uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
- uchar chip_addr,/* I2C device address on the bus */
- uint byte_addr, /* Byte address within I2C device */
- uchar * buffer /* pointer to data buffer */
- )
-{
- u32 temp;
- u32 to_count = I2C_DELAY;
- u32 op_status = TSI108_I2C_TIMEOUT_ERR;
- u32 chan_offset = TSI108_I2C_OFFSET;
-
- DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
- i2c_chan, chip_addr, byte_addr));
-
- if (0 != i2c_chan)
- chan_offset = TSI108_I2C_SDRAM_OFFSET;
-
- /* Check if I2C operation is in progress */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
- I2C_CNTRL2_START))) {
- /* Set device address and operation (read = 0) */
- temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
- ((chip_addr >> 3) & 0x0F);
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
- temp;
-
- /* Issue the read command
- * (at this moment all other parameters are 0
- * (size = 1 byte, lane = 0)
- */
-
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
- (I2C_CNTRL2_START);
-
- /* Wait until operation completed */
- do {
- /* Read I2C operation status */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
- if (0 == (temp &
- (I2C_CNTRL2_I2C_CFGERR |
- I2C_CNTRL2_I2C_TO_ERR))
- ) {
- op_status = TSI108_I2C_SUCCESS;
-
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- chan_offset +
- I2C_RD_DATA);
-
- *buffer = (u8) (temp & 0xFF);
- } else {
- /* report HW error */
- op_status = TSI108_I2C_IF_ERROR;
-
- DPRINT (("I2C HW error reported: 0x%02x\n", temp));
- }
-
- break;
- }
- } while (to_count--);
- } else {
- op_status = TSI108_I2C_IF_BUSY;
-
- DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
- }
-
- DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
- return op_status;
-}
-
-/*
- * I2C Read interface as defined in "include/i2c.h" :
- * chip_addr: I2C chip address, range 0..127
- * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
- * NOTE: The bit 7 in the chip_addr serves as a channel select.
- * This hack is for enabling "i2c sdram" command on Tsi108 boards
- * without changes to common code. Used for I2C reads only.
- * byte_addr: Memory or register address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Pointer to destination buffer for data to be read
- * len: How many bytes to read
- *
- * Returns: 0 on success, not 0 on failure
- */
-
-int i2c_read (uchar chip_addr, uint byte_addr, int alen,
- uchar * buffer, int len)
-{
- u32 op_status = TSI108_I2C_PARAM_ERR;
- u32 i2c_if = 0;
-
- /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
- if (0xD0 == (chip_addr & ~0x07)) {
- i2c_if = 1;
- chip_addr &= 0x7F;
- }
- /* Check for valid I2C address */
- if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
- while (len--) {
- op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
-
- if (TSI108_I2C_SUCCESS != op_status) {
- DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
-
- break;
- }
- }
- }
-
- DPRINT (("I2C read() status: 0x%02x\n", op_status));
- return op_status;
-}
-
-/* I2C write helper function */
-
-static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
- uint byte_addr, /* Byte address within I2C device */
- uchar * buffer /* pointer to data buffer */
- )
-{
- u32 temp;
- u32 to_count = I2C_DELAY;
- u32 op_status = TSI108_I2C_TIMEOUT_ERR;
-
- /* Check if I2C operation is in progress */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
- /* Place data into the I2C Tx Register */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_TX_DATA) = (u32) * buffer;
-
- /* Set device address and operation */
- temp =
- I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
- ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_CNTRL1) = temp;
-
- /* Issue the write command (at this moment all other parameters
- * are 0 (size = 1 byte, lane = 0)
- */
-
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_CNTRL2) = (I2C_CNTRL2_START);
-
- op_status = TSI108_I2C_TIMEOUT_ERR;
-
- /* Wait until operation completed */
- do {
- /* Read I2C operation status */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
- if (0 == (temp &
- (I2C_CNTRL2_I2C_CFGERR |
- I2C_CNTRL2_I2C_TO_ERR))) {
- op_status = TSI108_I2C_SUCCESS;
- } else {
- /* report detected HW error */
- op_status = TSI108_I2C_IF_ERROR;
-
- DPRINT (("I2C HW error reported: 0x%02x\n", temp));
- }
-
- break;
- }
-
- } while (to_count--);
- } else {
- op_status = TSI108_I2C_IF_BUSY;
-
- DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
- }
-
- return op_status;
-}
-
-/*
- * I2C Write interface as defined in "include/i2c.h" :
- * chip_addr: I2C chip address, range 0..127
- * byte_addr: Memory or register address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Pointer to data to be written
- * len: How many bytes to write
- *
- * Returns: 0 on success, not 0 on failure
- */
-
-int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
- int len)
-{
- u32 op_status = TSI108_I2C_PARAM_ERR;
-
- /* Check for valid I2C address */
- if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
- while (len--) {
- op_status =
- i2c_write_byte (chip_addr, byte_addr++, buffer++);
-
- if (TSI108_I2C_SUCCESS != op_status) {
- DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
-
- break;
- }
- }
- }
-
- return op_status;
-}
-
-/*
- * I2C interface function as defined in "include/i2c.h".
- * Probe the given I2C chip address by reading single byte from offset 0.
- * Returns 0 if a chip responded, not 0 on failure.
- */
-
-int i2c_probe (uchar chip)
-{
- u32 tmp;
-
- /*
- * Try to read the first location of the chip.
- * The Tsi108 HW doesn't support sending just the chip address
- * and checkong for an <ACK> back.
- */
- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-#endif
help
The I2C address of the PCA9551 LED controller.
+config STM32MP_FUSE
+ bool "Enable STM32MP fuse wrapper providing the fuse API"
+ depends on ARCH_STM32MP && MISC
+ default y if CMD_FUSE
+ help
+ If you say Y here, you will get support for the fuse API (OTP)
+ for STM32MP architecture.
+ This API is needed for CMD_FUSE.
+
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
depends on STM32 && MISC
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <command.h>
+#include <misc.h>
+#include <errno.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+#define STM32MP_OTP_BANK 0
+
+/*
+ * The 'fuse' command API
+ */
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ int ret = 0;
+ struct udevice *dev;
+
+ switch (bank) {
+ case STM32MP_OTP_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
+ val, 4);
+ break;
+
+ default:
+ printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ struct udevice *dev;
+ int ret;
+
+ switch (bank) {
+ case STM32MP_OTP_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET,
+ &val, 4);
+ break;
+
+ default:
+ printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ struct udevice *dev;
+ int ret;
+
+ switch (bank) {
+ case STM32MP_OTP_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4);
+ break;
+
+ default:
+ printf("stm32mp %s: wrong value for bank %i\n", __func__, bank);
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ struct udevice *dev;
+ int ret;
+
+ switch (bank) {
+ case STM32MP_OTP_BANK:
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret)
+ return ret;
+ ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET,
+ &val, 4);
+ break;
+
+ default:
+ printf("stm32mp %s: wrong value for bank %i\n",
+ __func__, bank);
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
This adds a command and an API to do hardware partitioning on eMMC
devices.
+config SUPPORT_EMMC_RPMB
+ bool "Support eMMC replay protected memory block (RPMB)"
+ imply CMD_MMC_RPMB
+ help
+ Enable support for reading, writing and programming the
+ key for the Replay Protection Memory Block partition in eMMC.
+
config MMC_IO_VOLTAGE
bool "Support IO voltage configuration"
help
int clock; /* Current clock speed */
unsigned int max_clk; /* Max possible freq */
unsigned int blocks; /* remaining PIO blocks */
- int irq; /* Device IRQ */
u32 ns_per_fifo_word;
struct mmc_cmd *cmd; /* Current command */
struct mmc_data *data; /* Current data request */
- bool data_complete:1;/* Data finished before cmd */
bool use_busy:1; /* Wait for busy interrupt */
- bool wait_data_complete:1; /* Wait for data */
-
- /* for threaded irq handler */
- bool irq_block;
- bool irq_busy;
- bool irq_data;
struct udevice *dev;
struct mmc *mmc;
writel(host->cdiv, host->ioaddr + SDCDIV);
}
-static int bcm2835_finish_command(struct bcm2835_host *host);
-
-static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
+static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
{
- int timediff;
- u32 alternate_idle;
-
- alternate_idle = (host->data->flags & MMC_DATA_READ) ?
- SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
-
- timediff = 0;
+ int timediff = 0;
while (1) {
u32 edm, fsm;
if ((fsm == SDEDM_FSM_IDENTMODE) ||
(fsm == SDEDM_FSM_DATAMODE))
break;
- if (fsm == alternate_idle) {
+
+ if ((fsm == SDEDM_FSM_READWAIT) ||
+ (fsm == SDEDM_FSM_WRITESTART1) ||
+ (fsm == SDEDM_FSM_READDATA)) {
writel(edm | SDEDM_FORCE_DATA_MODE,
host->ioaddr + SDEDM);
break;
"wait_transfer_complete - still waiting after %d retries\n",
timediff);
bcm2835_dumpregs(host);
- return;
+ return -ETIMEDOUT;
}
}
+
+ return 0;
}
static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
fsm_state != SDEDM_FSM_READCRC)) ||
(!is_read &&
(fsm_state != SDEDM_FSM_WRITEDATA &&
+ fsm_state != SDEDM_FSM_WRITEWAIT1 &&
+ fsm_state != SDEDM_FSM_WRITEWAIT2 &&
+ fsm_state != SDEDM_FSM_WRITECRC &&
fsm_state != SDEDM_FSM_WRITESTART1 &&
fsm_state != SDEDM_FSM_WRITESTART2))) {
hsts = readl(host->ioaddr + SDHSTS);
is_read = (host->data->flags & MMC_DATA_READ) != 0;
ret = bcm2835_transfer_block_pio(host, is_read);
-
- if (host->wait_data_complete)
- bcm2835_wait_transfer_complete(host);
+ if (ret)
+ return ret;
sdhsts = readl(host->ioaddr + SDHSTS);
if (sdhsts & (SDHSTS_CRC16_ERROR |
return ret;
}
-static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
-{
- u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
- SDHCFG_BUSY_IRPT_EN;
-
- host->hcfg = (host->hcfg & ~all_irqs) |
- SDHCFG_DATA_IRPT_EN |
- SDHCFG_BUSY_IRPT_EN;
-
- writel(host->hcfg, host->ioaddr + SDHCFG);
-}
-
-static
-void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
WARN_ON(host->data);
if (!data)
return;
- host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK;
- host->data_complete = false;
-
/* Use PIO */
host->blocks = data->blocks;
- bcm2835_set_transfer_irqs(host);
-
writel(data->blocksize, host->ioaddr + SDHBCT);
writel(data->blocks, host->ioaddr + SDHBLC);
}
return 0;
}
-static int bcm2835_transfer_complete(struct bcm2835_host *host)
-{
- int ret = 0;
-
- WARN_ON(!host->data_complete);
-
- host->data = NULL;
-
- return ret;
-}
-
-static void bcm2835_finish_data(struct bcm2835_host *host)
-{
- host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
- writel(host->hcfg, host->ioaddr + SDHCFG);
-
- host->data_complete = true;
-
- if (host->cmd) {
- /* Data managed to finish before the
- * command completed. Make sure we do
- * things in the proper order.
- */
- dev_dbg(dev, "Finished early - HSTS %08x\n",
- readl(host->ioaddr + SDHSTS));
- } else {
- bcm2835_transfer_complete(host);
- }
-}
-
static int bcm2835_finish_command(struct bcm2835_host *host)
{
struct mmc_cmd *cmd = host->cmd;
/* Processed actual command. */
host->cmd = NULL;
- if (host->data && host->data_complete)
- ret = bcm2835_transfer_complete(host);
return ret;
}
return ret;
}
-static void bcm2835_busy_irq(struct bcm2835_host *host)
-{
- if (WARN_ON(!host->cmd)) {
- bcm2835_dumpregs(host);
- return;
- }
-
- if (WARN_ON(!host->use_busy)) {
- bcm2835_dumpregs(host);
- return;
- }
- host->use_busy = false;
-
- bcm2835_finish_command(host);
-}
-
-static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
+static int bcm2835_transmit(struct bcm2835_host *host)
{
+ u32 intmask = readl(host->ioaddr + SDHSTS);
int ret;
- /*
- * There are no dedicated data/space available interrupt
- * status bits, so it is necessary to use the single shared
- * data/space available FIFO status bits. It is therefore not
- * an error to get here when there is no data transfer in
- * progress.
- */
- if (!host->data)
- return;
-
+ /* Check for errors */
ret = bcm2835_check_data_error(host, intmask);
if (ret)
- goto finished;
-
- if (host->data->flags & MMC_DATA_WRITE) {
- /* Use the block interrupt for writes after the first block */
- host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
- host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
- writel(host->hcfg, host->ioaddr + SDHCFG);
- bcm2835_transfer_pio(host);
- } else {
- bcm2835_transfer_pio(host);
- host->blocks--;
- if ((host->blocks == 0))
- goto finished;
- }
- return;
+ return ret;
-finished:
- host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
- writel(host->hcfg, host->ioaddr + SDHCFG);
-}
-
-static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
-{
- if (!host->data)
- return;
- if ((host->blocks == 0))
- bcm2835_finish_data(host);
-}
-
-static void bcm2835_block_irq(struct bcm2835_host *host)
-{
- if (WARN_ON(!host->data)) {
- bcm2835_dumpregs(host);
- return;
- }
-
- WARN_ON(!host->blocks);
- if ((--host->blocks == 0))
- bcm2835_finish_data(host);
- else
- bcm2835_transfer_pio(host);
-}
+ ret = bcm2835_check_cmd_error(host, intmask);
+ if (ret)
+ return ret;
-static irqreturn_t bcm2835_irq(int irq, void *dev_id)
-{
- irqreturn_t result = IRQ_NONE;
- struct bcm2835_host *host = dev_id;
- u32 intmask;
-
- intmask = readl(host->ioaddr + SDHSTS);
-
- writel(SDHSTS_BUSY_IRPT |
- SDHSTS_BLOCK_IRPT |
- SDHSTS_SDIO_IRPT |
- SDHSTS_DATA_FLAG,
- host->ioaddr + SDHSTS);
-
- if (intmask & SDHSTS_BLOCK_IRPT) {
- bcm2835_check_data_error(host, intmask);
- host->irq_block = true;
- result = IRQ_WAKE_THREAD;
+ /* Handle wait for busy end */
+ if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
+ writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
+ host->use_busy = false;
+ bcm2835_finish_command(host);
}
- if (intmask & SDHSTS_BUSY_IRPT) {
- if (!bcm2835_check_cmd_error(host, intmask)) {
- host->irq_busy = true;
- result = IRQ_WAKE_THREAD;
- } else {
- result = IRQ_HANDLED;
+ /* Handle PIO data transfer */
+ if (host->data) {
+ ret = bcm2835_transfer_pio(host);
+ if (ret)
+ return ret;
+ host->blocks--;
+ if (host->blocks == 0) {
+ /* Wait for command to complete for real */
+ ret = bcm2835_wait_transfer_complete(host);
+ if (ret)
+ return ret;
+ /* Transfer complete */
+ host->data = NULL;
}
}
- /* There is no true data interrupt status bit, so it is
- * necessary to qualify the data flag with the interrupt
- * enable bit.
- */
- if ((intmask & SDHSTS_DATA_FLAG) &&
- (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
- bcm2835_data_irq(host, intmask);
- host->irq_data = true;
- result = IRQ_WAKE_THREAD;
- }
-
- return result;
-}
-
-static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
-{
- struct bcm2835_host *host = dev_id;
-
- if (host->irq_block) {
- host->irq_block = false;
- bcm2835_block_irq(host);
- }
-
- if (host->irq_busy) {
- host->irq_busy = false;
- bcm2835_busy_irq(host);
- }
-
- if (host->irq_data) {
- host->irq_data = false;
- bcm2835_data_threaded_irq(host);
- }
-
- return IRQ_HANDLED;
-}
-
-static void bcm2835_irq_poll(struct bcm2835_host *host)
-{
- u32 intmask;
-
- while (1) {
- intmask = readl(host->ioaddr + SDHSTS);
- if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT |
- SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) {
- bcm2835_irq(0, host);
- bcm2835_threaded_irq(0, host);
- return;
- }
- }
+ return 0;
}
static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
}
/* Wait for completion of busy signal or data transfer */
- while (host->use_busy || host->data)
- bcm2835_irq_poll(host);
+ while (host->use_busy || host->data) {
+ ret = bcm2835_transmit(host);
+ if (ret)
+ break;
+ }
return ret;
}
}
static const struct udevice_id ftsdc010_mmc_ids[] = {
- { .compatible = "andestech,atsdc010" },
+ { .compatible = "andestech,atfsdc010" },
{ }
};
static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
struct mmc_cmd *cmd, u32 cmd_param)
{
- if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN)
- writel(0, priv->base + SDMMC_ARG);
+ if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
+ writel(0, priv->base + SDMMC_CMD);
cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
if (cmd->resp_type & MMC_RSP_PRESENT) {
obj-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
-obj-$(CONFIG_FTSMC020) += ftsmc020.o
obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <faraday/ftsmc020.h>
-
-struct ftsmc020_config {
- unsigned int config;
- unsigned int timing;
-};
-
-static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
-{
- struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
-
- if (bank > 3) {
- printf("bank # %u invalid\n", bank);
- return;
- }
-
- writel(cfg->config, &smc->bank[bank].cr);
- writel(cfg->timing, &smc->bank[bank].tpr);
-}
-
-void ftsmc020_init(void)
-{
- struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(config); i++)
- ftsmc020_setup_bank(i, &config[i]);
-}
spin_unlock(&ubi->wl_lock);
}
+/**
+ * produce_free_peb - produce a free physical eraseblock.
+ * @ubi: UBI device description object
+ *
+ * This function tries to make a free PEB by means of synchronous execution of
+ * pending works. This may be needed if, for example the background thread is
+ * disabled. Returns zero in case of success and a negative error code in case
+ * of failure.
+ */
+static int produce_free_peb(struct ubi_device *ubi)
+{
+ int err;
+
+ while (!ubi->free.rb_node && ubi->works_count) {
+ dbg_wl("do one work synchronously");
+ err = do_work(ubi);
+
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
/**
* ubi_wl_get_peb - get a physical eraseblock.
* @ubi: UBI device description object
}
retried = 1;
up_read(&ubi->fm_eba_sem);
+ ret = produce_free_peb(ubi);
+ if (ret < 0) {
+ down_read(&ubi->fm_eba_sem);
+ goto out;
+ }
goto again;
}
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
- select PHYLIB
help
This driver supports the network interface units in the
Marvell Orion5x and Kirkwood SoCs
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
-obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
for (i = 0; i < PKTBUFSRX; i++) {
/* RXBUF_BADR */
- rxdes[i].rxdes2 = (unsigned int)net_rx_packets[i];
+ rxdes[i].rxdes2 = (unsigned int)(unsigned long)net_rx_packets[i];
rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
}
/* transmit ring */
- writel ((unsigned int)txdes, &ftmac100->txr_badr);
+ writel ((unsigned long)txdes, &ftmac100->txr_badr);
/* receive ring */
- writel ((unsigned int)rxdes, &ftmac100->rxr_badr);
+ writel ((unsigned long)rxdes, &ftmac100->rxr_badr);
/* poll receive descriptor automatically */
return -1;
}
- debug ("%s(%x, %x)\n", __func__, (int)packet, length);
+ debug ("%s(%lx, %x)\n", __func__, (unsigned long)packet, length);
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
/* initiate a transmit sequence */
- flush_dcache_range((u32)packet,(u32)packet+length);
- curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
+ flush_dcache_range((unsigned long)packet,(unsigned long)packet+length);
+ curr_des->txdes2 = (unsigned int)(unsigned long)packet; /* TXBUF_BADR */
curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
int len;
len = __ftmac100_recv(priv);
if (len)
- *packetp = (void *)curr_des->rxdes2;
+ *packetp = (uchar *)(unsigned long)curr_des->rxdes2;
return len ? len : -EAGAIN;
}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/***********************************************************************
- *
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- *
- * Description:
- * Ethernet interface for Tundra TSI108 bridge chip
- *
- ***********************************************************************/
-
-#include <config.h>
-
-#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
-#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/cache.h>
-
-#ifdef DEBUG
-#define TSI108_ETH_DEBUG 7
-#else
-#define TSI108_ETH_DEBUG 0
-#endif
-
-#if TSI108_ETH_DEBUG > 0
-#define debug_lev(lev, fmt, args...) \
-if (lev <= TSI108_ETH_DEBUG) \
-printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
-#else
-#define debug_lev(lev, fmt, args...) do{}while(0)
-#endif
-
-#define RX_PRINT_ERRORS
-#define TX_PRINT_ERRORS
-
-#define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
-
-#define ETH_PORT_OFFSET 0x400
-
-#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
-
-#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
-#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
-#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
-#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
-#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
-#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
-#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
-#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
-#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
-#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
-#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
-#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
-#define MAC_CONFIG_1_SIM_RESET (0x40000000)
-#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
-
-#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
-#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
-#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
-#define MAC_CONFIG_2_PAD_CRC (0x00000004)
-#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
-#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
-#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
-#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
-#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
-#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
-
-#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
-
-#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
-#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
-#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
-#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
-#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
-
-#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
-#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
-#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
-
-#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
-#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
-#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
-
-#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
-#define MII_MGMT_INDICATORS_BUSY (0x00000001)
-#define MII_MGMT_INDICATORS_SCAN (0x00000002)
-#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
-
-#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
-#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
-#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
-
-#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
-#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
-
-#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
-#define PORT_CONTROL_PRI (0x00000001)
-#define PORT_CONTROL_BPT (0x00010000)
-#define PORT_CONTROL_SPD (0x00040000)
-#define PORT_CONTROL_RBC (0x00080000)
-#define PORT_CONTROL_PRB (0x00200000)
-#define PORT_CONTROL_DIS (0x00400000)
-#define PORT_CONTROL_TBI (0x00800000)
-#define PORT_CONTROL_STE (0x10000000)
-#define PORT_CONTROL_ZOR (0x20000000)
-#define PORT_CONTROL_CLR (0x40000000)
-#define PORT_CONTROL_SRT (0x80000000)
-
-#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
-#define TX_CONFIG_START_Q (0x00000003)
-#define TX_CONFIG_EHP (0x00400000)
-#define TX_CONFIG_CHP (0x00800000)
-#define TX_CONFIG_RST (0x80000000)
-
-#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
-#define TX_CONTROL_GO (0x00008000)
-#define TX_CONTROL_MP (0x01000000)
-#define TX_CONTROL_EAI (0x20000000)
-#define TX_CONTROL_ABT (0x40000000)
-#define TX_CONTROL_EII (0x80000000)
-
-#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
-#define TX_STATUS_QUEUE_USABLE (0x0000000f)
-#define TX_STATUS_CURR_Q (0x00000300)
-#define TX_STATUS_ACT (0x00008000)
-#define TX_STATUS_QUEUE_IDLE (0x000f0000)
-#define TX_STATUS_EOQ_PENDING (0x0f000000)
-
-#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
-#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
-#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
-#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
-
-#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
-#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
-
-#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
-#define TX_ERROR_STATUS (0x00000278)
-#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
-#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
-#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
-#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
-
-#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
-#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define TX_QUEUE_0_CONFIG_AM (0x00004000)
-#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
-#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
-#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define OCN_PORT_HLP 0 /* HLP Interface */
-#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
-#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */
-#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
-#define OCN_PORT_MEMORY 4 /* Memory Controller */
-#define OCN_PORT_DMA 5 /* DMA Controller */
-#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
-#define OCN_PORT_PRINT 7 /* Print Engine Interface */
-
-#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
-
-#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
-#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-
-#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
-#define RX_CONFIG_DEF_Q (0x00000003)
-#define RX_CONFIG_EMF (0x00000100)
-#define RX_CONFIG_EUF (0x00000200)
-#define RX_CONFIG_BFE (0x00000400)
-#define RX_CONFIG_MFE (0x00000800)
-#define RX_CONFIG_UFE (0x00001000)
-#define RX_CONFIG_SE (0x00002000)
-#define RX_CONFIG_ABF (0x00200000)
-#define RX_CONFIG_APE (0x00400000)
-#define RX_CONFIG_CHP (0x00800000)
-#define RX_CONFIG_RST (0x80000000)
-
-#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
-#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
-#define GE_E0_RX_CONTROL_GO (0x00008000)
-#define GE_E0_RX_CONTROL_EAI (0x20000000)
-#define GE_E0_RX_CONTROL_ABT (0x40000000)
-#define GE_E0_RX_CONTROL_EII (0x80000000)
-
-#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
-#define RX_EXTENDED_STATUS (0x0000032c)
-#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
-#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
-#define RX_EXTENDED_STATUS_EOF (0x00000f00)
-#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
-
-#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
-#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
-
-#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
-#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define RX_QUEUE_0_CONFIG_AM (0x00004000)
-#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
-#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
-
-#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
-#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-
-/*
- * PHY register definitions
- */
-/* the first 15 PHY registers are standard. */
-#define PHY_CTRL_REG 0 /* Control Register */
-#define PHY_STATUS_REG 1 /* Status Regiser */
-#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */
-#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */
-#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */
-#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */
-#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */
-
-/*
- * PHY Register bit masks.
- */
-#define PHY_CTRL_RESET (1 << 15)
-#define PHY_CTRL_LOOPBACK (1 << 14)
-#define PHY_CTRL_SPEED0 (1 << 13)
-#define PHY_CTRL_AN_EN (1 << 12)
-#define PHY_CTRL_PWR_DN (1 << 11)
-#define PHY_CTRL_ISOLATE (1 << 10)
-#define PHY_CTRL_RESTART_AN (1 << 9)
-#define PHY_CTRL_FULL_DUPLEX (1 << 8)
-#define PHY_CTRL_CT_EN (1 << 7)
-#define PHY_CTRL_SPEED1 (1 << 6)
-
-#define PHY_STAT_100BASE_T4 (1 << 15)
-#define PHY_STAT_100BASE_X_FD (1 << 14)
-#define PHY_STAT_100BASE_X_HD (1 << 13)
-#define PHY_STAT_10BASE_T_FD (1 << 12)
-#define PHY_STAT_10BASE_T_HD (1 << 11)
-#define PHY_STAT_100BASE_T2_FD (1 << 10)
-#define PHY_STAT_100BASE_T2_HD (1 << 9)
-#define PHY_STAT_EXT_STAT (1 << 8)
-#define PHY_STAT_RESERVED (1 << 7)
-#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
-#define PHY_STAT_AN_COMPLETE (1 << 5)
-#define PHY_STAT_REM_FAULT (1 << 4)
-#define PHY_STAT_AN_CAP (1 << 3)
-#define PHY_STAT_LINK_UP (1 << 2)
-#define PHY_STAT_JABBER (1 << 1)
-#define PHY_STAT_EXT_CAP (1 << 0)
-
-#define TBI_CONTROL_2 0x11
-#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
-#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
-#define TBI_CONTROL_2_G_MII_MODE 0x0010
-#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
-#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
-#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
-#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
-#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
-#define TBI_CONTROL_2_SOFT_RESET 0x8000
-
-/* marvel specific */
-#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */
-#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */
-#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */
-
-/*
- * MARVELL 88E1111 PHY register bit masks
- */
-/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
-
-#define SPEC_STAT_SPEED_MASK (3 << 14)
-#define SPEC_STAT_FULL_DUP (1 << 13)
-#define SPEC_STAT_PAGE_RCVD (1 << 12)
-#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
-#define SPEC_STAT_LINK_UP (1 << 10)
-#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
-#define SPEC_STAT_MDIX (1 << 6)
-#define SPEC_STAT_POLARITY (1 << 1)
-#define SPEC_STAT_JABBER (1 << 0)
-
-#define SPEED_1000 (2 << 14)
-#define SPEED_100 (1 << 14)
-#define SPEED_10 (0 << 14)
-
-#define TBI_ADDR 0x1E /* Ten Bit Interface address */
-
-/* negotiated link parameters */
-#define LINK_SPEED_UNKNOWN 0
-#define LINK_SPEED_10 1
-#define LINK_SPEED_100 2
-#define LINK_SPEED_1000 3
-
-#define LINK_DUPLEX_UNKNOWN 0
-#define LINK_DUPLEX_HALF 1
-#define LINK_DUPLEX_FULL 2
-
-static unsigned int phy_address[] = { 8, 9 };
-
-#define vuint32 volatile u32
-
-/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
- * This structure is accessed by the ethernet DMA engine which means it
- * MUST be in LITTLE ENDIAN format */
-struct dma_descriptor {
- vuint32 start_addr0; /* buffer address, least significant bytes. */
- vuint32 start_addr1; /* buffer address, most significant bytes. */
- vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */
- vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
- vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
- vuint32 config_status; /* Configuration/Status. */
- vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */
- vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */
-};
-
-/* last next descriptor address flag */
-#define DMA_DESCR_LAST (1 << 31)
-
-/* TX DMA descriptor config status bits */
-#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */
-#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */
-#define DMA_DESCR_TX_PFVLAN (1 << 2)
-#define DMA_DESCR_TX_HUGE (1 << 3)
-#define DMA_DESCR_TX_PAD (1 << 4)
-#define DMA_DESCR_TX_CRC (1 << 5)
-#define DMA_DESCR_TX_DESCR_INT (1 << 14)
-#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000
-#define DMA_DESCR_TX_ONE_COLLISION (1 << 20)
-#define DMA_DESCR_TX_LATE_COLLISION (1 << 24)
-#define DMA_DESCR_TX_UNDERRUN (1 << 25)
-#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26)
-#define DMA_DESCR_TX_OK (1 << 30)
-#define DMA_DESCR_TX_OWNER (1 << 31)
-
-/* RX DMA descriptor status bits */
-#define DMA_DESCR_RX_EOF (1 << 0)
-#define DMA_DESCR_RX_SOF (1 << 1)
-#define DMA_DESCR_RX_VTF (1 << 2)
-#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3)
-#define DMA_DESCR_RX_SHORT_FRAME (1 << 4)
-#define DMA_DESCR_RX_HASH_MATCH (1 << 7)
-#define DMA_DESCR_RX_BAD_FRAME (1 << 8)
-#define DMA_DESCR_RX_OVERRUN (1 << 9)
-#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11)
-#define DMA_DESCR_RX_CRC_ERROR (1 << 12)
-#define DMA_DESCR_RX_DESCR_INT (1 << 13)
-#define DMA_DESCR_RX_OWNER (1 << 15)
-
-#define RX_BUFFER_SIZE PKTSIZE
-#define NUM_RX_DESC PKTBUFSRX
-
-static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
-
-static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
- __attribute__ ((aligned(32)));
-
-static struct dma_descriptor *rx_descr_current;
-
-static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
-static int tsi108_eth_send(struct eth_device *dev, void *packet, int length);
-static int tsi108_eth_recv (struct eth_device *dev);
-static void tsi108_eth_halt (struct eth_device *dev);
-static unsigned int read_phy (unsigned int base,
- unsigned int phy_addr, unsigned int phy_reg);
-static void write_phy (unsigned int base,
- unsigned int phy_addr,
- unsigned int phy_reg, unsigned int phy_data);
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print phy debug infomation
- */
-static void dump_phy_regs (unsigned int phy_addr)
-{
- int i;
-
- printf ("PHY %d registers\n", phy_addr);
- for (i = 0; i <= 30; i++) {
- printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
- }
- printf ("\n");
-
-}
-#else
-#define dump_phy_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void tx_diag_regs (unsigned int base)
-{
- int i;
- unsigned long dummy;
-
- printf ("TX diagnostics registers\n");
- reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_TX_DIAGNOSTIC_DATA(base);
- for (i = 0x00; i <= 0x05; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
- }
- reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_TX_DIAGNOSTIC_DATA(base);
- for (i = 0x40; i <= 0x47; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
- }
- printf ("\n");
-
-}
-#else
-#define tx_diag_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void rx_diag_regs (unsigned int base)
-{
- int i;
- unsigned long dummy;
-
- printf ("RX diagnostics registers\n");
- reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_RX_DIAGNOSTIC_DATA(base);
- for (i = 0x00; i <= 0x05; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
- }
- reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_RX_DIAGNOSTIC_DATA(base);
- for (i = 0x08; i <= 0x0a; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
- }
- printf ("\n");
-
-}
-#else
-#define rx_diag_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void debug_mii_regs (unsigned int base)
-{
- printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
- printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
- printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
- printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
- printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
- printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
- printf ("\n");
-
-}
-#else
-#define debug_mii_regs(base) do{}while(0)
-#endif
-
-/*
- * Wait until the phy bus is non-busy
- */
-static void phy_wait (unsigned int base, unsigned int condition)
-{
- int timeout;
-
- timeout = 0;
- while (reg_MII_MGMT_INDICATORS(base) & condition) {
- udelay (10);
- if (++timeout > 10000) {
- printf ("ERROR: timeout waiting for phy bus (%d)\n",
- condition);
- break;
- }
- }
-}
-
-/*
- * read phy register
- */
-static unsigned int read_phy (unsigned int base,
- unsigned int phy_addr, unsigned int phy_reg)
-{
- unsigned int value;
-
- phy_wait (base, MII_MGMT_INDICATORS_BUSY);
-
- reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
-
- /* Ensure that the Read Cycle bit is cleared prior to next read cycle */
- reg_MII_MGMT_COMMAND(base) = 0;
-
- /* start the read */
- reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
-
- /* wait for the read to complete */
- phy_wait (base,
- MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
-
- value = reg_MII_MGMT_STATUS(base);
-
- reg_MII_MGMT_COMMAND(base) = 0;
-
- return value;
-}
-
-/*
- * write phy register
- */
-static void write_phy (unsigned int base,
- unsigned int phy_addr,
- unsigned int phy_reg, unsigned int phy_data)
-{
- phy_wait (base, MII_MGMT_INDICATORS_BUSY);
-
- reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
-
- /* Ensure that the Read Cycle bit is cleared prior to next cycle */
- reg_MII_MGMT_COMMAND(base) = 0;
-
- /* start the write */
- reg_MII_MGMT_CONTROL(base) = phy_data;
-}
-
-/*
- * configure the marvell 88e1111 phy
- */
-static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
- int *duplex)
-{
- unsigned long base;
- unsigned long phy_addr;
- unsigned int phy_status;
- unsigned int phy_spec_status;
- int timeout;
- int phy_speed;
- int phy_duplex;
- unsigned int value;
-
- phy_speed = LINK_SPEED_UNKNOWN;
- phy_duplex = LINK_DUPLEX_UNKNOWN;
-
- base = dev->iobase;
- phy_addr = (unsigned long)dev->priv;
-
- /* Take the PHY out of reset. */
- write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
-
- /* Wait for the reset process to complete. */
- udelay (10);
- timeout = 0;
- while ((phy_status =
- read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
- udelay (10);
- if (++timeout > 10000) {
- printf ("ERROR: timeout waiting for phy reset\n");
- break;
- }
- }
-
- /* TBI Configuration. */
- write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
- TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
- /* Wait for the link to be established. */
- timeout = 0;
- do {
- udelay (20000);
- phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
- if (++timeout > 100) {
- debug_lev(1, "ERROR: unable to establish link!!!\n");
- break;
- }
- } while ((phy_status & PHY_STAT_LINK_UP) == 0);
-
- if ((phy_status & PHY_STAT_LINK_UP) == 0)
- return 0;
-
- value = 0;
- phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
- if (phy_spec_status & SPEC_STAT_RESOLVED) {
- switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
- case SPEED_1000:
- phy_speed = LINK_SPEED_1000;
- value |= PHY_CTRL_SPEED1;
- break;
- case SPEED_100:
- phy_speed = LINK_SPEED_100;
- value |= PHY_CTRL_SPEED0;
- break;
- case SPEED_10:
- phy_speed = LINK_SPEED_10;
- break;
- }
- if (phy_spec_status & SPEC_STAT_FULL_DUP) {
- phy_duplex = LINK_DUPLEX_FULL;
- value |= PHY_CTRL_FULL_DUPLEX;
- } else
- phy_duplex = LINK_DUPLEX_HALF;
- }
- /* set TBI speed */
- write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
- write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
-
-#if TSI108_ETH_DEBUG > 0
- printf ("%s link is up", dev->name);
- phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
- if (phy_spec_status & SPEC_STAT_RESOLVED) {
- switch (phy_speed) {
- case LINK_SPEED_1000:
- printf (", 1000 Mbps");
- break;
- case LINK_SPEED_100:
- printf (", 100 Mbps");
- break;
- case LINK_SPEED_10:
- printf (", 10 Mbps");
- break;
- }
- if (phy_duplex == LINK_DUPLEX_FULL)
- printf (", Full duplex");
- else
- printf (", Half duplex");
- }
- printf ("\n");
-#endif
-
- dump_phy_regs (TBI_ADDR);
- if (speed)
- *speed = phy_speed;
- if (duplex)
- *duplex = phy_duplex;
-
- return 1;
-}
-
-/*
- * External interface
- *
- * register the tsi108 ethernet controllers with the multi-ethernet system
- */
-int tsi108_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- int index;
-
- for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!dev) {
- printf("tsi108: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
- sprintf (dev->name, "TSI108_eth%d", index);
-
- dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
- dev->priv = (void *)(phy_address[index]);
- dev->init = tsi108_eth_probe;
- dev->halt = tsi108_eth_halt;
- dev->send = tsi108_eth_send;
- dev->recv = tsi108_eth_recv;
-
- eth_register(dev);
- }
- return index;
-}
-
-/*
- * probe for and initialize a single ethernet interface
- */
-static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
-{
- unsigned long base;
- unsigned long value;
- int index;
- struct dma_descriptor *tx_descr;
- struct dma_descriptor *rx_descr;
- int speed;
- int duplex;
-
- base = dev->iobase;
-
- reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
-
- /* Bring DMA/FIFO out of reset. */
- reg_TX_CONFIG(base) = 0x00000000;
- reg_RX_CONFIG(base) = 0x00000000;
-
- reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
- reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
-
- /* Bring MAC out of reset. */
- reg_MAC_CONFIG_1(base) = 0x00000000;
-
- /* DMA MAC configuration. */
- reg_MAC_CONFIG_1(base) =
- MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
-
- reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
- reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
-
- /* Note: Early tsi108 manual did not have correct byte order
- * for the station address.*/
- reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
- (dev->enetaddr[4] << 16) |
- (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
-
- reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
- (dev->enetaddr[0] << 16);
-
- if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
- return -1;
-
- value =
- MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
- MAC_CONFIG_2_CRC_ENABLE;
- if (speed == LINK_SPEED_1000)
- value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
- else {
- value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
- reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
- }
- if (duplex == LINK_DUPLEX_FULL) {
- value |= MAC_CONFIG_2_FULL_DUPLEX;
- reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
- } else
- reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
- reg_MAC_CONFIG_2(base) = value;
-
- reg_RX_CONFIG(base) = RX_CONFIG_SE;
- reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
- reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
-
- /* initialize the RX DMA descriptors */
- rx_descr = &rx_descr_array[0];
- rx_descr_current = rx_descr;
- for (index = 0; index < NUM_RX_DESC; index++) {
- /* make sure the receive buffers are not in cache */
- invalidate_dcache_range((unsigned long)net_rx_packets[index],
- (unsigned long)net_rx_packets[index] +
- RX_BUFFER_SIZE);
- rx_descr->start_addr0 =
- cpu_to_le32((vuint32) net_rx_packets[index]);
- rx_descr->start_addr1 = 0;
- rx_descr->next_descr_addr0 =
- cpu_to_le32((vuint32) (rx_descr + 1));
- rx_descr->next_descr_addr1 = 0;
- rx_descr->vlan_byte_count = 0;
- rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
- DMA_DESCR_RX_OWNER);
- rx_descr++;
- }
- rx_descr--;
- rx_descr->next_descr_addr0 = 0;
- rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- /* Push the descriptors to RAM so the ethernet DMA can see them */
- invalidate_dcache_range((unsigned long)rx_descr_array,
- (unsigned long)rx_descr_array +
- sizeof(rx_descr_array));
-
- /* enable RX queue */
- reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
- reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
- /* enable receive DMA */
- reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
-
- reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
- reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
-
- /* initialize the TX DMA descriptor */
- tx_descr = &tx_descriptor;
-
- tx_descr->start_addr0 = 0;
- tx_descr->start_addr1 = 0;
- tx_descr->next_descr_addr0 = 0;
- tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- tx_descr->vlan_byte_count = 0;
- tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
- DMA_DESCR_TX_SOF |
- DMA_DESCR_TX_EOF);
- /* enable TX queue */
- reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
-
- return 0;
-}
-
-/*
- * send a packet
- */
-static int tsi108_eth_send(struct eth_device *dev, void *packet, int length)
-{
- unsigned long base;
- int timeout;
- struct dma_descriptor *tx_descr;
- unsigned long status;
-
- base = dev->iobase;
- tx_descr = &tx_descriptor;
-
- /* Wait until the last packet has been transmitted. */
- timeout = 0;
- do {
- /* make sure we see the changes made by the DMA engine */
- invalidate_dcache_range((unsigned long)tx_descr,
- (unsigned long)tx_descr +
- sizeof(struct dma_descriptor));
-
- if (timeout != 0)
- udelay (15);
- if (++timeout > 10000) {
- tx_diag_regs(base);
- debug_lev(1,
- "ERROR: timeout waiting for last transmit packet to be sent\n");
- return 0;
- }
- } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
-
- status = le32_to_cpu(tx_descr->config_status);
- if ((status & DMA_DESCR_TX_OK) == 0) {
-#ifdef TX_PRINT_ERRORS
- printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
- status & DMA_DESCR_TX_OK ? "tx error, " : "",
- status & DMA_DESCR_TX_RETRY_LIMIT ?
- "retry limit reached, " : "",
- status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
- status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
- : "");
-#endif
- }
-
- debug_lev (9, "sending packet %d\n", length);
- tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
- tx_descr->start_addr1 = 0;
- tx_descr->next_descr_addr0 = 0;
- tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- tx_descr->vlan_byte_count = cpu_to_le32(length);
- tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
- DMA_DESCR_TX_CRC |
- DMA_DESCR_TX_PAD |
- DMA_DESCR_TX_SOF |
- DMA_DESCR_TX_EOF);
-
- invalidate_dcache_range((unsigned long)tx_descr,
- (unsigned long)tx_descr +
- sizeof(struct dma_descriptor));
-
- invalidate_dcache_range((unsigned long)packet,
- (unsigned long)packet + length);
-
- reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
- reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
-
- return length;
-}
-
-/*
- * Check for received packets and send them up the protocal stack
- */
-static int tsi108_eth_recv (struct eth_device *dev)
-{
- struct dma_descriptor *rx_descr;
- unsigned long base;
- int length = 0;
- unsigned long status;
- uchar *buffer;
-
- base = dev->iobase;
-
- /* make sure we see the changes made by the DMA engine */
- invalidate_dcache_range ((unsigned long)rx_descr_array,
- (unsigned long)rx_descr_array +
- sizeof(rx_descr_array));
-
- /* process all of the received packets */
- rx_descr = rx_descr_current;
- while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
- /* check for error */
- status = le32_to_cpu(rx_descr->config_status);
- if (status & DMA_DESCR_RX_BAD_FRAME) {
-#ifdef RX_PRINT_ERRORS
- printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
- status,
- status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
- : "",
- status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
- : "",
- status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
- "",
- status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
- status & DMA_DESCR_RX_MAX_FRAME_LEN ?
- "max length, " : "",
- status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
- "");
-#endif
- } else {
- length =
- le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
-
- /*** process packet ***/
- buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0));
- net_process_received_packet(buffer, length);
-
- invalidate_dcache_range ((unsigned long)buffer,
- (unsigned long)buffer +
- RX_BUFFER_SIZE);
- }
- /* Give this buffer back to the DMA engine */
- rx_descr->vlan_byte_count = 0;
- rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
- DMA_DESCR_RX_OWNER);
- /* move descriptor pointer forward */
- rx_descr =
- (struct dma_descriptor
- *)(le32_to_cpu (rx_descr->next_descr_addr0));
- if (rx_descr == 0)
- rx_descr = &rx_descr_array[0];
- }
- /* remember where we are for next time */
- rx_descr_current = rx_descr;
-
- /* If the DMA engine has reached the end of the queue
- * start over at the begining */
- if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
-
- reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
- reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
- reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
- }
-
- return length;
-}
-
-/*
- * disable an ethernet interface
- */
-static void tsi108_eth_halt (struct eth_device *dev)
-{
- unsigned long base;
-
- base = dev->iobase;
-
- /* Put DMA/FIFO into reset state. */
- reg_TX_CONFIG(base) = TX_CONFIG_RST;
- reg_RX_CONFIG(base) = RX_CONFIG_RST;
-
- /* Put MAC into reset state. */
- reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
-}
} else {
continue;
}
+
+ if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
+ type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
+ debug(" - beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
+
pos = -1;
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == type)
}
if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
- &bar_value) == 0) {
+ &bar_value,
+ found_mem64) == 0) {
/* Write it out and update our limit */
dm_pci_write_config32(dev, bar, (u32)bar_value);
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
if (pciauto_region_allocate(mem, bar_size,
- &bar_value) == 0) {
+ &bar_value,
+ false) == 0) {
dm_pci_write_config32(dev, rom_addr,
bar_value);
}
}
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
- pci_addr_t *bar)
+ pci_addr_t *bar, bool supports_64bit)
{
pci_addr_t addr;
if (!res) {
- debug("No resource");
+ debug("No resource\n");
goto error;
}
goto error;
}
+ if (upper_32_bits(addr) && !supports_64bit) {
+ debug("Cannot assign 64-bit address to 32-bit-only resource\n");
+ goto error;
+ }
+
res->bus_lower = addr + size;
- debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
+ debug("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
(unsigned long long)res->bus_lower);
*bar = addr;
}
#ifndef CONFIG_PCI_ENUM_ONLY
- if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
+ if (pciauto_region_allocate(bar_res, bar_size,
+ &bar_value, found_mem64) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
if (pciauto_region_allocate(mem, bar_size,
- &bar_value) == 0) {
+ &bar_value, false) == 0) {
pci_hose_write_config_dword(hose, dev, rom_addr,
bar_value);
}
used by USB2 and USB3 Host controllers available on
STiH407 SoC families.
+config PHY_STM32_USBPHYC
+ tristate "STMicroelectronics STM32 SoC USB HS PHY driver"
+ depends on PHY && ARCH_STM32MP
+ help
+ Enable this to support the High-Speed USB transceiver that is part of
+ STMicroelectronics STM32 SoCs.
+
+ This driver controls the entire USB PHY block: the USB PHY controller
+ (USBPHYC) and the two 8-bit wide UTMI+ interface. First interface is
+ used by an HS USB Host controller, and the second one is shared
+ between an HS USB OTG controller and an HS USB Host controller,
+ selected by an USB switch.
+
config MESON_GXL_USB_PHY
bool "Amlogic Meson GXL USB PHYs"
depends on PHY && ARCH_MESON && MESON_GXL
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <div64.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <power/regulator.h>
+
+/* USBPHYC registers */
+#define STM32_USBPHYC_PLL 0x0
+#define STM32_USBPHYC_MISC 0x8
+
+/* STM32_USBPHYC_PLL bit fields */
+#define PLLNDIV GENMASK(6, 0)
+#define PLLNDIV_SHIFT 0
+#define PLLFRACIN GENMASK(25, 10)
+#define PLLFRACIN_SHIFT 10
+#define PLLEN BIT(26)
+#define PLLSTRB BIT(27)
+#define PLLSTRBYP BIT(28)
+#define PLLFRACCTL BIT(29)
+#define PLLDITHEN0 BIT(30)
+#define PLLDITHEN1 BIT(31)
+
+/* STM32_USBPHYC_MISC bit fields */
+#define SWITHOST BIT(0)
+
+#define MAX_PHYS 2
+
+#define PLL_LOCK_TIME_US 100
+#define PLL_PWR_DOWN_TIME_US 5
+#define PLL_FVCO 2880 /* in MHz */
+#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
+#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
+
+struct pll_params {
+ u8 ndiv;
+ u16 frac;
+};
+
+struct stm32_usbphyc {
+ fdt_addr_t base;
+ struct clk clk;
+ struct stm32_usbphyc_phy {
+ struct udevice *vdd;
+ struct udevice *vdda1v1;
+ struct udevice *vdda1v8;
+ int index;
+ bool init;
+ bool powered;
+ } phys[MAX_PHYS];
+};
+
+void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
+{
+ unsigned long long fvco, ndiv, frac;
+
+ /*
+ * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
+ * | FVCO = 2880MHz
+ * | NDIV = integer part of input bits to set the LDF
+ * | FRACT = fractional part of input bits to set the LDF
+ * => PLLNDIV = integer part of (FVCO / (INFF*2))
+ * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
+ * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
+ */
+ fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
+
+ ndiv = fvco;
+ do_div(ndiv, (clk_rate * 2));
+ pll_params->ndiv = (u8)ndiv;
+
+ frac = fvco * (1 << 16);
+ do_div(frac, (clk_rate * 2));
+ frac = frac - (ndiv * (1 << 16));
+ pll_params->frac = (u16)frac;
+}
+
+static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
+{
+ struct pll_params pll_params;
+ u32 clk_rate = clk_get_rate(&usbphyc->clk);
+ u32 usbphyc_pll;
+
+ if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
+ pr_debug("%s: input clk freq (%dHz) out of range\n",
+ __func__, clk_rate);
+ return -EINVAL;
+ }
+
+ stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
+
+ usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
+ usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
+
+ if (pll_params.frac) {
+ usbphyc_pll |= PLLFRACCTL;
+ usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
+ & PLLFRACIN);
+ }
+
+ writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
+
+ pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
+ clk_rate, pll_params.ndiv, pll_params.frac);
+
+ return 0;
+}
+
+static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
+{
+ int i;
+
+ for (i = 0; i < MAX_PHYS; i++) {
+ if (usbphyc->phys[i].init)
+ return true;
+ }
+
+ return false;
+}
+
+static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
+{
+ int i;
+
+ for (i = 0; i < MAX_PHYS; i++) {
+ if (usbphyc->phys[i].powered)
+ return true;
+ }
+
+ return false;
+}
+
+static int stm32_usbphyc_phy_init(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
+ true : false;
+ int ret;
+
+ pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ /* Check if one phy port has already configured the pll */
+ if (pllen && stm32_usbphyc_is_init(usbphyc))
+ goto initialized;
+
+ if (pllen) {
+ clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
+ udelay(PLL_PWR_DOWN_TIME_US);
+ }
+
+ ret = stm32_usbphyc_pll_init(usbphyc);
+ if (ret)
+ return ret;
+
+ setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
+
+ /*
+ * We must wait PLL_LOCK_TIME_US before checking that PLLEN
+ * bit is still set
+ */
+ udelay(PLL_LOCK_TIME_US);
+
+ if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
+ return -EIO;
+
+initialized:
+ usbphyc_phy->init = true;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_exit(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+
+ pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ usbphyc_phy->init = false;
+
+ /* Check if other phy port requires pllen */
+ if (stm32_usbphyc_is_init(usbphyc))
+ return 0;
+
+ clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
+
+ /*
+ * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
+ * bit is still clear
+ */
+ udelay(PLL_PWR_DOWN_TIME_US);
+
+ if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
+ return -EIO;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_power_on(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
+
+ pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ if (usbphyc_phy->vdda1v1) {
+ ret = regulator_set_enable(usbphyc_phy->vdda1v1, true);
+ if (ret)
+ return ret;
+ }
+
+ if (usbphyc_phy->vdda1v8) {
+ ret = regulator_set_enable(usbphyc_phy->vdda1v8, true);
+ if (ret)
+ return ret;
+ }
+ if (usbphyc_phy->vdd) {
+ ret = regulator_set_enable(usbphyc_phy->vdd, true);
+ if (ret)
+ return ret;
+ }
+
+ usbphyc_phy->powered = true;
+
+ return 0;
+}
+
+static int stm32_usbphyc_phy_power_off(struct phy *phy)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
+ int ret;
+
+ pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ usbphyc_phy->powered = false;
+
+ if (stm32_usbphyc_is_powered(usbphyc))
+ return 0;
+
+ if (usbphyc_phy->vdda1v1) {
+ ret = regulator_set_enable(usbphyc_phy->vdda1v1, false);
+ if (ret)
+ return ret;
+ }
+
+ if (usbphyc_phy->vdda1v8) {
+ ret = regulator_set_enable(usbphyc_phy->vdda1v8, false);
+ if (ret)
+ return ret;
+ }
+
+ if (usbphyc_phy->vdd) {
+ ret = regulator_set_enable(usbphyc_phy->vdd, false);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
+ char *supply_name,
+ struct udevice **regulator)
+{
+ struct ofnode_phandle_args regulator_phandle;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, supply_name,
+ NULL, 0, 0,
+ ®ulator_phandle);
+ if (ret) {
+ dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
+ regulator_phandle.node,
+ regulator);
+
+ if (ret) {
+ dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int stm32_usbphyc_of_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count > 1) {
+ pr_debug("%s: invalid args_count: %d\n", __func__,
+ args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args[0] >= MAX_PHYS)
+ return -ENODEV;
+
+ if (args->args_count)
+ phy->id = args->args[0];
+ else
+ phy->id = 0;
+
+ return 0;
+}
+
+static const struct phy_ops stm32_usbphyc_phy_ops = {
+ .init = stm32_usbphyc_phy_init,
+ .exit = stm32_usbphyc_phy_exit,
+ .power_on = stm32_usbphyc_phy_power_on,
+ .power_off = stm32_usbphyc_phy_power_off,
+ .of_xlate = stm32_usbphyc_of_xlate,
+};
+
+static int stm32_usbphyc_probe(struct udevice *dev)
+{
+ struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
+ struct reset_ctl reset;
+ ofnode node;
+ int i, ret;
+
+ usbphyc->base = dev_read_addr(dev);
+ if (usbphyc->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* Enable clock */
+ ret = clk_get_by_index(dev, 0, &usbphyc->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&usbphyc->clk);
+ if (ret)
+ return ret;
+
+ /* Reset */
+ ret = reset_get_by_index(dev, 0, &reset);
+ if (!ret) {
+ reset_assert(&reset);
+ udelay(2);
+ reset_deassert(&reset);
+ }
+
+ /*
+ * parse all PHY subnodes in order to populate regulator associated
+ * to each PHY port
+ */
+ node = dev_read_first_subnode(dev);
+ for (i = 0; i < MAX_PHYS; i++) {
+ struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
+
+ usbphyc_phy->index = i;
+ usbphyc_phy->init = false;
+ usbphyc_phy->powered = false;
+ ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
+ &usbphyc_phy->vdd);
+ if (ret)
+ return ret;
+
+ ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply",
+ &usbphyc_phy->vdda1v1);
+ if (ret)
+ return ret;
+
+ ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply",
+ &usbphyc_phy->vdda1v8);
+ if (ret)
+ return ret;
+
+ node = dev_read_next_subnode(node);
+ }
+
+ /* Check if second port has to be used for host controller */
+ if (dev_read_bool(dev, "st,port2-switch-to-host"))
+ setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
+
+ return 0;
+}
+
+static const struct udevice_id stm32_usbphyc_of_match[] = {
+ { .compatible = "st,stm32mp1-usbphyc", },
+ { },
+};
+
+U_BOOT_DRIVER(stm32_usb_phyc) = {
+ .name = "stm32-usbphyc",
+ .id = UCLASS_PHY,
+ .of_match = stm32_usbphyc_of_match,
+ .ops = &stm32_usbphyc_phy_ops,
+ .probe = stm32_usbphyc_probe,
+ .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
+};
#include <asm/arch-armada8k/soc-info.h>
#include "pinctrl-mvebu.h"
+#define AP_EMMC_PHY_CTRL_REG 0x100
+#define CP_EMMC_PHY_CTRL_REG 0x424
+#define EMMC_PHY_CTRL_SDPHY_EN BIT(0)
+
+#define AP806_EMMC_CLK_PIN_ID 0
+#define AP806_EMMC_CLK_FUNC 0x1
+#define CP110_EMMC_CLK_PIN_ID 56
+#define CP110_EMMC_CLK_FUNC 0xe
+
DECLARE_GLOBAL_DATA_PTR;
+/* mvebu_pinctl_emmc_set_mux: configure sd/mmc PHY mux
+ * To enable SDIO/eMMC in Armada-APN806/CP110, need to configure PHY mux.
+ * eMMC/SD PHY register responsible for muxing between MPPs and SD/eMMC
+ * controller:
+ * - Bit0 enabled SDIO/eMMC PHY is used as a MPP muxltiplexer,
+ * - Bit0 disabled SDIO/eMMC PHY is connected to SDIO/eMMC controller
+ * If pin function is set to eMMC/SD, then configure the eMMC/SD PHY
+ * muxltiplexer register to be on SDIO/eMMC controller
+ */
+void mvebu_pinctl_emmc_set_mux(struct udevice *dev, u32 pin, u32 func)
+{
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ struct mvebu_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (!fdt_node_check_compatible(blob, node, "marvell,ap806-pinctrl")) {
+ if ((pin == AP806_EMMC_CLK_PIN_ID) &&
+ (func == AP806_EMMC_CLK_FUNC)) {
+ clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
+ EMMC_PHY_CTRL_SDPHY_EN);
+ }
+ } else if (!fdt_node_check_compatible(blob, node,
+ "marvell,armada-8k-cpm-pinctrl")) {
+ if ((pin == CP110_EMMC_CLK_PIN_ID) &&
+ (func == CP110_EMMC_CLK_FUNC)) {
+ clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
+ EMMC_PHY_CTRL_SDPHY_EN);
+ }
+ }
+}
+
/*
* mvebu_pinctrl_set_state: configure pin functions.
* @dev: the pinctrl device to be configured.
function = fdtdec_get_int(blob, node, "marvell,function", 0xff);
+ /*
+ * Check if setup of PHY mux is needed for this pins group.
+ * Only the first pin id in array is tested, all the rest use the same
+ * pin function.
+ */
+ mvebu_pinctl_emmc_set_mux(dev, pin_arr[0], function);
+
for (i = 0; i < pin_count; i++) {
- int reg_offset;
- int field_offset;
+ int reg_offset;
+ int field_offset;
int pin = pin_arr[i];
if (function > priv->max_func) {
return -EINVAL;
}
+ /* Check if setup of PHY mux is needed for this pins group. */
+ if (priv->pin_cnt < CP110_EMMC_CLK_PIN_ID)
+ mvebu_pinctl_emmc_set_mux(dev, AP806_EMMC_CLK_PIN_ID,
+ func_arr[AP806_EMMC_CLK_PIN_ID]);
+ else
+ mvebu_pinctl_emmc_set_mux(dev, CP110_EMMC_CLK_PIN_ID,
+ func_arr[CP110_EMMC_CLK_PIN_ID]);
+
for (pin = 0; pin < priv->pin_cnt; pin++) {
int reg_offset;
int field_offset;
static const struct udevice_id mvebu_pinctrl_ids[] = {
{ .compatible = "marvell,mvebu-pinctrl" },
- { .compatible = "marvell,armada-ap806-pinctrl" },
- { .compatible = "marvell,a70x0-pinctrl" },
- { .compatible = "marvell,a80x0-cp0-pinctrl" },
- { .compatible = "marvell,a80x0-cp1-pinctrl" },
+ { .compatible = "marvell,ap806-pinctrl" },
+ { .compatible = "marvell,armada-7k-pinctrl" },
+ { .compatible = "marvell,armada-8k-cpm-pinctrl" },
+ { .compatible = "marvell,armada-8k-cps-pinctrl" },
{ }
};
int pinctrl_select_state(struct udevice *dev, const char *statename)
{
+ /*
+ * Some device which is logical like mmc.blk, do not have
+ * a valid ofnode.
+ */
+ if (!ofnode_valid(dev->node))
+ return 0;
/*
* Try full-implemented pinctrl first.
* If it fails or is not implemented, try simple one.
This config enables implementation of driver-model pmic uclass features
for PMIC MAX8998. The driver implements read/write operations.
+config DM_PMIC_MC34708
+ bool "Enable Driver Model for PMIC MC34708"
+ depends on DM_PMIC
+ help
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC MC34708. The driver implements read/write operations.
+
config PMIC_MAX8997
bool "Enable Driver Model for PMIC MAX8997"
depends on DM_PMIC
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
+obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
* @reg: PMICs registers array
*/
struct sandbox_i2c_pmic_plat_data {
- u8 rw_reg;
- u8 reg[SANDBOX_PMIC_REG_COUNT];
+ u8 rw_reg, rw_idx;
+ u8 reg_count;
+ u8 trans_len;
+ u8 buf_size;
+ u8 *reg;
};
static int sandbox_i2c_pmic_read_data(struct udevice *emul, uchar chip,
{
struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
- if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) {
+ if (plat->rw_idx + len > plat->buf_size) {
pr_err("Request exceeds PMIC register range! Max register: %#x",
- SANDBOX_PMIC_REG_COUNT);
+ plat->reg_count);
return -EFAULT;
}
- debug("Read PMIC: %#x at register: %#x count: %d\n",
- (unsigned)chip & 0xff, plat->rw_reg, len);
+ debug("Read PMIC: %#x at register: %#x idx: %#x count: %d\n",
+ (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len);
- memcpy(buffer, &plat->reg[plat->rw_reg], len);
+ memcpy(buffer, plat->reg + plat->rw_idx, len);
return 0;
}
/* Set PMIC register for I/O */
plat->rw_reg = *buffer;
+ plat->rw_idx = plat->rw_reg * plat->trans_len;
- debug("Write PMIC: %#x at register: %#x count: %d\n",
- (unsigned)chip & 0xff, plat->rw_reg, len);
+ debug("Write PMIC: %#x at register: %#x idx: %#x count: %d\n",
+ (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len);
/* For read operation, set (write) only chip reg */
if (next_is_read)
buffer++;
len--;
- if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) {
+ if (plat->rw_idx + len > plat->buf_size) {
pr_err("Request exceeds PMIC register range! Max register: %#x",
- SANDBOX_PMIC_REG_COUNT);
+ plat->reg_count);
}
- memcpy(&plat->reg[plat->rw_reg], buffer, len);
+ memcpy(plat->reg + plat->rw_idx, buffer, len);
return 0;
}
static int sandbox_i2c_pmic_ofdata_to_platdata(struct udevice *emul)
{
struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+ struct udevice *pmic_dev = dev_get_parent(emul);
+ struct uc_pmic_priv *priv = dev_get_uclass_priv(pmic_dev);
const u8 *reg_defaults;
debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__);
+ plat->reg_count = pmic_reg_count(pmic_dev);
+ plat->trans_len = priv->trans_len;
+ plat->buf_size = plat->reg_count * plat->trans_len;
+
+ plat->reg = calloc(1, plat->buf_size);
+ if (!plat->reg) {
+ debug("Canot allocate memory (%d B) for PMIC I2C emulation!\n",
+ plat->buf_size);
+ return -ENOMEM;
+ }
reg_defaults = dev_read_u8_array_ptr(emul, "reg-defaults",
- SANDBOX_PMIC_REG_COUNT);
+ plat->buf_size);
if (!reg_defaults) {
pr_err("Property \"reg-defaults\" not found for device: %s!",
emul->name);
+ free(plat->reg);
return -EINVAL;
}
- memcpy(&plat->reg, reg_defaults, SANDBOX_PMIC_REG_COUNT);
+ memcpy(plat->reg, reg_defaults, plat->buf_size);
return 0;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fsl_pmic.h>
+#include <i2c.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int mc34708_reg_count(struct udevice *dev)
+{
+ return PMIC_NUM_OF_REGS;
+}
+
+static int mc34708_write(struct udevice *dev, uint reg, const u8 *buff,
+ int len)
+{
+ u8 buf[3] = { 0 };
+ int ret;
+
+ if (len != MC34708_TRANSFER_SIZE)
+ return -EINVAL;
+
+ /*
+ * The MC34708 sends data with big endian format, hence we need to
+ * perform manual byte swap.
+ */
+ buf[0] = buff[2];
+ buf[1] = buff[1];
+ buf[2] = buff[0];
+
+ ret = dm_i2c_write(dev, reg, buf, len);
+ if (ret)
+ printf("write error to device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static int mc34708_read(struct udevice *dev, uint reg, u8 *buff, int len)
+{
+ u8 buf[3] = { 0 };
+ int ret;
+
+ if (len != MC34708_TRANSFER_SIZE)
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev, reg, buf, len);
+ if (ret)
+ printf("read error from device: %p register: %#x!", dev, reg);
+
+ buff[0] = buf[2];
+ buff[1] = buf[1];
+ buff[2] = buf[0];
+
+ return ret;
+}
+
+static int mc34708_probe(struct udevice *dev)
+{
+ struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+
+ priv->trans_len = MC34708_TRANSFER_SIZE;
+
+ /*
+ * Handle PMIC Errata 37: APS mode not fully functional,
+ * use explicit PWM or PFM instead
+ */
+ pmic_clrsetbits(dev, MC34708_REG_SW12_OPMODE,
+ MC34708_SW1AMODE_MASK | MC34708_SW2MODE_MASK,
+ SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 14u));
+
+ pmic_clrsetbits(dev, MC34708_REG_SW345_OPMODE,
+ MC34708_SW3MODE_MASK | MC34708_SW4AMODE_MASK |
+ MC34708_SW4BMODE_MASK | MC34708_SW5MODE_MASK,
+ SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 6u) |
+ (SW_MODE_PWMPWM << 12u) | (SW_MODE_PWMPWM << 18u));
+
+ return 0;
+}
+
+static struct dm_pmic_ops mc34708_ops = {
+ .reg_count = mc34708_reg_count,
+ .read = mc34708_read,
+ .write = mc34708_write,
+};
+
+static const struct udevice_id mc34708_ids[] = {
+ { .compatible = "fsl,mc34708" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_mc34708) = {
+ .name = "mc34708_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = mc34708_ids,
+ .probe = mc34708_probe,
+ .ops = &mc34708_ops,
+};
int pmic_reg_read(struct udevice *dev, uint reg)
{
- u8 byte;
+ struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+ u32 val = 0;
int ret;
- debug("%s: reg=%x", __func__, reg);
- ret = pmic_read(dev, reg, &byte, 1);
- debug(", value=%x, ret=%d\n", byte, ret);
+ if (priv->trans_len < 1 || priv->trans_len > sizeof(val)) {
+ debug("Wrong transmission size [%d]\n", priv->trans_len);
+ return -EINVAL;
+ }
+
+ debug("%s: reg=%x priv->trans_len:%d", __func__, reg, priv->trans_len);
+ ret = pmic_read(dev, reg, (uint8_t *)&val, priv->trans_len);
+ debug(", value=%x, ret=%d\n", val, ret);
- return ret ? ret : byte;
+ return ret ? ret : val;
}
int pmic_reg_write(struct udevice *dev, uint reg, uint value)
{
- u8 byte = value;
+ struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
int ret;
- debug("%s: reg=%x, value=%x", __func__, reg, value);
- ret = pmic_write(dev, reg, &byte, 1);
+ if (priv->trans_len < 1 || priv->trans_len > sizeof(value)) {
+ debug("Wrong transmission size [%d]\n", priv->trans_len);
+ return -EINVAL;
+ }
+
+ debug("%s: reg=%x, value=%x priv->trans_len:%d", __func__, reg, value,
+ priv->trans_len);
+ ret = pmic_write(dev, reg, (uint8_t *)&value, priv->trans_len);
debug(", ret=%d\n", ret);
return ret;
int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
{
- u8 byte;
+ struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+ u32 val = 0;
int ret;
- ret = pmic_reg_read(dev, reg);
+ if (priv->trans_len < 1 || priv->trans_len > sizeof(val)) {
+ debug("Wrong transmission size [%d]\n", priv->trans_len);
+ return -EINVAL;
+ }
+
+ ret = pmic_read(dev, reg, (uint8_t *)&val, priv->trans_len);
if (ret < 0)
return ret;
- byte = (ret & ~clr) | set;
- return pmic_reg_write(dev, reg, byte);
+ val = (val & ~clr) | set;
+ return pmic_write(dev, reg, (uint8_t *)&val, priv->trans_len);
+}
+
+static int pmic_pre_probe(struct udevice *dev)
+{
+ struct uc_pmic_priv *pmic_priv = dev_get_uclass_priv(dev);
+
+ pmic_priv->trans_len = 1;
+ return 0;
}
UCLASS_DRIVER(pmic) = {
.id = UCLASS_PMIC,
.name = "pmic",
+ .pre_probe = pmic_pre_probe,
+ .per_device_auto_alloc_size = sizeof(struct uc_pmic_priv),
};
#include <asm/io.h>
#define MEM_MODE_MASK GENMASK(2, 0)
+#define SWP_FMC_OFFSET 10
+#define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
#define NOT_FOUND 0xff
struct stm32_fmc_regs {
struct ofnode_phandle_args args;
u32 *syscfg_base;
u32 mem_remap;
+ u32 swp_fmc;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
int ret;
- mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
- if (mem_remap != NOT_FOUND) {
- ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+ ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
- if (ret) {
- debug("%s: can't find syscon device (%d)\n", __func__,
- ret);
- return ret;
- }
-
+ if (ret) {
+ dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
+ } else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
- /* set memory mapping selection */
- clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
- } else {
- debug("%s: cannot find st,mem_remap property\n", __func__);
+ mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+ if (mem_remap != NOT_FOUND) {
+ /* set memory mapping selection */
+ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+ } else {
+ dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
+ }
+
+ swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
+ if (swp_fmc != NOT_FOUND) {
+ /* set fmc swapping selection */
+ clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
+ } else {
+ dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
+ }
+
+ dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
}
dev_for_each_subnode(bank_node, dev) {
driver will be available until the real driver model serial is
running.
+config DEBUG_ARC_SERIAL
+ bool "ARC UART"
+ depends on ARC_SERIAL
+ help
+ Select this to enable a debug UART using the ARC UART driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
config DEBUG_UART_ATMEL
bool "Atmel USART"
help
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_STM32
+ bool "STMicroelectronics STM32"
+ depends on STM32_SERIAL
+ help
+ Select this to enable a debug UART using the serial_stm32 driver
+ You will need to provide parameters to make this work.
+ The driver will be available until the real driver model
+ serial is running.
+
config DEBUG_UART_UNIPHIER
bool "UniPhier on-chip UART"
depends on ARCH_UNIPHIER
tree binding to operate, please refer to the document at
doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+config ARC_SERIAL
+ bool "ARC UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable support for ARC UART now typically
+ only used in Synopsys DesignWare ARC simulators like nSIM.
+
config ATMEL_USART
bool "Atmel USART support"
help
.ops = &arc_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+#ifdef CONFIG_DEBUG_ARC_SERIAL
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+ int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1;
+
+ writeb(arc_console_baud & 0xff, ®s->baudl);
+ writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readb(®s->status) & UART_TXEMPTY))
+ ;
+
+ writeb(c, ®s->data);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
+#include <dm/pinctrl.h>
/* Serial registers - this driver works in uartdm mode*/
#define UARTDM_RXFS 0x50 /* RX channel status register */
#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
#define UARTDM_RXFS_BUF_MASK 0x7
+#define UARTDM_MR1 0x00
+#define UARTDM_MR2 0x04
+#define UARTDM_CSR 0xA0
#define UARTDM_SR 0xA4 /* Status register */
#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
#define UARTDM_RF 0x140 /* UART Receive FIFO register */
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+static void uart_dm_init(struct msm_serial_data *priv)
+{
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR);
+ writel(0x0, priv->base + UARTDM_MR1);
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
+}
static int msm_serial_probe(struct udevice *dev)
{
+ int ret;
struct msm_serial_data *priv = dev_get_priv(dev);
- msm_uart_clk_init(dev); /* Ignore return value and hope clock was
- properly initialized by earlier loaders */
+ /* No need to reinitialize the UART after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
- if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
- writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
+ ret = msm_uart_clk_init(dev);
+ if (ret)
+ return ret;
- writel(0, priv->base + UARTDM_IMR);
- writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
- msm_serial_fetch(dev);
+ pinctrl_select_state(dev, "uart");
+ uart_dm_init(priv);
return 0;
}
#include <common.h>
#include <clk.h>
#include <dm.h>
-#include <asm/io.h>
#include <serial.h>
+#include <watchdog.h>
+#include <asm/io.h>
#include <asm/arch/stm32.h>
#include "serial_stm32.h"
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+static void _stm32_serial_setbrg(fdt_addr_t base,
+ struct stm32_uart_info *uart_info,
+ u32 clock_rate,
+ int baudrate)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ bool stm32f4 = uart_info->stm32f4;
u32 int_div, mantissa, fraction, oversampling;
- int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
+ int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
if (int_div < 16) {
oversampling = 8;
fraction = int_div % oversampling;
writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
+}
+
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ _stm32_serial_setbrg(plat->base, plat->uart_info,
+ plat->clock_rate, baudrate);
+
+ return 0;
+}
+
+static int stm32_serial_setparity(struct udevice *dev, enum serial_par parity)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
+ u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+ u32 config = 0;
+
+ if (stm32f4)
+ return -EINVAL; /* not supported in driver*/
+
+ clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
+ /* update usart configuration (uart need to be disable)
+ * PCE: parity check control
+ * PS : '0' : Even / '1' : Odd
+ * M[1:0] = '00' : 8 Data bits
+ * M[1:0] = '01' : 9 Data bits with parity
+ */
+ switch (parity) {
+ default:
+ case SERIAL_PAR_NONE:
+ config = 0;
+ break;
+ case SERIAL_PAR_ODD:
+ config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
+ break;
+ case SERIAL_PAR_EVEN:
+ config = USART_CR1_PCE | USART_CR1_M0;
+ break;
+ }
+ clrsetbits_le32(cr1,
+ USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
+ USART_CR1_M0,
+ config);
+ setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
return 0;
}
fdt_addr_t base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
- if ((isr & USART_ISR_FLAG_RXNE) == 0)
+ if ((isr & USART_ISR_RXNE) == 0)
return -EAGAIN;
- if (isr & USART_ISR_FLAG_ORE) {
+ if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
if (!stm32f4)
- setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
+ setbits_le32(base + ICR_OFFSET,
+ USART_ICR_PCECF | USART_ICR_ORECF);
else
readl(base + RDR_OFFSET(stm32f4));
return -EIO;
return readl(base + RDR_OFFSET(stm32f4));
}
-static int stm32_serial_putc(struct udevice *dev, const char c)
+static int _stm32_serial_putc(fdt_addr_t base,
+ struct stm32_uart_info *uart_info,
+ const char c)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ bool stm32f4 = uart_info->stm32f4;
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
return -EAGAIN;
writel(c, base + TDR_OFFSET(stm32f4));
return 0;
}
+static int stm32_serial_putc(struct udevice *dev, const char c)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ return _stm32_serial_putc(plat->base, plat->uart_info, c);
+}
+
static int stm32_serial_pending(struct udevice *dev, bool input)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
if (input)
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_ISR_FLAG_RXNE ? 1 : 0;
+ USART_ISR_RXNE ? 1 : 0;
else
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_ISR_FLAG_TXE ? 0 : 1;
+ USART_ISR_TXE ? 0 : 1;
+}
+
+static void _stm32_serial_init(fdt_addr_t base,
+ struct stm32_uart_info *uart_info)
+{
+ bool stm32f4 = uart_info->stm32f4;
+ u8 uart_enable_bit = uart_info->uart_enable_bit;
+
+ /* Disable uart-> enable fifo -> enable uart */
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+ if (uart_info->has_fifo)
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
}
static int stm32_serial_probe(struct udevice *dev)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
struct clk clk;
- fdt_addr_t base = plat->base;
int ret;
- bool stm32f4;
- u8 uart_enable_bit;
plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
- stm32f4 = plat->uart_info->stm32f4;
- uart_enable_bit = plat->uart_info->uart_enable_bit;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return plat->clock_rate;
};
- /* Disable uart-> enable fifo-> enable uart */
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
- if (plat->uart_info->has_fifo)
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
+ _stm32_serial_init(plat->base, plat->uart_info);
return 0;
}
.pending = stm32_serial_pending,
.getc = stm32_serial_getc,
.setbrg = stm32_serial_setbrg,
+ .setparity = stm32_serial_setparity
};
U_BOOT_DRIVER(serial_stm32) = {
.probe = stm32_serial_probe,
.flags = DM_FLAG_PRE_RELOC,
};
+
+#ifdef CONFIG_DEBUG_UART_STM32
+#include <debug_uart.h>
+static inline struct stm32_uart_info *_debug_uart_info(void)
+{
+ struct stm32_uart_info *uart_info;
+
+#if defined(CONFIG_STM32F4)
+ uart_info = &stm32f4_info;
+#elif defined(CONFIG_STM32F7)
+ uart_info = &stm32f7_info;
+#else
+ uart_info = &stm32h7_info;
+#endif
+ return uart_info;
+}
+
+static inline void _debug_uart_init(void)
+{
+ fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ struct stm32_uart_info *uart_info = _debug_uart_info();
+
+ _stm32_serial_init(base, uart_info);
+ _stm32_serial_setbrg(base, uart_info,
+ CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
+ printf("DEBUG done\n");
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ struct stm32_uart_info *uart_info = _debug_uart_info();
+
+ while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
+ WATCHDOG_RESET();
+}
+
+DEBUG_UART_FUNCS
+#endif
#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
#define ICR_OFFSET 0x20
+
/*
* STM32F4 has one Data Register (DR) for received or transmitted
* data, so map Receive Data Register (RDR) and Transmit Data
};
#define USART_CR1_FIFOEN BIT(29)
+#define USART_CR1_M1 BIT(28)
#define USART_CR1_OVER8 BIT(15)
+#define USART_CR1_M0 BIT(12)
+#define USART_CR1_PCE BIT(10)
+#define USART_CR1_PS BIT(9)
#define USART_CR1_TE BIT(3)
#define USART_CR1_RE BIT(2)
#define USART_CR3_OVRDIS BIT(12)
-#define USART_ISR_FLAG_ORE BIT(3)
-#define USART_ISR_FLAG_RXNE BIT(5)
-#define USART_ISR_FLAG_TXE BIT(7)
+#define USART_ISR_TXE BIT(7)
+#define USART_ISR_RXNE BIT(5)
+#define USART_ISR_ORE BIT(3)
+#define USART_ISR_PE BIT(0)
#define USART_BRR_F_MASK GENMASK(7, 0)
#define USART_BRR_M_SHIFT 4
#define USART_BRR_M_MASK GENMASK(15, 4)
-#define USART_ICR_OREF BIT(3)
+#define USART_ICR_ORECF BIT(3)
+#define USART_ICR_PCECF BIT(0)
+
#endif
int num_bytes;
u8 *cmd_buf = ns->cmd_buf;
size_t cmd_len = ns->cmd_len;
- size_t data_len = bitlen / 8;
+ unsigned long data_len = bitlen / 8;
int rf_cnt;
int ret = 0;
break;
}
if (data_out)
- debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n",
+ debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
*(uint *)data_out, data_out, *(uint *)data_in,
data_in, data_len);
num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
din = data_in;
dout = data_out;
while (num_chunks--) {
- tran_len = min(data_len, (size_t)max_tran_len);
+ tran_len = min((size_t)data_len, (size_t)max_tran_len);
ns->tran_len = tran_len;
num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
num_bytes = (tran_len) % CHUNK_SIZE;
menu "TPM support"
+comment "Please select only one TPM revision"
+ depends on TPM_V1 && TPM_V2
+
+config TPM_V1
+ bool "TPMv1.x support"
+ depends on TPM
+ default y
+ help
+ Major TPM versions are not compatible at all, choose either
+ one or the other. This option enables TPMv1.x drivers/commands.
+
+if TPM_V1 && !TPM_V2
+
config TPM_TIS_SANDBOX
bool "Enable sandbox TPM driver"
- depends on SANDBOX
+ depends on TPM_V1 && SANDBOX
help
- This driver emulates a TPM, providing access to base functions
+ This driver emulates a TPMv1.x, providing access to base functions
such as reading and writing TPM private data. This is enough to
support Chrome OS verified boot. Extend functionality is not
implemented.
config TPM_ATMEL_TWI
bool "Enable Atmel TWI TPM device driver"
- depends on TPM
+ depends on TPM_V1
help
This driver supports an Atmel TPM device connected on the I2C bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_TIS_INFINEON
bool "Enable support for Infineon SLB9635/45 TPMs on I2C"
- depends on TPM && DM_I2C
+ depends on TPM_V1 && DM_I2C
help
This driver supports Infineon TPM devices connected on the I2C bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_TIS_LPC
bool "Enable support for Infineon SLB9635/45 TPMs on LPC"
- depends on TPM && X86
+ depends on TPM_V1 && X86
+ select TPM_DRIVER_SELECTED
help
This driver supports Infineon TPM devices connected on the LPC bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_AUTH_SESSIONS
bool "Enable TPM authentication session support"
- depends on TPM
+ depends on TPM_V1
help
Enable support for authorised (AUTH1) commands as specified in the
TCG Main Specification 1.2. OIAP-authorised versions of the commands
config TPM_ST33ZP24_I2C
bool "STMicroelectronics ST33ZP24 I2C TPM"
- depends on TPM && DM_I2C
+ depends on TPM_V1 && DM_I2C
---help---
This driver supports STMicroelectronics TPM devices connected on the I2C bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_ST33ZP24_SPI
bool "STMicroelectronics ST33ZP24 SPI TPM"
- depends on TPM && DM_SPI
+ depends on TPM_V1 && DM_SPI
---help---
This driver supports STMicroelectronics TPM devices connected on the SPI bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_FLUSH_RESOURCES
bool "Enable TPM resource flushing support"
- depends on TPM
+ depends on TPM_V1
help
Enable support to flush specific resources (e.g. keys) from the TPM.
The functionality is available via the 'tpm' command as well.
config TPM_LOAD_KEY_BY_SHA1
bool "Enable TPM key loading by SHA1 support"
- depends on TPM
+ depends on TPM_V1
help
Enable support to load keys into the TPM by identifying
their parent via the public key's SHA1 hash.
config TPM_LIST_RESOURCES
bool "Enable TPM resource listing support"
- depends on TPM
+ depends on TPM_V1
help
Enable support to list specific resources (e.g. keys) within the TPM.
The functionality is available via the 'tpm' command as well.
+
+endif # TPM_V1
+
+config TPM_V2
+ bool "TPMv2.x support"
+ depends on TPM
+ help
+ Major TPM versions are not compatible at all, choose either
+ one or the other. This option enables TPMv2.x drivers/commands.
+
+if TPM_V2 && !TPM_V1
+
+config TPM2_TIS_SANDBOX
+ bool "Enable sandbox TPMv2.x driver"
+ depends on TPM_V2 && SANDBOX
+ select TPM_DRIVER_SELECTED
+ help
+ This driver emulates a TPMv2.x, providing access to base functions
+ such as basic configuration, PCR extension and PCR read. Extended
+ functionalities are not implemented.
+
+config TPM2_TIS_SPI
+ bool "Enable support for TPMv2.x SPI chips"
+ depends on TPM_V2 && DM_SPI
+ select TPM_DRIVER_SELECTED
+ help
+ This driver supports TPMv2.x devices connected on the SPI bus.
+ The usual TPM operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol.
+
+endif # TPM_V2
+
endmenu
obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
+
+obj-$(CONFIG_TPM2_TIS_SANDBOX) += tpm2_tis_sandbox.o
+obj-$(CONFIG_TPM2_TIS_SPI) += tpm2_tis_spi.o
#include <common.h>
#include <dm.h>
-#include <tpm.h>
#include <linux/unaligned/be_byteshift.h>
+#if defined(CONFIG_TPM_V1)
+#include <tpm-v1.h>
+#elif defined(CONFIG_TPM_V2)
+#include <tpm-v2.h>
+#endif
#include "tpm_internal.h"
int tpm_open(struct udevice *dev)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018, Bootlin
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <tpm-v2.h>
+#include <asm/state.h>
+#include <asm/unaligned.h>
+#include <linux/crc8.h>
+
+/* Hierarchies */
+enum tpm2_hierarchy {
+ TPM2_HIERARCHY_LOCKOUT = 0,
+ TPM2_HIERARCHY_ENDORSEMENT,
+ TPM2_HIERARCHY_PLATFORM,
+ TPM2_HIERARCHY_NB,
+};
+
+/* Subset of supported capabilities */
+enum tpm2_capability {
+ TPM_CAP_TPM_PROPERTIES = 0x6,
+};
+
+/* Subset of supported properties */
+#define TPM2_PROPERTIES_OFFSET 0x0000020E
+
+enum tpm2_cap_tpm_property {
+ TPM2_FAIL_COUNTER = 0,
+ TPM2_PROP_MAX_TRIES,
+ TPM2_RECOVERY_TIME,
+ TPM2_LOCKOUT_RECOVERY,
+ TPM2_PROPERTY_NB,
+};
+
+#define SANDBOX_TPM_PCR_NB 1
+
+static const u8 sandbox_extended_once_pcr[] = {
+ 0xf5, 0xa5, 0xfd, 0x42, 0xd1, 0x6a, 0x20, 0x30,
+ 0x27, 0x98, 0xef, 0x6e, 0xd3, 0x09, 0x97, 0x9b,
+ 0x43, 0x00, 0x3d, 0x23, 0x20, 0xd9, 0xf0, 0xe8,
+ 0xea, 0x98, 0x31, 0xa9, 0x27, 0x59, 0xfb, 0x4b,
+};
+
+struct sandbox_tpm2 {
+ /* TPM internal states */
+ bool init_done;
+ bool startup_done;
+ bool tests_done;
+ /* TPM password per hierarchy */
+ char pw[TPM2_HIERARCHY_NB][TPM2_DIGEST_LEN + 1];
+ int pw_sz[TPM2_HIERARCHY_NB];
+ /* TPM properties */
+ u32 properties[TPM2_PROPERTY_NB];
+ /* TPM PCRs */
+ u8 pcr[SANDBOX_TPM_PCR_NB][TPM2_DIGEST_LEN];
+ /* TPM PCR extensions */
+ u32 pcr_extensions[SANDBOX_TPM_PCR_NB];
+};
+
+/*
+ * Check the tag validity depending on the command (authentication required or
+ * not). If authentication is required, check it is valid. Update the auth
+ * pointer to point to the next chunk of data to process if needed.
+ */
+static int sandbox_tpm2_check_session(struct udevice *dev, u32 command, u16 tag,
+ const u8 **auth,
+ enum tpm2_hierarchy *hierarchy)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+ u32 handle, auth_sz, session_handle;
+ u16 nonce_sz, pw_sz;
+ const char *pw;
+
+ switch (command) {
+ case TPM2_CC_STARTUP:
+ case TPM2_CC_SELF_TEST:
+ case TPM2_CC_GET_CAPABILITY:
+ case TPM2_CC_PCR_READ:
+ if (tag != TPM2_ST_NO_SESSIONS) {
+ printf("No session required for command 0x%x\n",
+ command);
+ return TPM2_RC_BAD_TAG;
+ }
+
+ return 0;
+
+ case TPM2_CC_CLEAR:
+ case TPM2_CC_HIERCHANGEAUTH:
+ case TPM2_CC_DAM_RESET:
+ case TPM2_CC_DAM_PARAMETERS:
+ case TPM2_CC_PCR_EXTEND:
+ if (tag != TPM2_ST_SESSIONS) {
+ printf("Session required for command 0x%x\n", command);
+ return TPM2_RC_AUTH_CONTEXT;
+ }
+
+ handle = get_unaligned_be32(*auth);
+ *auth += sizeof(handle);
+
+ /*
+ * PCR_Extend had a different protection mechanism and does not
+ * use the same standards as other commands.
+ */
+ if (command == TPM2_CC_PCR_EXTEND)
+ break;
+
+ switch (handle) {
+ case TPM2_RH_LOCKOUT:
+ *hierarchy = TPM2_HIERARCHY_LOCKOUT;
+ break;
+ case TPM2_RH_ENDORSEMENT:
+ if (command == TPM2_CC_CLEAR) {
+ printf("Endorsement hierarchy unsupported\n");
+ return TPM2_RC_AUTH_MISSING;
+ }
+ *hierarchy = TPM2_HIERARCHY_ENDORSEMENT;
+ break;
+ case TPM2_RH_PLATFORM:
+ *hierarchy = TPM2_HIERARCHY_PLATFORM;
+ break;
+ default:
+ printf("Wrong handle 0x%x\n", handle);
+ return TPM2_RC_VALUE;
+ }
+
+ break;
+
+ default:
+ printf("Command code not recognized: 0x%x\n", command);
+ return TPM2_RC_COMMAND_CODE;
+ }
+
+ auth_sz = get_unaligned_be32(*auth);
+ *auth += sizeof(auth_sz);
+
+ session_handle = get_unaligned_be32(*auth);
+ *auth += sizeof(session_handle);
+ if (session_handle != TPM2_RS_PW) {
+ printf("Wrong session handle 0x%x\n", session_handle);
+ return TPM2_RC_VALUE;
+ }
+
+ nonce_sz = get_unaligned_be16(*auth);
+ *auth += sizeof(nonce_sz);
+ if (nonce_sz) {
+ printf("Nonces not supported in Sandbox, aborting\n");
+ return TPM2_RC_HANDLE;
+ }
+
+ /* Ignore attributes */
+ *auth += sizeof(u8);
+
+ pw_sz = get_unaligned_be16(*auth);
+ *auth += sizeof(pw_sz);
+ if (auth_sz != (9 + nonce_sz + pw_sz)) {
+ printf("Authentication size (%d) do not match %d\n",
+ auth_sz, 9 + nonce_sz + pw_sz);
+ return TPM2_RC_SIZE;
+ }
+
+ /* No passwork is acceptable */
+ if (!pw_sz && !tpm->pw_sz[*hierarchy])
+ return TPM2_RC_SUCCESS;
+
+ /* Password is too long */
+ if (pw_sz > TPM2_DIGEST_LEN) {
+ printf("Password should not be more than %dB\n",
+ TPM2_DIGEST_LEN);
+ return TPM2_RC_AUTHSIZE;
+ }
+
+ pw = (const char *)*auth;
+ *auth += pw_sz;
+
+ /* Password is wrong */
+ if (pw_sz != tpm->pw_sz[*hierarchy] ||
+ strncmp(pw, tpm->pw[*hierarchy], tpm->pw_sz[*hierarchy])) {
+ printf("Authentication failed: wrong password.\n");
+ return TPM2_RC_BAD_AUTH;
+ }
+
+ return TPM2_RC_SUCCESS;
+}
+
+static int sandbox_tpm2_check_readyness(struct udevice *dev, int command)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+
+ switch (command) {
+ case TPM2_CC_STARTUP:
+ if (!tpm->init_done || tpm->startup_done)
+ return TPM2_RC_INITIALIZE;
+
+ break;
+ case TPM2_CC_GET_CAPABILITY:
+ if (!tpm->init_done || !tpm->startup_done)
+ return TPM2_RC_INITIALIZE;
+
+ break;
+ case TPM2_CC_SELF_TEST:
+ if (!tpm->startup_done)
+ return TPM2_RC_INITIALIZE;
+
+ break;
+ default:
+ if (!tpm->tests_done)
+ return TPM2_RC_NEEDS_TEST;
+
+ break;
+ }
+
+ return 0;
+}
+
+static int sandbox_tpm2_fill_buf(u8 **recv, size_t *recv_len, u16 tag, u32 rc)
+{
+ *recv_len = sizeof(tag) + sizeof(u32) + sizeof(rc);
+
+ /* Write tag */
+ put_unaligned_be16(tag, *recv);
+ *recv += sizeof(tag);
+
+ /* Write length */
+ put_unaligned_be32(*recv_len, *recv);
+ *recv += sizeof(u32);
+
+ /* Write return code */
+ put_unaligned_be32(rc, *recv);
+ *recv += sizeof(rc);
+
+ /* Add trailing \0 */
+ *recv = '\0';
+
+ return 0;
+}
+
+static int sandbox_tpm2_extend(struct udevice *dev, int pcr_index,
+ const u8 *extension)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+ int i;
+
+ /* Only simulate the first extensions from all '0' with only '0' */
+ for (i = 0; i < TPM2_DIGEST_LEN; i++)
+ if (tpm->pcr[pcr_index][i] || extension[i])
+ return TPM2_RC_FAILURE;
+
+ memcpy(tpm->pcr[pcr_index], sandbox_extended_once_pcr,
+ TPM2_DIGEST_LEN);
+ tpm->pcr_extensions[pcr_index]++;
+
+ return 0;
+};
+
+static int sandbox_tpm2_xfer(struct udevice *dev, const u8 *sendbuf,
+ size_t send_size, u8 *recvbuf,
+ size_t *recv_len)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+ enum tpm2_hierarchy hierarchy = 0;
+ const u8 *sent = sendbuf;
+ u8 *recv = recvbuf;
+ u32 length, command, rc = 0;
+ u16 tag, mode, new_pw_sz;
+ u8 yes_no;
+ int i, j;
+
+ /* TPM2_GetProperty */
+ u32 capability, property, property_count;
+
+ /* TPM2_PCR_Read/Extend variables */
+ int pcr_index;
+ u64 pcr_map = 0;
+ u32 selections, pcr_nb;
+ u16 alg;
+ u8 pcr_array_sz;
+
+ tag = get_unaligned_be16(sent);
+ sent += sizeof(tag);
+
+ length = get_unaligned_be32(sent);
+ sent += sizeof(length);
+ if (length != send_size) {
+ printf("TPM2: Unmatching length, received: %ld, expected: %d\n",
+ send_size, length);
+ rc = TPM2_RC_SIZE;
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ return 0;
+ }
+
+ command = get_unaligned_be32(sent);
+ sent += sizeof(command);
+ rc = sandbox_tpm2_check_readyness(dev, command);
+ if (rc) {
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ return 0;
+ }
+
+ rc = sandbox_tpm2_check_session(dev, command, tag, &sent, &hierarchy);
+ if (rc) {
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ return 0;
+ }
+
+ switch (command) {
+ case TPM2_CC_STARTUP:
+ mode = get_unaligned_be16(sent);
+ sent += sizeof(mode);
+ switch (mode) {
+ case TPM2_SU_CLEAR:
+ case TPM2_SU_STATE:
+ break;
+ default:
+ rc = TPM2_RC_VALUE;
+ }
+
+ tpm->startup_done = true;
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ case TPM2_CC_SELF_TEST:
+ yes_no = *sent;
+ sent += sizeof(yes_no);
+ switch (yes_no) {
+ case TPMI_YES:
+ case TPMI_NO:
+ break;
+ default:
+ rc = TPM2_RC_VALUE;
+ }
+
+ tpm->tests_done = true;
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ case TPM2_CC_CLEAR:
+ /* Reset this hierarchy password */
+ tpm->pw_sz[hierarchy] = 0;
+
+ /* Reset all password if thisis the PLATFORM hierarchy */
+ if (hierarchy == TPM2_HIERARCHY_PLATFORM)
+ for (i = 0; i < TPM2_HIERARCHY_NB; i++)
+ tpm->pw_sz[i] = 0;
+
+ /* Reset the properties */
+ for (i = 0; i < TPM2_PROPERTY_NB; i++)
+ tpm->properties[i] = 0;
+
+ /* Reset the PCRs and their number of extensions */
+ for (i = 0; i < SANDBOX_TPM_PCR_NB; i++) {
+ tpm->pcr_extensions[i] = 0;
+ for (j = 0; j < TPM2_DIGEST_LEN; j++)
+ tpm->pcr[i][j] = 0;
+ }
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ case TPM2_CC_HIERCHANGEAUTH:
+ new_pw_sz = get_unaligned_be16(sent);
+ sent += sizeof(new_pw_sz);
+ if (new_pw_sz > TPM2_DIGEST_LEN) {
+ rc = TPM2_RC_SIZE;
+ } else if (new_pw_sz) {
+ tpm->pw_sz[hierarchy] = new_pw_sz;
+ memcpy(tpm->pw[hierarchy], sent, new_pw_sz);
+ sent += new_pw_sz;
+ }
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ case TPM2_CC_GET_CAPABILITY:
+ capability = get_unaligned_be32(sent);
+ sent += sizeof(capability);
+ if (capability != TPM_CAP_TPM_PROPERTIES) {
+ printf("Sandbox TPM only support TPM_CAPABILITIES\n");
+ return TPM2_RC_HANDLE;
+ }
+
+ property = get_unaligned_be32(sent);
+ sent += sizeof(property);
+ property -= TPM2_PROPERTIES_OFFSET;
+
+ property_count = get_unaligned_be32(sent);
+ sent += sizeof(property_count);
+ if (!property_count ||
+ property + property_count > TPM2_PROPERTY_NB) {
+ rc = TPM2_RC_HANDLE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ /* Write tag */
+ put_unaligned_be16(tag, recv);
+ recv += sizeof(tag);
+
+ /* Ignore length for now */
+ recv += sizeof(u32);
+
+ /* Write return code */
+ put_unaligned_be32(rc, recv);
+ recv += sizeof(rc);
+
+ /* Tell there is more data to read */
+ *recv = TPMI_YES;
+ recv += sizeof(yes_no);
+
+ /* Repeat the capability */
+ put_unaligned_be32(capability, recv);
+ recv += sizeof(capability);
+
+ /* Give the number of properties that follow */
+ put_unaligned_be32(property_count, recv);
+ recv += sizeof(property_count);
+
+ /* Fill with the properties */
+ for (i = 0; i < property_count; i++) {
+ put_unaligned_be32(TPM2_PROPERTIES_OFFSET + property +
+ i, recv);
+ recv += sizeof(property);
+ put_unaligned_be32(tpm->properties[property + i],
+ recv);
+ recv += sizeof(property);
+ }
+
+ /* Add trailing \0 */
+ *recv = '\0';
+
+ /* Write response length */
+ *recv_len = recv - recvbuf;
+ put_unaligned_be32(*recv_len, recvbuf + sizeof(tag));
+
+ break;
+
+ case TPM2_CC_DAM_PARAMETERS:
+ tpm->properties[TPM2_PROP_MAX_TRIES] = get_unaligned_be32(sent);
+ sent += sizeof(*tpm->properties);
+ tpm->properties[TPM2_RECOVERY_TIME] = get_unaligned_be32(sent);
+ sent += sizeof(*tpm->properties);
+ tpm->properties[TPM2_LOCKOUT_RECOVERY] = get_unaligned_be32(sent);
+ sent += sizeof(*tpm->properties);
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ case TPM2_CC_PCR_READ:
+ selections = get_unaligned_be32(sent);
+ sent += sizeof(selections);
+ if (selections != 1) {
+ printf("Sandbox cannot handle more than one PCR\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ alg = get_unaligned_be16(sent);
+ sent += sizeof(alg);
+ if (alg != TPM2_ALG_SHA256) {
+ printf("Sandbox TPM only handle SHA256 algorithm\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ pcr_array_sz = *sent;
+ sent += sizeof(pcr_array_sz);
+ if (!pcr_array_sz || pcr_array_sz > 8) {
+ printf("Sandbox TPM cannot handle so much PCRs\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ for (i = 0; i < pcr_array_sz; i++)
+ pcr_map += (u64)sent[i] << (i * 8);
+
+ if (pcr_map >> SANDBOX_TPM_PCR_NB) {
+ printf("Sandbox TPM handles up to %d PCR(s)\n",
+ SANDBOX_TPM_PCR_NB);
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ if (pcr_map >> SANDBOX_TPM_PCR_NB) {
+ printf("Wrong PCR map.\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ for (i = 0; i < SANDBOX_TPM_PCR_NB; i++)
+ if (pcr_map & BIT(i))
+ pcr_index = i;
+
+ /* Write tag */
+ put_unaligned_be16(tag, recv);
+ recv += sizeof(tag);
+
+ /* Ignore length for now */
+ recv += sizeof(u32);
+
+ /* Write return code */
+ put_unaligned_be32(rc, recv);
+ recv += sizeof(rc);
+
+ /* Number of extensions */
+ put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv);
+ recv += sizeof(u32);
+
+ /* Copy the PCR */
+ memcpy(recv, tpm->pcr[pcr_index], TPM2_DIGEST_LEN);
+ recv += TPM2_DIGEST_LEN;
+
+ /* Add trailing \0 */
+ *recv = '\0';
+
+ /* Write response length */
+ *recv_len = recv - recvbuf;
+ put_unaligned_be32(*recv_len, recvbuf + sizeof(tag));
+
+ break;
+
+ case TPM2_CC_PCR_EXTEND:
+ /* Get the PCR index */
+ pcr_index = get_unaligned_be32(sendbuf + sizeof(tag) +
+ sizeof(length) +
+ sizeof(command));
+ if (pcr_index > SANDBOX_TPM_PCR_NB) {
+ printf("Sandbox TPM handles up to %d PCR(s)\n",
+ SANDBOX_TPM_PCR_NB);
+ rc = TPM2_RC_VALUE;
+ }
+
+ /* Check the number of hashes */
+ pcr_nb = get_unaligned_be32(sent);
+ sent += sizeof(pcr_nb);
+ if (pcr_nb != 1) {
+ printf("Sandbox cannot handle more than one PCR\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ /* Check the hash algorithm */
+ alg = get_unaligned_be16(sent);
+ sent += sizeof(alg);
+ if (alg != TPM2_ALG_SHA256) {
+ printf("Sandbox TPM only handle SHA256 algorithm\n");
+ rc = TPM2_RC_VALUE;
+ return sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ /* Extend the PCR */
+ rc = sandbox_tpm2_extend(dev, pcr_index, sent);
+
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ break;
+
+ default:
+ printf("TPM2 command %02x unknown in Sandbox\n", command);
+ rc = TPM2_RC_COMMAND_CODE;
+ sandbox_tpm2_fill_buf(&recv, recv_len, tag, rc);
+ }
+
+ return 0;
+}
+
+static int sandbox_tpm2_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < 15)
+ return -ENOSPC;
+
+ return snprintf(buf, size, "Sandbox TPM2.x");
+}
+
+static int sandbox_tpm2_open(struct udevice *dev)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+
+ if (tpm->init_done)
+ return -EIO;
+
+ tpm->init_done = true;
+
+ return 0;
+}
+
+static int sandbox_tpm2_probe(struct udevice *dev)
+{
+ struct sandbox_tpm2 *tpm = dev_get_priv(dev);
+ struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+
+ memset(tpm, 0, sizeof(*tpm));
+
+ priv->pcr_count = 32;
+ priv->pcr_select_min = 2;
+
+ return 0;
+}
+
+static int sandbox_tpm2_close(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct tpm_ops sandbox_tpm2_ops = {
+ .open = sandbox_tpm2_open,
+ .close = sandbox_tpm2_close,
+ .get_desc = sandbox_tpm2_get_desc,
+ .xfer = sandbox_tpm2_xfer,
+};
+
+static const struct udevice_id sandbox_tpm2_ids[] = {
+ { .compatible = "sandbox,tpm2" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_tpm2) = {
+ .name = "sandbox_tpm2",
+ .id = UCLASS_TPM,
+ .of_match = sandbox_tpm2_ids,
+ .ops = &sandbox_tpm2_ops,
+ .probe = sandbox_tpm2_probe,
+ .priv_auto_alloc_size = sizeof(struct sandbox_tpm2),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author:
+ * Miquel Raynal <miquel.raynal@bootlin.com>
+ *
+ * Description:
+ * SPI-level driver for TCG/TIS TPM (trusted platform module).
+ * Specifications at www.trustedcomputinggroup.org
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG SPI protocol stack version 2.0.
+ *
+ * It is based on the U-Boot driver tpm_tis_infineon_i2c.c.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <spi.h>
+#include <tpm-v2.h>
+#include <linux/errno.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <asm-generic/gpio.h>
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
+#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
+#define TPM_STS(l) (0x0018 | ((l) << 12))
+#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
+#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
+#define TPM_RID(l) (0x0F04 | ((l) << 12))
+
+#define MAX_SPI_FRAMESIZE 64
+
+/* Number of wait states to wait for */
+#define TPM_WAIT_STATES 100
+
+/**
+ * struct tpm_tis_chip_data - Non-discoverable TPM information
+ *
+ * @pcr_count: Number of PCR per bank
+ * @pcr_select_min: Size in octets of the pcrSelect array
+ */
+struct tpm_tis_chip_data {
+ unsigned int pcr_count;
+ unsigned int pcr_select_min;
+ unsigned int time_before_first_cmd_ms;
+};
+
+/**
+ * tpm_tis_spi_read() - Read from TPM register
+ *
+ * @addr: register address to read from
+ * @buffer: provided by caller
+ * @len: number of bytes to read
+ *
+ * Read len bytes from TPM register and put them into
+ * buffer (little-endian format, i.e. first byte is put into buffer[0]).
+ *
+ * NOTE: TPM is big-endian for multi-byte values. Multi-byte
+ * values have to be swapped.
+ *
+ * @return -EIO on error, 0 on success.
+ */
+static int tpm_tis_spi_xfer(struct udevice *dev, u32 addr, const u8 *out,
+ u8 *in, u16 len)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ int transfer_len, ret;
+ u8 tx_buf[MAX_SPI_FRAMESIZE];
+ u8 rx_buf[MAX_SPI_FRAMESIZE];
+
+ if (in && out) {
+ log(LOGC_NONE, LOGL_ERR, "%s: can't do full duplex\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ ret = spi_claim_bus(slave);
+ if (ret < 0) {
+ log(LOGC_NONE, LOGL_ERR, "%s: could not claim bus\n", __func__);
+ return ret;
+ }
+
+ while (len) {
+ /* Request */
+ transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE);
+ tx_buf[0] = (in ? BIT(7) : 0) | (transfer_len - 1);
+ tx_buf[1] = 0xD4;
+ tx_buf[2] = addr >> 8;
+ tx_buf[3] = addr;
+
+ ret = spi_xfer(slave, 4 * 8, tx_buf, rx_buf, SPI_XFER_BEGIN);
+ if (ret < 0) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: spi request transfer failed (err: %d)\n",
+ __func__, ret);
+ goto release_bus;
+ }
+
+ /* Wait state */
+ if (!(rx_buf[3] & 0x1)) {
+ int i;
+
+ for (i = 0; i < TPM_WAIT_STATES; i++) {
+ ret = spi_xfer(slave, 1 * 8, NULL, rx_buf, 0);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: wait state failed: %d\n",
+ __func__, ret);
+ goto release_bus;
+ }
+
+ if (rx_buf[0] & 0x1)
+ break;
+ }
+
+ if (i == TPM_WAIT_STATES) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: timeout on wait state\n", __func__);
+ ret = -ETIMEDOUT;
+ goto release_bus;
+ }
+ }
+
+ /* Read/Write */
+ if (out) {
+ memcpy(tx_buf, out, transfer_len);
+ out += transfer_len;
+ }
+
+ ret = spi_xfer(slave, transfer_len * 8,
+ out ? tx_buf : NULL,
+ in ? rx_buf : NULL,
+ SPI_XFER_END);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: spi read transfer failed (err: %d)\n",
+ __func__, ret);
+ goto release_bus;
+ }
+
+ if (in) {
+ memcpy(in, rx_buf, transfer_len);
+ in += transfer_len;
+ }
+
+ len -= transfer_len;
+ }
+
+release_bus:
+ /* If an error occurred, release the chip by deasserting the CS */
+ if (ret < 0)
+ spi_xfer(slave, 0, NULL, NULL, SPI_XFER_END);
+
+ spi_release_bus(slave);
+
+ return ret;
+}
+
+static int tpm_tis_spi_read(struct udevice *dev, u16 addr, u8 *in, u16 len)
+{
+ return tpm_tis_spi_xfer(dev, addr, NULL, in, len);
+}
+
+static int tpm_tis_spi_read32(struct udevice *dev, u32 addr, u32 *result)
+{
+ __le32 result_le;
+ int ret;
+
+ ret = tpm_tis_spi_read(dev, addr, (u8 *)&result_le, sizeof(u32));
+ if (!ret)
+ *result = le32_to_cpu(result_le);
+
+ return ret;
+}
+
+static int tpm_tis_spi_write(struct udevice *dev, u16 addr, const u8 *out,
+ u16 len)
+{
+ return tpm_tis_spi_xfer(dev, addr, out, NULL, len);
+}
+
+static int tpm_tis_spi_check_locality(struct udevice *dev, int loc)
+{
+ const u8 mask = TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID;
+ struct tpm_chip *chip = dev_get_priv(dev);
+ u8 buf;
+ int ret;
+
+ ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1);
+ if (ret)
+ return ret;
+
+ if ((buf & mask) == mask) {
+ chip->locality = loc;
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static void tpm_tis_spi_release_locality(struct udevice *dev, int loc,
+ bool force)
+{
+ const u8 mask = TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID;
+ u8 buf;
+
+ if (tpm_tis_spi_read(dev, TPM_ACCESS(loc), &buf, 1) < 0)
+ return;
+
+ if (force || (buf & mask) == mask) {
+ buf = TPM_ACCESS_ACTIVE_LOCALITY;
+ tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
+ }
+}
+
+static int tpm_tis_spi_request_locality(struct udevice *dev, int loc)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ unsigned long start, stop;
+ u8 buf = TPM_ACCESS_REQUEST_USE;
+ int ret;
+
+ ret = tpm_tis_spi_check_locality(dev, loc);
+ if (!ret)
+ return 0;
+
+ if (ret != -ENOENT) {
+ log(LOGC_NONE, LOGL_ERR, "%s: Failed to get locality: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = tpm_tis_spi_write(dev, TPM_ACCESS(loc), &buf, 1);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR, "%s: Failed to write to TPM: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ start = get_timer(0);
+ stop = chip->timeout_a;
+ do {
+ ret = tpm_tis_spi_check_locality(dev, loc);
+ if (!ret)
+ return 0;
+
+ if (ret != -ENOENT) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: Failed to get locality: %d\n", __func__, ret);
+ return ret;
+ }
+
+ mdelay(TPM_TIMEOUT_MS);
+ } while (get_timer(start) < stop);
+
+ log(LOGC_NONE, LOGL_ERR, "%s: Timeout getting locality: %d\n", __func__,
+ ret);
+
+ return ret;
+}
+
+static u8 tpm_tis_spi_status(struct udevice *dev, u8 *status)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ return tpm_tis_spi_read(dev, TPM_STS(chip->locality), status, 1);
+}
+
+static int tpm_tis_spi_wait_for_stat(struct udevice *dev, u8 mask,
+ unsigned long timeout, u8 *status)
+{
+ unsigned long start = get_timer(0);
+ unsigned long stop = timeout;
+ int ret;
+
+ do {
+ mdelay(TPM_TIMEOUT_MS);
+ ret = tpm_tis_spi_status(dev, status);
+ if (ret)
+ return ret;
+
+ if ((*status & mask) == mask)
+ return 0;
+ } while (get_timer(start) < stop);
+
+ return -ETIMEDOUT;
+}
+
+static int tpm_tis_spi_get_burstcount(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ unsigned long start, stop;
+ u32 burstcount, ret;
+
+ /* wait for burstcount */
+ start = get_timer(0);
+ stop = chip->timeout_d;
+ do {
+ ret = tpm_tis_spi_read32(dev, TPM_STS(chip->locality),
+ &burstcount);
+ if (ret)
+ return -EBUSY;
+
+ burstcount = (burstcount >> 8) & 0xFFFF;
+ if (burstcount)
+ return burstcount;
+
+ mdelay(TPM_TIMEOUT_MS);
+ } while (get_timer(start) < stop);
+
+ return -EBUSY;
+}
+
+static int tpm_tis_spi_cancel(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ u8 data = TPM_STS_COMMAND_READY;
+
+ return tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
+}
+
+static int tpm_tis_spi_recv_data(struct udevice *dev, u8 *buf, size_t count)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int size = 0, burstcnt, len, ret;
+ u8 status;
+
+ while (size < count &&
+ tpm_tis_spi_wait_for_stat(dev,
+ TPM_STS_DATA_AVAIL | TPM_STS_VALID,
+ chip->timeout_c, &status) == 0) {
+ burstcnt = tpm_tis_spi_get_burstcount(dev);
+ if (burstcnt < 0)
+ return burstcnt;
+
+ len = min_t(int, burstcnt, count - size);
+ ret = tpm_tis_spi_read(dev, TPM_DATA_FIFO(chip->locality),
+ buf + size, len);
+ if (ret < 0)
+ return ret;
+
+ size += len;
+ }
+
+ return size;
+}
+
+static int tpm_tis_spi_recv(struct udevice *dev, u8 *buf, size_t count)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int size, expected;
+
+ if (!chip)
+ return -ENODEV;
+
+ if (count < TPM_HEADER_SIZE) {
+ size = -EIO;
+ goto out;
+ }
+
+ size = tpm_tis_spi_recv_data(dev, buf, TPM_HEADER_SIZE);
+ if (size < TPM_HEADER_SIZE) {
+ log(LOGC_NONE, LOGL_ERR, "TPM error, unable to read header\n");
+ goto out;
+ }
+
+ expected = get_unaligned_be32(buf + 2);
+ if (expected > count) {
+ size = -EIO;
+ goto out;
+ }
+
+ size += tpm_tis_spi_recv_data(dev, &buf[TPM_HEADER_SIZE],
+ expected - TPM_HEADER_SIZE);
+ if (size < expected) {
+ log(LOGC_NONE, LOGL_ERR,
+ "TPM error, unable to read remaining bytes of result\n");
+ size = -EIO;
+ goto out;
+ }
+
+out:
+ tpm_tis_spi_cancel(dev);
+ tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+ return size;
+}
+
+static int tpm_tis_spi_send(struct udevice *dev, const u8 *buf, size_t len)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ u32 i, size;
+ u8 status;
+ int burstcnt, ret;
+ u8 data;
+
+ if (!chip)
+ return -ENODEV;
+
+ if (len > TPM_DEV_BUFSIZE)
+ return -E2BIG; /* Command is too long for our tpm, sorry */
+
+ ret = tpm_tis_spi_request_locality(dev, 0);
+ if (ret < 0)
+ return -EBUSY;
+
+ /*
+ * Check if the TPM is ready. If not, if not, cancel the pending command
+ * and poll on the status to be finally ready.
+ */
+ ret = tpm_tis_spi_status(dev, &status);
+ if (ret)
+ return ret;
+
+ if (!(status & TPM_STS_COMMAND_READY)) {
+ /* Force the transition, usually this will be done at startup */
+ ret = tpm_tis_spi_cancel(dev);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: Could not cancel previous operation\n",
+ __func__);
+ goto out_err;
+ }
+
+ ret = tpm_tis_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY,
+ chip->timeout_b, &status);
+ if (ret < 0 || !(status & TPM_STS_COMMAND_READY)) {
+ log(LOGC_NONE, LOGL_ERR,
+ "status %d after wait for stat returned %d\n",
+ status, ret);
+ goto out_err;
+ }
+ }
+
+ for (i = 0; i < len - 1;) {
+ burstcnt = tpm_tis_spi_get_burstcount(dev);
+ if (burstcnt < 0)
+ return burstcnt;
+
+ size = min_t(int, len - i - 1, burstcnt);
+ ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
+ buf + i, size);
+ if (ret < 0)
+ goto out_err;
+
+ i += size;
+ }
+
+ ret = tpm_tis_spi_status(dev, &status);
+ if (ret)
+ goto out_err;
+
+ if ((status & TPM_STS_DATA_EXPECT) == 0) {
+ ret = -EIO;
+ goto out_err;
+ }
+
+ ret = tpm_tis_spi_write(dev, TPM_DATA_FIFO(chip->locality),
+ buf + len - 1, 1);
+ if (ret)
+ goto out_err;
+
+ ret = tpm_tis_spi_status(dev, &status);
+ if (ret)
+ goto out_err;
+
+ if ((status & TPM_STS_DATA_EXPECT) != 0) {
+ ret = -EIO;
+ goto out_err;
+ }
+
+ data = TPM_STS_GO;
+ ret = tpm_tis_spi_write(dev, TPM_STS(chip->locality), &data, 1);
+ if (ret)
+ goto out_err;
+
+ return len;
+
+out_err:
+ tpm_tis_spi_cancel(dev);
+ tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+ return ret;
+}
+
+static int tpm_tis_spi_cleanup(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ tpm_tis_spi_cancel(dev);
+ /*
+ * The TPM needs some time to clean up here,
+ * so we sleep rather than keeping the bus busy
+ */
+ mdelay(2);
+ tpm_tis_spi_release_locality(dev, chip->locality, false);
+
+ return 0;
+}
+
+static int tpm_tis_spi_open(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ if (chip->is_open)
+ return -EBUSY;
+
+ chip->is_open = 1;
+
+ return 0;
+}
+
+static int tpm_tis_spi_close(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ if (chip->is_open) {
+ tpm_tis_spi_release_locality(dev, chip->locality, true);
+ chip->is_open = 0;
+ }
+
+ return 0;
+}
+
+static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ if (size < 80)
+ return -ENOSPC;
+
+ return snprintf(buf, size,
+ "%s v2.0: VendorID 0x%04x, DeviceID 0x%04x, RevisionID 0x%02x [%s]",
+ dev->name, chip->vend_dev & 0xFFFF,
+ chip->vend_dev >> 16, chip->rid,
+ (chip->is_open ? "open" : "closed"));
+}
+
+static int tpm_tis_wait_init(struct udevice *dev, int loc)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+ unsigned long start, stop;
+ u8 status;
+ int ret;
+
+ start = get_timer(0);
+ stop = chip->timeout_b;
+ do {
+ mdelay(TPM_TIMEOUT_MS);
+
+ ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), &status, 1);
+ if (ret)
+ break;
+
+ if (status & TPM_ACCESS_VALID)
+ return 0;
+ } while (get_timer(start) < stop);
+
+ return -EIO;
+}
+
+static int tpm_tis_spi_probe(struct udevice *dev)
+{
+ struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev);
+ struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+ struct tpm_chip *chip = dev_get_priv(dev);
+ int ret;
+
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ struct gpio_desc reset_gpio;
+
+ ret = gpio_request_by_name(dev, "gpio-reset", 0,
+ &reset_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
+ __func__);
+ } else {
+ dm_gpio_set_value(&reset_gpio, 0);
+ mdelay(1);
+ dm_gpio_set_value(&reset_gpio, 1);
+ }
+ }
+
+ /* Ensure a minimum amount of time elapsed since reset of the TPM */
+ mdelay(drv_data->time_before_first_cmd_ms);
+
+ chip->locality = 0;
+ chip->timeout_a = TIS_SHORT_TIMEOUT_MS;
+ chip->timeout_b = TIS_LONG_TIMEOUT_MS;
+ chip->timeout_c = TIS_SHORT_TIMEOUT_MS;
+ chip->timeout_d = TIS_SHORT_TIMEOUT_MS;
+ priv->pcr_count = drv_data->pcr_count;
+ priv->pcr_select_min = drv_data->pcr_select_min;
+
+ ret = tpm_tis_wait_init(dev, chip->locality);
+ if (ret) {
+ log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__);
+ return ret;
+ }
+
+ ret = tpm_tis_spi_request_locality(dev, chip->locality);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR, "%s: could not request locality %d\n",
+ __func__, chip->locality);
+ return ret;
+ }
+
+ ret = tpm_tis_spi_read32(dev, TPM_DID_VID(chip->locality),
+ &chip->vend_dev);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR,
+ "%s: could not retrieve VendorID/DeviceID\n", __func__);
+ return ret;
+ }
+
+ ret = tpm_tis_spi_read(dev, TPM_RID(chip->locality), &chip->rid, 1);
+ if (ret) {
+ log(LOGC_NONE, LOGL_ERR, "%s: could not retrieve RevisionID\n",
+ __func__);
+ return ret;
+ }
+
+ log(LOGC_NONE, LOGL_ERR,
+ "SPI TPMv2.0 found (vid:%04x, did:%04x, rid:%02x)\n",
+ chip->vend_dev & 0xFFFF, chip->vend_dev >> 16, chip->rid);
+
+ return 0;
+}
+
+static int tpm_tis_spi_remove(struct udevice *dev)
+{
+ struct tpm_chip *chip = dev_get_priv(dev);
+
+ tpm_tis_spi_release_locality(dev, chip->locality, true);
+
+ return 0;
+}
+
+static const struct tpm_ops tpm_tis_spi_ops = {
+ .open = tpm_tis_spi_open,
+ .close = tpm_tis_spi_close,
+ .get_desc = tpm_tis_get_desc,
+ .send = tpm_tis_spi_send,
+ .recv = tpm_tis_spi_recv,
+ .cleanup = tpm_tis_spi_cleanup,
+};
+
+static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
+ .pcr_count = 24,
+ .pcr_select_min = 3,
+ .time_before_first_cmd_ms = 30,
+};
+
+static const struct udevice_id tpm_tis_spi_ids[] = {
+ {
+ .compatible = "tis,tpm2-spi",
+ .data = (ulong)&tpm_tis_std_chip_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tpm_tis_spi) = {
+ .name = "tpm_tis_spi",
+ .id = UCLASS_TPM,
+ .of_match = tpm_tis_spi_ids,
+ .ops = &tpm_tis_spi_ops,
+ .probe = tpm_tis_spi_probe,
+ .remove = tpm_tis_spi_remove,
+ .priv_auto_alloc_size = sizeof(struct tpm_chip),
+};
#include <common.h>
#include <dm.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <i2c.h>
#include <asm/unaligned.h>
int is_open;
int locality;
u32 vend_dev;
+ u8 rid;
unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */
ulong chip_type;
};
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <linux/errno.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <common.h>
#include <dm.h>
#include <mapmem.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <asm/io.h>
#define PREFIX "lpc_tpm: "
#include <common.h>
#include <dm.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <asm/state.h>
#include <asm/unaligned.h>
#include <linux/crc8.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <errno.h>
#include <linux/types.h>
#include <asm/unaligned.h>
#include <dm.h>
#include <fdtdec.h>
#include <spi.h>
-#include <tpm.h>
+#include <tpm-v1.h>
#include <errno.h>
#include <linux/types.h>
#include <asm/unaligned.h>
#include <common.h>
#include <linux/libfdt.h>
#include <linux/usb/otg.h>
+#include <linux/usb/ch9.h>
DECLARE_GLOBAL_DATA_PTR;
return USB_DR_MODE_UNKNOWN;
}
+
+static const char *const speed_names[] = {
+ [USB_SPEED_UNKNOWN] = "UNKNOWN",
+ [USB_SPEED_LOW] = "low-speed",
+ [USB_SPEED_FULL] = "full-speed",
+ [USB_SPEED_HIGH] = "high-speed",
+ [USB_SPEED_WIRELESS] = "wireless",
+ [USB_SPEED_SUPER] = "super-speed",
+};
+
+enum usb_device_speed usb_get_maximum_speed(int node)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *max_speed;
+ int i;
+
+ max_speed = fdt_getprop(fdt, node, "maximum-speed", NULL);
+ if (!max_speed) {
+ pr_err("usb maximum-speed not found\n");
+ return USB_SPEED_UNKNOWN;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(speed_names); i++)
+ if (!strcmp(max_speed, speed_names[i]))
+ return i;
+
+ return USB_SPEED_UNKNOWN;
+}
Say 'Y' here if you have one such device
+config USB_DWC3_GENERIC
+ bool "Xilinx ZynqMP and similar Platforms"
+ depends on DM_USB && USB_DWC3
+ help
+ Some platforms can reuse this DWC3 generic implementation.
+
config USB_DWC3_UNIPHIER
bool "DesignWare USB3 Host Support on UniPhier Platforms"
depends on ARCH_UNIPHIER && USB_XHCI_DWC3
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
+obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
#include <dwc3-uboot.h>
#include <asm/dma-mapping.h>
#include <linux/ioport.h>
+#include <dm.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
{
struct dwc3_event_buffer *evt;
- evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
+ evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
+ GFP_KERNEL);
if (!evt)
return ERR_PTR(-ENOMEM);
void *mem;
- mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
+ mem = devm_kzalloc((struct udevice *)dev,
+ sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
if (!mem)
return -ENOMEM;
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
+
+#ifdef CONFIG_DM_USB
+
+int dwc3_init(struct dwc3 *dwc)
+{
+ int ret;
+
+ dwc3_cache_hwparams(dwc);
+
+ ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
+ if (ret) {
+ dev_err(dwc->dev, "failed to allocate event buffers\n");
+ return -ENOMEM;
+ }
+
+ ret = dwc3_core_init(dwc);
+ if (ret) {
+ dev_err(dev, "failed to initialize core\n");
+ goto core_fail;
+ }
+
+ ret = dwc3_event_buffers_setup(dwc);
+ if (ret) {
+ dev_err(dwc->dev, "failed to setup event buffers\n");
+ goto event_fail;
+ }
+
+ ret = dwc3_core_init_mode(dwc);
+ if (ret)
+ goto mode_fail;
+
+ return 0;
+
+mode_fail:
+ dwc3_event_buffers_cleanup(dwc);
+
+event_fail:
+ dwc3_core_exit(dwc);
+
+core_fail:
+ dwc3_free_event_buffers(dwc);
+
+ return ret;
+}
+
+void dwc3_remove(struct dwc3 *dwc)
+{
+ dwc3_core_exit_mode(dwc);
+ dwc3_event_buffers_cleanup(dwc);
+ dwc3_free_event_buffers(dwc);
+ dwc3_core_exit(dwc);
+ kfree(dwc->mem);
+}
+
+#endif
/* device lock */
spinlock_t lock;
+#if defined(__UBOOT__) && defined(CONFIG_DM_USB)
+ struct udevice *dev;
+#else
struct device *dev;
+#endif
struct platform_device *xhci;
struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
/* prototypes */
int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
+int dwc3_init(struct dwc3 *dwc);
+void dwc3_remove(struct dwc3 *dwc);
#ifdef CONFIG_USB_DWC3_HOST
int dwc3_host_init(struct dwc3 *dwc);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Generic DWC3 Glue layer
+ *
+ * Copyright (C) 2016 - 2018 Xilinx, Inc.
+ *
+ * Based on dwc3-omap.c.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/usb/otg.h>
+#include <linux/compat.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <malloc.h>
+#include <usb.h>
+#include "core.h"
+#include "gadget.h"
+#include "linux-compat.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int usb_gadget_handle_interrupts(int index)
+{
+ struct dwc3 *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
+ if (!dev || ret) {
+ pr_err("No USB device found\n");
+ return -ENODEV;
+ }
+
+ priv = dev_get_priv(dev);
+
+ dwc3_gadget_uboot_handle_interrupt(priv);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_probe(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
+
+ return dwc3_init(priv);
+}
+
+static int dwc3_generic_peripheral_remove(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
+
+ dwc3_remove(priv);
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dwc3 *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
+
+ priv->regs = (void *)devfdt_get_addr(dev);
+ priv->regs += DWC3_GLOBALS_REGS_START;
+
+ priv->maximum_speed = usb_get_maximum_speed(node);
+ if (priv->maximum_speed == USB_SPEED_UNKNOWN) {
+ pr_err("Invalid usb maximum speed\n");
+ return -ENODEV;
+ }
+
+ priv->dr_mode = usb_get_dr_mode(node);
+ if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
+ pr_err("Invalid usb mode setup\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int dwc3_generic_peripheral_bind(struct udevice *dev)
+{
+ return device_probe(dev);
+}
+
+U_BOOT_DRIVER(dwc3_generic_peripheral) = {
+ .name = "dwc3-generic-peripheral",
+ .id = UCLASS_USB_DEV_GENERIC,
+ .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata,
+ .probe = dwc3_generic_peripheral_probe,
+ .remove = dwc3_generic_peripheral_remove,
+ .bind = dwc3_generic_peripheral_bind,
+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+ .priv_auto_alloc_size = sizeof(struct dwc3),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static int dwc3_generic_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ int node;
+ int ret;
+
+ for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
+ node = fdt_next_subnode(fdt, node)) {
+ const char *name = fdt_get_name(fdt, node, NULL);
+ enum usb_dr_mode dr_mode;
+ struct udevice *dev;
+ const char *driver;
+
+ debug("%s: subnode name: %s\n", __func__, name);
+ if (strncmp(name, "dwc3@", 4))
+ continue;
+
+ dr_mode = usb_get_dr_mode(node);
+
+ switch (dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ case USB_DR_MODE_OTG:
+ debug("%s: dr_mode: OTG or Peripheral\n", __func__);
+ driver = "dwc3-generic-peripheral";
+ break;
+ case USB_DR_MODE_HOST:
+ debug("%s: dr_mode: HOST\n", __func__);
+ driver = "dwc3-generic-host";
+ break;
+ default:
+ debug("%s: unsupported dr_mode\n", __func__);
+ return -ENODEV;
+ };
+
+ ret = device_bind_driver_to_node(parent, driver, name,
+ offset_to_ofnode(node), &dev);
+ if (ret) {
+ debug("%s: not able to bind usb device mode\n",
+ __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id dwc3_generic_ids[] = {
+ { .compatible = "xlnx,zynqmp-dwc3" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc3_generic_wrapper) = {
+ .name = "dwc3-generic-wrapper",
+ .id = UCLASS_MISC,
+ .of_match = dwc3_generic_ids,
+ .bind = dwc3_generic_bind,
+};
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
+#include <dm.h>
#include <dwc3-omap-uboot.h>
#include <linux/usb/dwc3-omap.h>
#include <linux/ioport.h>
struct device *dev = NULL;
struct dwc3_omap *omap;
- omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
+ omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);
if (!omap)
return -ENOMEM;
if (ret)
goto err4;
- ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
+ ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
if (ret) {
dev_err(dwc->dev, "failed to register udc\n");
goto err4;
return strlen(dest) + strlen(src);
}
-static inline void *devm_kzalloc(struct device *dev, unsigned int size,
- unsigned int flags)
-{
- return kzalloc(size, flags);
-}
#endif
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <dm.h>
#include "linux-compat.h"
/* ********************************************************** */
/* THOR protocol - transmission handling */
/* ********************************************************** */
-DEFINE_CACHE_ALIGN_BUFFER(char, f_name, F_NAME_BUF_SIZE);
+DEFINE_CACHE_ALIGN_BUFFER(char, f_name, F_NAME_BUF_SIZE + 1);
static unsigned long long int thor_file_size;
static int alt_setting_num;
switch (rqt->rqt_data) {
case RQT_DL_INIT:
- thor_file_size = rqt->int_data[0];
- debug("INIT: total %d bytes\n", rqt->int_data[0]);
+ thor_file_size = (unsigned long long int)rqt->int_data[0] +
+ (((unsigned long long int)rqt->int_data[1])
+ << 32);
+ debug("INIT: total %llu bytes\n", thor_file_size);
break;
case RQT_DL_FILE_INFO:
file_type = rqt->int_data[0];
break;
}
- thor_file_size = rqt->int_data[1];
+ thor_file_size = (unsigned long long int)rqt->int_data[1] +
+ (((unsigned long long int)rqt->int_data[2])
+ << 32);
memcpy(f_name, rqt->str_data[0], F_NAME_BUF_SIZE);
+ f_name[F_NAME_BUF_SIZE] = '\0';
debug("INFO: name(%s, %d), size(%llu), type(%d)\n",
f_name, 0, thor_file_size, file_type);
__u8 DAUValue;
} __packed;
-#define VER_PROTOCOL_MAJOR 4
+#define VER_PROTOCOL_MAJOR 5
#define VER_PROTOCOL_MINOR 0
enum rqt {
config USB_XHCI_ZYNQMP
bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
depends on ARCH_ZYNQMP
+ depends on DM_USB
help
Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
*/
#include <common.h>
+#include <dm.h>
#include <usb.h>
#include <linux/errno.h>
#include <asm/arch-zynqmp/hardware.h>
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
struct zynqmp_xhci {
+ struct usb_platdata usb_plat;
+ struct xhci_ctrl ctrl;
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
};
-static struct zynqmp_xhci zynqmp_xhci;
-
-unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST;
+struct zynqmp_xhci_platdata {
+ fdt_addr_t hcd_base;
+};
static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
{
return ret;
}
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+void xhci_hcd_stop(int index)
{
- struct zynqmp_xhci *ctx = &zynqmp_xhci;
- int ret = 0;
- uint32_t hclen;
+ /*
+ * Currently zynqmp socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
- if (index < 0 || index >= ARRAY_SIZE(ctr_addr))
- return -EINVAL;
+ return;
+}
- ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
- ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET);
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
+ struct zynqmp_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int ret;
- ret = board_usb_init(index, USB_INIT_HOST);
- if (ret != 0) {
- puts("Failed to initialize board for USB\n");
- return ret;
- }
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
ret = zynqmp_xhci_core_init(ctx);
- if (ret < 0) {
- puts("Failed to initialize xhci\n");
- return ret;
+ if (ret) {
+ puts("XHCI: failed to initialize controller\n");
+ return -EINVAL;
}
- *hccr = (struct xhci_hccr *)ctx->hcd;
- hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase));
- *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen);
+ hcor = (struct xhci_hcor *)((ulong)ctx->hcd +
+ HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
- debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n",
- *hccr, *hcor, hclen);
+ return xhci_register(dev, ctx->hcd, hcor);
+}
- return ret;
+static int xhci_usb_remove(struct udevice *dev)
+{
+ return xhci_deregister(dev);
}
-void xhci_hcd_stop(int index)
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
- /*
- * Currently zynqmp socs do not support PHY shutdown from
- * sw. But this support may be added in future socs.
- */
+ struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
+ const void *blob = gd->fdt_blob;
+
+ /* Get the base address for XHCI controller from the device node */
+ plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
- return;
+ return 0;
}
+
+U_BOOT_DRIVER(dwc3_generic_host) = {
+ .name = "dwc3-generic-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .probe = xhci_usb_probe,
+ .remove = xhci_usb_remove,
+ .ops = &xhci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct zynqmp_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
int ext4fs_ls(const char *dirname)
{
- struct ext2fs_node *dirnode;
+ struct ext2fs_node *dirnode = NULL;
int status;
if (dirname == NULL)
FILETYPE_DIRECTORY);
if (status != 1) {
printf("** Can not find directory. **\n");
- ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+ if (dirnode)
+ ext4fs_free_node(dirnode, &ext4fs_root->diropen);
return 1;
}
#define BOOTEFI_NAME "bootia32.efi"
#elif defined(CONFIG_X86_RUN_64BIT)
#define BOOTEFI_NAME "bootx64.efi"
+#elif defined(CONFIG_CPU_RISCV_32)
+#define BOOTEFI_NAME "bootriscv32.efi"
+#elif defined(CONFIG_CPU_RISCV_64)
+#define BOOTEFI_NAME "bootriscv64.efi"
#endif
#endif
#if defined(CONFIG_CMD_DHCP)
#if defined(CONFIG_EFI_LOADER)
+/* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */
#if defined(CONFIG_ARM64)
#define BOOTENV_EFI_PXE_ARCH "0xb"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
/* Always assume we're running 64bit */
#define BOOTENV_EFI_PXE_ARCH "0x7"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#elif defined(CONFIG_CPU_RISCV_32)
+#define BOOTENV_EFI_PXE_ARCH "0x19"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000"
+#elif defined(CONFIG_CPU_RISCV_64)
+#define BOOTENV_EFI_PXE_ARCH "0x1b"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000"
#else
#error Please specify an EFI client identifier
#endif
/* MMC Configs */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_BOUNCE_BUFFER
/* USB Configs */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
/*
* SATA Configs
#ifdef CONFIG_NAND_BOOT
/* u-boot env in nand flash */
-#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
#elif defined(CONFIG_SYS_USE_NANDFLASH)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#else /* CONFIG_SYS_USE_NANDFLASH */
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND \
#elif CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read " \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE 0x000f0000
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1 \
+ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
+#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
+#define CONFIG_SYS_NS16550_CLK 19660800
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
+
+/*
+ * memtest works on 512 MB in DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+/* support JEDEC */
+#ifdef CONFIG_CFI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+*/
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+/* environments */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OVERWRITE
+
+/* SPI FLASH */
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+/* When we use RAM as ENV */
+#define CONFIG_ENV_SIZE 0x2000
+
+/* Enable distro boot */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x00080000\0" \
+ "pxefile_addr_r=0x01f00000\0" \
+ "scriptaddr=0x01f00000\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "ramdisk_addr_r=0x02800000\0" \
+ BOOTENV
+
+#endif /* __CONFIG_H */
#include "rcar-gen2-common.h"
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SCIF */
-#define CONFIG_CONS_SCIF0
-
-#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
-
#undef CONFIG_SYS_MEMTEST_SCRATCH
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
#undef CONFIG_CMD_SPI
#endif
-
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
#endif
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* SDHI0 */
-#define CONFIG_SMSTP3_ENA 0x00004000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
-/* QSPI */
-#define CONFIG_SMSTP9_ENA 0x00020000
-/* SYS-DMAC0 */
-#define CONFIG_RMSTP2_ENA 0x00080000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
-
#endif /* __BLANCHE_H */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_BZIP2
/* Size of malloc() pool */
/*
* Commands configuration
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
#define CONFIG_NR_DRAM_BANKS 1
#endif
/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
-#define BX50V3_BOOTARGS_EXTRA
-#if defined(CONFIG_TARGET_GE_B450V3)
-#define CONFIG_BOARD_NAME "General Electric B450v3"
-#elif defined(CONFIG_TARGET_GE_B650V3)
-#define CONFIG_BOARD_NAME "General Electric B650v3"
-#elif defined(CONFIG_TARGET_GE_B850V3)
-#define CONFIG_BOARD_NAME "General Electric B850v3"
-#undef BX50V3_BOOTARGS_EXTRA
-#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \
- "video=HDMI-A-1:1024x768@60 "
-#else
-#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
-#endif
+#define CONFIG_BOARD_NAME "General Electric Bx50v3"
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONSOLE_DEV "ttymxc2"
/* MMC Configs */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_BOUNCE_BUFFER
/* USB Configs */
#ifdef CONFIG_USB
"ro rootwait cma=128M " \
"bootcause=${bootcause} " \
"${quiet} console=${console} ${rtc_status} " \
- BX50V3_BOOTARGS_EXTRA "\0" \
+ "${videoargs}" "\0" \
"doquiet=" \
"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
"then setenv quiet; fi\0" \
* Commands configuration
*/
-#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* Standard filesystems
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_BZIP2
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-plug-common.h should be defined after CMD configs since it used them
/* eMMC Configs */
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_SUPPORT_EMMC_RPMB
/*
* SATA Configs
/*
* Commands configuration
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* Commands configuration
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * Configuration settings for the BTicion i.MX6DL Mamoj board.
+ */
+
+#ifndef __IMX6DL_MAMOJ_CONFIG_H
+#define __IMX6DL_MAMOJ_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+# define CONFIG_ENV_OFFSET 0x100000
+# endif
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x14000000\0" \
+ "fdt_addr_r=0x13000000\0" \
+ "kernel_addr_r=0x10008000\0" \
+ "fdt_high=0xffffffff\0" \
+ "dfu_alt_info_spl=spl raw 0x2 0x400\0" \
+ "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART3_BASE
+
+/* MMC */
+#define CONFIG_SYS_MMC_ENV_DEV 2
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* Ethernet */
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_MII
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* Falcon */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
+#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
+
+/* MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPL */
+#include "imx6_spl.h"
+
+#endif /* __IMX6DL_MAMOJ_CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __CONFIG_H_
+#define __CONFIG_H_
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/* Eth Configs */
+#define CONFIG_MII
+
+/* USB Configs */
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc1,115200\0" \
+ "fdt_addr=0x75000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "scriptaddr=0x74000000\0" \
+ "kernel_file=fitImage\0"\
+ "rdinit=/sbin/init\0" \
+ "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
+ "upd_image=st.4k\0" \
+ "uboot_file=u-boot.imx\0" \
+ "updargs=setenv bootargs console=${console} ${smp}"\
+ "rdinit=${rdinit} ${debug} ${displayargs}\0" \
+ "loadusb=usb start; " \
+ "fatload usb 0 ${loadaddr} ${upd_image}\0" \
+ "up=if tftp ${loadaddr} ${uboot_file}; then " \
+ "setexpr blkc ${filesize} / 0x200; " \
+ "setexpr blkc ${blkc} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${blkc}" \
+ "; fi\0" \
+ "upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
+ "if tftp ${loadaddr} ${wic_file}; then " \
+ "setexpr blkc ${filesize} / 0x200; " \
+ "setexpr blkc ${blkc} + 1; " \
+ "mmc write ${loadaddr} 0x0 ${blkc}" \
+ "; fi\0" \
+ "usbupd=echo Booting update from usb ...; " \
+ "setenv bootargs; " \
+ "run updargs; " \
+ "run loadusb; " \
+ "bootm ${loadaddr}#${fit_config}\0" \
+ BOOTENV
+
+#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * SZ_1M)
+#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET (SZ_1M)
+#define CONFIG_ENV_SIZE (SZ_8K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif /* __CONFIG_H_ */
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_BOUNCE_BUFFER
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/*
- * CLKs configurations
- */
-
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
-/*
- * Common SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#endif
-
-/*
- * File system
- */
-#ifdef CONFIG_SYS_MVFS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#endif
-
#endif /* _MV_COMMON_H */
/* Add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET "u-boot.kwb"
-/*
- * Compression configuration
- */
-#ifdef CONFIG_SYS_MVFS
-#define CONFIG_BZIP2
-#endif /* CONFIG_SYS_MVFS */
-
-/*
- * Commands configuration
- */
-
-/*
- * Extra file system
- */
-
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_MX31 /* This is a mx31 */
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* FLASH and environment organization */
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
#define CONFIG_ENV_SIZE (10 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_CMD_FUSE
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif
-#define CONFIG_MP
#endif
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MXC_GPT_HCLK
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-/* Filesystems and image support */
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_PREBOOT ""
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
+#ifdef CONFIG_CMD_MMC
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
-#define CONFIG_DRIVE_SATA
+#define DISTRO_BOOT_DEV_MMC(func)
#endif
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
+#ifdef CONFIG_CMD_SATA
+#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
#else
-#define CONFIG_DRIVE_MMC
+#define DISTRO_BOOT_DEV_SATA(func)
#endif
#ifdef CONFIG_USB_STORAGE
-#define CONFIG_DRIVE_USB "usb "
+#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
#else
-#define CONFIG_DRIVE_USB
+#define DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_PXE
+#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
+#else
+#define DISTRO_BOOT_DEV_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define DISTRO_BOOT_DEV_DHCP(func)
#endif
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB
-#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
#if defined(CONFIG_SABRELITE)
+#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
+#else
+/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
+#define FDTFILE
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ DISTRO_BOOT_DEV_MMC(func) \
+ DISTRO_BOOT_DEV_SATA(func) \
+ DISTRO_BOOT_DEV_USB(func) \
+ DISTRO_BOOT_DEV_PXE(func) \
+ DISTRO_BOOT_DEV_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=uImage\0" \
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "fdt_file=imx6q-sabrelite.dtb\0" \
- "fdt_addr=0x18000000\0" \
- "boot_fdt=try\0" \
+ "fdt_addr_r=0x18000000\0" \
+ FDTFILE \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_addr_r=0x13000000\0" \
+ "ramdiskaddr=0x13000000\0" \
"ip_dyn=yes\0" \
"usb_pgood_delay=2000\0" \
- "mmcdevs=0 1\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootm; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootm; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${uimage}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootm ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootm; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootm; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "for mmcdev in ${mmcdevs}; do " \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "done; " \
- "run netboot; "
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootdevs=" CONFIG_DRIVE_TYPES "\0" \
- "umsdevs=" CONFIG_UMSDEVS "\0" \
- "usb_pgood_delay=2000\0" \
- "console=ttymxc1\0" \
- "clearenv=if sf probe || sf probe || sf probe 1 ; then " \
- "sf erase 0xc0000 0x2000 && " \
- "echo restored environment to factory default ; fi\0" \
- "bootcmd=for dtype in ${bootdevs}" \
- "; do " \
- "if itest.s \"xusb\" == \"x${dtype}\" ; then " \
- "usb start ;" \
- "fi; " \
- "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
- "load " \
- "${dtype} ${disk}:1 " \
- "10008000 " \
- "/6x_bootscript" \
- "&& source 10008000 ; " \
- "done ; " \
- "done; " \
- "setenv stdout serial,vga ; " \
- "echo ; echo 6x_bootscript not found ; " \
- "echo ; echo serial console at 115200, 8N1 ; echo ; " \
- "echo details at http://boundarydevices.com/6q_bootscript ; " \
- "setenv stdout serial;" \
- "setenv stdin serial,usbkbd;" \
- "for dtype in ${umsdevs} ; do " \
- "if itest.s sata == ${dtype}; then " \
- "initcmd='sata init' ;" \
- "else " \
- "initcmd='mmc rescan' ;" \
- "fi; " \
- "for disk in 0 1 ; do " \
- "if $initcmd && $dtype dev $disk ; then " \
- "setenv stdout serial,vga; " \
- "echo expose ${dtype} ${disk} " \
- "over USB; " \
- "ums 0 $dtype $disk ;" \
- "fi; " \
- " done; " \
- "done ;" \
- "setenv stdout serial,vga; " \
- "echo no block devices found;" \
- "\0" \
- "initrd_high=0xffffffff\0" \
- "upgradeu=for dtype in ${bootdevs}" \
- "; do " \
- "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
- "load ${dtype} ${disk}:1 10008000 " \
- "/6x_upgrade " \
- "&& source 10008000 ; " \
- "done ; " \
- "done\0" \
+ BOOTENV
-#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_BZIP2
/* commands configuration */
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_SYS_BOOTM_LEN SZ_32M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
-/*
- * UART configuration
- *
- */
-#define CONFIG_ARC_SERIAL
-
-/*
- * Command line configuration
- */
-
/*
* Environment settings
*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * CPU and Board Configuration Options
- */
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SERVERIP
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/*
- * Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/*
- * max number of command args
- */
-#define CONFIG_SYS_MAXARGS 16
-
-/*
- * Boot Argument Buffer Size
- */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * Size of malloc() pool
- * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
- */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-
-/* DT blob (fdt) address */
-#define CONFIG_SYS_FDT_BASE 0x000f0000
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1 \
- (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
-#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
-
-/*
- * Serial console configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#endif
-#define CONFIG_SYS_NS16550_CLK 19660800
-
-/* Init Stack Pointer */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Load address and memory test area should agree with
- * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
-
-/*
- * memtest works on 512 MB in DRAM
- */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
-
-/* environments */
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_OVERWRITE
-
-/* SPI FLASH */
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#define CONFIG_SF_DEFAULT_MODE 0
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-
-/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
-/* Increase max gunzip size */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#endif /* __CONFIG_H */
/*
* Commands configuration
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* Commands configuration
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-common.h should be defined after CMD configs since it used them
*
* I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
*
- * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
- * binary firmware loads a DT to address 0x100, so we choose this address to
- * match it. This allows custom boot scripts to pass this DT on to Linux
- * simply by not over-writing the data at this address. When using U-Boot,
- * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
- * and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
+ * Older versions of the boot firmware place the firmware-loaded DTB at 0x100,
+ * newer versions place it in high memory. So prevent U-Boot from doing its own
+ * DTB + initrd relocation so that we won't accidentally relocate the initrd
+ * over the firmware-loaded DTB and generally try to lay out things starting
+ * from the bottom of RAM.
*
- * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
- * something else. Put it low in memory to avoid conflicts.
+ * kernel_addr_r has different constraints on ARM and Aarch64. For 32-bit ARM,
+ * it must be within the first 128M of RAM in order for the kernel's
+ * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed
+ * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The
+ * decompressor also likes to relocate itself to right past the end of the
+ * decompressed kernel, so in total the sum of the compressed and and
+ * decompressed kernel needs to be reserved.
*
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
+ * For Aarch64, the kernel image is uncompressed and must be loaded at
+ * text_offset bytes (specified in the header of the Image) into a 2MB
+ * boundary. The 'booti' command relocates the image if necessary. Linux uses
+ * a default text_offset of 0x80000. In summary, loading at 0x80000
+ * satisfies all these constraints and reserving memory up to 0x02400000
+ * permits fairly large (roughly 36M) kernels.
*
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Choosing 32M allows for the compressed kernel to be up to 16M.
+ * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't
+ * conflict with something else. Reserving 1M for each of them at
+ * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty.
*
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for any boot script to be up to 1M, which is hopefully plenty.
+ * On ARM, both the DTB and any possible initrd must be loaded such that they
+ * fit inside the lowmem mapping in Linux. In practice, this usually means not
+ * more than ~700M away from the start of the kernel image but this number can
+ * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line
+ * parameter given to the kernel. So reserving memory from low to high
+ * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for
+ * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000.
+ * Even with the smallest possible CPU-GPU memory split of the CPU getting
+ * only 64M, the remaining 25M starting at 0x02700000 should allow quite
+ * large initrds before they start colliding with U-Boot.
*/
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_high=ffffffff\0" \
"initrd_high=ffffffff\0" \
- "fdt_addr_r=0x00000100\0" \
- "pxefile_addr_r=0x00100000\0" \
- "kernel_addr_r=0x01000000\0" \
- "scriptaddr=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0" \
+ "kernel_addr_r=0x00080000\0" \
+ "scriptaddr=0x02400000\0" \
+ "pxefile_addr_r=0x02500000\0" \
+ "fdt_addr_r=0x02600000\0" \
+ "ramdisk_addr_r=0x02700000\0"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
"fatload mmc 1:1 0x22000000 zImage; " \
"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SPI_BOOT
+
+/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \
+ "ext4load mmc 0:1 0x22000000 /boot/zImage; " \
+ "bootz 0x22000000 - 0x21000000"
+
#endif
/* SPL */
/*
* Standard filesystems
*/
-#define CONFIG_SYS_MVFS
+#define CONFIG_BZIP2
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
/*
* mv-plug-common.h should be defined after CMD configs since it used them
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
-/* Virtual target or real hardware */
-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-
/*
* High level configuration
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
#endif
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* Ethernet on SoC (EMAC)
*/
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#ifdef CONFIG_CMD_NET
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#endif
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_TIMER_RATE 2400000
-#else
#define CONFIG_SYS_TIMER_RATE 25000000
-#endif
/*
* L4 Watchdog
* Serial Driver
*/
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_SYS_NS16550_CLK 1000000
-#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 100000000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 50000000
-#endif
/*
* USB
/*
* SPL
*
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ...... Malloc area
* 0xFFFF_zzzz ...... Global Data
* 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
*/
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
+ CONFIG_SYS_SPL_MALLOC_SIZE + \
+ CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
+
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
/*
* Stack setup
*/
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
+#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
-#define CONFIG_SYS_RAM_BASE 0xD0000000
+#define CONFIG_SYS_RAM_BASE 0x90000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
-#define CONFIG_SYS_LOAD_ADDR 0xD0400000
-#define CONFIG_LOADADDR 0xD0400000
+#define CONFIG_SYS_LOAD_ADDR 0x90400000
+#define CONFIG_LOADADDR 0x90400000
#define CONFIG_SYS_MAX_FLASH_SECT 12
#define CONFIG_SYS_MAX_FLASH_BANKS 2
"run boot_common\0" \
"tftpboot=tftpboot $kernel_addr_load $bootfile && " \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
- "tftpboot $fdt_addr_r $fdt_file &&" \
+ "tftpboot $fdt_addr_r $fdtfile &&" \
"run boot_common\0" \
"__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
- "tftpboot $fdt_addr_r $fdt_file &&" \
+ "tftpboot $fdt_addr_r $fdtfile &&" \
"setenv ramdisk_addr_r - &&" \
"run boot_common\0"
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_SUPPORT_EMMC_RPMB
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
#define CONFIG_ZYNQ_SDHCI1
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */
{0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
}
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_PCA953X
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_PCA953X
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#include <configs/xilinx_zynqmp.h>
#define CONFIG_PCA953X
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_PCA953X
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
--- /dev/null
+/*
+ * This header provides constants for netxbig LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_NETXBIG_H
+#define _DT_BINDINGS_LEDS_NETXBIG_H
+
+#define NETXBIG_LED_OFF 0
+#define NETXBIG_LED_ON 1
+#define NETXBIG_LED_SATA 2
+#define NETXBIG_LED_TIMER1 3
+#define NETXBIG_LED_TIMER2 4
+
+#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_LEDS_NS2_H
+#define _DT_BINDINGS_LEDS_NS2_H
+
+#define NS_V2_LED_OFF 0
+#define NS_V2_LED_ON 1
+#define NS_V2_LED_SATA 2
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Qualcomm Snapdragon pinctrl bindings.
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+
+/* GPIO Drive Strength */
+#define DRIVE_STRENGTH_2MA 0
+#define DRIVE_STRENGTH_4MA 1
+#define DRIVE_STRENGTH_6MA 2
+#define DRIVE_STRENGTH_8MA 3
+#define DRIVE_STRENGTH_10MA 4
+#define DRIVE_STRENGTH_12MA 5
+#define DRIVE_STRENGTH_14MA 6
+#define DRIVE_STRENGTH_16MA 7
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/system/libufdt
+ * File: utils/src/dt_table.h
+ * Commit: 2626d8b9e4d8e8c6cc67ceb1dc4e05a47779785c
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+
+#ifndef DT_TABLE_H
+#define DT_TABLE_H
+
+#include <linux/types.h>
+
+#define DT_TABLE_MAGIC 0xd7b7ab1e
+#define DT_TABLE_DEFAULT_PAGE_SIZE 2048
+#define DT_TABLE_DEFAULT_VERSION 0
+
+struct dt_table_header {
+ u32 magic; /* DT_TABLE_MAGIC */
+ u32 total_size; /* includes dt_table_header + all dt_table_entry
+ * and all dtb/dtbo
+ */
+ u32 header_size; /* sizeof(dt_table_header) */
+
+ u32 dt_entry_size; /* sizeof(dt_table_entry) */
+ u32 dt_entry_count; /* number of dt_table_entry */
+ u32 dt_entries_offset; /* offset to the first dt_table_entry
+ * from head of dt_table_header.
+ * The value will be equal to header_size if
+ * no padding is appended
+ */
+ u32 page_size; /* flash page size we assume */
+ u32 version; /* DTBO image version, the current version is 0.
+ * The version will be incremented when the
+ * dt_table_header struct is updated.
+ */
+};
+
+struct dt_table_entry {
+ u32 dt_size;
+ u32 dt_offset; /* offset from head of dt_table_header */
+
+ u32 id; /* optional, must be zero if unused */
+ u32 rev; /* optional, must be zero if unused */
+ u32 custom[4]; /* optional, must be zero if unused */
+};
+
+#endif
##__VA_ARGS__); \
})
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+#else
+/* Just use the greatest cache flush alignment requirement I'm aware of */
+#define EFI_CACHELINE_SIZE 128
+#endif
+
extern struct efi_runtime_services efi_runtime_services;
extern struct efi_system_table systab;
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */
COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */
+ COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */
COMPAT_COUNT,
};
/* MC34708 Definitions */
#define SWx_VOLT_MASK_MC34708 0x3F
+#define SWx_1_110V_MC34708 0x24
#define SWx_1_250V_MC34708 0x30
#define SWx_1_300V_MC34708 0x34
#define TIMER_MASK_MC34708 0x300
#define SWBST_CTRL 31
#define SWBST_AUTO 0x8
+#define MC34708_REG_SW12_OPMODE 28
+
+#define MC34708_SW1AMODE_MASK 0x00000f
+#define MC34708_SW1AMHMODE 0x000010
+#define MC34708_SW1AUOMODE 0x000020
+#define MC34708_SW1DVSSPEED 0x0000c0
+#define MC34708_SW2MODE_MASK 0x03c000
+#define MC34708_SW2MHMODE 0x040000
+#define MC34708_SW2UOMODE 0x080000
+#define MC34708_SW2DVSSPEED 0x300000
+#define MC34708_PLLEN 0x400000
+#define MC34708_PLLX 0x800000
+
+#define MC34708_REG_SW345_OPMODE 29
+
+#define MC34708_SW3MODE_MASK 0x00000f
+#define MC34708_SW3MHMODE 0x000010
+#define MC34708_SW3UOMODE 0x000020
+#define MC34708_SW4AMODE_MASK 0x0003c0
+#define MC34708_SW4AMHMODE 0x000400
+#define MC34708_SW4AUOMODE 0x000800
+#define MC34708_SW4BMODE_MASK 0x00f000
+#define MC34708_SW4BMHMODE 0x010000
+#define MC34708_SW4BUOMODE 0x020000
+#define MC34708_SW5MODE_MASK 0x3c0000
+#define MC34708_SW5MHMODE 0x400000
+#define MC34708_SW5UOMODE 0x800000
+
+#define SW_MODE_OFFOFF 0x00
+#define SW_MODE_PWMOFF 0x01
+#define SW_MODE_PFMOFF 0x03
+#define SW_MODE_APSOFF 0x04
+#define SW_MODE_PWMPWM 0x05
+#define SW_MODE_PWMAPS 0x06
+#define SW_MODE_APSAPS 0x08
+#define SW_MODE_APSPFM 0x0c
+#define SW_MODE_PWMPFM 0x0d
+#define SW_MODE_PFMPFM 0x0f
+
+#define MC34708_TRANSFER_SIZE 3
#endif
#define FIT_SETUP_PROP "setup"
#define FIT_FPGA_PROP "fpga"
#define FIT_FIRMWARE_PROP "firmware"
+#define FIT_STANDALONE_PROP "standalone"
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
int fit_image_get_data_position(const void *fit, int noffset,
int *data_position);
int fit_image_get_data_size(const void *fit, int noffset, int *data_size);
+int fit_image_get_data_and_size(const void *fit, int noffset,
+ const void **data, size_t *size);
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
int fit_conf_get_prop_node(const void *fit, int noffset,
const char *prop_name);
-void fit_conf_print(const void *fit, int noffset, const char *p);
-
int fit_check_ramdisk(const void *fit, int os_noffset,
uint8_t arch, int verify);
*/
enum usb_dr_mode usb_get_dr_mode(int node);
+/**
+ * usb_get_maximum_speed() - Get maximum speed for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'maximum-speed',
+ * and returns the correspondig enum usb_device_speed
+ */
+enum usb_device_speed usb_get_maximum_speed(int node);
+
#endif /* __LINUX_USB_OTG_H */
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
-int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int armada100_fec_register(unsigned long base_addr);
void pciauto_region_init(struct pci_region *res);
void pciauto_region_align(struct pci_region *res, pci_size_t size);
void pciauto_config_init(struct pci_controller *hose);
+
+/**
+ * pciauto_region_allocate() - Allocate resources from a PCI resource region
+ *
+ * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
+ * false, the result will be guaranteed to fit in 32 bits.
+ *
+ * @res: PCI region to allocate from
+ * @size: Amount of bytes to allocate
+ * @bar: Returns the PCI bus address of the allocated resource
+ * @supports_64bit: Whether to allow allocations above the 32-bit boundary
+ * @return 0 if successful, -1 on failure
+ */
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
- pci_addr_t *bar);
+ pci_addr_t *bar, bool supports_64bit);
#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
*/
int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
+/*
+ * This structure holds the private data for PMIC uclass
+ * For now we store information about the number of bytes
+ * being sent at once to the device.
+ */
+struct uc_pmic_priv {
+ uint trans_len;
+};
+
#endif /* CONFIG_DM_PMIC */
#ifdef CONFIG_POWER
struct udevice;
+enum serial_par {
+ SERIAL_PAR_NONE,
+ SERIAL_PAR_ODD,
+ SERIAL_PAR_EVEN
+};
+
/**
* struct struct dm_serial_ops - Driver model serial operations
*
*/
int (*loop)(struct udevice *dev, int on);
#endif
+ /**
+ * setparity() - Set up the parity
+ *
+ * Set up a new parity for this device.
+ *
+ * @dev: Device pointer
+ * @parity: parity to use
+ * @return 0 if OK, -ve on error
+ */
+ int (*setparity)(struct udevice *dev, enum serial_par parity);
};
/**
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_COMMON_H
+#define __TPM_COMMON_H
+
+enum tpm_duration {
+ TPM_SHORT = 0,
+ TPM_MEDIUM = 1,
+ TPM_LONG = 2,
+ TPM_UNDEFINED,
+
+ TPM_DURATION_COUNT,
+};
+
+/*
+ * Here is a partial implementation of TPM commands. Please consult TCG Main
+ * Specification for definitions of TPM commands.
+ */
+
+#define TPM_HEADER_SIZE 10
+
+/* Max buffer size supported by our tpm */
+#define TPM_DEV_BUFSIZE 1260
+
+/**
+ * struct tpm_chip_priv - Information about a TPM, stored by the uclass
+ *
+ * These values must be set up by the device's probe() method before
+ * communcation is attempted. If the device has an xfer() method, this is
+ * not needed. There is no need to set up @buf.
+ *
+ * @duration_ms: Length of each duration type in milliseconds
+ * @retry_time_ms: Time to wait before retrying receive
+ * @pcr_count: Number of PCR per bank
+ * @pcr_select_min: Minimum size in bytes of the pcrSelect array
+ * @buf: Buffer used during the exchanges with the chip
+ */
+struct tpm_chip_priv {
+ uint duration_ms[TPM_DURATION_COUNT];
+ uint retry_time_ms;
+#if defined(CONFIG_TPM_V2)
+ uint pcr_count;
+ uint pcr_select_min;
+#endif
+ u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
+};
+
+/**
+ * struct tpm_ops - low-level TPM operations
+ *
+ * These are designed to avoid loops and delays in the driver itself. These
+ * should be handled in the uclass.
+ *
+ * In gneral you should implement everything except xfer(). Where you need
+ * complete control of the transfer, then xfer() can be provided and will
+ * override the other methods.
+ *
+ * This interface is for low-level TPM access. It does not understand the
+ * concept of localities or the various TPM messages. That interface is
+ * defined in the functions later on in this file, but they all translate
+ * to bytes which are sent and received.
+ */
+struct tpm_ops {
+ /**
+ * open() - Request access to locality 0 for the caller
+ *
+ * After all commands have been completed the caller should call
+ * close().
+ *
+ * @dev: Device to close
+ * @return 0 ok OK, -ve on error
+ */
+ int (*open)(struct udevice *dev);
+
+ /**
+ * close() - Close the current session
+ *
+ * Releasing the locked locality. Returns 0 on success, -ve 1 on
+ * failure (in case lock removal did not succeed).
+ *
+ * @dev: Device to close
+ * @return 0 ok OK, -ve on error
+ */
+ int (*close)(struct udevice *dev);
+
+ /**
+ * get_desc() - Get a text description of the TPM
+ *
+ * @dev: Device to check
+ * @buf: Buffer to put the string
+ * @size: Maximum size of buffer
+ * @return length of string, or -ENOSPC it no space
+ */
+ int (*get_desc)(struct udevice *dev, char *buf, int size);
+
+ /**
+ * send() - send data to the TPM
+ *
+ * @dev: Device to talk to
+ * @sendbuf: Buffer of the data to send
+ * @send_size: Size of the data to send
+ *
+ * Returns 0 on success or -ve on failure.
+ */
+ int (*send)(struct udevice *dev, const u8 *sendbuf, size_t send_size);
+
+ /**
+ * recv() - receive a response from the TPM
+ *
+ * @dev: Device to talk to
+ * @recvbuf: Buffer to save the response to
+ * @max_size: Maximum number of bytes to receive
+ *
+ * Returns number of bytes received on success, -EAGAIN if the TPM
+ * response is not ready, -EINTR if cancelled, or other -ve value on
+ * failure.
+ */
+ int (*recv)(struct udevice *dev, u8 *recvbuf, size_t max_size);
+
+ /**
+ * cleanup() - clean up after an operation in progress
+ *
+ * This is called if receiving times out. The TPM may need to abort
+ * the current transaction if it did not complete, and make itself
+ * ready for another.
+ *
+ * @dev: Device to talk to
+ */
+ int (*cleanup)(struct udevice *dev);
+
+ /**
+ * xfer() - send data to the TPM and get response
+ *
+ * This method is optional. If it exists it is used in preference
+ * to send(), recv() and cleanup(). It should handle all aspects of
+ * TPM communication for a single transfer.
+ *
+ * @dev: Device to talk to
+ * @sendbuf: Buffer of the data to send
+ * @send_size: Size of the data to send
+ * @recvbuf: Buffer to save the response to
+ * @recv_size: Pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at
+ * recv_size) or -ve on failure.
+ */
+ int (*xfer)(struct udevice *dev, const u8 *sendbuf, size_t send_size,
+ u8 *recvbuf, size_t *recv_size);
+};
+
+#define tpm_get_ops(dev) ((struct tpm_ops *)device_get_ops(dev))
+
+#define MAKE_TPM_CMD_ENTRY(cmd) \
+ U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
+
+#define TPM_COMMAND_NO_ARG(cmd) \
+int do_##cmd(cmd_tbl_t *cmdtp, int flag, \
+ int argc, char * const argv[]) \
+{ \
+ if (argc != 1) \
+ return CMD_RET_USAGE; \
+ return report_return_code(cmd()); \
+}
+
+/**
+ * tpm_get_desc() - Get a text description of the TPM
+ *
+ * @dev: Device to check
+ * @buf: Buffer to put the string
+ * @size: Maximum size of buffer
+ * @return length of string, or -ENOSPC it no space
+ */
+int tpm_get_desc(struct udevice *dev, char *buf, int size);
+
+/**
+ * tpm_xfer() - send data to the TPM and get response
+ *
+ * This first uses the device's send() method to send the bytes. Then it calls
+ * recv() to get the reply. If recv() returns -EAGAIN then it will delay a
+ * short time and then call recv() again.
+ *
+ * Regardless of whether recv() completes successfully, it will then call
+ * cleanup() to finish the transaction.
+ *
+ * Note that the outgoing data is inspected to determine command type
+ * (ordinal) and a timeout is used for that command type.
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at
+ * recv_len) or -ve on failure.
+ */
+int tpm_xfer(struct udevice *dev, const u8 *sendbuf, size_t send_size,
+ u8 *recvbuf, size_t *recv_size);
+
+/**
+ * Initialize TPM device. It must be called before any TPM commands.
+ *
+ * @return 0 on success, non-0 on error.
+ */
+int tpm_init(void);
+
+/**
+ * Retrieve the array containing all the commands.
+ *
+ * @return a cmd_tbl_t array.
+ */
+cmd_tbl_t *get_tpm_commands(unsigned int *size);
+
+#endif /* __TPM_COMMON_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_V1_H
+#define __TPM_V1_H
+
+#include <tpm-common.h>
+
+/* Useful constants */
+enum {
+ TPM_REQUEST_HEADER_LENGTH = 10,
+ TPM_RESPONSE_HEADER_LENGTH = 10,
+ PCR_DIGEST_LENGTH = 20,
+ DIGEST_LENGTH = 20,
+ TPM_REQUEST_AUTH_LENGTH = 45,
+ TPM_RESPONSE_AUTH_LENGTH = 41,
+ /* some max lengths, valid for RSA keys <= 2048 bits */
+ TPM_KEY12_MAX_LENGTH = 618,
+ TPM_PUBKEY_MAX_LENGTH = 288,
+};
+
+enum tpm_startup_type {
+ TPM_ST_CLEAR = 0x0001,
+ TPM_ST_STATE = 0x0002,
+ TPM_ST_DEACTIVATED = 0x0003,
+};
+
+enum tpm_physical_presence {
+ TPM_PHYSICAL_PRESENCE_HW_DISABLE = 0x0200,
+ TPM_PHYSICAL_PRESENCE_CMD_DISABLE = 0x0100,
+ TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK = 0x0080,
+ TPM_PHYSICAL_PRESENCE_HW_ENABLE = 0x0040,
+ TPM_PHYSICAL_PRESENCE_CMD_ENABLE = 0x0020,
+ TPM_PHYSICAL_PRESENCE_NOTPRESENT = 0x0010,
+ TPM_PHYSICAL_PRESENCE_PRESENT = 0x0008,
+ TPM_PHYSICAL_PRESENCE_LOCK = 0x0004,
+};
+
+enum tpm_nv_index {
+ TPM_NV_INDEX_LOCK = 0xffffffff,
+ TPM_NV_INDEX_0 = 0x00000000,
+ TPM_NV_INDEX_DIR = 0x10000001,
+};
+
+enum tpm_resource_type {
+ TPM_RT_KEY = 0x00000001,
+ TPM_RT_AUTH = 0x00000002,
+ TPM_RT_HASH = 0x00000003,
+ TPM_RT_TRANS = 0x00000004,
+ TPM_RT_CONTEXT = 0x00000005,
+ TPM_RT_COUNTER = 0x00000006,
+ TPM_RT_DELEGATE = 0x00000007,
+ TPM_RT_DAA_TPM = 0x00000008,
+ TPM_RT_DAA_V0 = 0x00000009,
+ TPM_RT_DAA_V1 = 0x0000000A,
+};
+
+enum tpm_capability_areas {
+ TPM_CAP_ORD = 0x00000001,
+ TPM_CAP_ALG = 0x00000002,
+ TPM_CAP_PID = 0x00000003,
+ TPM_CAP_FLAG = 0x00000004,
+ TPM_CAP_PROPERTY = 0x00000005,
+ TPM_CAP_VERSION = 0x00000006,
+ TPM_CAP_KEY_HANDLE = 0x00000007,
+ TPM_CAP_CHECK_LOADED = 0x00000008,
+ TPM_CAP_SYM_MODE = 0x00000009,
+ TPM_CAP_KEY_STATUS = 0x0000000C,
+ TPM_CAP_NV_LIST = 0x0000000D,
+ TPM_CAP_MFR = 0x00000010,
+ TPM_CAP_NV_INDEX = 0x00000011,
+ TPM_CAP_TRANS_ALG = 0x00000012,
+ TPM_CAP_HANDLE = 0x00000014,
+ TPM_CAP_TRANS_ES = 0x00000015,
+ TPM_CAP_AUTH_ENCRYPT = 0x00000017,
+ TPM_CAP_SELECT_SIZE = 0x00000018,
+ TPM_CAP_DA_LOGIC = 0x00000019,
+ TPM_CAP_VERSION_VAL = 0x0000001A,
+};
+
+#define TPM_NV_PER_GLOBALLOCK BIT(15)
+#define TPM_NV_PER_PPREAD BIT(16)
+#define TPM_NV_PER_PPWRITE BIT(0)
+#define TPM_NV_PER_READ_STCLEAR BIT(31)
+#define TPM_NV_PER_WRITE_STCLEAR BIT(14)
+#define TPM_NV_PER_WRITEDEFINE BIT(13)
+#define TPM_NV_PER_WRITEALL BIT(12)
+
+enum {
+ TPM_PUBEK_SIZE = 256,
+};
+
+/**
+ * TPM return codes as defined in the TCG Main specification
+ * (TPM Main Part 2 Structures; Specification version 1.2)
+ */
+enum tpm_return_code {
+ TPM_BASE = 0x00000000,
+ TPM_NON_FATAL = 0x00000800,
+ TPM_SUCCESS = TPM_BASE,
+ /* TPM-defined fatal error codes */
+ TPM_AUTHFAIL = TPM_BASE + 1,
+ TPM_BADINDEX = TPM_BASE + 2,
+ TPM_BAD_PARAMETER = TPM_BASE + 3,
+ TPM_AUDITFAILURE = TPM_BASE + 4,
+ TPM_CLEAR_DISABLED = TPM_BASE + 5,
+ TPM_DEACTIVATED = TPM_BASE + 6,
+ TPM_DISABLED = TPM_BASE + 7,
+ TPM_DISABLED_CMD = TPM_BASE + 8,
+ TPM_FAIL = TPM_BASE + 9,
+ TPM_BAD_ORDINAL = TPM_BASE + 10,
+ TPM_INSTALL_DISABLED = TPM_BASE + 11,
+ TPM_INVALID_KEYHANDLE = TPM_BASE + 12,
+ TPM_KEYNOTFOUND = TPM_BASE + 13,
+ TPM_INAPPROPRIATE_ENC = TPM_BASE + 14,
+ TPM_MIGRATE_FAIL = TPM_BASE + 15,
+ TPM_INVALID_PCR_INFO = TPM_BASE + 16,
+ TPM_NOSPACE = TPM_BASE + 17,
+ TPM_NOSRK = TPM_BASE + 18,
+ TPM_NOTSEALED_BLOB = TPM_BASE + 19,
+ TPM_OWNER_SET = TPM_BASE + 20,
+ TPM_RESOURCES = TPM_BASE + 21,
+ TPM_SHORTRANDOM = TPM_BASE + 22,
+ TPM_SIZE = TPM_BASE + 23,
+ TPM_WRONGPCRVAL = TPM_BASE + 24,
+ TPM_BAD_PARAM_SIZE = TPM_BASE + 25,
+ TPM_SHA_THREAD = TPM_BASE + 26,
+ TPM_SHA_ERROR = TPM_BASE + 27,
+ TPM_FAILEDSELFTEST = TPM_BASE + 28,
+ TPM_AUTH2FAIL = TPM_BASE + 29,
+ TPM_BADTAG = TPM_BASE + 30,
+ TPM_IOERROR = TPM_BASE + 31,
+ TPM_ENCRYPT_ERROR = TPM_BASE + 32,
+ TPM_DECRYPT_ERROR = TPM_BASE + 33,
+ TPM_INVALID_AUTHHANDLE = TPM_BASE + 34,
+ TPM_NO_ENDORSEMENT = TPM_BASE + 35,
+ TPM_INVALID_KEYUSAGE = TPM_BASE + 36,
+ TPM_WRONG_ENTITYTYPE = TPM_BASE + 37,
+ TPM_INVALID_POSTINIT = TPM_BASE + 38,
+ TPM_INAPPROPRIATE_SIG = TPM_BASE + 39,
+ TPM_BAD_KEY_PROPERTY = TPM_BASE + 40,
+ TPM_BAD_MIGRATION = TPM_BASE + 41,
+ TPM_BAD_SCHEME = TPM_BASE + 42,
+ TPM_BAD_DATASIZE = TPM_BASE + 43,
+ TPM_BAD_MODE = TPM_BASE + 44,
+ TPM_BAD_PRESENCE = TPM_BASE + 45,
+ TPM_BAD_VERSION = TPM_BASE + 46,
+ TPM_NO_WRAP_TRANSPORT = TPM_BASE + 47,
+ TPM_AUDITFAIL_UNSUCCESSFUL = TPM_BASE + 48,
+ TPM_AUDITFAIL_SUCCESSFUL = TPM_BASE + 49,
+ TPM_NOTRESETABLE = TPM_BASE + 50,
+ TPM_NOTLOCAL = TPM_BASE + 51,
+ TPM_BAD_TYPE = TPM_BASE + 52,
+ TPM_INVALID_RESOURCE = TPM_BASE + 53,
+ TPM_NOTFIPS = TPM_BASE + 54,
+ TPM_INVALID_FAMILY = TPM_BASE + 55,
+ TPM_NO_NV_PERMISSION = TPM_BASE + 56,
+ TPM_REQUIRES_SIGN = TPM_BASE + 57,
+ TPM_KEY_NOTSUPPORTED = TPM_BASE + 58,
+ TPM_AUTH_CONFLICT = TPM_BASE + 59,
+ TPM_AREA_LOCKED = TPM_BASE + 60,
+ TPM_BAD_LOCALITY = TPM_BASE + 61,
+ TPM_READ_ONLY = TPM_BASE + 62,
+ TPM_PER_NOWRITE = TPM_BASE + 63,
+ TPM_FAMILY_COUNT = TPM_BASE + 64,
+ TPM_WRITE_LOCKED = TPM_BASE + 65,
+ TPM_BAD_ATTRIBUTES = TPM_BASE + 66,
+ TPM_INVALID_STRUCTURE = TPM_BASE + 67,
+ TPM_KEY_OWNER_CONTROL = TPM_BASE + 68,
+ TPM_BAD_COUNTER = TPM_BASE + 69,
+ TPM_NOT_FULLWRITE = TPM_BASE + 70,
+ TPM_CONTEXT_GAP = TPM_BASE + 71,
+ TPM_MAXNVWRITES = TPM_BASE + 72,
+ TPM_NOOPERATOR = TPM_BASE + 73,
+ TPM_RESOURCEMISSING = TPM_BASE + 74,
+ TPM_DELEGATE_LOCK = TPM_BASE + 75,
+ TPM_DELEGATE_FAMILY = TPM_BASE + 76,
+ TPM_DELEGATE_ADMIN = TPM_BASE + 77,
+ TPM_TRANSPORT_NOTEXCLUSIVE = TPM_BASE + 78,
+ TPM_OWNER_CONTROL = TPM_BASE + 79,
+ TPM_DAA_RESOURCES = TPM_BASE + 80,
+ TPM_DAA_INPUT_DATA0 = TPM_BASE + 81,
+ TPM_DAA_INPUT_DATA1 = TPM_BASE + 82,
+ TPM_DAA_ISSUER_SETTINGS = TPM_BASE + 83,
+ TPM_DAA_TPM_SETTINGS = TPM_BASE + 84,
+ TPM_DAA_STAGE = TPM_BASE + 85,
+ TPM_DAA_ISSUER_VALIDITY = TPM_BASE + 86,
+ TPM_DAA_WRONG_W = TPM_BASE + 87,
+ TPM_BAD_HANDLE = TPM_BASE + 88,
+ TPM_BAD_DELEGATE = TPM_BASE + 89,
+ TPM_BADCONTEXT = TPM_BASE + 90,
+ TPM_TOOMANYCONTEXTS = TPM_BASE + 91,
+ TPM_MA_TICKET_SIGNATURE = TPM_BASE + 92,
+ TPM_MA_DESTINATION = TPM_BASE + 93,
+ TPM_MA_SOURCE = TPM_BASE + 94,
+ TPM_MA_AUTHORITY = TPM_BASE + 95,
+ TPM_PERMANENTEK = TPM_BASE + 97,
+ TPM_BAD_SIGNATURE = TPM_BASE + 98,
+ TPM_NOCONTEXTSPACE = TPM_BASE + 99,
+ /* TPM-defined non-fatal errors */
+ TPM_RETRY = TPM_BASE + TPM_NON_FATAL,
+ TPM_NEEDS_SELFTEST = TPM_BASE + TPM_NON_FATAL + 1,
+ TPM_DOING_SELFTEST = TPM_BASE + TPM_NON_FATAL + 2,
+ TPM_DEFEND_LOCK_RUNNING = TPM_BASE + TPM_NON_FATAL + 3,
+};
+
+struct tpm_permanent_flags {
+ __be16 tag;
+ u8 disable;
+ u8 ownership;
+ u8 deactivated;
+ u8 read_pubek;
+ u8 disable_owner_clear;
+ u8 allow_maintenance;
+ u8 physical_presence_lifetime_lock;
+ u8 physical_presence_hw_enable;
+ u8 physical_presence_cmd_enable;
+ u8 cekp_used;
+ u8 tpm_post;
+ u8 tpm_post_lock;
+ u8 fips;
+ u8 operator;
+ u8 enable_revoke_ek;
+ u8 nv_locked;
+ u8 read_srk_pub;
+ u8 tpm_established;
+ u8 maintenance_done;
+ u8 disable_full_da_logic_info;
+} __packed;
+
+/**
+ * Issue a TPM_Startup command.
+ *
+ * @param mode TPM startup mode
+ * @return return code of the operation
+ */
+u32 tpm_startup(enum tpm_startup_type mode);
+
+/**
+ * Issue a TPM_SelfTestFull command.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_self_test_full(void);
+
+/**
+ * Issue a TPM_ContinueSelfTest command.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_continue_self_test(void);
+
+/**
+ * Issue a TPM_NV_DefineSpace command. The implementation is limited
+ * to specify TPM_NV_ATTRIBUTES and size of the area. The area index
+ * could be one of the special value listed in enum tpm_nv_index.
+ *
+ * @param index index of the area
+ * @param perm TPM_NV_ATTRIBUTES of the area
+ * @param size size of the area
+ * @return return code of the operation
+ */
+u32 tpm_nv_define_space(u32 index, u32 perm, u32 size);
+
+/**
+ * Issue a TPM_NV_ReadValue command. This implementation is limited
+ * to read the area from offset 0. The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param index index of the area
+ * @param data output buffer of the area contents
+ * @param count size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_nv_read_value(u32 index, void *data, u32 count);
+
+/**
+ * Issue a TPM_NV_WriteValue command. This implementation is limited
+ * to write the area from offset 0. The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param index index of the area
+ * @param data input buffer to be wrote to the area
+ * @param length length of data bytes of input buffer
+ * @return return code of the operation
+ */
+u32 tpm_nv_write_value(u32 index, const void *data, u32 length);
+
+/**
+ * Issue a TPM_Extend command.
+ *
+ * @param index index of the PCR
+ * @param in_digest 160-bit value representing the event to be
+ * recorded
+ * @param out_digest 160-bit PCR value after execution of the
+ * command
+ * @return return code of the operation
+ */
+u32 tpm_extend(u32 index, const void *in_digest, void *out_digest);
+
+/**
+ * Issue a TPM_PCRRead command.
+ *
+ * @param index index of the PCR
+ * @param data output buffer for contents of the named PCR
+ * @param count size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_pcr_read(u32 index, void *data, size_t count);
+
+/**
+ * Issue a TSC_PhysicalPresence command. TPM physical presence flag
+ * is bit-wise OR'ed of flags listed in enum tpm_physical_presence.
+ *
+ * @param presence TPM physical presence flag
+ * @return return code of the operation
+ */
+u32 tpm_tsc_physical_presence(u16 presence);
+
+/**
+ * Issue a TPM_ReadPubek command.
+ *
+ * @param data output buffer for the public endorsement key
+ * @param count size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_read_pubek(void *data, size_t count);
+
+/**
+ * Issue a TPM_ForceClear command.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_force_clear(void);
+
+/**
+ * Issue a TPM_PhysicalEnable command.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_physical_enable(void);
+
+/**
+ * Issue a TPM_PhysicalDisable command.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_physical_disable(void);
+
+/**
+ * Issue a TPM_PhysicalSetDeactivated command.
+ *
+ * @param state boolean state of the deactivated flag
+ * @return return code of the operation
+ */
+u32 tpm_physical_set_deactivated(u8 state);
+
+/**
+ * Issue a TPM_GetCapability command. This implementation is limited
+ * to query sub_cap index that is 4-byte wide.
+ *
+ * @param cap_area partition of capabilities
+ * @param sub_cap further definition of capability, which is
+ * limited to be 4-byte wide
+ * @param cap output buffer for capability information
+ * @param count size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count);
+
+/**
+ * Issue a TPM_FlushSpecific command for a AUTH resource.
+ *
+ * @param auth_handle handle of the auth session
+ * @return return code of the operation
+ */
+u32 tpm_terminate_auth_session(u32 auth_handle);
+
+/**
+ * Issue a TPM_OIAP command to setup an object independent authorization
+ * session.
+ * Information about the session is stored internally.
+ * If there was already an OIAP session active it is terminated and a new
+ * session is set up.
+ *
+ * @param auth_handle pointer to the (new) auth handle or NULL.
+ * @return return code of the operation
+ */
+u32 tpm_oiap(u32 *auth_handle);
+
+/**
+ * Ends an active OIAP session.
+ *
+ * @return return code of the operation
+ */
+u32 tpm_end_oiap(void);
+
+/**
+ * Issue a TPM_LoadKey2 (Auth1) command using an OIAP session for authenticating
+ * the usage of the parent key.
+ *
+ * @param parent_handle handle of the parent key.
+ * @param key pointer to the key structure (TPM_KEY or TPM_KEY12).
+ * @param key_length size of the key structure
+ * @param parent_key_usage_auth usage auth for the parent key
+ * @param key_handle pointer to the key handle
+ * @return return code of the operation
+ */
+u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length,
+ const void *parent_key_usage_auth, u32 *key_handle);
+
+/**
+ * Issue a TPM_GetPubKey (Auth1) command using an OIAP session for
+ * authenticating the usage of the key.
+ *
+ * @param key_handle handle of the key
+ * @param usage_auth usage auth for the key
+ * @param pubkey pointer to the pub key buffer; may be NULL if the pubkey
+ * should not be stored.
+ * @param pubkey_len pointer to the pub key buffer len. On entry: the size of
+ * the provided pubkey buffer. On successful exit: the size
+ * of the stored TPM_PUBKEY structure (iff pubkey != NULL).
+ * @return return code of the operation
+ */
+u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey,
+ size_t *pubkey_len);
+
+/**
+ * Get the TPM permanent flags value
+ *
+ * @param pflags Place to put permanent flags
+ * @return return code of the operation
+ */
+u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags);
+
+/**
+ * Get the TPM permissions
+ *
+ * @param perm Returns permissions value
+ * @return return code of the operation
+ */
+u32 tpm_get_permissions(u32 index, u32 *perm);
+
+/**
+ * Flush a resource with a given handle and type from the TPM
+ *
+ * @param key_handle handle of the resource
+ * @param resource_type type of the resource
+ * @return return code of the operation
+ */
+u32 tpm_flush_specific(u32 key_handle, u32 resource_type);
+
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+/**
+ * Search for a key by usage AuthData and the hash of the parent's pub key.
+ *
+ * @param auth Usage auth of the key to search for
+ * @param pubkey_digest SHA1 hash of the pub key structure of the key
+ * @param[out] handle The handle of the key (Non-null iff found)
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20],
+ u32 *handle);
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
+/**
+ * Read random bytes from the TPM RNG. The implementation deals with the fact
+ * that the TPM may legally return fewer bytes than requested by retrying
+ * until @p count bytes have been received.
+ *
+ * @param data output buffer for the random bytes
+ * @param count size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_get_random(void *data, u32 count);
+
+#endif /* __TPM_V1_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Bootlin
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#ifndef __TPM_V2_H
+#define __TPM_V2_H
+
+#include <tpm-common.h>
+
+#define TPM2_DIGEST_LEN 32
+
+/**
+ * TPM2 Structure Tags for command/response buffers.
+ *
+ * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
+ * @TPM2_ST_SESSIONS: the command needs an authentication.
+ */
+enum tpm2_structures {
+ TPM2_ST_NO_SESSIONS = 0x8001,
+ TPM2_ST_SESSIONS = 0x8002,
+};
+
+/**
+ * TPM2 type of boolean.
+ */
+enum tpm2_yes_no {
+ TPMI_YES = 1,
+ TPMI_NO = 0,
+};
+
+/**
+ * TPM2 startup values.
+ *
+ * @TPM2_SU_CLEAR: reset the internal state.
+ * @TPM2_SU_STATE: restore saved state (if any).
+ */
+enum tpm2_startup_types {
+ TPM2_SU_CLEAR = 0x0000,
+ TPM2_SU_STATE = 0x0001,
+};
+
+/**
+ * TPM2 permanent handles.
+ *
+ * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
+ * @TPM2_RS_PW: indicates a password.
+ * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
+ * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
+ * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
+ */
+enum tpm2_handles {
+ TPM2_RH_OWNER = 0x40000001,
+ TPM2_RS_PW = 0x40000009,
+ TPM2_RH_LOCKOUT = 0x4000000A,
+ TPM2_RH_ENDORSEMENT = 0x4000000B,
+ TPM2_RH_PLATFORM = 0x4000000C,
+};
+
+/**
+ * TPM2 command codes used at the beginning of a buffer, gives the command.
+ *
+ * @TPM2_CC_STARTUP: TPM2_Startup().
+ * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
+ * @TPM2_CC_CLEAR: TPM2_Clear().
+ * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
+ * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
+ * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
+ * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
+ * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
+ * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
+ * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
+ * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
+ * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
+ */
+enum tpm2_command_codes {
+ TPM2_CC_STARTUP = 0x0144,
+ TPM2_CC_SELF_TEST = 0x0143,
+ TPM2_CC_CLEAR = 0x0126,
+ TPM2_CC_CLEARCONTROL = 0x0127,
+ TPM2_CC_HIERCHANGEAUTH = 0x0129,
+ TPM2_CC_PCR_SETAUTHPOL = 0x012C,
+ TPM2_CC_DAM_RESET = 0x0139,
+ TPM2_CC_DAM_PARAMETERS = 0x013A,
+ TPM2_CC_GET_CAPABILITY = 0x017A,
+ TPM2_CC_PCR_READ = 0x017E,
+ TPM2_CC_PCR_EXTEND = 0x0182,
+ TPM2_CC_PCR_SETAUTHVAL = 0x0183,
+};
+
+/**
+ * TPM2 return codes.
+ */
+enum tpm2_return_codes {
+ TPM2_RC_SUCCESS = 0x0000,
+ TPM2_RC_BAD_TAG = 0x001E,
+ TPM2_RC_FMT1 = 0x0080,
+ TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
+ TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
+ TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
+ TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
+ TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
+ TPM2_RC_VER1 = 0x0100,
+ TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
+ TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
+ TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
+ TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
+ TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
+ TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
+ TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
+ TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
+ TPM2_RC_WARN = 0x0900,
+ TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
+ TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
+ TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
+};
+
+/**
+ * TPM2 algorithms.
+ */
+enum tpm2_algorithms {
+ TPM2_ALG_XOR = 0x0A,
+ TPM2_ALG_SHA256 = 0x0B,
+ TPM2_ALG_SHA384 = 0x0C,
+ TPM2_ALG_SHA512 = 0x0D,
+ TPM2_ALG_NULL = 0x10,
+};
+
+/**
+ * Issue a TPM2_Startup command.
+ *
+ * @mode TPM startup mode
+ *
+ * @return code of the operation
+ */
+u32 tpm2_startup(enum tpm2_startup_types mode);
+
+/**
+ * Issue a TPM2_SelfTest command.
+ *
+ * @full_test Asking to perform all tests or only the untested ones
+ *
+ * @return code of the operation
+ */
+u32 tpm2_self_test(enum tpm2_yes_no full_test);
+
+/**
+ * Issue a TPM2_Clear command.
+ *
+ * @handle Handle
+ * @pw Password
+ * @pw_sz Length of the password
+ *
+ * @return code of the operation
+ */
+u32 tpm2_clear(u32 handle, const char *pw, const ssize_t pw_sz);
+
+/**
+ * Issue a TPM2_PCR_Extend command.
+ *
+ * @index Index of the PCR
+ * @digest Value representing the event to be recorded
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_extend(u32 index, const uint8_t *digest);
+
+/**
+ * Issue a TPM2_PCR_Read command.
+ *
+ * @idx Index of the PCR
+ * @idx_min_sz Minimum size in bytes of the pcrSelect array
+ * @data Output buffer for contents of the named PCR
+ * @updates Optional out parameter: number of updates for this PCR
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data,
+ unsigned int *updates);
+
+/**
+ * Issue a TPM2_GetCapability command. This implementation is limited
+ * to query property index that is 4-byte wide.
+ *
+ * @capability Partition of capabilities
+ * @property Further definition of capability, limited to be 4 bytes wide
+ * @buf Output buffer for capability information
+ * @prop_count Size of output buffer
+ *
+ * @return code of the operation
+ */
+u32 tpm2_get_capability(u32 capability, u32 property, void *buf,
+ size_t prop_count);
+
+/**
+ * Issue a TPM2_DictionaryAttackLockReset command.
+ *
+ * @pw Password
+ * @pw_sz Length of the password
+ *
+ * @return code of the operation
+ */
+u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz);
+
+/**
+ * Issue a TPM2_DictionaryAttackParameters command.
+ *
+ * @pw Password
+ * @pw_sz Length of the password
+ * @max_tries Count of authorizations before lockout
+ * @recovery_time Time before decrementation of the failure count
+ * @lockout_recovery Time to wait after a lockout
+ *
+ * @return code of the operation
+ */
+u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz,
+ unsigned int max_tries, unsigned int recovery_time,
+ unsigned int lockout_recovery);
+
+/**
+ * Issue a TPM2_HierarchyChangeAuth command.
+ *
+ * @handle Handle
+ * @newpw New password
+ * @newpw_sz Length of the new password
+ * @oldpw Old password
+ * @oldpw_sz Length of the old password
+ *
+ * @return code of the operation
+ */
+int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz,
+ const char *oldpw, const ssize_t oldpw_sz);
+
+/**
+ * Issue a TPM_PCR_SetAuthPolicy command.
+ *
+ * @pw Platform password
+ * @pw_sz Length of the password
+ * @index Index of the PCR
+ * @digest New key to access the PCR
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index,
+ const char *key);
+
+/**
+ * Issue a TPM_PCR_SetAuthValue command.
+ *
+ * @pw Platform password
+ * @pw_sz Length of the password
+ * @index Index of the PCR
+ * @digest New key to access the PCR
+ * @key_sz Length of the new key
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_setauthvalue(const char *pw, const ssize_t pw_sz, u32 index,
+ const char *key, const ssize_t key_sz);
+
+#endif /* __TPM_V2_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013 The Chromium OS Authors.
- * Coypright (c) 2013 Guntermann & Drunck GmbH
- */
-
-#ifndef __TPM_H
-#define __TPM_H
-
-/*
- * Here is a partial implementation of TPM commands. Please consult TCG Main
- * Specification for definitions of TPM commands.
- */
-
-#define TPM_HEADER_SIZE 10
-
-enum tpm_duration {
- TPM_SHORT = 0,
- TPM_MEDIUM = 1,
- TPM_LONG = 2,
- TPM_UNDEFINED,
-
- TPM_DURATION_COUNT,
-};
-
-enum tpm_startup_type {
- TPM_ST_CLEAR = 0x0001,
- TPM_ST_STATE = 0x0002,
- TPM_ST_DEACTIVATED = 0x0003,
-};
-
-enum tpm_physical_presence {
- TPM_PHYSICAL_PRESENCE_HW_DISABLE = 0x0200,
- TPM_PHYSICAL_PRESENCE_CMD_DISABLE = 0x0100,
- TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK = 0x0080,
- TPM_PHYSICAL_PRESENCE_HW_ENABLE = 0x0040,
- TPM_PHYSICAL_PRESENCE_CMD_ENABLE = 0x0020,
- TPM_PHYSICAL_PRESENCE_NOTPRESENT = 0x0010,
- TPM_PHYSICAL_PRESENCE_PRESENT = 0x0008,
- TPM_PHYSICAL_PRESENCE_LOCK = 0x0004,
-};
-
-enum tpm_nv_index {
- TPM_NV_INDEX_LOCK = 0xffffffff,
- TPM_NV_INDEX_0 = 0x00000000,
- TPM_NV_INDEX_DIR = 0x10000001,
-};
-
-enum tpm_resource_type {
- TPM_RT_KEY = 0x00000001,
- TPM_RT_AUTH = 0x00000002,
- TPM_RT_HASH = 0x00000003,
- TPM_RT_TRANS = 0x00000004,
- TPM_RT_CONTEXT = 0x00000005,
- TPM_RT_COUNTER = 0x00000006,
- TPM_RT_DELEGATE = 0x00000007,
- TPM_RT_DAA_TPM = 0x00000008,
- TPM_RT_DAA_V0 = 0x00000009,
- TPM_RT_DAA_V1 = 0x0000000A,
-};
-
-enum tpm_capability_areas {
- TPM_CAP_ORD = 0x00000001,
- TPM_CAP_ALG = 0x00000002,
- TPM_CAP_PID = 0x00000003,
- TPM_CAP_FLAG = 0x00000004,
- TPM_CAP_PROPERTY = 0x00000005,
- TPM_CAP_VERSION = 0x00000006,
- TPM_CAP_KEY_HANDLE = 0x00000007,
- TPM_CAP_CHECK_LOADED = 0x00000008,
- TPM_CAP_SYM_MODE = 0x00000009,
- TPM_CAP_KEY_STATUS = 0x0000000C,
- TPM_CAP_NV_LIST = 0x0000000D,
- TPM_CAP_MFR = 0x00000010,
- TPM_CAP_NV_INDEX = 0x00000011,
- TPM_CAP_TRANS_ALG = 0x00000012,
- TPM_CAP_HANDLE = 0x00000014,
- TPM_CAP_TRANS_ES = 0x00000015,
- TPM_CAP_AUTH_ENCRYPT = 0x00000017,
- TPM_CAP_SELECT_SIZE = 0x00000018,
- TPM_CAP_DA_LOGIC = 0x00000019,
- TPM_CAP_VERSION_VAL = 0x0000001A,
-};
-
-#define TPM_NV_PER_GLOBALLOCK (1U << 15)
-#define TPM_NV_PER_PPREAD (1U << 16)
-#define TPM_NV_PER_PPWRITE (1U << 0)
-#define TPM_NV_PER_READ_STCLEAR (1U << 31)
-#define TPM_NV_PER_WRITE_STCLEAR (1U << 14)
-#define TPM_NV_PER_WRITEDEFINE (1U << 13)
-#define TPM_NV_PER_WRITEALL (1U << 12)
-
-enum {
- TPM_PUBEK_SIZE = 256,
-};
-
-/**
- * TPM return codes as defined in the TCG Main specification
- * (TPM Main Part 2 Structures; Specification version 1.2)
- */
-enum tpm_return_code {
- TPM_BASE = 0x00000000,
- TPM_NON_FATAL = 0x00000800,
- TPM_SUCCESS = TPM_BASE,
- /* TPM-defined fatal error codes */
- TPM_AUTHFAIL = TPM_BASE + 1,
- TPM_BADINDEX = TPM_BASE + 2,
- TPM_BAD_PARAMETER = TPM_BASE + 3,
- TPM_AUDITFAILURE = TPM_BASE + 4,
- TPM_CLEAR_DISABLED = TPM_BASE + 5,
- TPM_DEACTIVATED = TPM_BASE + 6,
- TPM_DISABLED = TPM_BASE + 7,
- TPM_DISABLED_CMD = TPM_BASE + 8,
- TPM_FAIL = TPM_BASE + 9,
- TPM_BAD_ORDINAL = TPM_BASE + 10,
- TPM_INSTALL_DISABLED = TPM_BASE + 11,
- TPM_INVALID_KEYHANDLE = TPM_BASE + 12,
- TPM_KEYNOTFOUND = TPM_BASE + 13,
- TPM_INAPPROPRIATE_ENC = TPM_BASE + 14,
- TPM_MIGRATE_FAIL = TPM_BASE + 15,
- TPM_INVALID_PCR_INFO = TPM_BASE + 16,
- TPM_NOSPACE = TPM_BASE + 17,
- TPM_NOSRK = TPM_BASE + 18,
- TPM_NOTSEALED_BLOB = TPM_BASE + 19,
- TPM_OWNER_SET = TPM_BASE + 20,
- TPM_RESOURCES = TPM_BASE + 21,
- TPM_SHORTRANDOM = TPM_BASE + 22,
- TPM_SIZE = TPM_BASE + 23,
- TPM_WRONGPCRVAL = TPM_BASE + 24,
- TPM_BAD_PARAM_SIZE = TPM_BASE + 25,
- TPM_SHA_THREAD = TPM_BASE + 26,
- TPM_SHA_ERROR = TPM_BASE + 27,
- TPM_FAILEDSELFTEST = TPM_BASE + 28,
- TPM_AUTH2FAIL = TPM_BASE + 29,
- TPM_BADTAG = TPM_BASE + 30,
- TPM_IOERROR = TPM_BASE + 31,
- TPM_ENCRYPT_ERROR = TPM_BASE + 32,
- TPM_DECRYPT_ERROR = TPM_BASE + 33,
- TPM_INVALID_AUTHHANDLE = TPM_BASE + 34,
- TPM_NO_ENDORSEMENT = TPM_BASE + 35,
- TPM_INVALID_KEYUSAGE = TPM_BASE + 36,
- TPM_WRONG_ENTITYTYPE = TPM_BASE + 37,
- TPM_INVALID_POSTINIT = TPM_BASE + 38,
- TPM_INAPPROPRIATE_SIG = TPM_BASE + 39,
- TPM_BAD_KEY_PROPERTY = TPM_BASE + 40,
- TPM_BAD_MIGRATION = TPM_BASE + 41,
- TPM_BAD_SCHEME = TPM_BASE + 42,
- TPM_BAD_DATASIZE = TPM_BASE + 43,
- TPM_BAD_MODE = TPM_BASE + 44,
- TPM_BAD_PRESENCE = TPM_BASE + 45,
- TPM_BAD_VERSION = TPM_BASE + 46,
- TPM_NO_WRAP_TRANSPORT = TPM_BASE + 47,
- TPM_AUDITFAIL_UNSUCCESSFUL = TPM_BASE + 48,
- TPM_AUDITFAIL_SUCCESSFUL = TPM_BASE + 49,
- TPM_NOTRESETABLE = TPM_BASE + 50,
- TPM_NOTLOCAL = TPM_BASE + 51,
- TPM_BAD_TYPE = TPM_BASE + 52,
- TPM_INVALID_RESOURCE = TPM_BASE + 53,
- TPM_NOTFIPS = TPM_BASE + 54,
- TPM_INVALID_FAMILY = TPM_BASE + 55,
- TPM_NO_NV_PERMISSION = TPM_BASE + 56,
- TPM_REQUIRES_SIGN = TPM_BASE + 57,
- TPM_KEY_NOTSUPPORTED = TPM_BASE + 58,
- TPM_AUTH_CONFLICT = TPM_BASE + 59,
- TPM_AREA_LOCKED = TPM_BASE + 60,
- TPM_BAD_LOCALITY = TPM_BASE + 61,
- TPM_READ_ONLY = TPM_BASE + 62,
- TPM_PER_NOWRITE = TPM_BASE + 63,
- TPM_FAMILY_COUNT = TPM_BASE + 64,
- TPM_WRITE_LOCKED = TPM_BASE + 65,
- TPM_BAD_ATTRIBUTES = TPM_BASE + 66,
- TPM_INVALID_STRUCTURE = TPM_BASE + 67,
- TPM_KEY_OWNER_CONTROL = TPM_BASE + 68,
- TPM_BAD_COUNTER = TPM_BASE + 69,
- TPM_NOT_FULLWRITE = TPM_BASE + 70,
- TPM_CONTEXT_GAP = TPM_BASE + 71,
- TPM_MAXNVWRITES = TPM_BASE + 72,
- TPM_NOOPERATOR = TPM_BASE + 73,
- TPM_RESOURCEMISSING = TPM_BASE + 74,
- TPM_DELEGATE_LOCK = TPM_BASE + 75,
- TPM_DELEGATE_FAMILY = TPM_BASE + 76,
- TPM_DELEGATE_ADMIN = TPM_BASE + 77,
- TPM_TRANSPORT_NOTEXCLUSIVE = TPM_BASE + 78,
- TPM_OWNER_CONTROL = TPM_BASE + 79,
- TPM_DAA_RESOURCES = TPM_BASE + 80,
- TPM_DAA_INPUT_DATA0 = TPM_BASE + 81,
- TPM_DAA_INPUT_DATA1 = TPM_BASE + 82,
- TPM_DAA_ISSUER_SETTINGS = TPM_BASE + 83,
- TPM_DAA_TPM_SETTINGS = TPM_BASE + 84,
- TPM_DAA_STAGE = TPM_BASE + 85,
- TPM_DAA_ISSUER_VALIDITY = TPM_BASE + 86,
- TPM_DAA_WRONG_W = TPM_BASE + 87,
- TPM_BAD_HANDLE = TPM_BASE + 88,
- TPM_BAD_DELEGATE = TPM_BASE + 89,
- TPM_BADCONTEXT = TPM_BASE + 90,
- TPM_TOOMANYCONTEXTS = TPM_BASE + 91,
- TPM_MA_TICKET_SIGNATURE = TPM_BASE + 92,
- TPM_MA_DESTINATION = TPM_BASE + 93,
- TPM_MA_SOURCE = TPM_BASE + 94,
- TPM_MA_AUTHORITY = TPM_BASE + 95,
- TPM_PERMANENTEK = TPM_BASE + 97,
- TPM_BAD_SIGNATURE = TPM_BASE + 98,
- TPM_NOCONTEXTSPACE = TPM_BASE + 99,
- /* TPM-defined non-fatal errors */
- TPM_RETRY = TPM_BASE + TPM_NON_FATAL,
- TPM_NEEDS_SELFTEST = TPM_BASE + TPM_NON_FATAL + 1,
- TPM_DOING_SELFTEST = TPM_BASE + TPM_NON_FATAL + 2,
- TPM_DEFEND_LOCK_RUNNING = TPM_BASE + TPM_NON_FATAL + 3,
-};
-
-struct tpm_permanent_flags {
- __be16 tag;
- u8 disable;
- u8 ownership;
- u8 deactivated;
- u8 read_pubek;
- u8 disable_owner_clear;
- u8 allow_maintenance;
- u8 physical_presence_lifetime_lock;
- u8 physical_presence_hw_enable;
- u8 physical_presence_cmd_enable;
- u8 cekp_used;
- u8 tpm_post;
- u8 tpm_post_lock;
- u8 fips;
- u8 operator;
- u8 enable_revoke_ek;
- u8 nv_locked;
- u8 read_srk_pub;
- u8 tpm_established;
- u8 maintenance_done;
- u8 disable_full_da_logic_info;
-} __packed;
-
-/* Max buffer size supported by our tpm */
-#define TPM_DEV_BUFSIZE 1260
-
-/**
- * struct tpm_chip_priv - Information about a TPM, stored by the uclass
- *
- * These values must be set up by the device's probe() method before
- * communcation is attempted. If the device has an xfer() method, this is
- * not needed. There is no need to set up @buf.
- *
- * @duration_ms: Length of each duration type in milliseconds
- * @retry_time_ms: Time to wait before retrying receive
- */
-struct tpm_chip_priv {
- uint duration_ms[TPM_DURATION_COUNT];
- uint retry_time_ms;
- u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
-};
-
-/**
- * struct tpm_ops - low-level TPM operations
- *
- * These are designed to avoid loops and delays in the driver itself. These
- * should be handled in the uclass.
- *
- * In gneral you should implement everything except xfer(). Where you need
- * complete control of the transfer, then xfer() can be provided and will
- * override the other methods.
- *
- * This interface is for low-level TPM access. It does not understand the
- * concept of localities or the various TPM messages. That interface is
- * defined in the functions later on in this file, but they all translate
- * to bytes which are sent and received.
- */
-struct tpm_ops {
- /**
- * open() - Request access to locality 0 for the caller
- *
- * After all commands have been completed the caller should call
- * close().
- *
- * @dev: Device to close
- * @return 0 ok OK, -ve on error
- */
- int (*open)(struct udevice *dev);
-
- /**
- * close() - Close the current session
- *
- * Releasing the locked locality. Returns 0 on success, -ve 1 on
- * failure (in case lock removal did not succeed).
- *
- * @dev: Device to close
- * @return 0 ok OK, -ve on error
- */
- int (*close)(struct udevice *dev);
-
- /**
- * get_desc() - Get a text description of the TPM
- *
- * @dev: Device to check
- * @buf: Buffer to put the string
- * @size: Maximum size of buffer
- * @return length of string, or -ENOSPC it no space
- */
- int (*get_desc)(struct udevice *dev, char *buf, int size);
-
- /**
- * send() - send data to the TPM
- *
- * @dev: Device to talk to
- * @sendbuf: Buffer of the data to send
- * @send_size: Size of the data to send
- *
- * Returns 0 on success or -ve on failure.
- */
- int (*send)(struct udevice *dev, const uint8_t *sendbuf,
- size_t send_size);
-
- /**
- * recv() - receive a response from the TPM
- *
- * @dev: Device to talk to
- * @recvbuf: Buffer to save the response to
- * @max_size: Maximum number of bytes to receive
- *
- * Returns number of bytes received on success, -EAGAIN if the TPM
- * response is not ready, -EINTR if cancelled, or other -ve value on
- * failure.
- */
- int (*recv)(struct udevice *dev, uint8_t *recvbuf, size_t max_size);
-
- /**
- * cleanup() - clean up after an operation in progress
- *
- * This is called if receiving times out. The TPM may need to abort
- * the current transaction if it did not complete, and make itself
- * ready for another.
- *
- * @dev: Device to talk to
- */
- int (*cleanup)(struct udevice *dev);
-
- /**
- * xfer() - send data to the TPM and get response
- *
- * This method is optional. If it exists it is used in preference
- * to send(), recv() and cleanup(). It should handle all aspects of
- * TPM communication for a single transfer.
- *
- * @dev: Device to talk to
- * @sendbuf: Buffer of the data to send
- * @send_size: Size of the data to send
- * @recvbuf: Buffer to save the response to
- * @recv_size: Pointer to the size of the response buffer
- *
- * Returns 0 on success (and places the number of response bytes at
- * recv_size) or -ve on failure.
- */
- int (*xfer)(struct udevice *dev, const uint8_t *sendbuf,
- size_t send_size, uint8_t *recvbuf, size_t *recv_size);
-};
-
-#define tpm_get_ops(dev) ((struct tpm_ops *)device_get_ops(dev))
-
-/**
- * tpm_open() - Request access to locality 0 for the caller
- *
- * After all commands have been completed the caller is supposed to
- * call tpm_close().
- *
- * Returns 0 on success, -ve on failure.
- */
-int tpm_open(struct udevice *dev);
-
-/**
- * tpm_close() - Close the current session
- *
- * Releasing the locked locality. Returns 0 on success, -ve 1 on
- * failure (in case lock removal did not succeed).
- */
-int tpm_close(struct udevice *dev);
-
-/**
- * tpm_get_desc() - Get a text description of the TPM
- *
- * @dev: Device to check
- * @buf: Buffer to put the string
- * @size: Maximum size of buffer
- * @return length of string, or -ENOSPC it no space
- */
-int tpm_get_desc(struct udevice *dev, char *buf, int size);
-
-/**
- * tpm_xfer() - send data to the TPM and get response
- *
- * This first uses the device's send() method to send the bytes. Then it calls
- * recv() to get the reply. If recv() returns -EAGAIN then it will delay a
- * short time and then call recv() again.
- *
- * Regardless of whether recv() completes successfully, it will then call
- * cleanup() to finish the transaction.
- *
- * Note that the outgoing data is inspected to determine command type
- * (ordinal) and a timeout is used for that command type.
- *
- * @sendbuf - buffer of the data to send
- * @send_size size of the data to send
- * @recvbuf - memory to save the response to
- * @recv_len - pointer to the size of the response buffer
- *
- * Returns 0 on success (and places the number of response bytes at
- * recv_len) or -ve on failure.
- */
-int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, size_t send_size,
- uint8_t *recvbuf, size_t *recv_size);
-
-/**
- * Initialize TPM device. It must be called before any TPM commands.
- *
- * @return 0 on success, non-0 on error.
- */
-int tpm_init(void);
-
-/**
- * Issue a TPM_Startup command.
- *
- * @param mode TPM startup mode
- * @return return code of the operation
- */
-uint32_t tpm_startup(enum tpm_startup_type mode);
-
-/**
- * Issue a TPM_SelfTestFull command.
- *
- * @return return code of the operation
- */
-uint32_t tpm_self_test_full(void);
-
-/**
- * Issue a TPM_ContinueSelfTest command.
- *
- * @return return code of the operation
- */
-uint32_t tpm_continue_self_test(void);
-
-/**
- * Issue a TPM_NV_DefineSpace command. The implementation is limited
- * to specify TPM_NV_ATTRIBUTES and size of the area. The area index
- * could be one of the special value listed in enum tpm_nv_index.
- *
- * @param index index of the area
- * @param perm TPM_NV_ATTRIBUTES of the area
- * @param size size of the area
- * @return return code of the operation
- */
-uint32_t tpm_nv_define_space(uint32_t index, uint32_t perm, uint32_t size);
-
-/**
- * Issue a TPM_NV_ReadValue command. This implementation is limited
- * to read the area from offset 0. The area index could be one of
- * the special value listed in enum tpm_nv_index.
- *
- * @param index index of the area
- * @param data output buffer of the area contents
- * @param count size of output buffer
- * @return return code of the operation
- */
-uint32_t tpm_nv_read_value(uint32_t index, void *data, uint32_t count);
-
-/**
- * Issue a TPM_NV_WriteValue command. This implementation is limited
- * to write the area from offset 0. The area index could be one of
- * the special value listed in enum tpm_nv_index.
- *
- * @param index index of the area
- * @param data input buffer to be wrote to the area
- * @param length length of data bytes of input buffer
- * @return return code of the operation
- */
-uint32_t tpm_nv_write_value(uint32_t index, const void *data, uint32_t length);
-
-/**
- * Issue a TPM_Extend command.
- *
- * @param index index of the PCR
- * @param in_digest 160-bit value representing the event to be
- * recorded
- * @param out_digest 160-bit PCR value after execution of the
- * command
- * @return return code of the operation
- */
-uint32_t tpm_extend(uint32_t index, const void *in_digest, void *out_digest);
-
-/**
- * Issue a TPM_PCRRead command.
- *
- * @param index index of the PCR
- * @param data output buffer for contents of the named PCR
- * @param count size of output buffer
- * @return return code of the operation
- */
-uint32_t tpm_pcr_read(uint32_t index, void *data, size_t count);
-
-/**
- * Issue a TSC_PhysicalPresence command. TPM physical presence flag
- * is bit-wise OR'ed of flags listed in enum tpm_physical_presence.
- *
- * @param presence TPM physical presence flag
- * @return return code of the operation
- */
-uint32_t tpm_tsc_physical_presence(uint16_t presence);
-
-/**
- * Issue a TPM_ReadPubek command.
- *
- * @param data output buffer for the public endorsement key
- * @param count size of ouput buffer
- * @return return code of the operation
- */
-uint32_t tpm_read_pubek(void *data, size_t count);
-
-/**
- * Issue a TPM_ForceClear command.
- *
- * @return return code of the operation
- */
-uint32_t tpm_force_clear(void);
-
-/**
- * Issue a TPM_PhysicalEnable command.
- *
- * @return return code of the operation
- */
-uint32_t tpm_physical_enable(void);
-
-/**
- * Issue a TPM_PhysicalDisable command.
- *
- * @return return code of the operation
- */
-uint32_t tpm_physical_disable(void);
-
-/**
- * Issue a TPM_PhysicalSetDeactivated command.
- *
- * @param state boolean state of the deactivated flag
- * @return return code of the operation
- */
-uint32_t tpm_physical_set_deactivated(uint8_t state);
-
-/**
- * Issue a TPM_GetCapability command. This implementation is limited
- * to query sub_cap index that is 4-byte wide.
- *
- * @param cap_area partition of capabilities
- * @param sub_cap further definition of capability, which is
- * limited to be 4-byte wide
- * @param cap output buffer for capability information
- * @param count size of ouput buffer
- * @return return code of the operation
- */
-uint32_t tpm_get_capability(uint32_t cap_area, uint32_t sub_cap,
- void *cap, size_t count);
-
-/**
- * Issue a TPM_FlushSpecific command for a AUTH ressource.
- *
- * @param auth_handle handle of the auth session
- * @return return code of the operation
- */
-uint32_t tpm_terminate_auth_session(uint32_t auth_handle);
-
-/**
- * Issue a TPM_OIAP command to setup an object independant authorization
- * session.
- * Information about the session is stored internally.
- * If there was already an OIAP session active it is terminated and a new
- * session is set up.
- *
- * @param auth_handle pointer to the (new) auth handle or NULL.
- * @return return code of the operation
- */
-uint32_t tpm_oiap(uint32_t *auth_handle);
-
-/**
- * Ends an active OIAP session.
- *
- * @return return code of the operation
- */
-uint32_t tpm_end_oiap(void);
-
-/**
- * Issue a TPM_LoadKey2 (Auth1) command using an OIAP session for authenticating
- * the usage of the parent key.
- *
- * @param parent_handle handle of the parent key.
- * @param key pointer to the key structure (TPM_KEY or TPM_KEY12).
- * @param key_length size of the key structure
- * @param parent_key_usage_auth usage auth for the parent key
- * @param key_handle pointer to the key handle
- * @return return code of the operation
- */
-uint32_t tpm_load_key2_oiap(uint32_t parent_handle,
- const void *key, size_t key_length,
- const void *parent_key_usage_auth,
- uint32_t *key_handle);
-
-/**
- * Issue a TPM_GetPubKey (Auth1) command using an OIAP session for
- * authenticating the usage of the key.
- *
- * @param key_handle handle of the key
- * @param usage_auth usage auth for the key
- * @param pubkey pointer to the pub key buffer; may be NULL if the pubkey
- * should not be stored.
- * @param pubkey_len pointer to the pub key buffer len. On entry: the size of
- * the provided pubkey buffer. On successful exit: the size
- * of the stored TPM_PUBKEY structure (iff pubkey != NULL).
- * @return return code of the operation
- */
-uint32_t tpm_get_pub_key_oiap(uint32_t key_handle, const void *usage_auth,
- void *pubkey, size_t *pubkey_len);
-
-/**
- * Get the TPM permanent flags value
- *
- * @param pflags Place to put permanent flags
- * @return return code of the operation
- */
-uint32_t tpm_get_permanent_flags(struct tpm_permanent_flags *pflags);
-
-/**
- * Get the TPM permissions
- *
- * @param perm Returns permissions value
- * @return return code of the operation
- */
-uint32_t tpm_get_permissions(uint32_t index, uint32_t *perm);
-
-/**
- * Flush a resource with a given handle and type from the TPM
- *
- * @param key_handle handle of the resource
- * @param resource_type type of the resource
- * @return return code of the operation
- */
-uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type);
-
-#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
-/**
- * Search for a key by usage AuthData and the hash of the parent's pub key.
- *
- * @param auth Usage auth of the key to search for
- * @param pubkey_digest SHA1 hash of the pub key structure of the key
- * @param[out] handle The handle of the key (Non-null iff found)
- * @return 0 if key was found in TPM; != 0 if not.
- */
-uint32_t tpm_find_key_sha1(const uint8_t auth[20], const uint8_t
- pubkey_digest[20], uint32_t *handle);
-#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
-
-/**
- * Read random bytes from the TPM RNG. The implementation deals with the fact
- * that the TPM may legally return fewer bytes than requested by retrying
- * until @p count bytes have been received.
- *
- * @param data output buffer for the random bytes
- * @param count size of output buffer
- * @return return code of the operation
- */
-uint32_t tpm_get_random(void *data, uint32_t count);
-
-#endif /* __TPM_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*****************************************************************************
- * (C) Copyright 2003; Tundra Semiconductor Corp.
- * (C) Copyright 2006; Freescale Semiconductor Corp.
- *****************************************************************************/
-
-/*
- * FILENAME: tsi108.h
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Common definitions for the Tundra Tsi108 bridge chip
- *
- */
-
-#ifndef _TSI108_H_
-#define _TSI108_H_
-
-#define TSI108_HLP_REG_OFFSET (0x0000)
-#define TSI108_PCI_REG_OFFSET (0x1000)
-#define TSI108_CLK_REG_OFFSET (0x2000)
-#define TSI108_PB_REG_OFFSET (0x3000)
-#define TSI108_SD_REG_OFFSET (0x4000)
-#define TSI108_MPIC_REG_OFFSET (0x7400)
-
-#define PB_ID (0x000)
-#define PB_RSR (0x004)
-#define PB_BUS_MS_SELECT (0x008)
-#define PB_ISR (0x00C)
-#define PB_ARB_CTRL (0x018)
-#define PB_PVT_CTRL2 (0x034)
-#define PB_SCR (0x400)
-#define PB_ERRCS (0x404)
-#define PB_AERR (0x408)
-#define PB_REG_BAR (0x410)
-#define PB_OCN_BAR1 (0x414)
-#define PB_OCN_BAR2 (0x418)
-#define PB_SDRAM_BAR1 (0x41C)
-#define PB_SDRAM_BAR2 (0x420)
-#define PB_MCR (0xC00)
-#define PB_MCMD (0xC04)
-
-#define HLP_B0_ADDR (0x000)
-#define HLP_B1_ADDR (0x010)
-#define HLP_B2_ADDR (0x020)
-#define HLP_B3_ADDR (0x030)
-
-#define HLP_B0_MASK (0x004)
-#define HLP_B1_MASK (0x014)
-#define HLP_B2_MASK (0x024)
-#define HLP_B3_MASK (0x034)
-
-#define HLP_B0_CTRL0 (0x008)
-#define HLP_B1_CTRL0 (0x018)
-#define HLP_B2_CTRL0 (0x028)
-#define HLP_B3_CTRL0 (0x038)
-
-#define HLP_B0_CTRL1 (0x00C)
-#define HLP_B1_CTRL1 (0x01C)
-#define HLP_B2_CTRL1 (0x02C)
-#define HLP_B3_CTRL1 (0x03C)
-
-#define PCI_CSR (0x004)
-#define PCI_P2O_BAR0 (0x010)
-#define PCI_P2O_BAR0_UPPER (0x014)
-#define PCI_P2O_BAR2 (0x018)
-#define PCI_P2O_BAR2_UPPER (0x01C)
-#define PCI_P2O_BAR3 (0x020)
-#define PCI_P2O_BAR3_UPPER (0x024)
-
-#define PCI_MISC_CSR (0x040)
-#define PCI_P2O_PAGE_SIZES (0x04C)
-
-#define PCI_PCIX_STAT (0x0F4)
-
-#define PCI_IRP_STAT (0x184)
-
-#define PCI_PFAB_BAR0 (0x204)
-#define PCI_PFAB_BAR0_UPPER (0x208)
-#define PCI_PFAB_IO (0x20C)
-#define PCI_PFAB_IO_UPPER (0x210)
-
-#define PCI_PFAB_MEM32 (0x214)
-#define PCI_PFAB_MEM32_REMAP (0x218)
-#define PCI_PFAB_MEM32_MASK (0x21C)
-
-#define CG_PLL0_CTRL0 (0x210)
-#define CG_PLL0_CTRL1 (0x214)
-#define CG_PLL1_CTRL0 (0x220)
-#define CG_PLL1_CTRL1 (0x224)
-#define CG_PWRUP_STATUS (0x234)
-
-#define MPIC_CSR(n) (0x30C + (n * 0x40))
-
-#define SD_CTRL (0x000)
-#define SD_STATUS (0x004)
-#define SD_TIMING (0x008)
-#define SD_REFRESH (0x00C)
-#define SD_INT_STATUS (0x010)
-#define SD_INT_ENABLE (0x014)
-#define SD_INT_SET (0x018)
-#define SD_D0_CTRL (0x020)
-#define SD_D1_CTRL (0x024)
-#define SD_D0_BAR (0x028)
-#define SD_D1_BAR (0x02C)
-#define SD_ECC_CTRL (0x040)
-#define SD_DLL_STATUS (0x250)
-
-#define TS_SD_CTRL_ENABLE (1 << 31)
-
-#define PB_ERRCS_ES (1 << 1)
-#define PB_ISR_PBS_RD_ERR (1 << 8)
-#define PCI_IRP_STAT_P_CSR (1 << 23)
-
-/*
- * I2C : Register address offset definitions
- */
-#define I2C_CNTRL1 (0x00000000)
-#define I2C_CNTRL2 (0x00000004)
-#define I2C_RD_DATA (0x00000008)
-#define I2C_TX_DATA (0x0000000c)
-
-/*
- * I2C : Register Bit Masks and Reset Values
- * definitions for every register
- */
-
-/* I2C_CNTRL1 : Reset Value */
-#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
-
-/* I2C_CNTRL1 : Register Bits Masks Definitions */
-#define I2C_CNTRL1_DEVCODE (0x0000000f)
-#define I2C_CNTRL1_PAGE (0x00000700)
-#define I2C_CNTRL1_BYTADDR (0x00ff0000)
-#define I2C_CNTRL1_I2CWRITE (0x01000000)
-
-/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
-#define I2C_CNTRL1_RWMASK (0x01ff070f)
-
-/* I2C_CNTRL1 : Unused/Reserved bits Definition */
-#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
-
-/* I2C_CNTRL2 : Reset Value */
-#define I2C_CNTRL2_RESET_VALUE (0x00000000)
-
-/* I2C_CNTRL2 : Register Bits Masks Definitions */
-#define I2C_CNTRL2_SIZE (0x00000003)
-#define I2C_CNTRL2_LANE (0x0000000c)
-#define I2C_CNTRL2_MULTIBYTE (0x00000010)
-#define I2C_CNTRL2_START (0x00000100)
-#define I2C_CNTRL2_WR_STATUS (0x00010000)
-#define I2C_CNTRL2_RD_STATUS (0x00020000)
-#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
-#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
-#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
-
-/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
-#define I2C_CNTRL2_RWMASK (0x0000011f)
-
-/* I2C_CNTRL2 : Unused/Reserved bits Definition */
-#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
-
-/* I2C_RD_DATA : Reset Value */
-#define I2C_RD_DATA_RESET_VALUE (0x00000000)
-
-/* I2C_RD_DATA : Register Bits Masks Definitions */
-#define I2C_RD_DATA_RBYTE0 (0x000000ff)
-#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
-#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
-#define I2C_RD_DATA_RBYTE3 (0xff000000)
-
-/* I2C_RD_DATA : Read/Write Bit Mask Definition */
-#define I2C_RD_DATA_RWMASK (0x00000000)
-
-/* I2C_RD_DATA : Unused/Reserved bits Definition */
-#define I2C_RD_DATA_RESERVED (0x00000000)
-
-/* I2C_TX_DATA : Reset Value */
-#define I2C_TX_DATA_RESET_VALUE (0x00000000)
-
-/* I2C_TX_DATA : Register Bits Masks Definitions */
-#define I2C_TX_DATA_TBYTE0 (0x000000ff)
-#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
-#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
-#define I2C_TX_DATA_TBYTE3 (0xff000000)
-
-/* I2C_TX_DATA : Read/Write Bit Mask Definition */
-#define I2C_TX_DATA_RWMASK (0xffffffff)
-
-/* I2C_TX_DATA : Unused/Reserved bits Definition */
-#define I2C_TX_DATA_RESERVED (0x00000000)
-
-#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
-#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
-
-#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
-
-/* I2C status codes */
-
-#define TSI108_I2C_SUCCESS 0
-#define TSI108_I2C_PARAM_ERR 1
-#define TSI108_I2C_TIMEOUT_ERR 2
-#define TSI108_I2C_IF_BUSY 3
-#define TSI108_I2C_IF_ERROR 4
-
-#endif /* _TSI108_H_ */
obj-y += qsort.o
obj-y += rc4.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
-obj-$(CONFIG_TPM) += tpm.o
+obj-$(CONFIG_TPM) += tpm-common.o
+obj-$(CONFIG_TPM_V1) += tpm-v1.o
+obj-$(CONFIG_TPM_V2) += tpm-v2.o
obj-$(CONFIG_RBTREE) += rbtree.o
obj-$(CONFIG_BITREVERSE) += bitrev.o
obj-y += list_sort.o
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
- depends on (ARM || X86) && OF_LIBFDT
+ depends on (ARM || X86 || RISCV) && OF_LIBFDT
# We do not support bootefi booting ARMv7 in non-secure mode
depends on !ARMV7_NONSEC
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
/* Flush cache */
flush_cache((ulong)efi_reloc,
- ALIGN(virt_size, CONFIG_SYS_CACHELINE_SIZE));
+ ALIGN(virt_size, EFI_CACHELINE_SIZE));
invalidate_icache_all();
/* Populate the loaded image interface bits */
static efi_status_t __efi_runtime EFIAPI efi_device_error(void);
static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
-#else
-/* Just use the greatest cache flush alignment requirement I'm aware of */
-#define EFI_CACHELINE_SIZE 128
-#endif
-
#if defined(CONFIG_ARM64)
#define R_RELATIVE 1027
#define R_MASK 0xffffffffULL
#include <asm/elf.h>
#define R_RELATIVE R_386_RELATIVE
#define R_MASK 0xffULL
+#elif defined(CONFIG_RISCV)
+#include <elf.h>
+#define R_RELATIVE R_RISCV_RELATIVE
+#define R_MASK 0xffULL
+#define IS_RELA 1
+
+struct dyn_sym {
+ ulong foo1;
+ ulong addr;
+ u32 foo2;
+ u32 foo3;
+};
+#ifdef CONFIG_CPU_RISCV_32
+#define R_ABSOLUTE R_RISCV_32
+#define SYM_INDEX 8
+#else
+#define R_ABSOLUTE R_RISCV_64
+#define SYM_INDEX 32
+#endif
#else
#error Need to add relocation awareness
#endif
p = (void*)((ulong)rel->offset - base) + gd->relocaddr;
- if ((rel->info & R_MASK) != R_RELATIVE) {
- continue;
- }
+ debug("%s: rel->info=%#lx *p=%#lx rel->offset=%p\n", __func__, rel->info, *p, rel->offset);
+ switch (rel->info & R_MASK) {
+ case R_RELATIVE:
#ifdef IS_RELA
newaddr = rel->addend + offset - CONFIG_SYS_TEXT_BASE;
#else
newaddr = *p - lastoff + offset;
#endif
+ break;
+#ifdef R_ABSOLUTE
+ case R_ABSOLUTE: {
+ ulong symidx = rel->info >> SYM_INDEX;
+ extern struct dyn_sym __dyn_sym_start[];
+ newaddr = __dyn_sym_start[symidx].addr + offset;
+ break;
+ }
+#endif
+ default:
+ continue;
+ }
/* Check if the relocation is inside bounds */
if (map && ((newaddr < map->virtual_start) ||
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
+ COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/unaligned.h>
+#include <tpm-common.h>
+#include "tpm-utils.h"
+
+int pack_byte_string(u8 *str, size_t size, const char *format, ...)
+{
+ va_list args;
+ size_t offset = 0, length = 0;
+ u8 *data = NULL;
+ u32 value = 0;
+
+ va_start(args, format);
+ for (; *format; format++) {
+ switch (*format) {
+ case 'b':
+ offset = va_arg(args, size_t);
+ value = va_arg(args, int);
+ length = 1;
+ break;
+ case 'w':
+ offset = va_arg(args, size_t);
+ value = va_arg(args, int);
+ length = 2;
+ break;
+ case 'd':
+ offset = va_arg(args, size_t);
+ value = va_arg(args, u32);
+ length = 4;
+ break;
+ case 's':
+ offset = va_arg(args, size_t);
+ data = va_arg(args, u8 *);
+ length = va_arg(args, u32);
+ break;
+ default:
+ debug("Couldn't recognize format string\n");
+ va_end(args);
+ return -1;
+ }
+
+ if (offset + length > size) {
+ va_end(args);
+ return -1;
+ }
+
+ switch (*format) {
+ case 'b':
+ str[offset] = value;
+ break;
+ case 'w':
+ put_unaligned_be16(value, str + offset);
+ break;
+ case 'd':
+ put_unaligned_be32(value, str + offset);
+ break;
+ case 's':
+ memcpy(str + offset, data, length);
+ break;
+ }
+ }
+ va_end(args);
+
+ return 0;
+}
+
+int unpack_byte_string(const u8 *str, size_t size, const char *format, ...)
+{
+ va_list args;
+ size_t offset = 0, length = 0;
+ u8 *ptr8 = NULL;
+ u16 *ptr16 = NULL;
+ u32 *ptr32 = NULL;
+
+ va_start(args, format);
+ for (; *format; format++) {
+ switch (*format) {
+ case 'b':
+ offset = va_arg(args, size_t);
+ ptr8 = va_arg(args, u8 *);
+ length = 1;
+ break;
+ case 'w':
+ offset = va_arg(args, size_t);
+ ptr16 = va_arg(args, u16 *);
+ length = 2;
+ break;
+ case 'd':
+ offset = va_arg(args, size_t);
+ ptr32 = va_arg(args, u32 *);
+ length = 4;
+ break;
+ case 's':
+ offset = va_arg(args, size_t);
+ ptr8 = va_arg(args, u8 *);
+ length = va_arg(args, u32);
+ break;
+ default:
+ va_end(args);
+ debug("Couldn't recognize format string\n");
+ return -1;
+ }
+
+ if (offset + length > size) {
+ va_end(args);
+ return -1;
+ }
+
+ switch (*format) {
+ case 'b':
+ *ptr8 = str[offset];
+ break;
+ case 'w':
+ *ptr16 = get_unaligned_be16(str + offset);
+ break;
+ case 'd':
+ *ptr32 = get_unaligned_be32(str + offset);
+ break;
+ case 's':
+ memcpy(ptr8, str + offset, length);
+ break;
+ }
+ }
+ va_end(args);
+
+ return 0;
+}
+
+u32 tpm_command_size(const void *command)
+{
+ const size_t command_size_offset = 2;
+
+ return get_unaligned_be32(command + command_size_offset);
+}
+
+u32 tpm_return_code(const void *response)
+{
+ const size_t return_code_offset = 6;
+
+ return get_unaligned_be32(response + return_code_offset);
+}
+
+u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr)
+{
+ struct udevice *dev;
+ int err, ret;
+ u8 response_buffer[COMMAND_BUFFER_SIZE];
+ size_t response_length;
+ int i;
+
+ if (response) {
+ response_length = *size_ptr;
+ } else {
+ response = response_buffer;
+ response_length = sizeof(response_buffer);
+ }
+
+ ret = uclass_first_device_err(UCLASS_TPM, &dev);
+ if (ret)
+ return ret;
+ err = tpm_xfer(dev, command, tpm_command_size(command),
+ response, &response_length);
+
+ if (err < 0)
+ return err;
+
+ if (size_ptr)
+ *size_ptr = response_length;
+
+ ret = tpm_return_code(response);
+
+ log(LOGC_NONE, LOGL_DEBUG, "TPM response [ret:%d]: ", ret);
+ for (i = 0; i < response_length; i++)
+ log(LOGC_NONE, LOGL_DEBUG, "%02x ", ((u8 *)response)[i]);
+ log(LOGC_NONE, LOGL_DEBUG, "\n");
+
+ return ret;
+}
+
+int tpm_init(void)
+{
+ struct udevice *dev;
+ int err;
+
+ err = uclass_first_device_err(UCLASS_TPM, &dev);
+ if (err)
+ return err;
+
+ return tpm_open(dev);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_UTILS_H
+#define __TPM_UTILS_H
+
+#define COMMAND_BUFFER_SIZE 256
+
+/* Internal error of TPM command library */
+#define TPM_LIB_ERROR ((u32)~0u)
+
+/* To make strings of commands more easily */
+#define __MSB(x) ((x) >> 8)
+#define __LSB(x) ((x) & 0xFF)
+#define tpm_u16(x) __MSB(x), __LSB(x)
+#define tpm_u32(x) tpm_u16((x) >> 16), tpm_u16((x) & 0xFFFF)
+
+/**
+ * tpm_open() - Request access to locality 0 for the caller
+ *
+ * After all commands have been completed the caller is supposed to
+ * call tpm_close().
+ *
+ * Returns 0 on success, -ve on failure.
+ */
+int tpm_open(struct udevice *dev);
+
+/**
+ * tpm_close() - Close the current session
+ *
+ * Releasing the locked locality. Returns 0 on success, -ve 1 on
+ * failure (in case lock removal did not succeed).
+ */
+int tpm_close(struct udevice *dev);
+
+/**
+ * Pack data into a byte string. The data types are specified in
+ * the format string: 'b' means unsigned byte, 'w' unsigned word,
+ * 'd' unsigned double word, and 's' byte string. The data are a
+ * series of offsets and values (for type byte string there are also
+ * lengths). The data values are packed into the byte string
+ * sequentially, and so a latter value could over-write a former
+ * value.
+ *
+ * @param str output string
+ * @param size size of output string
+ * @param format format string
+ * @param ... data points
+ * @return 0 on success, non-0 on error
+ */
+int pack_byte_string(u8 *str, size_t size, const char *format, ...);
+
+/**
+ * Unpack data from a byte string. The data types are specified in
+ * the format string: 'b' means unsigned byte, 'w' unsigned word,
+ * 'd' unsigned double word, and 's' byte string. The data are a
+ * series of offsets and pointers (for type byte string there are also
+ * lengths).
+ *
+ * @param str output string
+ * @param size size of output string
+ * @param format format string
+ * @param ... data points
+ * @return 0 on success, non-0 on error
+ */
+int unpack_byte_string(const u8 *str, size_t size, const char *format, ...);
+
+/**
+ * Get TPM command size.
+ *
+ * @param command byte string of TPM command
+ * @return command size of the TPM command
+ */
+u32 tpm_command_size(const void *command);
+
+/**
+ * Get TPM response return code, which is one of TPM_RESULT values.
+ *
+ * @param response byte string of TPM response
+ * @return return code of the TPM response
+ */
+u32 tpm_return_code(const void *response);
+
+/**
+ * Send a TPM command and return response's return code, and optionally
+ * return response to caller.
+ *
+ * @param command byte string of TPM command
+ * @param response output buffer for TPM response, or NULL if the
+ * caller does not care about it
+ * @param size_ptr output buffer size (input parameter) and TPM
+ * response length (output parameter); this parameter
+ * is a bidirectional
+ * @return return code of the TPM response
+ */
+u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr);
+
+#endif /* __TPM_UTILS_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/unaligned.h>
+#include <u-boot/sha1.h>
+#include <tpm-common.h>
+#include <tpm-v1.h>
+#include "tpm-utils.h"
+
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+
+#ifndef CONFIG_SHA1
+#error "TPM_AUTH_SESSIONS require SHA1 to be configured, too"
+#endif /* !CONFIG_SHA1 */
+
+struct session_data {
+ int valid;
+ u32 handle;
+ u8 nonce_even[DIGEST_LENGTH];
+ u8 nonce_odd[DIGEST_LENGTH];
+};
+
+static struct session_data oiap_session = {0, };
+
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+
+u32 tpm_startup(enum tpm_startup_type mode)
+{
+ const u8 command[12] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x0,
+ };
+ const size_t mode_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE];
+
+ if (pack_byte_string(buf, sizeof(buf), "sw",
+ 0, command, sizeof(command),
+ mode_offset, mode))
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(buf, NULL, NULL);
+}
+
+u32 tpm_self_test_full(void)
+{
+ const u8 command[10] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50,
+ };
+ return tpm_sendrecv_command(command, NULL, NULL);
+}
+
+u32 tpm_continue_self_test(void)
+{
+ const u8 command[10] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53,
+ };
+ return tpm_sendrecv_command(command, NULL, NULL);
+}
+
+u32 tpm_nv_define_space(u32 index, u32 perm, u32 size)
+{
+ const u8 command[101] = {
+ 0x0, 0xc1, /* TPM_TAG */
+ 0x0, 0x0, 0x0, 0x65, /* parameter size */
+ 0x0, 0x0, 0x0, 0xcc, /* TPM_COMMAND_CODE */
+ /* TPM_NV_DATA_PUBLIC->... */
+ 0x0, 0x18, /* ...->TPM_STRUCTURE_TAG */
+ 0, 0, 0, 0, /* ...->TPM_NV_INDEX */
+ /* TPM_NV_DATA_PUBLIC->TPM_PCR_INFO_SHORT */
+ 0x0, 0x3,
+ 0, 0, 0,
+ 0x1f,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* TPM_NV_DATA_PUBLIC->TPM_PCR_INFO_SHORT */
+ 0x0, 0x3,
+ 0, 0, 0,
+ 0x1f,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* TPM_NV_ATTRIBUTES->... */
+ 0x0, 0x17, /* ...->TPM_STRUCTURE_TAG */
+ 0, 0, 0, 0, /* ...->attributes */
+ /* End of TPM_NV_ATTRIBUTES */
+ 0, /* bReadSTClear */
+ 0, /* bWriteSTClear */
+ 0, /* bWriteDefine */
+ 0, 0, 0, 0, /* size */
+ };
+ const size_t index_offset = 12;
+ const size_t perm_offset = 70;
+ const size_t size_offset = 77;
+ u8 buf[COMMAND_BUFFER_SIZE];
+
+ if (pack_byte_string(buf, sizeof(buf), "sddd",
+ 0, command, sizeof(command),
+ index_offset, index,
+ perm_offset, perm,
+ size_offset, size))
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(buf, NULL, NULL);
+}
+
+u32 tpm_nv_read_value(u32 index, void *data, u32 count)
+{
+ const u8 command[22] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf,
+ };
+ const size_t index_offset = 10;
+ const size_t length_offset = 18;
+ const size_t data_size_offset = 10;
+ const size_t data_offset = 14;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 data_size;
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sdd",
+ 0, command, sizeof(command),
+ index_offset, index,
+ length_offset, count))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ data_size_offset, &data_size))
+ return TPM_LIB_ERROR;
+ if (data_size > count)
+ return TPM_LIB_ERROR;
+ if (unpack_byte_string(response, response_length, "s",
+ data_offset, data, data_size))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_nv_write_value(u32 index, const void *data, u32 length)
+{
+ const u8 command[256] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd,
+ };
+ const size_t command_size_offset = 2;
+ const size_t index_offset = 10;
+ const size_t length_offset = 18;
+ const size_t data_offset = 22;
+ const size_t write_info_size = 12;
+ const u32 total_length =
+ TPM_REQUEST_HEADER_LENGTH + write_info_size + length;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sddds",
+ 0, command, sizeof(command),
+ command_size_offset, total_length,
+ index_offset, index,
+ length_offset, length,
+ data_offset, data, length))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+u32 tpm_extend(u32 index, const void *in_digest, void *out_digest)
+{
+ const u8 command[34] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14,
+ };
+ const size_t index_offset = 10;
+ const size_t in_digest_offset = 14;
+ const size_t out_digest_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE];
+ u8 response[TPM_RESPONSE_HEADER_LENGTH + PCR_DIGEST_LENGTH];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sds",
+ 0, command, sizeof(command),
+ index_offset, index,
+ in_digest_offset, in_digest,
+ PCR_DIGEST_LENGTH))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+
+ if (unpack_byte_string(response, response_length, "s",
+ out_digest_offset, out_digest,
+ PCR_DIGEST_LENGTH))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_pcr_read(u32 index, void *data, size_t count)
+{
+ const u8 command[14] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15,
+ };
+ const size_t index_offset = 10;
+ const size_t out_digest_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (count < PCR_DIGEST_LENGTH)
+ return TPM_LIB_ERROR;
+
+ if (pack_byte_string(buf, sizeof(buf), "sd",
+ 0, command, sizeof(command),
+ index_offset, index))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "s",
+ out_digest_offset, data, PCR_DIGEST_LENGTH))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_tsc_physical_presence(u16 presence)
+{
+ const u8 command[12] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x0,
+ };
+ const size_t presence_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE];
+
+ if (pack_byte_string(buf, sizeof(buf), "sw",
+ 0, command, sizeof(command),
+ presence_offset, presence))
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(buf, NULL, NULL);
+}
+
+u32 tpm_read_pubek(void *data, size_t count)
+{
+ const u8 command[30] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c,
+ };
+ const size_t response_size_offset = 2;
+ const size_t data_offset = 10;
+ const size_t header_and_checksum_size = TPM_RESPONSE_HEADER_LENGTH + 20;
+ u8 response[COMMAND_BUFFER_SIZE + TPM_PUBEK_SIZE];
+ size_t response_length = sizeof(response);
+ u32 data_size;
+ u32 err;
+
+ err = tpm_sendrecv_command(command, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ response_size_offset, &data_size))
+ return TPM_LIB_ERROR;
+ if (data_size < header_and_checksum_size)
+ return TPM_LIB_ERROR;
+ data_size -= header_and_checksum_size;
+ if (data_size > count)
+ return TPM_LIB_ERROR;
+ if (unpack_byte_string(response, response_length, "s",
+ data_offset, data, data_size))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_force_clear(void)
+{
+ const u8 command[10] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d,
+ };
+
+ return tpm_sendrecv_command(command, NULL, NULL);
+}
+
+u32 tpm_physical_enable(void)
+{
+ const u8 command[10] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f,
+ };
+
+ return tpm_sendrecv_command(command, NULL, NULL);
+}
+
+u32 tpm_physical_disable(void)
+{
+ const u8 command[10] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70,
+ };
+
+ return tpm_sendrecv_command(command, NULL, NULL);
+}
+
+u32 tpm_physical_set_deactivated(u8 state)
+{
+ const u8 command[11] = {
+ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72,
+ };
+ const size_t state_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE];
+
+ if (pack_byte_string(buf, sizeof(buf), "sb",
+ 0, command, sizeof(command),
+ state_offset, state))
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(buf, NULL, NULL);
+}
+
+u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count)
+{
+ const u8 command[22] = {
+ 0x0, 0xc1, /* TPM_TAG */
+ 0x0, 0x0, 0x0, 0x16, /* parameter size */
+ 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
+ 0x0, 0x0, 0x0, 0x0, /* TPM_CAPABILITY_AREA */
+ 0x0, 0x0, 0x0, 0x4, /* subcap size */
+ 0x0, 0x0, 0x0, 0x0, /* subcap value */
+ };
+ const size_t cap_area_offset = 10;
+ const size_t sub_cap_offset = 18;
+ const size_t cap_offset = 14;
+ const size_t cap_size_offset = 10;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 cap_size;
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sdd",
+ 0, command, sizeof(command),
+ cap_area_offset, cap_area,
+ sub_cap_offset, sub_cap))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ cap_size_offset, &cap_size))
+ return TPM_LIB_ERROR;
+ if (cap_size > response_length || cap_size > count)
+ return TPM_LIB_ERROR;
+ if (unpack_byte_string(response, response_length, "s",
+ cap_offset, cap, cap_size))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags)
+{
+ const u8 command[22] = {
+ 0x0, 0xc1, /* TPM_TAG */
+ 0x0, 0x0, 0x0, 0x16, /* parameter size */
+ 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
+ 0x0, 0x0, 0x0, 0x4, /* TPM_CAP_FLAG_PERM */
+ 0x0, 0x0, 0x0, 0x4, /* subcap size */
+ 0x0, 0x0, 0x1, 0x8, /* subcap value */
+ };
+ const size_t data_size_offset = TPM_HEADER_SIZE;
+ const size_t data_offset = TPM_HEADER_SIZE + sizeof(u32);
+ u8 response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+ u32 data_size;
+
+ err = tpm_sendrecv_command(command, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ data_size_offset, &data_size))
+ return TPM_LIB_ERROR;
+ if (data_size < sizeof(*pflags))
+ return TPM_LIB_ERROR;
+ if (unpack_byte_string(response, response_length, "s",
+ data_offset, pflags, sizeof(*pflags)))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+u32 tpm_get_permissions(u32 index, u32 *perm)
+{
+ const u8 command[22] = {
+ 0x0, 0xc1, /* TPM_TAG */
+ 0x0, 0x0, 0x0, 0x16, /* parameter size */
+ 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
+ 0x0, 0x0, 0x0, 0x11,
+ 0x0, 0x0, 0x0, 0x4,
+ };
+ const size_t index_offset = 18;
+ const size_t perm_offset = 60;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "d", 0, command, sizeof(command),
+ index_offset, index))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ perm_offset, perm))
+ return TPM_LIB_ERROR;
+
+ return 0;
+}
+
+#ifdef CONFIG_TPM_FLUSH_RESOURCES
+u32 tpm_flush_specific(u32 key_handle, u32 resource_type)
+{
+ const u8 command[18] = {
+ 0x00, 0xc1, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x12, /* parameter size */
+ 0x00, 0x00, 0x00, 0xba, /* TPM_COMMAND_CODE */
+ 0x00, 0x00, 0x00, 0x00, /* key handle */
+ 0x00, 0x00, 0x00, 0x00, /* resource type */
+ };
+ const size_t key_handle_offset = 10;
+ const size_t resource_type_offset = 14;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sdd",
+ 0, command, sizeof(command),
+ key_handle_offset, key_handle,
+ resource_type_offset, resource_type))
+ return TPM_LIB_ERROR;
+
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ return 0;
+}
+#endif /* CONFIG_TPM_FLUSH_RESOURCES */
+
+#ifdef CONFIG_TPM_AUTH_SESSIONS
+
+/**
+ * Fill an authentication block in a request.
+ * This func can create the first as well as the second auth block (for
+ * double authorized commands).
+ *
+ * @param request pointer to the request (w/ uninitialised auth data)
+ * @param request_len0 length of the request without auth data
+ * @param handles_len length of the handles area in request
+ * @param auth_session pointer to the (valid) auth session to be used
+ * @param request_auth pointer to the auth block of the request to be filled
+ * @param auth authentication data (HMAC key)
+ */
+static u32 create_request_auth(const void *request, size_t request_len0,
+ size_t handles_len,
+ struct session_data *auth_session,
+ void *request_auth, const void *auth)
+{
+ u8 hmac_data[DIGEST_LENGTH * 3 + 1];
+ sha1_context hash_ctx;
+ const size_t command_code_offset = 6;
+ const size_t auth_nonce_odd_offset = 4;
+ const size_t auth_continue_offset = 24;
+ const size_t auth_auth_offset = 25;
+
+ if (!auth_session || !auth_session->valid)
+ return TPM_LIB_ERROR;
+
+ sha1_starts(&hash_ctx);
+ sha1_update(&hash_ctx, request + command_code_offset, 4);
+ if (request_len0 > TPM_REQUEST_HEADER_LENGTH + handles_len)
+ sha1_update(&hash_ctx,
+ request + TPM_REQUEST_HEADER_LENGTH + handles_len,
+ request_len0 - TPM_REQUEST_HEADER_LENGTH
+ - handles_len);
+ sha1_finish(&hash_ctx, hmac_data);
+
+ sha1_starts(&hash_ctx);
+ sha1_update(&hash_ctx, auth_session->nonce_odd, DIGEST_LENGTH);
+ sha1_update(&hash_ctx, hmac_data, sizeof(hmac_data));
+ sha1_finish(&hash_ctx, auth_session->nonce_odd);
+
+ if (pack_byte_string(request_auth, TPM_REQUEST_AUTH_LENGTH, "dsb",
+ 0, auth_session->handle,
+ auth_nonce_odd_offset, auth_session->nonce_odd,
+ DIGEST_LENGTH,
+ auth_continue_offset, 1))
+ return TPM_LIB_ERROR;
+ if (pack_byte_string(hmac_data, sizeof(hmac_data), "ss",
+ DIGEST_LENGTH,
+ auth_session->nonce_even,
+ DIGEST_LENGTH,
+ 2 * DIGEST_LENGTH,
+ request_auth + auth_nonce_odd_offset,
+ DIGEST_LENGTH + 1))
+ return TPM_LIB_ERROR;
+ sha1_hmac(auth, DIGEST_LENGTH, hmac_data, sizeof(hmac_data),
+ request_auth + auth_auth_offset);
+
+ return TPM_SUCCESS;
+}
+
+/**
+ * Verify an authentication block in a response.
+ * Since this func updates the nonce_even in the session data it has to be
+ * called when receiving a succesfull AUTH response.
+ * This func can verify the first as well as the second auth block (for
+ * double authorized commands).
+ *
+ * @param command_code command code of the request
+ * @param response pointer to the request (w/ uninitialised auth data)
+ * @param handles_len length of the handles area in response
+ * @param auth_session pointer to the (valid) auth session to be used
+ * @param response_auth pointer to the auth block of the response to be verified
+ * @param auth authentication data (HMAC key)
+ */
+static u32 verify_response_auth(u32 command_code, const void *response,
+ size_t response_len0, size_t handles_len,
+ struct session_data *auth_session,
+ const void *response_auth, const void *auth)
+{
+ u8 hmac_data[DIGEST_LENGTH * 3 + 1];
+ u8 computed_auth[DIGEST_LENGTH];
+ sha1_context hash_ctx;
+ const size_t return_code_offset = 6;
+ const size_t auth_continue_offset = 20;
+ const size_t auth_auth_offset = 21;
+ u8 auth_continue;
+
+ if (!auth_session || !auth_session->valid)
+ return TPM_AUTHFAIL;
+ if (pack_byte_string(hmac_data, sizeof(hmac_data), "d",
+ 0, command_code))
+ return TPM_LIB_ERROR;
+ if (response_len0 < TPM_RESPONSE_HEADER_LENGTH)
+ return TPM_LIB_ERROR;
+
+ sha1_starts(&hash_ctx);
+ sha1_update(&hash_ctx, response + return_code_offset, 4);
+ sha1_update(&hash_ctx, hmac_data, 4);
+ if (response_len0 > TPM_RESPONSE_HEADER_LENGTH + handles_len)
+ sha1_update(&hash_ctx,
+ response + TPM_RESPONSE_HEADER_LENGTH + handles_len,
+ response_len0 - TPM_RESPONSE_HEADER_LENGTH
+ - handles_len);
+ sha1_finish(&hash_ctx, hmac_data);
+
+ memcpy(auth_session->nonce_even, response_auth, DIGEST_LENGTH);
+ auth_continue = ((u8 *)response_auth)[auth_continue_offset];
+ if (pack_byte_string(hmac_data, sizeof(hmac_data), "ssb",
+ DIGEST_LENGTH,
+ response_auth,
+ DIGEST_LENGTH,
+ 2 * DIGEST_LENGTH,
+ auth_session->nonce_odd,
+ DIGEST_LENGTH,
+ 3 * DIGEST_LENGTH,
+ auth_continue))
+ return TPM_LIB_ERROR;
+
+ sha1_hmac(auth, DIGEST_LENGTH, hmac_data, sizeof(hmac_data),
+ computed_auth);
+
+ if (memcmp(computed_auth, response_auth + auth_auth_offset,
+ DIGEST_LENGTH))
+ return TPM_AUTHFAIL;
+
+ return TPM_SUCCESS;
+}
+
+u32 tpm_terminate_auth_session(u32 auth_handle)
+{
+ const u8 command[18] = {
+ 0x00, 0xc1, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x00, /* parameter size */
+ 0x00, 0x00, 0x00, 0xba, /* TPM_COMMAND_CODE */
+ 0x00, 0x00, 0x00, 0x00, /* TPM_HANDLE */
+ 0x00, 0x00, 0x00, 0x02, /* TPM_RESOURCE_TYPE */
+ };
+ const size_t req_handle_offset = TPM_REQUEST_HEADER_LENGTH;
+ u8 request[COMMAND_BUFFER_SIZE];
+
+ if (pack_byte_string(request, sizeof(request), "sd",
+ 0, command, sizeof(command),
+ req_handle_offset, auth_handle))
+ return TPM_LIB_ERROR;
+ if (oiap_session.valid && oiap_session.handle == auth_handle)
+ oiap_session.valid = 0;
+
+ return tpm_sendrecv_command(request, NULL, NULL);
+}
+
+u32 tpm_end_oiap(void)
+{
+ u32 err = TPM_SUCCESS;
+
+ if (oiap_session.valid)
+ err = tpm_terminate_auth_session(oiap_session.handle);
+ return err;
+}
+
+u32 tpm_oiap(u32 *auth_handle)
+{
+ const u8 command[10] = {
+ 0x00, 0xc1, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x0a, /* parameter size */
+ 0x00, 0x00, 0x00, 0x0a, /* TPM_COMMAND_CODE */
+ };
+ const size_t res_auth_handle_offset = TPM_RESPONSE_HEADER_LENGTH;
+ const size_t res_nonce_even_offset = TPM_RESPONSE_HEADER_LENGTH + 4;
+ u8 response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (oiap_session.valid)
+ tpm_terminate_auth_session(oiap_session.handle);
+
+ err = tpm_sendrecv_command(command, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "ds",
+ res_auth_handle_offset, &oiap_session.handle,
+ res_nonce_even_offset, &oiap_session.nonce_even,
+ (u32)DIGEST_LENGTH))
+ return TPM_LIB_ERROR;
+ oiap_session.valid = 1;
+ if (auth_handle)
+ *auth_handle = oiap_session.handle;
+ return 0;
+}
+
+u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length,
+ const void *parent_key_usage_auth, u32 *key_handle)
+{
+ const u8 command[14] = {
+ 0x00, 0xc2, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x00, /* parameter size */
+ 0x00, 0x00, 0x00, 0x41, /* TPM_COMMAND_CODE */
+ 0x00, 0x00, 0x00, 0x00, /* parent handle */
+ };
+ const size_t req_size_offset = 2;
+ const size_t req_parent_handle_offset = TPM_REQUEST_HEADER_LENGTH;
+ const size_t req_key_offset = TPM_REQUEST_HEADER_LENGTH + 4;
+ const size_t res_handle_offset = TPM_RESPONSE_HEADER_LENGTH;
+ u8 request[sizeof(command) + TPM_KEY12_MAX_LENGTH +
+ TPM_REQUEST_AUTH_LENGTH];
+ u8 response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (!oiap_session.valid) {
+ err = tpm_oiap(NULL);
+ if (err)
+ return err;
+ }
+ if (pack_byte_string(request, sizeof(request), "sdds",
+ 0, command, sizeof(command),
+ req_size_offset,
+ sizeof(command) + key_length
+ + TPM_REQUEST_AUTH_LENGTH,
+ req_parent_handle_offset, parent_handle,
+ req_key_offset, key, key_length
+ ))
+ return TPM_LIB_ERROR;
+
+ err = create_request_auth(request, sizeof(command) + key_length, 4,
+ &oiap_session,
+ request + sizeof(command) + key_length,
+ parent_key_usage_auth);
+ if (err)
+ return err;
+ err = tpm_sendrecv_command(request, response, &response_length);
+ if (err) {
+ if (err == TPM_AUTHFAIL)
+ oiap_session.valid = 0;
+ return err;
+ }
+
+ err = verify_response_auth(0x00000041, response,
+ response_length - TPM_RESPONSE_AUTH_LENGTH,
+ 4, &oiap_session,
+ response + response_length -
+ TPM_RESPONSE_AUTH_LENGTH,
+ parent_key_usage_auth);
+ if (err)
+ return err;
+
+ if (key_handle) {
+ if (unpack_byte_string(response, response_length, "d",
+ res_handle_offset, key_handle))
+ return TPM_LIB_ERROR;
+ }
+
+ return 0;
+}
+
+u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey,
+ size_t *pubkey_len)
+{
+ const u8 command[14] = {
+ 0x00, 0xc2, /* TPM_TAG */
+ 0x00, 0x00, 0x00, 0x00, /* parameter size */
+ 0x00, 0x00, 0x00, 0x21, /* TPM_COMMAND_CODE */
+ 0x00, 0x00, 0x00, 0x00, /* key handle */
+ };
+ const size_t req_size_offset = 2;
+ const size_t req_key_handle_offset = TPM_REQUEST_HEADER_LENGTH;
+ const size_t res_pubkey_offset = TPM_RESPONSE_HEADER_LENGTH;
+ u8 request[sizeof(command) + TPM_REQUEST_AUTH_LENGTH];
+ u8 response[TPM_RESPONSE_HEADER_LENGTH + TPM_PUBKEY_MAX_LENGTH +
+ TPM_RESPONSE_AUTH_LENGTH];
+ size_t response_length = sizeof(response);
+ u32 err;
+
+ if (!oiap_session.valid) {
+ err = tpm_oiap(NULL);
+ if (err)
+ return err;
+ }
+ if (pack_byte_string(request, sizeof(request), "sdd",
+ 0, command, sizeof(command),
+ req_size_offset,
+ (u32)(sizeof(command)
+ + TPM_REQUEST_AUTH_LENGTH),
+ req_key_handle_offset, key_handle
+ ))
+ return TPM_LIB_ERROR;
+ err = create_request_auth(request, sizeof(command), 4, &oiap_session,
+ request + sizeof(command), usage_auth);
+ if (err)
+ return err;
+ err = tpm_sendrecv_command(request, response, &response_length);
+ if (err) {
+ if (err == TPM_AUTHFAIL)
+ oiap_session.valid = 0;
+ return err;
+ }
+ err = verify_response_auth(0x00000021, response,
+ response_length - TPM_RESPONSE_AUTH_LENGTH,
+ 0, &oiap_session,
+ response + response_length -
+ TPM_RESPONSE_AUTH_LENGTH,
+ usage_auth);
+ if (err)
+ return err;
+
+ if (pubkey) {
+ if ((response_length - TPM_RESPONSE_HEADER_LENGTH
+ - TPM_RESPONSE_AUTH_LENGTH) > *pubkey_len)
+ return TPM_LIB_ERROR;
+ *pubkey_len = response_length - TPM_RESPONSE_HEADER_LENGTH
+ - TPM_RESPONSE_AUTH_LENGTH;
+ memcpy(pubkey, response + res_pubkey_offset,
+ response_length - TPM_RESPONSE_HEADER_LENGTH
+ - TPM_RESPONSE_AUTH_LENGTH);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20],
+ u32 *handle)
+{
+ u16 key_count;
+ u32 key_handles[10];
+ u8 buf[288];
+ u8 *ptr;
+ u32 err;
+ u8 digest[20];
+ size_t buf_len;
+ unsigned int i;
+
+ /* fetch list of already loaded keys in the TPM */
+ err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+ if (err)
+ return -1;
+ key_count = get_unaligned_be16(buf);
+ ptr = buf + 2;
+ for (i = 0; i < key_count; ++i, ptr += 4)
+ key_handles[i] = get_unaligned_be32(ptr);
+
+ /* now search a(/ the) key which we can access with the given auth */
+ for (i = 0; i < key_count; ++i) {
+ buf_len = sizeof(buf);
+ err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+ if (err && err != TPM_AUTHFAIL)
+ return -1;
+ if (err)
+ continue;
+ sha1_csum(buf, buf_len, digest);
+ if (!memcmp(digest, pubkey_digest, 20)) {
+ *handle = key_handles[i];
+ return 0;
+ }
+ }
+ return 1;
+}
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
+#endif /* CONFIG_TPM_AUTH_SESSIONS */
+
+u32 tpm_get_random(void *data, u32 count)
+{
+ const u8 command[14] = {
+ 0x0, 0xc1, /* TPM_TAG */
+ 0x0, 0x0, 0x0, 0xe, /* parameter size */
+ 0x0, 0x0, 0x0, 0x46, /* TPM_COMMAND_CODE */
+ };
+ const size_t length_offset = 10;
+ const size_t data_size_offset = 10;
+ const size_t data_offset = 14;
+ u8 buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
+ size_t response_length = sizeof(response);
+ u32 data_size;
+ u8 *out = data;
+
+ while (count > 0) {
+ u32 this_bytes = min((size_t)count,
+ sizeof(response) - data_offset);
+ u32 err;
+
+ if (pack_byte_string(buf, sizeof(buf), "sd",
+ 0, command, sizeof(command),
+ length_offset, this_bytes))
+ return TPM_LIB_ERROR;
+ err = tpm_sendrecv_command(buf, response, &response_length);
+ if (err)
+ return err;
+ if (unpack_byte_string(response, response_length, "d",
+ data_size_offset, &data_size))
+ return TPM_LIB_ERROR;
+ if (data_size > count)
+ return TPM_LIB_ERROR;
+ if (unpack_byte_string(response, response_length, "s",
+ data_offset, out, data_size))
+ return TPM_LIB_ERROR;
+
+ count -= data_size;
+ out += data_size;
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Bootlin
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <tpm-common.h>
+#include <tpm-v2.h>
+#include "tpm-utils.h"
+
+u32 tpm2_startup(enum tpm2_startup_types mode)
+{
+ const u8 command_v2[12] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS),
+ tpm_u32(12),
+ tpm_u32(TPM2_CC_STARTUP),
+ tpm_u16(mode),
+ };
+ int ret;
+
+ /*
+ * Note TPM2_Startup command will return RC_SUCCESS the first time,
+ * but will return RC_INITIALIZE otherwise.
+ */
+ ret = tpm_sendrecv_command(command_v2, NULL, NULL);
+ if (ret && ret != TPM2_RC_INITIALIZE)
+ return ret;
+
+ return 0;
+}
+
+u32 tpm2_self_test(enum tpm2_yes_no full_test)
+{
+ const u8 command_v2[12] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS),
+ tpm_u32(11),
+ tpm_u32(TPM2_CC_SELF_TEST),
+ full_test,
+ };
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_clear(u32 handle, const char *pw, const ssize_t pw_sz)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(27 + pw_sz), /* Length */
+ tpm_u32(TPM2_CC_CLEAR), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(handle), /* TPM resource handle */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + pw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* Session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(pw_sz), /* Size of <hmac/password> */
+ /* STRING(pw) <hmac/password> (if any) */
+ };
+ unsigned int offset = 27;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the password (if any)
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "s",
+ offset, pw, pw_sz);
+ offset += pw_sz;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_pcr_extend(u32 index, const uint8_t *digest)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(33 + TPM2_DIGEST_LEN), /* Length */
+ tpm_u32(TPM2_CC_PCR_EXTEND), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(index), /* Handle (PCR Index) */
+
+ /* AUTH_SESSION */
+ tpm_u32(9), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* Session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(0), /* Size of <hmac/password> */
+ /* <hmac/password> (if any) */
+ tpm_u32(1), /* Count (number of hashes) */
+ tpm_u16(TPM2_ALG_SHA256), /* Algorithm of the hash */
+ /* STRING(digest) Digest */
+ };
+ unsigned int offset = 33;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the digest
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "s",
+ offset, digest, TPM2_DIGEST_LEN);
+ offset += TPM2_DIGEST_LEN;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data,
+ unsigned int *updates)
+{
+ u8 idx_array_sz = max(idx_min_sz, DIV_ROUND_UP(idx, 8));
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(17 + idx_array_sz), /* Length */
+ tpm_u32(TPM2_CC_PCR_READ), /* Command code */
+
+ /* TPML_PCR_SELECTION */
+ tpm_u32(1), /* Number of selections */
+ tpm_u16(TPM2_ALG_SHA256), /* Algorithm of the hash */
+ idx_array_sz, /* Array size for selection */
+ /* bitmap(idx) Selected PCR bitmap */
+ };
+ size_t response_len = COMMAND_BUFFER_SIZE;
+ u8 response[COMMAND_BUFFER_SIZE];
+ unsigned int pcr_sel_idx = idx / 8;
+ u8 pcr_sel_bit = BIT(idx % 8);
+ unsigned int counter = 0;
+ int ret;
+
+ if (pack_byte_string(command_v2, COMMAND_BUFFER_SIZE, "b",
+ 17 + pcr_sel_idx, pcr_sel_bit))
+ return TPM_LIB_ERROR;
+
+ ret = tpm_sendrecv_command(command_v2, response, &response_len);
+ if (ret)
+ return ret;
+
+ if (unpack_byte_string(response, response_len, "ds",
+ 10, &counter,
+ response_len - TPM2_DIGEST_LEN, data,
+ TPM2_DIGEST_LEN))
+ return TPM_LIB_ERROR;
+
+ if (updates)
+ *updates = counter;
+
+ return 0;
+}
+
+u32 tpm2_get_capability(u32 capability, u32 property, void *buf,
+ size_t prop_count)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */
+ tpm_u32(22), /* Length */
+ tpm_u32(TPM2_CC_GET_CAPABILITY), /* Command code */
+
+ tpm_u32(capability), /* Capability */
+ tpm_u32(property), /* Property */
+ tpm_u32(prop_count), /* Property count */
+ };
+ u8 response[COMMAND_BUFFER_SIZE];
+ size_t response_len = COMMAND_BUFFER_SIZE;
+ unsigned int properties_off;
+ int ret;
+
+ ret = tpm_sendrecv_command(command_v2, response, &response_len);
+ if (ret)
+ return ret;
+
+ /*
+ * In the response buffer, the properties are located after the:
+ * tag (u16), response size (u32), response code (u32),
+ * YES/NO flag (u8), TPM_CAP (u32) and TPMU_CAPABILITIES (u32).
+ */
+ properties_off = sizeof(u16) + sizeof(u32) + sizeof(u32) +
+ sizeof(u8) + sizeof(u32) + sizeof(u32);
+ memcpy(buf, &response[properties_off], response_len - properties_off);
+
+ return 0;
+}
+
+u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(27 + pw_sz), /* Length */
+ tpm_u32(TPM2_CC_DAM_RESET), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(TPM2_RH_LOCKOUT), /* TPM resource handle */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + pw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* Session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(pw_sz), /* Size of <hmac/password> */
+ /* STRING(pw) <hmac/password> (if any) */
+ };
+ unsigned int offset = 27;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the password (if any)
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "s",
+ offset, pw, pw_sz);
+ offset += pw_sz;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz,
+ unsigned int max_tries, unsigned int recovery_time,
+ unsigned int lockout_recovery)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(27 + pw_sz + 12), /* Length */
+ tpm_u32(TPM2_CC_DAM_PARAMETERS), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(TPM2_RH_LOCKOUT), /* TPM resource handle */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + pw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* Session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(pw_sz), /* Size of <hmac/password> */
+ /* STRING(pw) <hmac/password> (if any) */
+
+ /* LOCKOUT PARAMETERS */
+ /* tpm_u32(max_tries) Max tries (0, always lock) */
+ /* tpm_u32(recovery_time) Recovery time (0, no lock) */
+ /* tpm_u32(lockout_recovery) Lockout recovery */
+ };
+ unsigned int offset = 27;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the password (if any)
+ * - max tries
+ * - recovery time
+ * - lockout recovery
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "sddd",
+ offset, pw, pw_sz,
+ offset + pw_sz, max_tries,
+ offset + pw_sz + 4, recovery_time,
+ offset + pw_sz + 8, lockout_recovery);
+ offset += pw_sz + 12;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz,
+ const char *oldpw, const ssize_t oldpw_sz)
+{
+ unsigned int offset = 27;
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(offset + oldpw_sz + 2 + newpw_sz), /* Length */
+ tpm_u32(TPM2_CC_HIERCHANGEAUTH), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(handle), /* TPM resource handle */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + oldpw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* Session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(oldpw_sz) /* Size of <hmac/password> */
+ /* STRING(oldpw) <hmac/password> (if any) */
+
+ /* TPM2B_AUTH (TPM2B_DIGEST) */
+ /* tpm_u16(newpw_sz) Digest size, new pw length */
+ /* STRING(newpw) Digest buffer, new pw */
+ };
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the old password (if any)
+ * - size of the new password
+ * - new password
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "sws",
+ offset, oldpw, oldpw_sz,
+ offset + oldpw_sz, newpw_sz,
+ offset + oldpw_sz + 2, newpw, newpw_sz);
+ offset += oldpw_sz + 2 + newpw_sz;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index,
+ const char *key)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(35 + pw_sz + TPM2_DIGEST_LEN), /* Length */
+ tpm_u32(TPM2_CC_PCR_SETAUTHPOL), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(TPM2_RH_PLATFORM), /* TPM resource handle */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + pw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(pw_sz) /* Size of <hmac/password> */
+ /* STRING(pw) <hmac/password> (if any) */
+
+ /* TPM2B_AUTH (TPM2B_DIGEST) */
+ /* tpm_u16(TPM2_DIGEST_LEN) Digest size length */
+ /* STRING(key) Digest buffer (PCR key) */
+
+ /* TPMI_ALG_HASH */
+ /* tpm_u16(TPM2_ALG_SHA256) Algorithm of the hash */
+
+ /* TPMI_DH_PCR */
+ /* tpm_u32(index), PCR Index */
+ };
+ unsigned int offset = 27;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the password (if any)
+ * - the PCR key length
+ * - the PCR key
+ * - the hash algorithm
+ * - the PCR index
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "swswd",
+ offset, pw, pw_sz,
+ offset + pw_sz, TPM2_DIGEST_LEN,
+ offset + pw_sz + 2, key, TPM2_DIGEST_LEN,
+ offset + pw_sz + 2 + TPM2_DIGEST_LEN,
+ TPM2_ALG_SHA256,
+ offset + pw_sz + 4 + TPM2_DIGEST_LEN, index);
+ offset += pw_sz + 2 + TPM2_DIGEST_LEN + 2 + 4;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+
+u32 tpm2_pcr_setauthvalue(const char *pw, const ssize_t pw_sz, u32 index,
+ const char *key, const ssize_t key_sz)
+{
+ u8 command_v2[COMMAND_BUFFER_SIZE] = {
+ tpm_u16(TPM2_ST_SESSIONS), /* TAG */
+ tpm_u32(33 + pw_sz + TPM2_DIGEST_LEN), /* Length */
+ tpm_u32(TPM2_CC_PCR_SETAUTHVAL), /* Command code */
+
+ /* HANDLE */
+ tpm_u32(index), /* Handle (PCR Index) */
+
+ /* AUTH_SESSION */
+ tpm_u32(9 + pw_sz), /* Authorization size */
+ tpm_u32(TPM2_RS_PW), /* session handle */
+ tpm_u16(0), /* Size of <nonce> */
+ /* <nonce> (if any) */
+ 0, /* Attributes: Cont/Excl/Rst */
+ tpm_u16(pw_sz), /* Size of <hmac/password> */
+ /* STRING(pw) <hmac/password> (if any) */
+
+ /* TPM2B_DIGEST */
+ /* tpm_u16(key_sz) Key length */
+ /* STRING(key) Key */
+ };
+ unsigned int offset = 27;
+ int ret;
+
+ /*
+ * Fill the command structure starting from the first buffer:
+ * - the password (if any)
+ * - the number of digests, 1 in our case
+ * - the algorithm, sha256 in our case
+ * - the digest (64 bytes)
+ */
+ ret = pack_byte_string(command_v2, sizeof(command_v2), "sws",
+ offset, pw, pw_sz,
+ offset + pw_sz, key_sz,
+ offset + pw_sz + 2, key, key_sz);
+ offset += pw_sz + 2 + key_sz;
+ if (ret)
+ return TPM_LIB_ERROR;
+
+ return tpm_sendrecv_command(command_v2, NULL, NULL);
+}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2013 The Chromium OS Authors.
- * Coypright (c) 2013 Guntermann & Drunck GmbH
- */
-
-#include <common.h>
-#include <dm.h>
-#include <tpm.h>
-#include <asm/unaligned.h>
-#include <u-boot/sha1.h>
-
-/* Internal error of TPM command library */
-#define TPM_LIB_ERROR ((uint32_t)~0u)
-
-/* Useful constants */
-enum {
- COMMAND_BUFFER_SIZE = 256,
- TPM_REQUEST_HEADER_LENGTH = 10,
- TPM_RESPONSE_HEADER_LENGTH = 10,
- PCR_DIGEST_LENGTH = 20,
- DIGEST_LENGTH = 20,
- TPM_REQUEST_AUTH_LENGTH = 45,
- TPM_RESPONSE_AUTH_LENGTH = 41,
- /* some max lengths, valid for RSA keys <= 2048 bits */
- TPM_KEY12_MAX_LENGTH = 618,
- TPM_PUBKEY_MAX_LENGTH = 288,
-};
-
-#ifdef CONFIG_TPM_AUTH_SESSIONS
-
-#ifndef CONFIG_SHA1
-#error "TPM_AUTH_SESSIONS require SHA1 to be configured, too"
-#endif /* !CONFIG_SHA1 */
-
-struct session_data {
- int valid;
- uint32_t handle;
- uint8_t nonce_even[DIGEST_LENGTH];
- uint8_t nonce_odd[DIGEST_LENGTH];
-};
-
-static struct session_data oiap_session = {0, };
-
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-
-/**
- * Pack data into a byte string. The data types are specified in
- * the format string: 'b' means unsigned byte, 'w' unsigned word,
- * 'd' unsigned double word, and 's' byte string. The data are a
- * series of offsets and values (for type byte string there are also
- * lengths). The data values are packed into the byte string
- * sequentially, and so a latter value could over-write a former
- * value.
- *
- * @param str output string
- * @param size size of output string
- * @param format format string
- * @param ... data points
- * @return 0 on success, non-0 on error
- */
-int pack_byte_string(uint8_t *str, size_t size, const char *format, ...)
-{
- va_list args;
- size_t offset = 0, length = 0;
- uint8_t *data = NULL;
- uint32_t value = 0;
-
- va_start(args, format);
- for (; *format; format++) {
- switch (*format) {
- case 'b':
- offset = va_arg(args, size_t);
- value = va_arg(args, int);
- length = 1;
- break;
- case 'w':
- offset = va_arg(args, size_t);
- value = va_arg(args, int);
- length = 2;
- break;
- case 'd':
- offset = va_arg(args, size_t);
- value = va_arg(args, uint32_t);
- length = 4;
- break;
- case 's':
- offset = va_arg(args, size_t);
- data = va_arg(args, uint8_t *);
- length = va_arg(args, uint32_t);
- break;
- default:
- debug("Couldn't recognize format string\n");
- va_end(args);
- return -1;
- }
-
- if (offset + length > size) {
- va_end(args);
- return -1;
- }
-
- switch (*format) {
- case 'b':
- str[offset] = value;
- break;
- case 'w':
- put_unaligned_be16(value, str + offset);
- break;
- case 'd':
- put_unaligned_be32(value, str + offset);
- break;
- case 's':
- memcpy(str + offset, data, length);
- break;
- }
- }
- va_end(args);
-
- return 0;
-}
-
-/**
- * Unpack data from a byte string. The data types are specified in
- * the format string: 'b' means unsigned byte, 'w' unsigned word,
- * 'd' unsigned double word, and 's' byte string. The data are a
- * series of offsets and pointers (for type byte string there are also
- * lengths).
- *
- * @param str output string
- * @param size size of output string
- * @param format format string
- * @param ... data points
- * @return 0 on success, non-0 on error
- */
-int unpack_byte_string(const uint8_t *str, size_t size, const char *format, ...)
-{
- va_list args;
- size_t offset = 0, length = 0;
- uint8_t *ptr8 = NULL;
- uint16_t *ptr16 = NULL;
- uint32_t *ptr32 = NULL;
-
- va_start(args, format);
- for (; *format; format++) {
- switch (*format) {
- case 'b':
- offset = va_arg(args, size_t);
- ptr8 = va_arg(args, uint8_t *);
- length = 1;
- break;
- case 'w':
- offset = va_arg(args, size_t);
- ptr16 = va_arg(args, uint16_t *);
- length = 2;
- break;
- case 'd':
- offset = va_arg(args, size_t);
- ptr32 = va_arg(args, uint32_t *);
- length = 4;
- break;
- case 's':
- offset = va_arg(args, size_t);
- ptr8 = va_arg(args, uint8_t *);
- length = va_arg(args, uint32_t);
- break;
- default:
- va_end(args);
- debug("Couldn't recognize format string\n");
- return -1;
- }
-
- if (offset + length > size) {
- va_end(args);
- return -1;
- }
-
- switch (*format) {
- case 'b':
- *ptr8 = str[offset];
- break;
- case 'w':
- *ptr16 = get_unaligned_be16(str + offset);
- break;
- case 'd':
- *ptr32 = get_unaligned_be32(str + offset);
- break;
- case 's':
- memcpy(ptr8, str + offset, length);
- break;
- }
- }
- va_end(args);
-
- return 0;
-}
-
-/**
- * Get TPM command size.
- *
- * @param command byte string of TPM command
- * @return command size of the TPM command
- */
-static uint32_t tpm_command_size(const void *command)
-{
- const size_t command_size_offset = 2;
- return get_unaligned_be32(command + command_size_offset);
-}
-
-/**
- * Get TPM response return code, which is one of TPM_RESULT values.
- *
- * @param response byte string of TPM response
- * @return return code of the TPM response
- */
-static uint32_t tpm_return_code(const void *response)
-{
- const size_t return_code_offset = 6;
- return get_unaligned_be32(response + return_code_offset);
-}
-
-/**
- * Send a TPM command and return response's return code, and optionally
- * return response to caller.
- *
- * @param command byte string of TPM command
- * @param response output buffer for TPM response, or NULL if the
- * caller does not care about it
- * @param size_ptr output buffer size (input parameter) and TPM
- * response length (output parameter); this parameter
- * is a bidirectional
- * @return return code of the TPM response
- */
-static uint32_t tpm_sendrecv_command(const void *command,
- void *response, size_t *size_ptr)
-{
- struct udevice *dev;
- int err, ret;
- uint8_t response_buffer[COMMAND_BUFFER_SIZE];
- size_t response_length;
-
- if (response) {
- response_length = *size_ptr;
- } else {
- response = response_buffer;
- response_length = sizeof(response_buffer);
- }
-
- ret = uclass_first_device_err(UCLASS_TPM, &dev);
- if (ret)
- return ret;
- err = tpm_xfer(dev, command, tpm_command_size(command),
- response, &response_length);
-
- if (err < 0)
- return TPM_LIB_ERROR;
- if (size_ptr)
- *size_ptr = response_length;
-
- return tpm_return_code(response);
-}
-
-int tpm_init(void)
-{
- int err;
- struct udevice *dev;
-
- err = uclass_first_device_err(UCLASS_TPM, &dev);
- if (err)
- return err;
- return tpm_open(dev);
-}
-
-uint32_t tpm_startup(enum tpm_startup_type mode)
-{
- const uint8_t command[12] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x0,
- };
- const size_t mode_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE];
-
- if (pack_byte_string(buf, sizeof(buf), "sw",
- 0, command, sizeof(command),
- mode_offset, mode))
- return TPM_LIB_ERROR;
-
- return tpm_sendrecv_command(buf, NULL, NULL);
-}
-
-uint32_t tpm_self_test_full(void)
-{
- const uint8_t command[10] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50,
- };
- return tpm_sendrecv_command(command, NULL, NULL);
-}
-
-uint32_t tpm_continue_self_test(void)
-{
- const uint8_t command[10] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53,
- };
- return tpm_sendrecv_command(command, NULL, NULL);
-}
-
-uint32_t tpm_nv_define_space(uint32_t index, uint32_t perm, uint32_t size)
-{
- const uint8_t command[101] = {
- 0x0, 0xc1, /* TPM_TAG */
- 0x0, 0x0, 0x0, 0x65, /* parameter size */
- 0x0, 0x0, 0x0, 0xcc, /* TPM_COMMAND_CODE */
- /* TPM_NV_DATA_PUBLIC->... */
- 0x0, 0x18, /* ...->TPM_STRUCTURE_TAG */
- 0, 0, 0, 0, /* ...->TPM_NV_INDEX */
- /* TPM_NV_DATA_PUBLIC->TPM_PCR_INFO_SHORT */
- 0x0, 0x3,
- 0, 0, 0,
- 0x1f,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* TPM_NV_DATA_PUBLIC->TPM_PCR_INFO_SHORT */
- 0x0, 0x3,
- 0, 0, 0,
- 0x1f,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* TPM_NV_ATTRIBUTES->... */
- 0x0, 0x17, /* ...->TPM_STRUCTURE_TAG */
- 0, 0, 0, 0, /* ...->attributes */
- /* End of TPM_NV_ATTRIBUTES */
- 0, /* bReadSTClear */
- 0, /* bWriteSTClear */
- 0, /* bWriteDefine */
- 0, 0, 0, 0, /* size */
- };
- const size_t index_offset = 12;
- const size_t perm_offset = 70;
- const size_t size_offset = 77;
- uint8_t buf[COMMAND_BUFFER_SIZE];
-
- if (pack_byte_string(buf, sizeof(buf), "sddd",
- 0, command, sizeof(command),
- index_offset, index,
- perm_offset, perm,
- size_offset, size))
- return TPM_LIB_ERROR;
-
- return tpm_sendrecv_command(buf, NULL, NULL);
-}
-
-uint32_t tpm_nv_read_value(uint32_t index, void *data, uint32_t count)
-{
- const uint8_t command[22] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf,
- };
- const size_t index_offset = 10;
- const size_t length_offset = 18;
- const size_t data_size_offset = 10;
- const size_t data_offset = 14;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t data_size;
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sdd",
- 0, command, sizeof(command),
- index_offset, index,
- length_offset, count))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- data_size_offset, &data_size))
- return TPM_LIB_ERROR;
- if (data_size > count)
- return TPM_LIB_ERROR;
- if (unpack_byte_string(response, response_length, "s",
- data_offset, data, data_size))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_nv_write_value(uint32_t index, const void *data, uint32_t length)
-{
- const uint8_t command[256] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd,
- };
- const size_t command_size_offset = 2;
- const size_t index_offset = 10;
- const size_t length_offset = 18;
- const size_t data_offset = 22;
- const size_t write_info_size = 12;
- const uint32_t total_length =
- TPM_REQUEST_HEADER_LENGTH + write_info_size + length;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sddds",
- 0, command, sizeof(command),
- command_size_offset, total_length,
- index_offset, index,
- length_offset, length,
- data_offset, data, length))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
-
- return 0;
-}
-
-uint32_t tpm_extend(uint32_t index, const void *in_digest, void *out_digest)
-{
- const uint8_t command[34] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14,
- };
- const size_t index_offset = 10;
- const size_t in_digest_offset = 14;
- const size_t out_digest_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE];
- uint8_t response[TPM_RESPONSE_HEADER_LENGTH + PCR_DIGEST_LENGTH];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sds",
- 0, command, sizeof(command),
- index_offset, index,
- in_digest_offset, in_digest,
- PCR_DIGEST_LENGTH))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
-
- if (unpack_byte_string(response, response_length, "s",
- out_digest_offset, out_digest,
- PCR_DIGEST_LENGTH))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_pcr_read(uint32_t index, void *data, size_t count)
-{
- const uint8_t command[14] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15,
- };
- const size_t index_offset = 10;
- const size_t out_digest_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (count < PCR_DIGEST_LENGTH)
- return TPM_LIB_ERROR;
-
- if (pack_byte_string(buf, sizeof(buf), "sd",
- 0, command, sizeof(command),
- index_offset, index))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "s",
- out_digest_offset, data, PCR_DIGEST_LENGTH))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_tsc_physical_presence(uint16_t presence)
-{
- const uint8_t command[12] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x0,
- };
- const size_t presence_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE];
-
- if (pack_byte_string(buf, sizeof(buf), "sw",
- 0, command, sizeof(command),
- presence_offset, presence))
- return TPM_LIB_ERROR;
-
- return tpm_sendrecv_command(buf, NULL, NULL);
-}
-
-uint32_t tpm_read_pubek(void *data, size_t count)
-{
- const uint8_t command[30] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c,
- };
- const size_t response_size_offset = 2;
- const size_t data_offset = 10;
- const size_t header_and_checksum_size = TPM_RESPONSE_HEADER_LENGTH + 20;
- uint8_t response[COMMAND_BUFFER_SIZE + TPM_PUBEK_SIZE];
- size_t response_length = sizeof(response);
- uint32_t data_size;
- uint32_t err;
-
- err = tpm_sendrecv_command(command, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- response_size_offset, &data_size))
- return TPM_LIB_ERROR;
- if (data_size < header_and_checksum_size)
- return TPM_LIB_ERROR;
- data_size -= header_and_checksum_size;
- if (data_size > count)
- return TPM_LIB_ERROR;
- if (unpack_byte_string(response, response_length, "s",
- data_offset, data, data_size))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_force_clear(void)
-{
- const uint8_t command[10] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d,
- };
-
- return tpm_sendrecv_command(command, NULL, NULL);
-}
-
-uint32_t tpm_physical_enable(void)
-{
- const uint8_t command[10] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f,
- };
-
- return tpm_sendrecv_command(command, NULL, NULL);
-}
-
-uint32_t tpm_physical_disable(void)
-{
- const uint8_t command[10] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70,
- };
-
- return tpm_sendrecv_command(command, NULL, NULL);
-}
-
-uint32_t tpm_physical_set_deactivated(uint8_t state)
-{
- const uint8_t command[11] = {
- 0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72,
- };
- const size_t state_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE];
-
- if (pack_byte_string(buf, sizeof(buf), "sb",
- 0, command, sizeof(command),
- state_offset, state))
- return TPM_LIB_ERROR;
-
- return tpm_sendrecv_command(buf, NULL, NULL);
-}
-
-uint32_t tpm_get_capability(uint32_t cap_area, uint32_t sub_cap,
- void *cap, size_t count)
-{
- const uint8_t command[22] = {
- 0x0, 0xc1, /* TPM_TAG */
- 0x0, 0x0, 0x0, 0x16, /* parameter size */
- 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
- 0x0, 0x0, 0x0, 0x0, /* TPM_CAPABILITY_AREA */
- 0x0, 0x0, 0x0, 0x4, /* subcap size */
- 0x0, 0x0, 0x0, 0x0, /* subcap value */
- };
- const size_t cap_area_offset = 10;
- const size_t sub_cap_offset = 18;
- const size_t cap_offset = 14;
- const size_t cap_size_offset = 10;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t cap_size;
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sdd",
- 0, command, sizeof(command),
- cap_area_offset, cap_area,
- sub_cap_offset, sub_cap))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- cap_size_offset, &cap_size))
- return TPM_LIB_ERROR;
- if (cap_size > response_length || cap_size > count)
- return TPM_LIB_ERROR;
- if (unpack_byte_string(response, response_length, "s",
- cap_offset, cap, cap_size))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_get_permanent_flags(struct tpm_permanent_flags *pflags)
-{
- const uint8_t command[22] = {
- 0x0, 0xc1, /* TPM_TAG */
- 0x0, 0x0, 0x0, 0x16, /* parameter size */
- 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
- 0x0, 0x0, 0x0, 0x4, /* TPM_CAP_FLAG_PERM */
- 0x0, 0x0, 0x0, 0x4, /* subcap size */
- 0x0, 0x0, 0x1, 0x8, /* subcap value */
- };
- const size_t data_size_offset = TPM_HEADER_SIZE;
- const size_t data_offset = TPM_HEADER_SIZE + sizeof (uint32_t);
- uint8_t response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
- uint32_t data_size;
-
- err = tpm_sendrecv_command(command, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- data_size_offset, &data_size))
- return TPM_LIB_ERROR;
- if (data_size < sizeof(*pflags))
- return TPM_LIB_ERROR;
- if (unpack_byte_string(response, response_length, "s",
- data_offset, pflags, sizeof(*pflags)))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-uint32_t tpm_get_permissions(uint32_t index, uint32_t *perm)
-{
- const uint8_t command[22] = {
- 0x0, 0xc1, /* TPM_TAG */
- 0x0, 0x0, 0x0, 0x16, /* parameter size */
- 0x0, 0x0, 0x0, 0x65, /* TPM_COMMAND_CODE */
- 0x0, 0x0, 0x0, 0x11,
- 0x0, 0x0, 0x0, 0x4,
- };
- const size_t index_offset = 18;
- const size_t perm_offset = 60;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "d", 0, command, sizeof(command),
- index_offset, index))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- perm_offset, perm))
- return TPM_LIB_ERROR;
-
- return 0;
-}
-
-#ifdef CONFIG_TPM_FLUSH_RESOURCES
-uint32_t tpm_flush_specific(uint32_t key_handle, uint32_t resource_type)
-{
- const uint8_t command[18] = {
- 0x00, 0xc1, /* TPM_TAG */
- 0x00, 0x00, 0x00, 0x12, /* parameter size */
- 0x00, 0x00, 0x00, 0xba, /* TPM_COMMAND_CODE */
- 0x00, 0x00, 0x00, 0x00, /* key handle */
- 0x00, 0x00, 0x00, 0x00, /* resource type */
- };
- const size_t key_handle_offset = 10;
- const size_t resource_type_offset = 14;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sdd",
- 0, command, sizeof(command),
- key_handle_offset, key_handle,
- resource_type_offset, resource_type))
- return TPM_LIB_ERROR;
-
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- return 0;
-}
-#endif /* CONFIG_TPM_FLUSH_RESOURCES */
-
-#ifdef CONFIG_TPM_AUTH_SESSIONS
-
-/**
- * Fill an authentication block in a request.
- * This func can create the first as well as the second auth block (for
- * double authorized commands).
- *
- * @param request pointer to the request (w/ uninitialised auth data)
- * @param request_len0 length of the request without auth data
- * @param handles_len length of the handles area in request
- * @param auth_session pointer to the (valid) auth session to be used
- * @param request_auth pointer to the auth block of the request to be filled
- * @param auth authentication data (HMAC key)
- */
-static uint32_t create_request_auth(const void *request, size_t request_len0,
- size_t handles_len,
- struct session_data *auth_session,
- void *request_auth, const void *auth)
-{
- uint8_t hmac_data[DIGEST_LENGTH * 3 + 1];
- sha1_context hash_ctx;
- const size_t command_code_offset = 6;
- const size_t auth_nonce_odd_offset = 4;
- const size_t auth_continue_offset = 24;
- const size_t auth_auth_offset = 25;
-
- if (!auth_session || !auth_session->valid)
- return TPM_LIB_ERROR;
-
- sha1_starts(&hash_ctx);
- sha1_update(&hash_ctx, request + command_code_offset, 4);
- if (request_len0 > TPM_REQUEST_HEADER_LENGTH + handles_len)
- sha1_update(&hash_ctx,
- request + TPM_REQUEST_HEADER_LENGTH + handles_len,
- request_len0 - TPM_REQUEST_HEADER_LENGTH
- - handles_len);
- sha1_finish(&hash_ctx, hmac_data);
-
- sha1_starts(&hash_ctx);
- sha1_update(&hash_ctx, auth_session->nonce_odd, DIGEST_LENGTH);
- sha1_update(&hash_ctx, hmac_data, sizeof(hmac_data));
- sha1_finish(&hash_ctx, auth_session->nonce_odd);
-
- if (pack_byte_string(request_auth, TPM_REQUEST_AUTH_LENGTH, "dsb",
- 0, auth_session->handle,
- auth_nonce_odd_offset, auth_session->nonce_odd,
- DIGEST_LENGTH,
- auth_continue_offset, 1))
- return TPM_LIB_ERROR;
- if (pack_byte_string(hmac_data, sizeof(hmac_data), "ss",
- DIGEST_LENGTH,
- auth_session->nonce_even,
- DIGEST_LENGTH,
- 2 * DIGEST_LENGTH,
- request_auth + auth_nonce_odd_offset,
- DIGEST_LENGTH + 1))
- return TPM_LIB_ERROR;
- sha1_hmac(auth, DIGEST_LENGTH, hmac_data, sizeof(hmac_data),
- request_auth + auth_auth_offset);
-
- return TPM_SUCCESS;
-}
-
-/**
- * Verify an authentication block in a response.
- * Since this func updates the nonce_even in the session data it has to be
- * called when receiving a succesfull AUTH response.
- * This func can verify the first as well as the second auth block (for
- * double authorized commands).
- *
- * @param command_code command code of the request
- * @param response pointer to the request (w/ uninitialised auth data)
- * @param handles_len length of the handles area in response
- * @param auth_session pointer to the (valid) auth session to be used
- * @param response_auth pointer to the auth block of the response to be verified
- * @param auth authentication data (HMAC key)
- */
-static uint32_t verify_response_auth(uint32_t command_code,
- const void *response, size_t response_len0,
- size_t handles_len,
- struct session_data *auth_session,
- const void *response_auth, const void *auth)
-{
- uint8_t hmac_data[DIGEST_LENGTH * 3 + 1];
- uint8_t computed_auth[DIGEST_LENGTH];
- sha1_context hash_ctx;
- const size_t return_code_offset = 6;
- const size_t auth_continue_offset = 20;
- const size_t auth_auth_offset = 21;
- uint8_t auth_continue;
-
- if (!auth_session || !auth_session->valid)
- return TPM_AUTHFAIL;
- if (pack_byte_string(hmac_data, sizeof(hmac_data), "d",
- 0, command_code))
- return TPM_LIB_ERROR;
- if (response_len0 < TPM_RESPONSE_HEADER_LENGTH)
- return TPM_LIB_ERROR;
-
- sha1_starts(&hash_ctx);
- sha1_update(&hash_ctx, response + return_code_offset, 4);
- sha1_update(&hash_ctx, hmac_data, 4);
- if (response_len0 > TPM_RESPONSE_HEADER_LENGTH + handles_len)
- sha1_update(&hash_ctx,
- response + TPM_RESPONSE_HEADER_LENGTH + handles_len,
- response_len0 - TPM_RESPONSE_HEADER_LENGTH
- - handles_len);
- sha1_finish(&hash_ctx, hmac_data);
-
- memcpy(auth_session->nonce_even, response_auth, DIGEST_LENGTH);
- auth_continue = ((uint8_t *)response_auth)[auth_continue_offset];
- if (pack_byte_string(hmac_data, sizeof(hmac_data), "ssb",
- DIGEST_LENGTH,
- response_auth,
- DIGEST_LENGTH,
- 2 * DIGEST_LENGTH,
- auth_session->nonce_odd,
- DIGEST_LENGTH,
- 3 * DIGEST_LENGTH,
- auth_continue))
- return TPM_LIB_ERROR;
-
- sha1_hmac(auth, DIGEST_LENGTH, hmac_data, sizeof(hmac_data),
- computed_auth);
-
- if (memcmp(computed_auth, response_auth + auth_auth_offset,
- DIGEST_LENGTH))
- return TPM_AUTHFAIL;
-
- return TPM_SUCCESS;
-}
-
-
-uint32_t tpm_terminate_auth_session(uint32_t auth_handle)
-{
- const uint8_t command[18] = {
- 0x00, 0xc1, /* TPM_TAG */
- 0x00, 0x00, 0x00, 0x00, /* parameter size */
- 0x00, 0x00, 0x00, 0xba, /* TPM_COMMAND_CODE */
- 0x00, 0x00, 0x00, 0x00, /* TPM_HANDLE */
- 0x00, 0x00, 0x00, 0x02, /* TPM_RESSOURCE_TYPE */
- };
- const size_t req_handle_offset = TPM_REQUEST_HEADER_LENGTH;
- uint8_t request[COMMAND_BUFFER_SIZE];
-
- if (pack_byte_string(request, sizeof(request), "sd",
- 0, command, sizeof(command),
- req_handle_offset, auth_handle))
- return TPM_LIB_ERROR;
- if (oiap_session.valid && oiap_session.handle == auth_handle)
- oiap_session.valid = 0;
-
- return tpm_sendrecv_command(request, NULL, NULL);
-}
-
-uint32_t tpm_end_oiap(void)
-{
- uint32_t err = TPM_SUCCESS;
- if (oiap_session.valid)
- err = tpm_terminate_auth_session(oiap_session.handle);
- return err;
-}
-
-uint32_t tpm_oiap(uint32_t *auth_handle)
-{
- const uint8_t command[10] = {
- 0x00, 0xc1, /* TPM_TAG */
- 0x00, 0x00, 0x00, 0x0a, /* parameter size */
- 0x00, 0x00, 0x00, 0x0a, /* TPM_COMMAND_CODE */
- };
- const size_t res_auth_handle_offset = TPM_RESPONSE_HEADER_LENGTH;
- const size_t res_nonce_even_offset = TPM_RESPONSE_HEADER_LENGTH + 4;
- uint8_t response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (oiap_session.valid)
- tpm_terminate_auth_session(oiap_session.handle);
-
- err = tpm_sendrecv_command(command, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "ds",
- res_auth_handle_offset, &oiap_session.handle,
- res_nonce_even_offset, &oiap_session.nonce_even,
- (uint32_t)DIGEST_LENGTH))
- return TPM_LIB_ERROR;
- oiap_session.valid = 1;
- if (auth_handle)
- *auth_handle = oiap_session.handle;
- return 0;
-}
-
-uint32_t tpm_load_key2_oiap(uint32_t parent_handle,
- const void *key, size_t key_length,
- const void *parent_key_usage_auth,
- uint32_t *key_handle)
-{
- const uint8_t command[14] = {
- 0x00, 0xc2, /* TPM_TAG */
- 0x00, 0x00, 0x00, 0x00, /* parameter size */
- 0x00, 0x00, 0x00, 0x41, /* TPM_COMMAND_CODE */
- 0x00, 0x00, 0x00, 0x00, /* parent handle */
- };
- const size_t req_size_offset = 2;
- const size_t req_parent_handle_offset = TPM_REQUEST_HEADER_LENGTH;
- const size_t req_key_offset = TPM_REQUEST_HEADER_LENGTH + 4;
- const size_t res_handle_offset = TPM_RESPONSE_HEADER_LENGTH;
- uint8_t request[sizeof(command) + TPM_KEY12_MAX_LENGTH
- + TPM_REQUEST_AUTH_LENGTH];
- uint8_t response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (!oiap_session.valid) {
- err = tpm_oiap(NULL);
- if (err)
- return err;
- }
- if (pack_byte_string(request, sizeof(request), "sdds",
- 0, command, sizeof(command),
- req_size_offset,
- sizeof(command) + key_length
- + TPM_REQUEST_AUTH_LENGTH,
- req_parent_handle_offset, parent_handle,
- req_key_offset, key, key_length
- ))
- return TPM_LIB_ERROR;
-
- err = create_request_auth(request, sizeof(command) + key_length, 4,
- &oiap_session,
- request + sizeof(command) + key_length,
- parent_key_usage_auth);
- if (err)
- return err;
- err = tpm_sendrecv_command(request, response, &response_length);
- if (err) {
- if (err == TPM_AUTHFAIL)
- oiap_session.valid = 0;
- return err;
- }
-
- err = verify_response_auth(0x00000041, response,
- response_length - TPM_RESPONSE_AUTH_LENGTH,
- 4, &oiap_session,
- response + response_length - TPM_RESPONSE_AUTH_LENGTH,
- parent_key_usage_auth);
- if (err)
- return err;
-
- if (key_handle) {
- if (unpack_byte_string(response, response_length, "d",
- res_handle_offset, key_handle))
- return TPM_LIB_ERROR;
- }
-
- return 0;
-}
-
-uint32_t tpm_get_pub_key_oiap(uint32_t key_handle, const void *usage_auth,
- void *pubkey, size_t *pubkey_len)
-{
- const uint8_t command[14] = {
- 0x00, 0xc2, /* TPM_TAG */
- 0x00, 0x00, 0x00, 0x00, /* parameter size */
- 0x00, 0x00, 0x00, 0x21, /* TPM_COMMAND_CODE */
- 0x00, 0x00, 0x00, 0x00, /* key handle */
- };
- const size_t req_size_offset = 2;
- const size_t req_key_handle_offset = TPM_REQUEST_HEADER_LENGTH;
- const size_t res_pubkey_offset = TPM_RESPONSE_HEADER_LENGTH;
- uint8_t request[sizeof(command) + TPM_REQUEST_AUTH_LENGTH];
- uint8_t response[TPM_RESPONSE_HEADER_LENGTH + TPM_PUBKEY_MAX_LENGTH
- + TPM_RESPONSE_AUTH_LENGTH];
- size_t response_length = sizeof(response);
- uint32_t err;
-
- if (!oiap_session.valid) {
- err = tpm_oiap(NULL);
- if (err)
- return err;
- }
- if (pack_byte_string(request, sizeof(request), "sdd",
- 0, command, sizeof(command),
- req_size_offset,
- (uint32_t)(sizeof(command)
- + TPM_REQUEST_AUTH_LENGTH),
- req_key_handle_offset, key_handle
- ))
- return TPM_LIB_ERROR;
- err = create_request_auth(request, sizeof(command), 4, &oiap_session,
- request + sizeof(command), usage_auth);
- if (err)
- return err;
- err = tpm_sendrecv_command(request, response, &response_length);
- if (err) {
- if (err == TPM_AUTHFAIL)
- oiap_session.valid = 0;
- return err;
- }
- err = verify_response_auth(0x00000021, response,
- response_length - TPM_RESPONSE_AUTH_LENGTH,
- 0, &oiap_session,
- response + response_length - TPM_RESPONSE_AUTH_LENGTH,
- usage_auth);
- if (err)
- return err;
-
- if (pubkey) {
- if ((response_length - TPM_RESPONSE_HEADER_LENGTH
- - TPM_RESPONSE_AUTH_LENGTH) > *pubkey_len)
- return TPM_LIB_ERROR;
- *pubkey_len = response_length - TPM_RESPONSE_HEADER_LENGTH
- - TPM_RESPONSE_AUTH_LENGTH;
- memcpy(pubkey, response + res_pubkey_offset,
- response_length - TPM_RESPONSE_HEADER_LENGTH
- - TPM_RESPONSE_AUTH_LENGTH);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
-uint32_t tpm_find_key_sha1(const uint8_t auth[20], const uint8_t
- pubkey_digest[20], uint32_t *handle)
-{
- uint16_t key_count;
- uint32_t key_handles[10];
- uint8_t buf[288];
- uint8_t *ptr;
- uint32_t err;
- uint8_t digest[20];
- size_t buf_len;
- unsigned int i;
-
- /* fetch list of already loaded keys in the TPM */
- err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
- if (err)
- return -1;
- key_count = get_unaligned_be16(buf);
- ptr = buf + 2;
- for (i = 0; i < key_count; ++i, ptr += 4)
- key_handles[i] = get_unaligned_be32(ptr);
-
- /* now search a(/ the) key which we can access with the given auth */
- for (i = 0; i < key_count; ++i) {
- buf_len = sizeof(buf);
- err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
- if (err && err != TPM_AUTHFAIL)
- return -1;
- if (err)
- continue;
- sha1_csum(buf, buf_len, digest);
- if (!memcmp(digest, pubkey_digest, 20)) {
- *handle = key_handles[i];
- return 0;
- }
- }
- return 1;
-}
-#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
-
-#endif /* CONFIG_TPM_AUTH_SESSIONS */
-
-uint32_t tpm_get_random(void *data, uint32_t count)
-{
- const uint8_t command[14] = {
- 0x0, 0xc1, /* TPM_TAG */
- 0x0, 0x0, 0x0, 0xe, /* parameter size */
- 0x0, 0x0, 0x0, 0x46, /* TPM_COMMAND_CODE */
- };
- const size_t length_offset = 10;
- const size_t data_size_offset = 10;
- const size_t data_offset = 14;
- uint8_t buf[COMMAND_BUFFER_SIZE], response[COMMAND_BUFFER_SIZE];
- size_t response_length = sizeof(response);
- uint32_t data_size;
- uint8_t *out = data;
-
- while (count > 0) {
- uint32_t this_bytes = min((size_t)count,
- sizeof (response) - data_offset);
- uint32_t err;
-
- if (pack_byte_string(buf, sizeof(buf), "sd",
- 0, command, sizeof(command),
- length_offset, this_bytes))
- return TPM_LIB_ERROR;
- err = tpm_sendrecv_command(buf, response, &response_length);
- if (err)
- return err;
- if (unpack_byte_string(response, response_length, "d",
- data_size_offset, &data_size))
- return TPM_LIB_ERROR;
- if (data_size > count)
- return TPM_LIB_ERROR;
- if (unpack_byte_string(response, response_length, "s",
- data_offset, out, data_size))
- return TPM_LIB_ERROR;
-
- count -= data_size;
- out += data_size;
- }
-
- return 0;
-}
CONFIG_ARCH_TEGRA
CONFIG_ARCH_USE_BUILTIN_BSWAP
CONFIG_ARC_MMU_VER
-CONFIG_ARC_SERIAL
CONFIG_ARIES_M28_V10
CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
CONFIG_MULTI_CS
CONFIG_MUSB_HOST
CONFIG_MVEBU_MMC
-CONFIG_MVGBE
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
CONFIG_SMSTP7_ENA
CONFIG_SMSTP8_ENA
CONFIG_SMSTP9_ENA
-CONFIG_SOCFPGA_VIRTUAL_TARGET
CONFIG_SOCRATES
CONFIG_SOC_AU1000
CONFIG_SOC_AU1100
CONFIG_SUNXI_USB_PHYS
CONFIG_SUPERH_ON_CHIP_R8A66597
CONFIG_SUPPORT_EMMC_BOOT
-CONFIG_SUPPORT_EMMC_RPMB
CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYS_MSC1_VAL
CONFIG_SYS_MSC2_VAL
CONFIG_SYS_MTDPARTS_RUNTIME
-CONFIG_SYS_MVFS
CONFIG_SYS_MX5_CLK32
CONFIG_SYS_MX5_HCLK
CONFIG_SYS_MX6_CLK32
CONFIG_TSECV2_1
CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TSI108_ETH_NUM_PORTS
CONFIG_TUGE1
CONFIG_TULIP
CONFIG_TULIP_FIX_DAVICOM
CONFIG_ZLT
CONFIG_ZM7300
CONFIG_ZYNQMP_EEPROM
-CONFIG_ZYNQMP_XHCI_LIST
CONFIG_ZYNQ_EEPROM
CONFIG_ZYNQ_EEPROM_BUS
CONFIG_ZYNQ_GEM_EEPROM_ADDR
--- /dev/null
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0
+# Disassemble the Code: line in Linux oopses
+# usage: decodecode < oops.file
+#
+# options: set env. variable AFLAGS=options to pass options to "as";
+# e.g., to decode an i386 oops on an x86_64 system, use:
+# AFLAGS=--32 decodecode < 386.oops
+
+cleanup() {
+ rm -f $T $T.s $T.o $T.oo $T.aa $T.dis
+ exit 1
+}
+
+die() {
+ echo "$@"
+ exit 1
+}
+
+trap cleanup EXIT
+
+T=`mktemp` || die "cannot create temp file"
+code=
+cont=
+
+while read i ; do
+
+case "$i" in
+*Code:*)
+ code=$i
+ cont=yes
+ ;;
+*)
+ [ -n "$cont" ] && {
+ xdump="$(echo $i | grep '^[[:xdigit:]<>[:space:]]\+$')"
+ if [ -n "$xdump" ]; then
+ code="$code $xdump"
+ else
+ cont=
+ fi
+ }
+ ;;
+esac
+
+done
+
+if [ -z "$code" ]; then
+ rm $T
+ exit
+fi
+
+echo $code
+code=`echo $code | sed -e 's/.*Code: //'`
+
+width=`expr index "$code" ' '`
+width=$((($width-1)/2))
+case $width in
+1) type=byte ;;
+2) type=2byte ;;
+4) type=4byte ;;
+esac
+
+disas() {
+ ${CROSS_COMPILE}as $AFLAGS -o $1.o $1.s > /dev/null 2>&1
+
+ if [ "$ARCH" = "arm" ]; then
+ if [ $width -eq 2 ]; then
+ OBJDUMPFLAGS="-M force-thumb"
+ fi
+
+ ${CROSS_COMPILE}strip $1.o
+ fi
+
+ if [ "$ARCH" = "arm64" ]; then
+ if [ $width -eq 4 ]; then
+ type=inst
+ fi
+
+ ${CROSS_COMPILE}strip $1.o
+ fi
+
+ ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $1.o | \
+ grep -v "/tmp\|Disassembly\|\.text\|^$" > $1.dis 2>&1
+}
+
+marker=`expr index "$code" "\<"`
+if [ $marker -eq 0 ]; then
+ marker=`expr index "$code" "\("`
+fi
+
+touch $T.oo
+if [ $marker -ne 0 ]; then
+ echo All code >> $T.oo
+ echo ======== >> $T.oo
+ beforemark=`echo "$code"`
+ echo -n " .$type 0x" > $T.s
+ echo $beforemark | sed -e 's/ /,0x/g; s/[<>()]//g' >> $T.s
+ disas $T
+ cat $T.dis >> $T.oo
+ rm -f $T.o $T.s $T.dis
+
+# and fix code at-and-after marker
+ code=`echo "$code" | cut -c$((${marker} + 1))-`
+fi
+echo Code starting with the faulting instruction > $T.aa
+echo =========================================== >> $T.aa
+code=`echo $code | sed -e 's/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'`
+echo -n " .$type 0x" > $T.s
+echo $code >> $T.s
+disas $T
+cat $T.dis >> $T.aa
+
+# (lines of whole $T.oo) - (lines of $T.aa, i.e. "Code starting") + 3,
+# i.e. the title + the "===..=" line (sed is counting from 1, 0 address is
+# special)
+faultlinenum=$(( $(wc -l $T.oo | cut -d" " -f1) - \
+ $(wc -l $T.aa | cut -d" " -f1) + 3))
+
+faultline=`cat $T.dis | head -1 | cut -d":" -f2-`
+faultline=`echo "$faultline" | sed -e 's/\[/\\\[/g; s/\]/\\\]/g'`
+
+cat $T.oo | sed -e "${faultlinenum}s/^\(.*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/"
+echo
+cat $T.aa
+cleanup
$(obj)/libfdt.i
quiet_cmd_pymod = PYMOD $@
- cmd_pymod = unset CC; unset CROSS_COMPILE; unset CFLAGS;\
+ cmd_pymod = unset CROSS_COMPILE; unset CFLAGS; \
+ CC="$(HOSTCC)" LDSHARED="$(HOSTCC) -shared " \
LDFLAGS="$(HOSTLDFLAGS)" \
VERSION="u-boot-$(UBOOTVERSION)" \
CPPFLAGS="$(HOSTCFLAGS) -I$(LIBFDT_srcdir)" OBJDIR=$(obj) \
#include <power/pmic.h>
#include <power/sandbox_pmic.h>
#include <test/ut.h>
+#include <fsl_pmic.h>
/* Test PMIC get method */
-static int dm_test_power_pmic_get(struct unit_test_state *uts)
+
+static inline int power_pmic_get(struct unit_test_state *uts, char *name)
{
- const char *name = "sandbox_pmic";
struct udevice *dev;
ut_assertok(pmic_get(name, &dev));
return 0;
}
+
+/* Test PMIC get method */
+static int dm_test_power_pmic_get(struct unit_test_state *uts)
+{
+ power_pmic_get(uts, "sandbox_pmic");
+
+ return 0;
+}
DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
+/* PMIC get method - MC34708 - for 3 bytes transmission */
+static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
+{
+ power_pmic_get(uts, "pmic@41");
+
+ return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
+
/* Test PMIC I/O */
static int dm_test_power_pmic_io(struct unit_test_state *uts)
{
return 0;
}
DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
+
+#define MC34708_PMIC_REG_COUNT 64
+#define MC34708_PMIC_TEST_VAL 0x125534
+static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ int reg_count;
+
+ ut_assertok(pmic_get("pmic@41", &dev));
+
+ /* Check number of PMIC registers */
+ reg_count = pmic_reg_count(dev);
+ ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
+
+ return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
+
+static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ int val;
+
+ ut_assertok(pmic_get("pmic@41", &dev));
+
+ /* Check if single 3 byte read is successful */
+ val = pmic_reg_read(dev, REG_POWER_CTL2);
+ ut_asserteq(val, 0x422100);
+
+ /* Check if RW works */
+ val = 0;
+ ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
+ ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
+ val = pmic_reg_read(dev, REG_RTC_TIME);
+ ut_asserteq(val, MC34708_PMIC_TEST_VAL);
+
+ pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
+ val = pmic_reg_read(dev, REG_POWER_CTL2);
+ ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
+
+ return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);
run bind
# Test Case 1 - ls
${PREFIX}ls host${SUFFIX} $6
+# In addition, test with a nonexistent directory to see if we crash.
+${PREFIX}ls host${SUFFIX} invalid_d
#
# We want ${PREFIX}size host 0:0 $3 for host commands and
# sb size hostfs - $3 for hostfs commands.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2018, Bootlin
+# Author: Miquel Raynal <miquel.raynal@bootlin.com>
+
+import os.path
+import pytest
+import u_boot_utils
+import re
+import time
+
+"""
+Test the TPMv2.x related commands. You must have a working hardware setup in
+order to do these tests.
+
+Notes:
+* These tests will prove the password mechanism. The TPM chip must be cleared of
+any password.
+* Commands like pcr_setauthpolicy and pcr_resetauthpolicy are not implemented
+here because they would fail the tests in most cases (TPMs do not implement them
+and return an error).
+"""
+
+updates = 0
+
+def force_init(u_boot_console, force=False):
+ """When a test fails, U-Boot is reset. Because TPM stack must be initialized
+ after each reboot, we must ensure these lines are always executed before
+ trying any command or they will fail with no reason. Executing 'tpm init'
+ twice will spawn an error used to detect that the TPM was not reset and no
+ initialization code should be run.
+ """
+ output = u_boot_console.run_command('tpm init')
+ if force or not 'Error' in output:
+ u_boot_console.run_command('echo --- start of init ---')
+ u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
+ u_boot_console.run_command('tpm self_test full')
+ u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ output = u_boot_console.run_command('echo $?')
+ if not output.endswith('0'):
+ u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('echo --- end of init ---')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_init(u_boot_console):
+ """Init the software stack to use TPMv2 commands."""
+
+ u_boot_console.run_command('tpm init')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_startup(u_boot_console):
+ """Execute a TPM2_Startup command.
+
+ Initiate the TPM internal state machine.
+ """
+
+ u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_self_test_full(u_boot_console):
+ """Execute a TPM2_SelfTest (full) command.
+
+ Ask the TPM to perform all self tests to also enable full capabilities.
+ """
+
+ u_boot_console.run_command('tpm self_test full')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_continue_self_test(u_boot_console):
+ """Execute a TPM2_SelfTest (continued) command.
+
+ Ask the TPM to finish its self tests (alternative to the full test) in order
+ to enter a fully operational state.
+ """
+
+ u_boot_console.run_command('tpm self_test continue')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_clear(u_boot_console):
+ """Execute a TPM2_Clear command.
+
+ Ask the TPM to reset entirely its internal state (including internal
+ configuration, passwords, counters and DAM parameters). This is half of the
+ TAKE_OWNERSHIP command from TPMv1.
+
+ Use the LOCKOUT hierarchy for this. The LOCKOUT/PLATFORM hierarchies must
+ not have a password set, otherwise this test will fail. ENDORSEMENT and
+ PLATFORM hierarchies are also available.
+ """
+
+ u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_change_auth(u_boot_console):
+ """Execute a TPM2_HierarchyChangeAuth command.
+
+ Ask the TPM to change the owner, ie. set a new password: 'unicorn'
+
+ Use the LOCKOUT hierarchy for this. ENDORSEMENT and PLATFORM hierarchies are
+ also available.
+ """
+
+ force_init(u_boot_console)
+
+ u_boot_console.run_command('tpm change_auth TPM2_RH_LOCKOUT unicorn')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT unicorn')
+ output = u_boot_console.run_command('echo $?')
+ u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ assert output.endswith('0')
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_get_capability(u_boot_console):
+ """Execute a TPM_GetCapability command.
+
+ Display one capability. In our test case, let's display the default DAM
+ lockout counter that should be 0 since the CLEAR:
+ - TPM_CAP_TPM_PROPERTIES = 0x6
+ - TPM_PT_LOCKOUT_COUNTER (1st parameter) = PTR_VAR + 14
+
+ There is no expected default values because it would depend on the chip
+ used. We can still save them in order to check they have changed later.
+ """
+
+ force_init(u_boot_console)
+ ram = u_boot_utils.find_ram_base(u_boot_console)
+
+ read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+ assert 'Property 0x0000020e: 0x00000000' in read_cap
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_dam_parameters(u_boot_console):
+ """Execute a TPM2_DictionaryAttackParameters command.
+
+ Change Dictionary Attack Mitigation (DAM) parameters. Ask the TPM to change:
+ - Max number of failed authentication before lockout: 3
+ - Time before the failure counter is automatically decremented: 10 sec
+ - Time after a lockout failure before it can be attempted again: 0 sec
+
+ For an unknown reason, the DAM parameters must be changed before changing
+ the authentication, otherwise the lockout will be engaged after the first
+ failed authentication attempt.
+ """
+
+ force_init(u_boot_console)
+ ram = u_boot_utils.find_ram_base(u_boot_console)
+
+ # Set the DAM parameters to known values
+ u_boot_console.run_command('tpm dam_parameters 3 10 0')
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ # Check the values have been saved
+ read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20f 0x%x 3' % ram)
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+ assert 'Property 0x0000020f: 0x00000003' in read_cap
+ assert 'Property 0x00000210: 0x0000000a' in read_cap
+ assert 'Property 0x00000211: 0x00000000' in read_cap
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_pcr_read(u_boot_console):
+ """Execute a TPM2_PCR_Read command.
+
+ Perform a PCR read of the 0th PCR. Must be zero.
+ """
+
+ force_init(u_boot_console)
+ ram = u_boot_utils.find_ram_base(u_boot_console) + 1024
+
+ read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ # Save the number of PCR updates
+ str = re.findall(r'\d+ known updates', read_pcr)[0]
+ global updates
+ updates = int(re.findall(r'\d+', str)[0])
+
+ # Check the output value
+ assert 'PCR #0 content' in read_pcr
+ assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_pcr_extend(u_boot_console):
+ """Execute a TPM2_PCR_Extend command.
+
+ Perform a PCR extension with a known hash in memory (zeroed since the board
+ must have been rebooted).
+
+ No authentication mechanism is used here, not protecting against packet
+ replay, yet.
+ """
+
+ force_init(u_boot_console)
+ ram = u_boot_utils.find_ram_base(u_boot_console) + 1024
+
+ u_boot_console.run_command('tpm pcr_extend 0 0x%x' % ram)
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+
+ read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ output = u_boot_console.run_command('echo $?')
+ assert output.endswith('0')
+ assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
+ assert '43 00 3d 23 20 d9 f0 e8 ea 98 31 a9 27 59 fb 4b' in read_pcr
+
+ str = re.findall(r'\d+ known updates', read_pcr)[0]
+ new_updates = int(re.findall(r'\d+', str)[0])
+ assert (updates + 1) == new_updates
+
+@pytest.mark.buildconfigspec('cmd_tpm_v2')
+def test_tpm2_cleanup(u_boot_console):
+ """Ensure the TPM is cleared from password or test related configuration."""
+
+ force_init(u_boot_console, True)
import glob
import os
import shutil
+import sys
import threading
import command
os.mkdir(dirname)
except OSError as err:
if err.errno == errno.EEXIST:
+ if os.path.realpath('.') == os.path.realpath(dirname):
+ print "Cannot create the current working directory '%s'!" % dirname
+ sys.exit(1)
pass
else:
raise
print ('Total boards to build for each commit: %d\n' %
len(why_selected['all']))
+def CheckOutputDir(output_dir):
+ """Make sure that the output directory is not within the current directory
+
+ If we try to use an output directory which is within the current directory
+ (which is assumed to hold the U-Boot source) we may end up deleting the
+ U-Boot source code. Detect this and print an error in this case.
+
+ Args:
+ output_dir: Output directory path to check
+ """
+ path = os.path.realpath(output_dir)
+ cwd_path = os.path.realpath('.')
+ while True:
+ if os.path.realpath(path) == cwd_path:
+ Print("Cannot use output directory '%s' since it is within the current directtory '%s'" %
+ (path, cwd_path))
+ sys.exit(1)
+ parent = os.path.dirname(path)
+ if parent == path:
+ break
+ path = parent
+
def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
clean_dir=False):
"""The main control code for buildman
# output directory itself rather than any subdirectory.
if not options.no_subdirs:
output_dir = os.path.join(options.output_dir, dirname)
- if (clean_dir and output_dir != options.output_dir and
- os.path.exists(output_dir)):
- shutil.rmtree(output_dir)
+ if clean_dir and os.path.exists(output_dir):
+ shutil.rmtree(output_dir)
+ CheckOutputDir(output_dir)
builder = Builder(toolchains, output_dir, options.git_dir,
options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
show_unknown=options.show_unknown, step=options.step,
self._RunControl('-b', self._test_branch, clean_dir=False)
self.assertEqual(self._builder.count, self._total_builds)
self.assertEqual(self._builder.fail, 0)
+
+ def testBadOutputDir(self):
+ """Test building with an output dir the same as out current dir"""
+ self._test_branch = '/__dev/__testbranch'
+ with self.assertRaises(SystemExit):
+ self._RunControl('-b', self._test_branch, '-o', os.getcwd())
+ with self.assertRaises(SystemExit):
+ self._RunControl('-b', self._test_branch, '-o',
+ os.path.join(os.getcwd(), 'test'))
HTMLParser.__init__(self)
self.arch_link = None
self.links = []
- self._match = '_%s-' % arch
+ self.re_arch = re.compile('[-_]%s-' % arch)
def handle_starttag(self, tag, attrs):
if tag == 'a':
if tag == 'href':
if value and value.endswith('.xz'):
self.links.append(value)
- if self._match in value:
+ if self.re_arch.search(value):
self.arch_link = value
"""
arch = command.OutputOneLine('uname', '-m')
base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
- versions = ['4.9.0', '4.6.3', '4.6.2', '4.5.1', '4.2.4']
+ versions = ['7.3.0', '6.4.0', '4.9.4']
links = []
for version in versions:
url = '%s/%s/%s/' % (base, arch, version)
projects / u-boot / commitdiff