]> git.sur5r.net Git - u-boot/commitdiff
Blackfin: cm-bf548: new board port
authorMike Frysinger <vapier@gentoo.org>
Mon, 13 Oct 2008 01:54:07 +0000 (21:54 -0400)
committerMike Frysinger <vapier@gentoo.org>
Mon, 15 Jun 2009 00:01:07 +0000 (20:01 -0400)
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
MAINTAINERS
MAKEALL
Makefile
board/cm-bf548/.gitignore [new file with mode: 0644]
board/cm-bf548/Makefile [new file with mode: 0644]
board/cm-bf548/cm-bf548.c [new file with mode: 0644]
board/cm-bf548/config.mk [new file with mode: 0644]
board/cm-bf548/u-boot.lds.S [new file with mode: 0644]
board/cm-bf548/video.c [new file with mode: 0644]
include/configs/cm-bf548.h [new file with mode: 0644]

index 1dfcb842dc0d0e035c55eb89e704b4f166f7f4ef..ec8cda9d68013561ac0313c23291e4dbe51a3bb5 100644 (file)
@@ -876,6 +876,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 
        CM-BF533        BF533
        CM-BF537E       BF537
+       CM-BF548        BF548
        CM-BF561        BF561
        TCM-BF537       BF537
 
diff --git a/MAKEALL b/MAKEALL
index 849834af2037771d96794daaa29b6e006ae80555..cf5c6e2261301c35b49f5f04ddf48f2ffdd689ea 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -808,6 +808,7 @@ LIST_blackfin="             \
        bf561-ezkit     \
        cm-bf533        \
        cm-bf537e       \
+       cm-bf548        \
        cm-bf561        \
        tcm-bf537       \
 "
index f325624d3a1c7c1678c3ad66ee0d0d9ec107d165..345ff6f31b4d8ddf2139d9cf18f00215199a7ea8 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3391,7 +3391,7 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
        bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
 
 # Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf561 tcm-bf537
+BFIN_BOARDS += cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
 
 $(BFIN_BOARDS:%=%_config)      : unconfig
        @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
@@ -3567,7 +3567,7 @@ clean:
               $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
               $(obj)board/bf5{18f,26,27,33,38f,48,61}-ez{brd,kit}/u-boot.lds \
               $(obj)board/bf5{33,37}-stamp/u-boot.lds                    \
-              $(obj)board/{,t}cm-bf5{33,37e,61}/u-boot.lds               \
+              $(obj)board/{,t}cm-bf5{33,37e,48,61}/u-boot.lds            \
               $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
        @rm -f $(obj)include/bmp_logo.h
        @rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
diff --git a/board/cm-bf548/.gitignore b/board/cm-bf548/.gitignore
new file mode 100644 (file)
index 0000000..945f324
--- /dev/null
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
new file mode 100644 (file)
index 0000000..c2b98ec
--- /dev/null
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        := $(BOARD).o
+COBJS-$(CONFIG_VIDEO)      += video.o
+
+SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+       $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
new file mode 100644 (file)
index 0000000..1c26600
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       printf("Board: Bluetechnix CM-BF548 board\n");
+       printf("       Support: http://www.bluetechnix.at/\n");
+       return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+       return gd->bd->bi_memsize;
+}
+
+int board_early_init_f(void)
+{
+       /* Port H: PH8 - PH13 == A4 - A9
+        * address lines of the parallel asynchronous memory interface
+        */
+
+       /************************************************
+       * configure GPIO                                *
+       * set port H function enable register           *
+       *  configure PH8-PH13 as peripheral (not GPIO)  *
+       *************************************************/
+       bfin_write_PORTH_FER(0x3F03);
+
+       /************************************************
+       * set port H MUX to configure PH8-PH13          *
+       *  1st Function (MUX = 00) (bits 16-27 == 0)    *
+       *  Set to address signals A4-A9                 *
+       *************************************************/
+       bfin_write_PORTH_MUX(0);
+
+       /************************************************
+       * set port H direction register                 *
+       *  enable PH8-PH13 as outputs                   *
+       *************************************************/
+       bfin_write_PORTH_DIR_SET(0x3F00);
+
+       /* Port I: PI0 - PH14 == A10 - A24
+        * address lines of the parallel asynchronous memory interface
+        */
+
+       /************************************************
+       * set port I function enable register           *
+       *  configure PI0-PI14 as peripheral (not GPIO)  *
+       *************************************************/
+       bfin_write_PORTI_FER(0x7fff);
+
+       /**************************************************
+       * set PORT I MUX to configure PI14-PI0 as         *
+       * 1st Function (MUX=00) - address signals A10-A24 *
+       ***************************************************/
+       bfin_write_PORTI_MUX(0);
+
+       /****************************************
+       * set PORT I direction register         *
+       *  enable PI0 - PI14 as outputs         *
+       *****************************************/
+       bfin_write_PORTI_DIR_SET(0x7fff);
+
+       return 0;
+}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
new file mode 100644 (file)
index 0000000..0dbce93
--- /dev/null
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf548/u-boot.lds.S b/board/cm-bf548/u-boot.lds.S
new file mode 100644 (file)
index 0000000..3e8be35
--- /dev/null
@@ -0,0 +1,124 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+       ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+       l1_code : ORIGIN = L1_INST_SRAM,            LENGTH = L1_INST_SRAM_SIZE
+       l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+       .text :
+       {
+               cpu/blackfin/start.o (.text .text.*)
+               __initcode_start = .;
+               cpu/blackfin/initcode.o (.text .text.*)
+               __initcode_end = .;
+               *(.text .text.*)
+       } >ram
+
+       .rodata :
+       {
+               . = ALIGN(4);
+               *(.rodata .rodata.*)
+               *(.rodata1)
+               *(.eh_frame)
+               . = ALIGN(4);
+       } >ram
+
+       .data :
+       {
+               . = ALIGN(256);
+               *(.data .data.*)
+               *(.data1)
+               *(.sdata)
+               *(.sdata2)
+               *(.dynamic)
+               CONSTRUCTORS
+       } >ram
+
+       .u_boot_cmd :
+       {
+               ___u_boot_cmd_start = .;
+               *(.u_boot_cmd)
+               ___u_boot_cmd_end = .;
+       } >ram
+
+       .text_l1 :
+       {
+               . = ALIGN(4);
+               __stext_l1 = .;
+               *(.l1.text)
+               . = ALIGN(4);
+               __etext_l1 = .;
+       } >l1_code AT>ram
+       __stext_l1_lma = LOADADDR(.text_l1);
+
+       .data_l1 :
+       {
+               . = ALIGN(4);
+               __sdata_l1 = .;
+               *(.l1.data)
+               *(.l1.bss)
+               . = ALIGN(4);
+               __edata_l1 = .;
+       } >l1_data AT>ram
+       __sdata_l1_lma = LOADADDR(.data_l1);
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.sbss) *(.scommon)
+               *(.dynbss)
+               *(.bss .bss.*)
+               *(COMMON)
+               __bss_end = .;
+       } >ram
+}
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
new file mode 100644 (file)
index 0000000..49dbe77
--- /dev/null
@@ -0,0 +1,339 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+#ifdef CONFIG_VIDEO
+
+#define DMA_SIZE16     2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include <asm/bfin_logo_230x230.h>
+
+#define LCD_X_RES              480     /*Horizontal Resolution */
+#define LCD_Y_RES              272     /* Vertical Resolution */
+
+#define LCD_BPP                        24      /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE         (LCD_BPP / 8)
+#define        DMA_BUS_SIZE            32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/*     -- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency     1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period              TH - 525 - Clock
+ * Pulse width                 THp - 41 - Clock
+ * Horizontal period   THd - 480 - Clock
+ * Back porch          THb - 2 - Clock
+ * Front porch                 THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period              TV - 286 - Line
+ * Pulse width                 TVp - 10 - Line
+ * Vertical period     TVd - 272 - Line
+ * Back porch          TVb - 2 - Line
+ * Front porch                 TVf - 2 - Line
+ */
+
+#define        LCD_CLK                 (8*1000*1000)   /* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT            LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT            LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE              525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME             286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL          41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL         EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY            43
+
+/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB          (EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF         (EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY            12
+
+#define EPPI_CLIP              0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL           (0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+       u32 sclk = get_sclk();
+
+       /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+       return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+       u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+       bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+       bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+       bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+       bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+       bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+       bfin_write_EPPI0_FRAME(EPPI_FRAME);
+       bfin_write_EPPI0_LINE(EPPI_LINE);
+
+       bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+       bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+       bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+       bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+       bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+       bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+                                RGB_FMT_EN);
+#else
+       bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+                                ~RGB_FMT_EN);
+#endif
+
+}
+
+#define               DEB2_URGENT  0x2000      /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+
+#if defined(CONFIG_DEB_DMA_URGENT)
+       *pEBIU_DDRQUE |= DEB2_URGENT;
+#endif
+
+       *pDMA12_START_ADDR = dst;
+
+       /* X count */
+       *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
+       *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
+
+       /* Y count */
+       *pDMA12_Y_COUNT = LCD_Y_RES;
+       *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
+
+       /* DMA Config */
+       *pDMA12_CONFIG = WDSIZE_32 |    /* 32 bit DMA */
+           DMA2D |             /* 2D DMA */
+           FLOW_AUTO;          /* autobuffer mode */
+}
+
+void Init_Ports(void)
+{
+       *pPORTF_MUX = 0x00000000;
+       *pPORTF_FER |= 0xFFFF;  /* PPI0..15 */
+
+       *pPORTG_MUX &=
+           ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
+             PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
+       *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4;     /* CLK, FS1, FS2, PPI16..17  */
+
+#if !defined(CONFIG_VIDEO_RGB666)
+       *pPORTD_MUX &=
+           ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
+             PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
+       *pPORTD_MUX |=
+           (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 |
+            PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
+       *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5;       /* PPI18..23  */
+#endif
+
+       *pPORTE_FER &= ~PE3;    /* DISP */
+       *pPORTE_DIR_SET = PE3;
+       *pPORTE_SET = PE3;
+
+}
+
+void EnableDMA(void)
+{
+       *pDMA12_CONFIG |= DMAEN;
+}
+
+void DisableDMA(void)
+{
+       *pDMA12_CONFIG &= ~DMAEN;
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+       bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+       bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+       Init_Ports();
+       Init_DMA(dst);
+       EnableDMA();
+       Init_PPI();
+       EnablePPI();
+
+       return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+       if (dcache_status())
+               blackfin_dcache_flush_range(logo->data,
+                                           logo->data + logo->size);
+
+       bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+       /* Setup destination start address */
+       bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+                                     + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+       /* Setup destination xcount */
+       bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+       /* Setup destination xmodify */
+       bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+       /* Setup destination ycount */
+       bfin_write_MDMA_D0_Y_COUNT(logo->height);
+       /* Setup destination ymodify */
+       bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
+                                   DMA_SIZE16);
+
+       /* Setup Source start address */
+       bfin_write_MDMA_S0_START_ADDR(logo->data);
+       /* Setup Source xcount */
+       bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+       /* Setup Source xmodify */
+       bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+       /* Setup Source ycount */
+       bfin_write_MDMA_S0_Y_COUNT(logo->height);
+       /* Setup Source ymodify */
+       bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+       /* Enable source DMA */
+       bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+       SSYNC();
+       bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+       while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
+
+       bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
+                                     | DMA_ERR);
+       bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
+                                     | DMA_ERR);
+
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+int drv_video_init(void)
+{
+       int error, devices = 1;
+       device_t videodev;
+
+       u8 *dst;
+       u32 fbmem_size =
+           LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+       dst = malloc(fbmem_size);
+
+       if (dst == NULL) {
+               printf("Failed to alloc FB memory\n");
+               return -1;
+       }
+#ifdef EASYLOGO_ENABLE_GZIP
+       unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+       unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+       if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+               puts("Failed to decompress logo\n");
+               free(dst);
+               return -1;
+       }
+       bfin_logo.data = data;
+#endif
+
+       memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
+              fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+       dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+                   (LCD_X_RES - bfin_logo.width) / 2,
+                   (LCD_Y_RES - bfin_logo.height) / 2);
+
+       video_init(dst);        /* Video initialization */
+
+       memset(&videodev, 0, sizeof(videodev));
+
+       strcpy(videodev.name, "video");
+       videodev.ext = DEV_EXT_VIDEO;   /* Video extensions */
+       videodev.flags = DEV_FLAGS_SYSTEM;      /* No Output */
+       videodev.putc = video_putc;     /* 'putc' function */
+       videodev.puts = video_puts;     /* 'puts' function */
+
+       error = device_register(&videodev);
+
+       return (error == 0) ? devices : error;
+}
+
+#endif
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
new file mode 100644 (file)
index 0000000..b08b770
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * U-boot - Configuration file for cm-bf548 board
+ */
+
+#ifndef __CONFIG_CM_BF548_H__
+#define __CONFIG_CM_BF548_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf548-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *     CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *     SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz                                  */
+#define CONFIG_CLKIN_HZ                        25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN            */
+/*                                                1 = CLKIN / 2                */
+#define CONFIG_CLKIN_HALF              0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */
+/*                                                1 = bypass PLL       */
+#define CONFIG_PLL_BYPASS              0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL             */
+/* Values can range from 0-63 (where 0 means 64)                       */
+#define CONFIG_VCO_MULT                        21
+/* CCLK_DIV controls the core clock divider                            */
+/* Values can be 1, 2, 4, or 8 ONLY                                    */
+#define CONFIG_CCLK_DIV                        1
+/* SCLK_DIV controls the system clock divider                          */
+/* Values can range from 1-15                                          */
+#define CONFIG_SCLK_DIV                        4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH    10
+#define CONFIG_MEM_SIZE                64
+
+#define CONFIG_EBIU_DDRCTL0_VAL        0x218A83FE
+#define CONFIG_EBIU_DDRCTL1_VAL        0x20022222
+#define CONFIG_EBIU_DDRCTL2_VAL        0x00000021
+
+/* Default bank mapping:
+ *     Async Bank 0 - 32MB Burst Flash
+ *     Async Bank 1 - Ethernet
+ *     Async Bank 2 - Nothing
+ *     Async Bank 3 - Nothing
+ */
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL        0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL        0xFFC27BB0
+#define CONFIG_EBIU_FCTL_VAL   (BCLK_4)
+#define CONFIG_EBIU_MODE_VAL   (B0MODE_FLASH)
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN  (640 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK       1
+#define CONFIG_DRIVER_SMC911X  1
+#define CONFIG_DRIVER_SMC911X_BASE     0x24000000
+#define CONFIG_DRIVER_SMC911X_16_BIT
+#define CONFIG_HOSTNAME                cm-bf548
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR      02:80:ad:24:31:91 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE          0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      259
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR                0x20008000
+#define CONFIG_ENV_OFFSET      0x8000
+#define CONFIG_ENV_SIZE                0x8000
+#define ENV_IS_EMBEDDED_CUSTOM
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C    1
+#define CONFIG_HARD_I2C                1
+#define CONFIG_SYS_I2C_SPEED   50000
+#define CONFIG_SYS_I2C_SLAVE   0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE    1
+
+#ifndef __ADSPBF542__
+/* Don't waste time transferring a logo over the UART */
+# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+#  define CONFIG_VIDEO
+# endif
+# define CONFIG_DEB_DMA_URGENT
+#endif
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11       /* Should > = 11 */
+#define FLASH_END_POST_BLOCK   71       /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif