armv7: adapt omap4 to the new cache maintenance framework

adapt omap4 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index fcd29a73e0e51dc7ffaf64896d770073a20782e0..de4cc2ab84acd2926f5bb552bc6c7ef7819adda2 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -127,3 +127,15 @@ int arch_cpu_init(void)
        set_muxconf_regs();
        return 0;
 }
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+       set_pl310_ctrl_reg(1);
+}
+
+void v7_outer_cache_disable(void)
+{
+       set_pl310_ctrl_reg(0);
+}
+#endif

diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 026dfa46ef995c6366f921ae9d6f80409bea1028..6abfbbaa13115362b189595030d14e2bd98d98bb 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -45,3 +45,12 @@ lowlevel_init:
         */
        bl      s_init
        pop     {ip, pc}
+
+.globl set_pl310_ctrl_reg
+set_pl310_ctrl_reg:
+       PUSH    {r4-r11, lr}    @ save registers - ROM code may pollute
+                               @ our registers
+       LDR     r12, =0x102     @ Set PL310 control register - value in R0
+       .word   0xe1600070      @ SMC #0 - hand assembled because -march=armv5
+                               @ call ROM Code API to set control register
+       POP     {r4-r11, pc}

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4813e9e21d97f9d527c47d074c1d1269b0b974a6..4fa4f4b2db26941e0ff32ba836e86e9fc98f8a49 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,11 +31,11 @@ struct omap_sysinfo {
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void invalidate_dcache(u32);
 void set_muxconf_regs(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
+void set_pl310_ctrl_reg(u32 val);
 
 extern const struct omap_sysinfo sysinfo;
 

diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index ab878f9eb73bd0cf966a3e64edd816014d933e5d..1daffb7e933564d51ea38a82897c754138481b0b 100644 (file)
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -45,9 +45,6 @@
 #define CONFIG_DISPLAY_CPUINFO         1
 #define CONFIG_DISPLAY_BOARDINFO       1
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_L2CACHE_OFF                 1
-
 /* Clock Defines */
 #define V_OSCK                 38400000        /* Clock output from T2 */
 #define V_SCLK                   V_OSCK
@@ -235,4 +232,9 @@
                                         CONFIG_SYS_INIT_RAM_SIZE - \
                                         GENERATED_GBL_DATA_SIZE)
 
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310            1
+#define CONFIG_SYS_PL310_BASE  0x48242000
+#endif
+
 #endif /* __CONFIG_H */

diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 0ac407aad336e241063b06e1d7e092b1bbf1b317..68ffa87f1cf59ab9ecbbbff0036fb1719e3f3409 100644 (file)
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -46,9 +46,6 @@
 #define CONFIG_DISPLAY_CPUINFO         1
 #define CONFIG_DISPLAY_BOARDINFO       1
 
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_L2CACHE_OFF                 1
-
 /* Clock Defines */
 #define V_OSCK                 38400000        /* Clock output from T2 */
 #define V_SCLK                   V_OSCK
@@ -241,4 +238,9 @@
                                         CONFIG_SYS_INIT_RAM_SIZE - \
                                         GENERATED_GBL_DATA_SIZE)
 
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310            1
+#define CONFIG_SYS_PL310_BASE  0x48242000
+#endif
+
 #endif /* __CONFIG_H */