[MIPS] Rename Alchemy processor configs into CONFIG_SOC_*

CONFIG_SOC_AU1X00

  Common Alchemy Au1x00 stuff. All Alchemy processor based machines
  need to have this config as a system type specifier.

CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550

  Machine type specifiers. Each port should have one of aboves.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index d70c5fe9875cf4984e76876790a40aa26c541798..aeb96622812944072bd7c9da7234041cc30455b8 100644 (file)
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -23,7 +23,7 @@
  */
 #include <config.h>
 
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
 
 #if defined(CFG_DISCOVER_PHY)
 #error "PHY not supported yet"
@@ -33,20 +33,20 @@
 
 /* I assume ethernet behaves like au1000 */
 
-#ifdef CONFIG_AU1000
+#ifdef CONFIG_SOC_AU1000
 /* Base address differ between cpu:s */
 #define ETH0_BASE AU1000_ETH0_BASE
 #define MAC0_ENABLE AU1000_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1100
+#ifdef CONFIG_SOC_AU1100
 #define ETH0_BASE AU1100_ETH0_BASE
 #define MAC0_ENABLE AU1100_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1500
+#ifdef CONFIG_SOC_AU1500
 #define ETH0_BASE AU1500_ETH0_BASE
 #define MAC0_ENABLE AU1500_MAC0_ENABLE
 #else
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 #define ETH0_BASE AU1550_ETH0_BASE
 #define MAC0_ENABLE AU1550_MAC0_ENABLE
 #else
@@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){
        return 1;
 }
 
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */

diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c
index 42c668ee3d373a54e5609b3104742d8aa2e9b9f2..ec10ac03708fc30b52171292ed999b98c4b5a99e 100644 (file)
--- a/cpu/mips/au1x00_serial.c
+++ b/cpu/mips/au1x00_serial.c
@@ -27,7 +27,7 @@
 
 #include <config.h>
 
-#ifdef CONFIG_AU1X00
+#ifdef CONFIG_SOC_AU1X00
 
 #include <common.h>
 #include <asm/au1x00.h>
@@ -132,4 +132,4 @@ int serial_tstc (void)
        }
        return 0;
 }
-#endif /* CONFIG_SERIAL_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */

diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c
index dbf72dc6f8c9fb9b5d50cd8aff23c861b1613517..e03b1255ecb52483065ec831a097a7f063dca69d 100644 (file)
--- a/cpu/mips/au1x00_usb_ohci.c
+++ b/cpu/mips/au1x00_usb_ohci.c
@@ -35,7 +35,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI)
 
 /* #include <pci.h> no PCI on the AU1x00 */
 

diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 767804c71f946233d76784fb8c87d89384a7649c..3a1e6d615fa95863c1a967823c544e76cc510e04 100644 (file)
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -131,13 +131,13 @@
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
 /* We use a 36 bit physical address map here and
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else  /* !CONFIG_AU1X00 */
+#else  /* !CONFIG_SOC_AU1X00 */
 #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
-#endif /* CONFIG_AU1X00 */
+#endif /* CONFIG_SOC_AU1X00 */
 #endif /* __ASSEMBLY__ */
 
 /*

diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 6a33197f6cf9db1f950d9a0283a949ce0b5d188e..2a948e8fe7634273b76263b310ec242d5a761ca8 100644 (file)
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x)
 #define CP0_DEBUG              $23
 
 /* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 
 #define MEM_SDMODE0                0xB4000800
 #define MEM_SDMODE1                0xB4000808
@@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000888
 #define MEM_SDWRMD2                0xB4000890
 
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
@@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 45ff1e73055eec73b7065f4d3c363926a0ec11c7..0e10396dfa9659e91f7aeb871d3cba23d0f9d014 100644 (file)
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,21 +30,21 @@
 
 #define CONFIG_MIPS32          1  /* MIPS32 CPU core   */
 #define CONFIG_DBAU1X00                1
-#define CONFIG_AU1X00          1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00      1  /* alchemy series cpu */
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */
-#define CONFIG_AU1000          1
+#define CONFIG_SOC_AU1000      1
 #else
 #ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100          1
+#define CONFIG_SOC_AU1100      1
 #else
 #ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500          1
+#define CONFIG_SOC_AU1500      1
 #else
 #ifdef CONFIG_DBAU1550
 /* Cabernet */
-#define CONFIG_AU1550           1
+#define CONFIG_SOC_AU1550      1
 #else
 #error "No valid board set"
 #endif

diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index 23618db667d1a788b696a4b7846cae06ba0c6a09..c2d6ca70a5432557381d85943a2edda4fabb3140 100644 (file)
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -30,9 +30,9 @@
 
 #define CONFIG_MIPS32          1  /* MIPS32 CPU core   */
 #define CONFIG_GTH2            1
-#define CONFIG_AU1X00          1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00      1  /* alchemy series cpu */
 
-#define CONFIG_AU1000          1
+#define CONFIG_SOC_AU1000      1
 
 #define CONFIG_MISC_INIT_R     1
 

diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 181cd11b86eddc23530d9ef4ad78a3e824451f5f..2caa64173c8bd30effe6d2411c1a712cfe11f0e3 100644 (file)
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -30,16 +30,16 @@
 
 #define CONFIG_MIPS32          1  /* MIPS32 CPU core   */
 #define CONFIG_PB1X00          1
-#define CONFIG_AU1X00          1  /* alchemy series cpu */
+#define CONFIG_SOC_AU1X00      1  /* alchemy series cpu */
 
 #ifdef CONFIG_PB1000
-#define CONFIG_AU1000          1
+#define CONFIG_SOC_AU1000      1
 #else
 #ifdef CONFIG_PB1100
-#define CONFIG_AU1100          1
+#define CONFIG_SOC_AU1100      1
 #else
 #ifdef CONFIG_PB1500
-#define CONFIG_AU1500          1
+#define CONFIG_SOC_AU1500      1
 #else
 #error "No valid board set"
 #endif