]> git.sur5r.net Git - u-boot/commitdiff
mx6: add support for el6x board
authorStefano Babic <sbabic@denx.de>
Mon, 6 Jun 2016 09:19:42 +0000 (11:19 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Jul 2016 15:58:48 +0000 (17:58 +0200)
Custom Board based on MX6 Dual, 1GB RAM and eMMC.

There are two variants of the board with and without
PCIe (ZC5202 and ZC5601).

Signed-off-by: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/armv7/mx6/Kconfig
board/el/el6x/Kconfig [new file with mode: 0644]
board/el/el6x/MAINTAINERS [new file with mode: 0644]
board/el/el6x/Makefile [new file with mode: 0644]
board/el/el6x/el6x.c [new file with mode: 0644]
configs/zc5202_defconfig [new file with mode: 0644]
configs/zc5601_defconfig [new file with mode: 0644]
include/configs/el6x_common.h [new file with mode: 0644]
include/configs/zc5202.h [new file with mode: 0644]
include/configs/zc5601.h [new file with mode: 0644]

index 663f970c4c9f88fa66d269d980ebed63f1d81e5a..01117abc068b71a8b096b0dd627eb4c91a6d5d00 100644 (file)
@@ -178,6 +178,18 @@ config TARGET_XPRESS
        select DM_THERMAL
        select SUPPORT_SPL
 
+config TARGET_ZC5202
+       bool "zc5202"
+       select SUPPORT_SPL
+       select DM
+       select DM_THERMAL
+
+config TARGET_ZC5601
+       bool "zc5601"
+       select SUPPORT_SPL
+       select DM
+       select DM_THERMAL
+
 endchoice
 
 config SYS_SOC
@@ -192,6 +204,7 @@ source "board/boundary/nitrogen6x/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig
new file mode 100644 (file)
index 0000000..aa9bf25
--- /dev/null
@@ -0,0 +1,25 @@
+if TARGET_ZC5202
+
+config SYS_BOARD
+       default "el6x"
+
+config SYS_VENDOR
+       default "el"
+
+config SYS_CONFIG_NAME
+       default "zc5202"
+
+endif
+
+if TARGET_ZC5601
+
+config SYS_BOARD
+       default "el6x"
+
+config SYS_VENDOR
+       default "el"
+
+config SYS_CONFIG_NAME
+       default "zc5601"
+
+endif
diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS
new file mode 100644 (file)
index 0000000..9a40010
--- /dev/null
@@ -0,0 +1,8 @@
+EL6X BOARD
+M:     Stefano Babic <sbabic@denx.de>
+S:     Maintained
+F:     board/el/el6x/
+F:     include/configs/zc5202.h
+F:     include/configs/zc5601.h
+F:     configs/zc5202_defconfig
+F:     configs/zc5601_defconfig
diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile
new file mode 100644 (file)
index 0000000..48d5ad9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) Stefano Babic <sbabic@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := el6x.o
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
new file mode 100644 (file)
index 0000000..3b0fb32
--- /dev/null
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Based on other i.MX6 boards
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <asm/arch/mx6-ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OPEN_PAD_CTRL  (PAD_CTL_ODE  | PAD_CTL_DSE_DISABLE | (0 << 12))
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |             \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
+       PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC       1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define ETH_PHY_RESET  IMX_GPIO_NR(2, 4)
+
+int dram_init(void)
+{
+       gd->ram_size = imx_ddr_size();
+
+       return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+       MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+       imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_TARGET_ZC5202
+iomux_v3_cfg_t const enet_pads[] = {
+       MX6_PAD_GPIO_18__ENET_RX_CLK            | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_COL2__ENET_RX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_COL0__ENET_RX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+       MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_GPIO_19__ENET_TX_ER             | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_ROW2__ENET_TX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_ROW0__ENET_TX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       /* Switch Reset */
+       MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+       /* Switch Interrupt */
+       MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* use CRS and COL pads as GPIOs */
+       MX6_PAD_KEY_COL3__GPIO4_IO12            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
+       MX6_PAD_KEY_ROW1__GPIO4_IO09            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
+
+};
+
+#define BOARD_NAME "EL6x-ZC5202"
+#else
+iomux_v3_cfg_t const enet_pads[] = {
+       MX6_PAD_ENET_MDIO__ENET_MDIO    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_MDC__ENET_MDC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+       MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#define BOARD_NAME "EL6x-ZC5601"
+#endif
+
+static void setup_iomux_enet(void)
+{
+       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+#ifdef CONFIG_TARGET_ZC5202
+       /* set CRS and COL to input */
+       gpio_direction_input(IMX_GPIO_NR(4, 9));
+       gpio_direction_input(IMX_GPIO_NR(4, 12));
+
+       /* Reset Switch */
+       gpio_direction_output(ETH_PHY_RESET , 0);
+       mdelay(2);
+       gpio_set_value(ETH_PHY_RESET, 1);
+#endif
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+#ifdef CONFIG_TARGET_ZC5202
+iomux_v3_cfg_t const ecspi1_pads[] = {
+       MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT23__GPIO5_IO17  | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_DISP0_DAT15__GPIO5_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi3_pads[] = {
+       MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT7__GPIO4_IO28   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT8__GPIO4_IO29   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT9__GPIO4_IO30   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT10__GPIO4_IO31  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+#endif
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+       MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D20__GPIO3_IO20  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+               ? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
+static void setup_spi(void)
+{
+#ifdef CONFIG_TARGET_ZC5202
+       gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
+       gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
+       gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
+       gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+#endif
+
+       gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
+       gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
+       imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+
+       enable_spi_clk(true, 3);
+}
+#endif
+
+static struct i2c_pads_info i2c_pad_info1 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
+               .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
+               .gp = IMX_GPIO_NR(2, 30)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+               .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+               .gp = IMX_GPIO_NR(4, 13)
+       }
+};
+
+static struct i2c_pads_info i2c_pad_info2 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
+               .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
+               .gp = IMX_GPIO_NR(1, 5)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
+               .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
+               .gp = IMX_GPIO_NR(7, 11)
+       }
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_GPIO_4__SD2_CD_B        | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+       {USDHC2_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               break;
+       case USDHC4_BASE_ADDR:
+               ret = 1; /* eMMC/uSDHC4 is always present */
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+       int ret;
+       int i;
+
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * mmc0                    SD2
+        * mmc1                    SD3
+        * mmc2                    eMMC
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                              "(%d) then supported by the board (%d)\n",
+                              i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+                       return -EINVAL;
+               }
+
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+#else
+       struct src *psrc = (struct src *)SRC_BASE_ADDR;
+       unsigned reg = readl(&psrc->sbmr1) >> 11;
+
+       /*
+        * Upon reading BOOT_CFG register the following map is done:
+        * Bit 11 and 12 of BOOT_CFG register can determine the current
+        * mmc port
+        * 0x1                  SD1
+        * 0x2                  SD2
+        * 0x3                  SD4
+        */
+
+       switch (reg & 0x3) {
+       case 0x1:
+               imx_iomux_v3_setup_multiple_pads(
+                       usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+               usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+               break;
+       case 0x3:
+               imx_iomux_v3_setup_multiple_pads(
+                       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+               usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+               usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+               gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+               break;
+       }
+
+       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+
+}
+#endif
+
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+       return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       setup_iomux_enet();
+       enable_enet_clk(1);
+
+       return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+
+       setup_iomux_uart();
+       setup_spi();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+       setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+       return 0;
+}
+
+int power_init_board(void)
+{
+       struct pmic *p;
+       int ret;
+       unsigned int reg;
+
+       ret = power_pfuze100_init(I2C_PMIC);
+       if (ret)
+               return ret;
+
+       p = pmic_get("PFUZE100");
+       ret = pmic_probe(p);
+       if (ret)
+               return ret;
+
+       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+       /* Increase VGEN3 from 2.5 to 2.8V */
+       pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
+       reg &= ~LDO_VOL_MASK;
+       reg |= LDOB_2_80V;
+       pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+       /* Increase VGEN5 from 2.8 to 3V */
+       pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+       reg &= ~LDO_VOL_MASK;
+       reg |= LDOB_3_00V;
+       pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+       /* Set SW1AB stanby volage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+       reg &= ~SW1x_STBY_MASK;
+       reg |= SW1x_0_975V;
+       pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+       /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+       reg &= ~SW1xCONF_DVSSPEED_MASK;
+       reg |= SW1xCONF_DVSSPEED_4US;
+       pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+       /* Set SW1C standby voltage to 0.975V */
+       pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+       reg &= ~SW1x_STBY_MASK;
+       reg |= SW1x_0_975V;
+       pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+       /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+       pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+       reg &= ~SW1xCONF_DVSSPEED_MASK;
+       reg |= SW1xCONF_DVSSPEED_4US;
+       pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+       return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+       /* 4 bit bus width */
+       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+       /* 8 bit bus width */
+       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+       {NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+       add_board_boot_modes(board_boot_modes);
+#endif
+
+       setenv("board_name", BOARD_NAME);
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: ");
+       puts(BOARD_NAME "\n");
+
+       return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+       .dram_sdclk_0 =  0x00020030,
+       .dram_sdclk_1 =  0x00020030,
+       .dram_cas =  0x00020030,
+       .dram_ras =  0x00020030,
+       .dram_reset =  0x00020030,
+       .dram_sdcke0 =  0x00003000,
+       .dram_sdcke1 =  0x00003000,
+       .dram_sdba2 =  0x00000000,
+       .dram_sdodt0 =  0x00003030,
+       .dram_sdodt1 =  0x00003030,
+       .dram_sdqs0 =  0x00000030,
+       .dram_sdqs1 =  0x00000030,
+       .dram_sdqs2 =  0x00000030,
+       .dram_sdqs3 =  0x00000030,
+       .dram_sdqs4 =  0x00000030,
+       .dram_sdqs5 =  0x00000030,
+       .dram_sdqs6 =  0x00000030,
+       .dram_sdqs7 =  0x00000030,
+       .dram_dqm0 =  0x00020030,
+       .dram_dqm1 =  0x00020030,
+       .dram_dqm2 =  0x00020030,
+       .dram_dqm3 =  0x00020030,
+       .dram_dqm4 =  0x00020030,
+       .dram_dqm5 =  0x00020030,
+       .dram_dqm6 =  0x00020030,
+       .dram_dqm7 =  0x00020030,
+};
+
+const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+       .grp_ddr_type =  0x000C0000,
+       .grp_ddrmode_ctl =  0x00020000,
+       .grp_ddrpke =  0x00000000,
+       .grp_addds =  0x00000030,
+       .grp_ctlds =  0x00000030,
+       .grp_ddrmode =  0x00020000,
+       .grp_b0ds =  0x00000030,
+       .grp_b1ds =  0x00000030,
+       .grp_b2ds =  0x00000030,
+       .grp_b3ds =  0x00000030,
+       .grp_b4ds =  0x00000030,
+       .grp_b5ds =  0x00000030,
+       .grp_b6ds =  0x00000030,
+       .grp_b7ds =  0x00000030,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+       .p0_mpwldectrl0 =  0x001F001F,
+       .p0_mpwldectrl1 =  0x001F001F,
+       .p1_mpwldectrl0 =  0x00440044,
+       .p1_mpwldectrl1 =  0x00440044,
+       .p0_mpdgctrl0 =  0x434B0350,
+       .p0_mpdgctrl1 =  0x034C0359,
+       .p1_mpdgctrl0 =  0x434B0350,
+       .p1_mpdgctrl1 =  0x03650348,
+       .p0_mprddlctl =  0x4436383B,
+       .p1_mprddlctl =  0x39393341,
+       .p0_mpwrdlctl =  0x35373933,
+       .p1_mpwrdlctl =  0x48254A36,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mem_ddr = {
+       .mem_speed = 1600,
+       .density = 2,
+       .width = 16,
+       .banks = 8,
+       .rowaddr = 14,
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       writel(0x00C03F3F, &ccm->CCGR0);
+       writel(0x0030FC03, &ccm->CCGR1);
+       writel(0x0FFFC000, &ccm->CCGR2);
+       writel(0x3FF00000, &ccm->CCGR3);
+       writel(0x00FFF300, &ccm->CCGR4);
+       writel(0x0F0000C3, &ccm->CCGR5);
+       writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* enable AXI cache for VDOA/VPU/IPU */
+       writel(0xF00000CF, &iomux->gpr[4]);
+       /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+       writel(0x007F007F, &iomux->gpr[6]);
+       writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * This section requires the differentiation between iMX6 Sabre boards, but
+ * for now, it will configure only for the mx6q variant.
+ */
+static void spl_dram_init(void)
+{
+       struct mx6_ddr_sysinfo sysinfo = {
+               /* width of data bus:0=16,1=32,2=64 */
+               .dsize = 2,
+               /* config for full 4GB range so that get_mem_size() works */
+               .cs_density = 32, /* 32Gb per CS */
+               /* single chip select */
+               .ncs = 1,
+               .cs1_mirror = 0,
+               .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
+               .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
+               .walat = 1,     /* Write additional latency */
+               .ralat = 5,     /* Read additional latency */
+               .mif3_mode = 3, /* Command prediction working mode */
+               .bi_on = 1,     /* Bank interleaving enabled */
+               .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
+               .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+               .ddr_type = DDR_TYPE_DDR3,
+       };
+
+       mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+       mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+       /* setup AIPS and disable watchdog */
+       arch_cpu_init();
+
+       ccgr_init();
+       gpr_init();
+
+       /* iomux and setup of i2c */
+       board_early_init_f();
+
+       /* setup GP timer */
+       timer_init();
+
+       /* UART clocks enabled and gd valid - init serial console */
+       preloader_console_init();
+
+       /* DDR initialization */
+       spl_dram_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       /* load/boot image from boot device */
+       board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
new file mode 100644 (file)
index 0000000..2ebeec0
--- /dev/null
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_ZC5202=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
new file mode 100644 (file)
index 0000000..a52ae6f
--- /dev/null
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_ZC5601=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
new file mode 100644 (file)
index 0000000..55ef612
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __EL6Q_COMMON_CONFIG_H
+#define __EL6Q_COMMON_CONFIG_H
+
+#define CONFIG_BOARD_NAME              EL6Q
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     (64 * 1024)
+#define CONFIG_SPL_SPI_LOAD
+#include "imx6_spl.h"
+#endif
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+/* I2C config */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED                   100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* Commands */
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS          3
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                20000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MXC_UART_BASE   UART2_BASE
+#define CONFIG_BAUDRATE             115200
+
+/* Command definition */
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOARD_NAME      EL6Q
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS                                               \
+       "board="__stringify(CONFIG_BOARD_NAME)"\0"                              \
+       "cma_size="__stringify(EL6Q_CMA_SIZE)"\0"                               \
+       "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0"                     \
+       "console=" CONFIG_CONSOLE_DEV "\0"                                      \
+       "fdtfile=undefined\0" \
+       "fdt_high=0xffffffff\0" \
+       "fdt_addr_r=0x18000000\0" \
+       "fdt_addr=0x18000000\0" \
+       "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0"                  \
+       "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+       "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+       "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+       BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 0) \
+       func(MMC, mmc, 1) \
+       func(PXE, PXE, na) \
+       func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+          "run findfdt; " \
+          "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10800000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV         1
+#define CONFIG_SYS_MMC_ENV_PART                2
+#define CONFIG_ENV_OFFSET              0x0
+#endif
+
+#endif                         /* __EL6Q_COMMON_CONFIG_H */
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
new file mode 100644 (file)
index 0000000..073a42c
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __EL_ZC5202_H
+#define __EL_ZC5202_H
+
+#define CONFIG_MXC_UART_BASE   UART2_BASE
+#define CONFIG_CONSOLE_DEV             "ttymxc1"
+#define CONFIG_MMCROOT                 "/dev/mmcblk0p2"
+
+#define CONFIG_DEFAULT_FDT_FILE        "imx6q-zc5202.dtb"
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                           ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE                    MII100
+#define CONFIG_ETHPRIME                                "FEC"
+#define CONFIG_FEC_MXC_PHYADDR                 0
+#define CONFIG_MV88E6352_SWITCH
+
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+
+#endif                         /*__EL6Q_CONFIG_H */
diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h
new file mode 100644 (file)
index 0000000..28b9c6b
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __EL_ZC5601_H
+#define __EL_ZC5601_H
+
+
+#define CONFIG_MXC_UART_BASE   UART2_BASE
+#define CONFIG_CONSOLE_DEV             "ttymxc1"
+#define CONFIG_MMCROOT                 "/dev/mmcblk0p1"
+
+#define CONFIG_DEFAULT_FDT_FILE        "imx6q-zc5601.dtb"
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                           ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE                    RGMII
+#define CONFIG_ETHPRIME                                "FEC"
+#define CONFIG_FEC_MXC_PHYADDR                 0x10
+#define CONFIG_PHYLIB
+#define CONFIG_FEC_FIXED_SPEED                 1000 /* No autoneg, fix Gb */
+
+#endif                         /*__EL6Q_CONFIG_H */