ARM64: zynqmp: Read RAM information from DT

Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.

dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.

Memory test start/end were changed to DDR location to let memtest still
compiled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 44d347ed3bf0e857244ebb2971bf7990db73432e..0f44b04c1efa85231e7640450cc6cae9955468dd 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -50,12 +50,133 @@ int board_early_init_r(void)
        return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+                              const u32 *cell, int n)
+{
+       int i = 0, b, banks;
+       int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+       int address_cells = fdt_address_cells(fdt, parent_offset);
+       int size_cells = fdt_size_cells(fdt, parent_offset);
+       char *p = buf;
+       phys_addr_t val;
+       phys_size_t vals;
+
+       debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+             __func__, address_cells, size_cells, buf, cell);
+
+       /* Check memory bank setup */
+       banks = n % (address_cells + size_cells);
+       if (banks)
+               panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+                     n, address_cells, size_cells);
+
+       banks = n / (address_cells + size_cells);
+
+       for (b = 0; b < banks; b++) {
+               debug("%s: Bank #%d:\n", __func__, b);
+               if (address_cells == 2) {
+                       val = cell[i + 1];
+                       val <<= 32;
+                       val |= cell[i];
+                       val = fdt64_to_cpu(val);
+                       debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+                             __func__, val, p, &cell[i]);
+                       *(phys_addr_t *)p = val;
+               } else {
+                       debug("%s: addr32=%x, ptr=%p\n",
+                             __func__, fdt32_to_cpu(cell[i]), p);
+                       *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+               }
+               p += sizeof(phys_addr_t);
+               i += address_cells;
+
+               debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+                     sizeof(phys_addr_t));
+
+               if (size_cells == 2) {
+                       vals = cell[i + 1];
+                       vals <<= 32;
+                       vals |= cell[i];
+                       vals = fdt64_to_cpu(vals);
+
+                       debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+                             __func__, vals, p, &cell[i]);
+                       *(phys_size_t *)p = vals;
+               } else {
+                       debug("%s: size32=%x, ptr=%p\n",
+                             __func__, fdt32_to_cpu(cell[i]), p);
+                       *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+               }
+               p += sizeof(phys_size_t);
+               i += size_cells;
+
+               debug("%s: ps=%p, i=%x, size=%zu\n",
+                     __func__, p, i, sizeof(phys_size_t));
+       }
+
+       /* Return the first address size */
+       return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+       int bank;
+
+       memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+       for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+               debug("Bank #%d: start %llx\n", bank,
+                     (unsigned long long)gd->bd->bi_dram[bank].start);
+               debug("Bank #%d: size %llx\n", bank,
+                     (unsigned long long)gd->bd->bi_dram[bank].size);
+       }
+}
+
+int dram_init(void)
+{
+       int node, len;
+       const void *blob = gd->fdt_blob;
+       const u32 *cell;
+
+       memset(&tmp, 0, sizeof(tmp));
+
+       /* find or create "/memory" node. */
+       node = fdt_subnode_offset(blob, 0, "memory");
+       if (node < 0) {
+               printf("%s: Can't get memory node\n", __func__);
+               return node;
+       }
+
+       /* Get pointer to cells and lenght of it */
+       cell = fdt_getprop(blob, node, "reg", &len);
+       if (!cell) {
+               printf("%s: Can't get reg property\n", __func__);
+               return -1;
+       }
+
+       gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+       debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
+
+       return 0;
+}
+#else
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
        return 0;
 }
+#endif
 
 void reset_cpu(ulong addr)
 {

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index ed47283c1766bad76faee3289fc3b6762307ac42..4062e01824e3ef19335b32f75042c9c7b6d14f8f 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -26,8 +26,11 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
 
-#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END         CONFIG_SYS_SDRAM_SIZE
+#ifndef CONFIG_NR_DRAM_BANKS
+# define CONFIG_NR_DRAM_BANKS          2
+#endif
+#define CONFIG_SYS_MEMTEST_START       0
+#define CONFIG_SYS_MEMTEST_END         1000
 
 /* Have release address at the end of 256MB for now */
 #define CPU_RELEASE_ADDR       0xFFFFFF0
@@ -39,7 +42,7 @@
 # define CONFIG_IDENT_STRING           " Xilinx ZynqMP"
 #endif
 
-#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_TEXT_BASE
 
 /* Flat Device Tree Definitions */
 

diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 337312e58c0a72213b133ad959b7e5c005481e41..aa58b62531d4b76d96aae9b6424af6794cb4c474 100644 (file)
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -22,11 +22,6 @@
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
                                 ZYNQMP_USB1_XHCI_BASEADDR}
 
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_SDRAM_BASE          0
-#define CONFIG_SYS_SDRAM_SIZE          0x40000000
-
 #define COUNTER_FREQUENCY      4000000
 
 #include <configs/xilinx_zynqmp.h>