]> git.sur5r.net Git - u-boot/commitdiff
mxc: Define architecture identifier
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Mon, 13 Aug 2012 07:27:58 +0000 (07:27 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:30 +0000 (14:58 +0200)
Define ARCH_MXC for i.MX devices. This is useful to identify features or
behaviors common to all i.MX SoCs.

The i.MX28 is omitted because its architecture is a bit different (like imx/mxc
vs. mxs in Linux).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
arch/arm/include/asm/arch-imx/imx-regs.h
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx27/imx-regs.h
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h

index ec94ba913f44ee1eb21d017929bf1e39f2e4c298..4de0779d28bebff6017d4d40bb0303b34b7c03a2 100644 (file)
@@ -1,5 +1,8 @@
 #ifndef _IMX_REGS_H
 #define _IMX_REGS_H
+
+#define ARCH_MXC
+
 /* ------------------------------------------------------------------------
  *  Motorola IMX system registers
  * ------------------------------------------------------------------------
index cf925d70d52fa70c8484ee0c86581987bc19b731..672f9d74b85d1b196fa3953a99962c82c0e95f29 100644 (file)
@@ -172,6 +172,8 @@ struct aips_regs {
 
 #endif
 
+#define ARCH_MXC
+
 /* AIPS 1 */
 #define IMX_AIPS1_BASE         (0x43F00000)
 #define IMX_MAX_BASE           (0x43F04000)
index f78d5f2b9ba312f8a29211fd3e722442096b26f8..2f6c823722a0d2f8c0672460594d52f0f2a84197 100644 (file)
@@ -196,6 +196,8 @@ struct fuse_bank0_regs {
 
 #endif
 
+#define ARCH_MXC
+
 #define IMX_IO_BASE            0x10000000
 
 #define IMX_AIPI1_BASE         (0x00000 + IMX_IO_BASE)
index bba37acdc1ebb32bbaf6d3d3d53b56c0aeee06db..1dd952c55ffa7191e589374edbbdd74dbb82adf4 100644 (file)
@@ -541,6 +541,8 @@ struct esdc_regs {
 
 #endif
 
+#define ARCH_MXC
+
 #define __REG(x)     (*((volatile u32 *)(x)))
 #define __REG16(x)   (*((volatile u16 *)(x)))
 #define __REG8(x)    (*((volatile u8 *)(x)))
index 3083df07b10c408a8cc178bdad98a3345ec617a6..2c6e59c32452c70156764b3ef27938be1b84a953 100644 (file)
@@ -25,6 +25,8 @@
 #ifndef __ASM_ARCH_MX35_H
 #define __ASM_ARCH_MX35_H
 
+#define ARCH_MXC
+
 /*
  * IRAM
  */
index c53465f69f5aa2a07301010a5e4d3e406c864a0e..d1ef15d043da143cd81b7b6d85ed86b8a75ef54d 100644 (file)
@@ -23,6 +23,8 @@
 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
 #define __ASM_ARCH_MX5_IMX_REGS_H__
 
+#define ARCH_MXC
+
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
index b89dfe55f20cf54d5802da7c2252476f39165b2b..8834c59dccefe40dbc4007dfbfa71ed73e74d22a 100644 (file)
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define ARCH_MXC
+
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000