Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge.
Signed-off-by: Tom Rini <trini@konsulko.com>
BUILDMAN="^qemu-x86$"
TOOLCHAIN="x86_64"
BUILD_ROM="yes"
+ - env:
+ - TEST_PY_BD="zynq_zc702"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="arm-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^zynq_zc702$"
# TODO make it perfect ;-r
ARM_SOC_BOOT0_HOOK which contains the required assembler
preprocessor code.
+config USE_ARCH_MEMCPY
+ bool "Use an assembly optimized implementation of memcpy"
+ default y if CPU_V7
+ depends on !ARM64 && !SPL
+ help
+ Enable the generation of an optimized version of memcpy.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
+config USE_ARCH_MEMSET
+ bool "Use an assembly optimized implementation of memset"
+ default y if CPU_V7
+ depends on !ARM64 && !SPL
+ help
+ Enable the generation of an optimized version of memset.
+ Such implementation may be faster under some conditions
+ but may increase the binary size.
+
config ARCH_OMAP2
bool
select CPU_V7
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+ -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
Select Y here to make use of PSCI calls for system reset
+config ARMV8_PSCI
+ bool "Enable PSCI support" if EXPERT
+ default n
+ help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV8_PSCI
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+ int "Number of CPUs per cluster"
+ depends on ARMV8_PSCI
+ default 0
+ help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+ hex "Secure address for PSCI image"
+ depends on ARMV8_PSCI
+ help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
endif
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
#include <common.h>
#include <asm/psci.h>
+#include <asm/system.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
int psci_update_dt(void *fdt)
{
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
return 0;
#endif
fdt_psci(fdt);
+
+#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
+ /* secure code lives in RAM, keep it alive */
+ fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+ __secure_end - __secure_start);
+#endif
+
#endif
#endif
return 0;
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/secure.h>
#include <linux/compiler.h>
int cleanup_before_linux(void)
return 0;
}
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ size_t sz = __secure_end - __secure_start;
+
+ memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+ flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+ CONFIG_ARMV8_SECURE_BASE + sz + 1);
+ invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+ relocate_secure_section();
+ secure_ram_addr(psci_setup_vectors)();
+ secure_ram_addr(psci_arch_init)();
+}
+#endif
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+menu "Layerscape PPA"
+config FSL_LS_PPA
+ bool "FSL Layerscape PPA firmware support"
+ depends on !ARMV8_PSCI
+ depends on ARCH_LS1043A || ARCH_LS1046A
+ select FSL_PPA_ARMV8_PSCI
+ help
+ The FSL Primary Protected Application (PPA) is a software component
+ which is loaded during boot stage, and then remains resident in RAM
+ and runs in the TrustZone after boot.
+ Say y to enable it.
+
+config FSL_PPA_ARMV8_PSCI
+ bool "PSCI implementation in PPA firmware"
+ depends on FSL_LS_PPA
+ help
+ This config enables the ARMv8 PSCI implementation in PPA firmware.
+ This is a private PSCI implementation and different from those
+ implemented under the common ARMv8 PSCI framework.
+endmenu
+
config SYS_FSL_MMDC
bool
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
erratum_a009942_check_cpo();
#endif
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
#endif
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
--- /dev/null
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+ ldr w0, =0x00010000 /* PSCI v1.0 */
+ ret
+
+ .popsection
--- /dev/null
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+ ENTRY(__fn); \
+ mov w0, #ARM_PSCI_RET_NI; \
+ ret; \
+ ENDPROC(__fn); \
+ .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+ .word __id; \
+ .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+
+.align 3
+_psci_64_table:
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
+PSCI_TABLE(0, 0)
+
+.macro psci_enter
+ /* PSCI call is Fast Call(atomic), so mask DAIF */
+ mrs x15, DAIF
+ stp x15, xzr, [sp, #-16]!
+ ldr x15, =0x3C0
+ msr DAIF, x15
+ /* SMC convention, x18 ~ x30 should be saved by callee */
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ mrs x15, elr_el3
+ stp x18, x15, [sp, #-16]!
+.endm
+
+.macro psci_return
+ /* restore registers */
+ ldp x18, x15, [sp], #16
+ msr elr_el3, x15
+ ldp x19, x20, [sp], #16
+ ldp x21, x22, [sp], #16
+ ldp x23, x24, [sp], #16
+ ldp x25, x26, [sp], #16
+ ldp x27, x28, [sp], #16
+ ldp x29, x30, [sp], #16
+ /* restore DAIF */
+ ldp x15, xzr, [sp], #16
+ msr DAIF, x15
+ eret
+.endm
+
+/* Caller must put PSCI function-ID table base in x9 */
+handle_psci:
+ psci_enter
+1: ldr x10, [x9] /* Load PSCI function table */
+ ubfx x11, x10, #32, #32
+ ubfx x10, x10, #0, #32
+ cbz x10, 3f /* If reach the end, bail out */
+ cmp x10, x0
+ b.eq 2f /* PSCI function found */
+ add x9, x9, #8 /* If not match, try next entry */
+ b 1b
+
+2: blr x11 /* Call PSCI function */
+ psci_return
+
+3: mov x0, #ARM_PSCI_RET_NI
+ psci_return
+
+unknown_smc_id:
+ ldr x0, =0xFFFFFFFF
+ eret
+
+handle_smc32:
+ /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
+ ldr w9, =0x8400001F
+ cmp w0, w9
+ b.gt unknown_smc_id
+ ldr w9, =0x84000000
+ cmp w0, w9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_32_table
+ b handle_psci
+
+handle_smc64:
+ /* check SMC32 or SMC64 calls */
+ ubfx x9, x0, #30, #1
+ cbz x9, handle_smc32
+
+ /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
+ ldr x9, =0xC400001F
+ cmp x0, x9
+ b.gt unknown_smc_id
+ ldr x9, =0xC4000000
+ cmp x0, x9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_64_table
+ b handle_psci
+
+/*
+ * Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
+ * Platform with asymmetric clusters should implement their own interface.
+ * In case this function being called by other platform's C code, the ARM
+ * Architecture Procedure Call Standard is considered, e.g. register X0 is
+ * used for the return value, while in this PSCI environment, X0 usually holds
+ * the SMC function identifier, so X0 should be saved by caller function.
+ */
+ENTRY(psci_get_cpu_id)
+#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mrs x9, MPIDR_EL1
+ ubfx x9, x9, #8, #8
+ ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mul x9, x10, x9
+#else
+ mov x9, xzr
+#endif
+ mrs x10, MPIDR_EL1
+ ubfx x10, x10, #0, #8
+ add x0, x10, x9
+ ret
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
+/* CPU ID input in x0, stack top output in x0*/
+LENTRY(psci_get_cpu_stack_top)
+ adr x9, __secure_stack_end
+ lsl x0, x0, #ARM_PSCI_STACK_SHIFT
+ sub x0, x9, x0
+ ret
+ENDPROC(psci_get_cpu_stack_top)
+
+unhandled_exception:
+ b unhandled_exception /* simply dead loop */
+
+handle_sync:
+ mov x15, x30
+ mov x14, x0
+
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ mov x0, x14
+ mov x30, x15
+
+ mrs x9, esr_el3
+ ubfx x9, x9, #26, #6
+ cmp x9, #0x13
+ b.eq handle_smc32
+ cmp x9, #0x17
+ b.eq handle_smc64
+
+ b unhandled_exception
+
+ .align 11
+ .globl el3_exception_vectors
+el3_exception_vectors:
+ b unhandled_exception /* Sync, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* Sync, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SPx */
+ .align 7
+ b handle_sync /* Sync, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* Sync, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch32 */
+
+ENTRY(psci_setup_vectors)
+ adr x0, el3_exception_vectors
+ msr vbar_el3, x0
+ ret
+ENDPROC(psci_setup_vectors)
+
+ENTRY(psci_arch_init)
+ ret
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
+.popsection
return true;
}
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
/*
* The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
* v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
ret
ENDPROC(_sec_firmware_entry)
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x84000000
mov x1, 0x0
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
+#include <asm/psci.h>
+
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x00000000;
. = ALIGN(8);
*(.text*)
}
+#ifdef CONFIG_ARMV8_PSCI
+ .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+ ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+ {
+ KEEP(*(.__secure_start))
+ }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+ .secure_text CONFIG_ARMV8_SECURE_BASE :
+ AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+ {
+ *(._secure.text)
+ }
+
+ .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+ {
+ *(._secure.data)
+ }
+
+ .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+ CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+ AT(ADDR(.secure_stack))
+#else
+ AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+ {
+ KEEP(*(.__secure_stack_start))
+
+ . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+ . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+ KEEP(*(.__secure_stack_end))
+ }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+ . = LOADADDR(.secure_stack);
+#endif
+
+ .__secure_end : AT(ADDR(.__secure_end)) {
+ KEEP(*(.__secure_end))
+ LONG(0x1d1071c); /* Must output something to reset LMA */
+ }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l", "spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
device-width = <1>;
};
- nand@2,0 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
- fpga: board-control@3,0 {
+ fpga: board-control@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- reg = <0x3 0x0 0x0000100>;
+ reg = <0x2 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
- ranges = <0 3 0 0x100>;
+ ranges = <0 2 0 0x100>;
};
};
compatible = "adi,adt7461a";
reg = <0x4c>;
};
- eeprom@56 {
+ eeprom@52 {
compatible = "at24,24c512";
reg = <0x52>;
};
- eeprom@57 {
+ eeprom@53 {
compatible = "at24,24c512";
reg = <0x53>;
};
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
nor@0,0 {
compatible = "cfi-flash";
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
#endif
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
- * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * and the SMD depends on requirements.
*/
+#ifdef CONFIG_ARMV8_PSCI
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
+#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
#define ARM_PSCI_0_2_FN_BASE 0x84000000
#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+#define ARM_PSCI_0_2_FN64_BASE 0xC4000000
+#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n))
+
#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1)
+#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3)
+#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
+#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
+#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12)
+#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13)
+#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14)
+#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
+#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
+
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
*
void __noreturn psci_system_reset(void);
void __noreturn psci_system_off(void);
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
return ret;
#endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
announce_and_cleanup(fake);
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+ armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
update_os_arch_secondary_cores(images->os.arch);
int fdt_psci(void *fdt)
{
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_ARMV7_PSCI) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
init_psci_node:
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
#endif
switch (psci_ver) {
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007798
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_ERRATUM_A004477
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_SYS_FSL_SFP_VER_3_0
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x3e;
}
phys_size_t initdram(int board_type)
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x59;
#else
popts->cswl_override = DDR_CSWL_CS0;
config SYS_CONFIG_NAME
default "ls1043ardb"
+config SYS_HAS_ARMV8_SECURE_BASE
+ bool "Enable secure address for PSCI image"
+ depends on ARMV8_PSCI
+ default n
+ help
+ PSCI image can be re-located to secure RAM.
+ If enabled, please also define the value for ARMV8_SECURE_BASE,
+ for LS1043ARDB, it could be some address in OCRAM.
+
endif
/* Enable ZQ calibration */
popts->zq_en = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x46;
+
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x70;
}
phys_size_t initdram(int board_type)
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x70;
}
phys_size_t initdram(int board_type)
/* Enable ZQ calibration */
popts->zq_en = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x6e;
+
if (ddr_freq < 2350) {
if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
/* four chip-selects */
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x5f;
#endif
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
#ifdef CONFIG_T1023RDB
popts->wrlvl_ctl_2 = 0x07070606;
popts->half_strength_driver_enable = 1;
+ popts->cpo_sample = 0x43;
+#elif defined(CONFIG_T1024RDB)
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x52;
#endif
}
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x69;
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
*/
#ifdef CONFIG_SYS_FSL_DDR4
popts->half_strength_driver_enable = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x59;
#else
popts->half_strength_driver_enable = 0;
#endif
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x64;
}
phys_size_t initdram(int board_type)
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x54;
}
phys_size_t initdram(int board_type)
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x63;
}
phys_size_t initdram(int board_type)
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x64;
}
phys_size_t initdram(int board_type)
#define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06
#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70
-#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
#define STATUS_QEB_WINSPAN BIT(1)
#define STATUS_QEB_MXIC BIT(6)
#define STATUS_PEC BIT(7)
-#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int read_evcr(struct spi_flash *flash, u8 *evcr)
-{
- int ret;
- const u8 cmd = CMD_READ_EVCR;
-
- ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
- if (ret < 0) {
- debug("SF: error reading EVCR\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_evcr(struct spi_flash *flash, u8 evcr)
-{
- u8 cmd;
- int ret;
-
- cmd = CMD_WRITE_EVCR;
- ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
- if (ret < 0) {
- debug("SF: error while writing EVCR register\n");
- return ret;
- }
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_SPI_FLASH_BAR
static int write_bar(struct spi_flash *flash, u32 offset)
{
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int micron_quad_enable(struct spi_flash *flash)
-{
- u8 qeb_status;
- int ret;
-
- ret = read_evcr(flash, &qeb_status);
- if (ret < 0)
- return ret;
-
- if (!(qeb_status & STATUS_QEB_MICRON))
- return 0;
-
- ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
- if (ret < 0)
- return ret;
-
- /* read EVCR and check it */
- ret = read_evcr(flash, &qeb_status);
- if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
- printf("SF: Micron EVCR Quad bit not clear\n");
- return -EINVAL;
- }
-
- return ret;
-}
-#endif
-
static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
int tmp;
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- return micron_quad_enable(flash);
+ debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
+ return 0;
#endif
default:
printf("SF: Need set QEB func for %02x flash\n",
return 0;
}
- if (flash->size != size) {
+ if (flash->size > size) {
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
{
struct spi_slave *spi = flash->spi;
const struct spi_flash_info *info = NULL;
- int ret = -1;
+ int ret;
info = spi_flash_read_id(flash);
if (IS_ERR_OR_NULL(info))
}
#endif
- return ret;
+ return 0;
}
#define QBMAN_CENA_SWP_VDQCR 0x780
/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
-#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0xff) >> 6)
+#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
/*******************************/
/* Pre-defined attribute codes */
{
int ret;
struct qbman_swp *p = malloc(sizeof(struct qbman_swp));
+ u32 major = 0, minor = 0;
if (!p)
return NULL;
atomic_set(&p->vdq.busy, 1);
p->vdq.valid_bit = QB_VALID_BIT;
p->dqrr.next_idx = 0;
+
+ qbman_version(&major, &minor);
+ if (!major) {
+ printf("invalid qbman version\n");
+ return NULL;
+ }
+
+ if (major >= 4 && minor >= 1)
+ p->dqrr.dqrr_size = QBMAN_VER_4_1_DQRR_SIZE;
+ else
+ p->dqrr.dqrr_size = QBMAN_VER_4_0_DQRR_SIZE;
+
p->dqrr.valid_bit = QB_VALID_BIT;
- ret = qbman_swp_sys_init(&p->sys, d);
+ ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
if (ret) {
free(p);
printf("qbman_swp_sys_init() failed %d\n", ret);
/* There's something there. Move "next_idx" attention to the next ring
* entry (and prefetch it) before returning what we found. */
s->dqrr.next_idx++;
- s->dqrr.next_idx &= QBMAN_DQRR_SIZE - 1; /* Wrap around at 4 */
+ s->dqrr.next_idx &= s->dqrr.dqrr_size - 1;/* Wrap around at dqrr_size */
/* TODO: it's possible to do all this without conditionals, optimise it
* later. */
if (!s->dqrr.next_idx)
/* Management command result codes */
#define QBMAN_MC_RSLT_OK 0xf0
-/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */
-#define QBMAN_DQRR_SIZE 4
+#define QBMAN_VER_4_0_DQRR_SIZE 4
+#define QBMAN_VER_4_1_DQRR_SIZE 8
/* --------------------- */
struct {
uint32_t next_idx;
uint32_t valid_bit;
+ uint8_t dqrr_size;
} dqrr;
};
#include <linux/types.h>
#include <asm/atomic.h>
#include <malloc.h>
+#include <asm/arch/soc.h>
#include <fsl-mc/fsl_qbman_base.h>
#define QBMAN_CHECKING
#define lwsync()
+void qbman_version(u32 *major, u32 *minor)
+{
+ u32 svr_dev_id;
+
+ /*
+ * LS2080A SoC and its personalities has qbman cotroller version 4.0
+ * New SoCs like LS2088A, LS1088A has qbman conroller version 4.1
+ */
+ svr_dev_id = get_svr() >> 16;
+ if (svr_dev_id == SVR_DEV_LS2080A) {
+ *major = 4;
+ *minor = 0;
+ } else {
+ *major = 4;
+ *minor = 1;
+ }
+}
+
#include "qbman_sys.h"
{
uint32_t reg;
- reg = e32_uint8_t(20, 3, max_fill) | e32_uint8_t(16, 3, est) |
- e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) |
- e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) |
- e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) |
- e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn);
+ reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
+ e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) |
+ e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) |
+ e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) |
+ e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) |
+ e32_uint8_t(14, 1, wn);
return reg;
}
static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
- const struct qbman_swp_desc *d)
+ const struct qbman_swp_desc *d,
+ uint8_t dqrr_size)
{
uint32_t reg;
BUG_ON(reg);
#endif
#ifdef QBMAN_CINH_ONLY
- reg = qbman_set_swp_cfg(4, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+ reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
#else
- reg = qbman_set_swp_cfg(4, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+ reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
#endif
qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
- unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
- unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
/* Set SPI mode */
- cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+ cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
/* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase);
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
+ plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
- plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);
-void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
- unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,
#include <spi.h>
#include "cadence_qspi.h"
-#define CQSPI_REG_POLL_US (1) /* 1us */
-#define CQSPI_REG_RETRY (10000)
-#define CQSPI_POLL_IDLE_RETRY (3)
+#define CQSPI_REG_POLL_US 1 /* 1us */
+#define CQSPI_REG_RETRY 10000
+#define CQSPI_POLL_IDLE_RETRY 3
-#define CQSPI_FIFO_WIDTH (4)
+#define CQSPI_FIFO_WIDTH 4
-#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
+#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
/* Transfer mode */
-#define CQSPI_INST_TYPE_SINGLE (0)
-#define CQSPI_INST_TYPE_DUAL (1)
-#define CQSPI_INST_TYPE_QUAD (2)
+#define CQSPI_INST_TYPE_SINGLE 0
+#define CQSPI_INST_TYPE_DUAL 1
+#define CQSPI_INST_TYPE_QUAD 2
-#define CQSPI_STIG_DATA_LEN_MAX (8)
-
-#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
-#define CQSPI_DUMMY_BYTES_MAX (4)
+#define CQSPI_STIG_DATA_LEN_MAX 8
+#define CQSPI_DUMMY_CLKS_PER_BYTE 8
+#define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_REG_SRAM_FILL_THRESHOLD \
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
+
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
#define CQSPI_REG_CONFIG 0x00
-#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
-#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
-#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
-#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7)
-#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
-#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18)
+#define CQSPI_REG_CONFIG_ENABLE BIT(0)
+#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
+#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
+#define CQSPI_REG_CONFIG_DIRECT BIT(7)
+#define CQSPI_REG_CONFIG_DECODE BIT(9)
+#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
-#define CQSPI_READLCAPTURE 0x10
-#define CQSPI_READLCAPTURE_BYPASS_LSB 0
-#define CQSPI_READLCAPTURE_DELAY_LSB 1
-#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
+#define CQSPI_REG_RD_DATA_CAPTURE 0x10
+#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
#define CQSPI_REG_SIZE 0x14
#define CQSPI_REG_SIZE_ADDRESS_LSB 0
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
-#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
-#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
-#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2)
-#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
+#define CQSPI_REG_INDIRECTRD_START BIT(0)
+#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
+#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
+#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
-#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
-#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
+#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
+#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70
-#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
-#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
-#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2)
-#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
+#define CQSPI_REG_INDIRECTWR_START BIT(0)
+#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
+#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
+#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
-#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
- ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
-
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
{
unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
+ reg |= CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG);
- return;
}
void cadence_qspi_apb_controller_disable(void *reg_base)
{
unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
+ reg &= ~CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG);
- return;
}
/* Return 1 if idle, otherwise return 0 (busy). */
unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base);
- reg = readl(reg_base + CQSPI_READLCAPTURE);
+ reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
if (bypass)
- reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+ reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
else
- reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
+ reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
- reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
- << CQSPI_READLCAPTURE_DELAY_LSB);
+ reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
+ << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
- reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
- << CQSPI_READLCAPTURE_DELAY_LSB);
+ reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
+ << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
- writel(reg, reg_base + CQSPI_READLCAPTURE);
+ writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
- div = ref_clk_hz / sclk_hz;
-
- if (div > 32)
- div = 32;
-
- /* Check if even number. */
- if ((div & 1)) {
- div = (div / 2);
- } else {
- if (ref_clk_hz % sclk_hz)
- /* ensure generated SCLK doesn't exceed user
- specified sclk_hz */
- div = (div / 2);
- else
- div = (div / 2) - 1;
- }
-
- debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
- ref_clk_hz, sclk_hz, div);
+ /*
+ * The baud_div field in the config reg is 4 bits, and the ref clock is
+ * divided by 2 * (baud_div + 1). Round up the divider to ensure the
+ * SPI clock rate is less than or equal to the requested clock rate.
+ */
+ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
/* ensure the baud rate doesn't exceed the max value */
if (div > CQSPI_REG_CONFIG_BAUD_MASK)
div = CQSPI_REG_CONFIG_BAUD_MASK;
+ debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
+ ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
+
reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
-void cadence_qspi_apb_set_clk_mode(void *reg_base,
- unsigned int clk_pol, unsigned int clk_pha)
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
{
unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base);
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg &= ~(1 <<
- (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
+ reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
- reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
- reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
+ if (mode & SPI_CPOL)
+ reg |= CQSPI_REG_CONFIG_CLK_POL;
+ if (mode & SPI_CPHA)
+ reg |= CQSPI_REG_CONFIG_CLK_PHA;
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_chipselect(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG);
/* docoder */
if (decoder_enable) {
- reg |= CQSPI_REG_CONFIG_DECODE_MASK;
+ reg |= CQSPI_REG_CONFIG_DECODE;
} else {
- reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
+ reg &= ~CQSPI_REG_CONFIG_DECODE;
/* Convert CS if without decoder.
* CS0 to 4b'1110
* CS1 to 4b'1101
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_delay(void *reg_base,
cadence_qspi_apb_controller_disable(reg_base);
/* Convert to ns. */
- ref_clk_ns = (1000000000) / ref_clk;
+ ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
/* Convert to ns. */
- sclk_ns = (1000000000) / sclk_hz;
-
- /* Plus 1 to round up 1 clock cycle. */
- tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
- tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
- tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
- tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+ sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
+
+ /* The controller adds additional delay to that programmed in the reg */
+ if (tshsl_ns >= sclk_ns + ref_clk_ns)
+ tshsl_ns -= sclk_ns + ref_clk_ns;
+ if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
+ tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
+ tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
+ tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
+ tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
+ tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
<< CQSPI_REG_DELAY_TSHSL_LSB);
writel(reg, reg_base + CQSPI_REG_DELAY);
cadence_qspi_apb_controller_enable(reg_base);
- return;
}
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
cadence_qspi_apb_controller_enable(plat->regbase);
- return;
}
static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
/* Write the CMDCTRL without start execution. */
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
/* Start execute */
- reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
+ reg |= CQSPI_REG_CMDCTRL_EXECUTE;
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
while (retry--) {
reg = readl(reg_base + CQSPI_REG_CMDCTRL);
- if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
+ if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
break;
udelay(1);
}
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
/* Start the indirect read transfer */
- writel(CQSPI_REG_INDIRECTRD_START_MASK,
+ writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
while (remaining > 0) {
/* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
+ CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
if (ret) {
printf("Indirect read completion error (%i)\n", ret);
goto failrd;
}
/* Clear indirect completion status */
- writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
+ writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
return 0;
failrd:
/* Cancel the indirect read */
- writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
+ writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD);
return ret;
}
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
/* Start the indirect write transfer */
- writel(CQSPI_REG_INDIRECTWR_START_MASK,
+ writel(CQSPI_REG_INDIRECTWR_START,
plat->regbase + CQSPI_REG_INDIRECTWR);
while (remaining > 0) {
/* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
+ CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
if (ret) {
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
/* Clear indirect completion status */
- writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
+ writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
return 0;
failwr:
/* Cancel the indirect write */
- writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
+ writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
return ret;
}
/* enter XiP mode immediately and enable direct mode */
reg = readl(reg_base + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
- reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
- reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
+ reg |= CQSPI_REG_CONFIG_ENABLE;
+ reg |= CQSPI_REG_CONFIG_DIRECT;
+ reg |= CQSPI_REG_CONFIG_XIP_IMM;
writel(reg, reg_base + CQSPI_REG_CONFIG);
/* keep the XiP mode */
mode |= SPI_TX_QUAD;
break;
default:
- error("spi-tx-bus-width %d not supported\n", value);
+ warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break;
}
mode |= SPI_RX_QUAD;
break;
default:
- error("spi-rx-bus-width %d not supported\n", value);
+ warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break;
}
#include "mx6_common.h"
#define CONFIG_SYS_THUMB_BUILD
-/* These are not provided in SPL and result in a linker error */
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-#endif
#undef CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_DCACHE_OFF
#include "rcar-gen2-common.h"
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
-
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
#define STACK_AREA_SIZE 0xC000
#include "mx6_common.h"
#define CONFIG_SYS_THUMB_BUILD
-/* These are not provided in SPL and result in a linker error */
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-#endif
#undef CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
#include "mx7_common.h"
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
/*#define CONFIG_DBG_MONITOR*/
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_VF610
#define CONFIG_SYS_THUMB_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_SYS_FSL_CLK
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-
/* Keep L2 Cache Disabled */
/* input clock of PLL: 24MHz input clock */
#if defined(CONFIG_FSL_LS_PPA)
#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#define SEC_FIRMWARE_ERET_ADDR_REVERT
-#define CONFIG_ARMV8_PSCI
#define CONFIG_SYS_LS_PPA_FW_IN_XIP
#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#ifndef CONFIG_ARM64
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USE_ARCH_MEMCPY
-#endif
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
-#define CONFIG_USE_ARCH_MEMSET
-#define CONFIG_USE_ARCH_MEMCPY
-#endif
-
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_CMD_NAND
-#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
projects / u-boot / commitdiff