/* 0x3937d322 */
 #define CONFIG_SYS_DDR_TIMING_2        0x02984cc8
 
-#define CONFIG_SYS_DDR_INTERVAL        ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
-                               | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+#define CONFIG_SYS_DDR_INTERVAL        ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+                               | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
                                /* 0x06090100 */
 
 #if defined(CONFIG_DDR_2T_TIMING)
                                /* 0x43000000 */
 #endif
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE            ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+#define CONFIG_SYS_DDR_MODE            ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
                                | (0x0442 << SDRAM_MODE_SD_SHIFT))
                                /* 0x04400442 */ /* DDR400 */
 #define CONFIG_SYS_DDR_MODE2           0x00000000