*omap4_revision = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
- *omap4_revision = OMAP4460_ES1_0;
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4460_CONTROL_ID_CODE_ES1_0:
+ *omap4_revision = OMAP4460_ES1_0;
+ break;
+ case OMAP4460_CONTROL_ID_CODE_ES1_1:
+ *omap4_revision = OMAP4460_ES1_1;
+ break;
+ default:
+ *omap4_revision = OMAP4460_ES1_0;
+ break;
+ }
break;
default:
*omap4_revision = OMAP4430_SILICON_ID_INVALID;
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
+/* 4430 */
#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
+/* 4460 */
+#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
+#define OMAP4460_ES1_1 0x44600110
/* ROM code defines */
/* Boot device */