spi: cadence_qspi: get sram size from device tree

sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index bf791c5ddef3c4c6db942d8808ae818cb975707d..9b1242025dcec7e6a091ae40b93490779ea1928c 100644 (file)
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -639,6 +639,7 @@
                        ext-decoder = <0>;  /* external decoder */
                        num-cs = <4>;
                        fifo-depth = <128>;
+                       sram-size = <128>;
                        bus-num = <2>;
                        status = "disabled";
                };

diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index 3b1efca3730ebdac6fd82c889e138a81978e3fd6..556df821e4e36f2167f50d9d021f0f18d7a551b5 100644 (file)
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -35,6 +35,7 @@
                        ext-decoder = <0>; /* external decoder */
                        num-cs = <4>;
                        fifo-depth = <256>;
+                       sram-size = <256>;
                        bus-num = <0>;
                        status = "okay";
 

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a75fc46e95dc5f060e0e8a6a3e89ef72e4dfb6ec..34a0f46a1ae0d5de7a43270acc9b87025d63950d 100644 (file)
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
        plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
        plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
        plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
+       plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
        debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
              __func__, plat->regbase, plat->ahbbase, plat->max_hz,

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index c9a6142e82d865e60930338fdf00e2ea0da9f7ed..98e57aa5bccceaedff06f0a9d7819db36bd3fb20 100644 (file)
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -25,6 +25,7 @@ struct cadence_spi_platdata {
        u32             tsd2d_ns;
        u32             tchsh_ns;
        u32             tslch_ns;
+       u32             sram_size;
 };
 
 struct cadence_spi_priv {

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index fb78892f180072bd08941359ab34ad048943454c..cbf0d428dd6f4c8e6f1322c4ffc27b6b86630447 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -36,9 +36,6 @@
 
 #define CQSPI_FIFO_WIDTH                       (4)
 
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD               (128)
-#define CQSPI_REG_SRAM_PARTITION_RD            (CQSPI_REG_SRAM_SIZE_WORD/2)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS         (50)
 
 /* Transfer mode */
@@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
        writel(0, plat->regbase + CQSPI_REG_REMAP);
 
        /* Indirect mode configurations */
-       writel(CQSPI_REG_SRAM_PARTITION_RD,
-              plat->regbase + CQSPI_REG_SRAMPARTITION);
+       writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 
        /* Disable all interrupts */
        writel(0, plat->regbase + CQSPI_REG_IRQMASK);