endif
ifneq ($(CONFIG_TEGRA),)
+ifneq ($(CONFIG_BINMAN),)
+u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin: \
+ spl/u-boot-spl u-boot.bin FORCE
+ $(call if_changed,binman)
+else
OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE
$(call if_changed,pad_cat)
u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE
$(call if_changed,copy)
+endif # binman
endif
OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
- -j .u_boot_list -j .rela.dyn -j .got -j .got.plt
+ -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+ -j .binman_sym_table
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
- -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
+ -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+ -j .binman_sym_table
endif
# if a dtb section exists we always have to include it
KEEP(*(SORT(.u_boot_list*)));
}
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
. = ALIGN(4);
__image_copy_end = .;
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
r8a7796-m3ulcb.dtb \
- r8a7796-salvator-x.dtb
+ r8a7796-salvator-x.dtb \
+ r8a77970-eagle.dtb \
+ r8a77995-draak.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
reg = <0x10440000 0x1000>;
};
- serial@13800000 {
+ gic: interrupt-controller@10490000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ cpu-offset = <0x4000>;
+ reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+ };
+
+ serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x3c>;
id = <0>;
};
- serial@13810000 {
+ serail_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x3c>;
id = <1>;
};
- serial@13820000 {
+ serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x3c>;
id = <2>;
};
- serial@13830000 {
+ serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x3c>;
id = <3>;
};
- serial@13840000 {
+ serial_4: serial@13840000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13840000 0x3c>;
id = <4>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <0 56 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <1 57 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <2 58 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <3 59 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138a0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <4 60 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138b0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <5 61 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138c0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <6 62 0>;
};
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138d0000 0x100>;
+ interrupt-parent = <&gic>;
interrupts = <7 63 0>;
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12510000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 75 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12520000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 76 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12530000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 77 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-sdhci";
reg = <0x12540000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 78 0>;
status = "disabled";
};
#size-cells = <0>;
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 131 0>;
status = "disabled";
};
cpu-offset = <0x8000>;
};
- combiner: interrupt-controller@10440000 {
- samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
- };
-
mct@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
};
};
};
+
+&combiner {
+ samsung,combiner-nr = <16>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+};
compatible = "samsung,odroid", "samsung,exynos4412";
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc0 = &mshc_0;
mmc1 = &sdhci2;
};
- i2c@13860000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_VM1M2_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDDQ_MMC2_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDDQ_MMC0/1/3_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VMPLL_1.0V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VPLL_1.1V";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD_MIPI/HDMI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD_MIPI/HDMI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD_ABB1_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD_UOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDD_C2C_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDD_ABB02_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDD_HSIC/OTG_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDD_HSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "VDDQ_CAM_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VDDQ_EMMC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "TFLASH_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "VDDQ_EMMC_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "VDDQ_LCD_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "VDD_MIF_1.0V";
- regulator-min-microvolt = <8500000>;
- regulator-max-microvolt = <1100000>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "VDD_ARM_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "VDD_INT_1.1V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "VDD_G3D_1.0V";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "VDDQ_AP_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "VCC_INL1/7_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "VCC_INL2/3/5_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "VCC_P3V3_2.85V";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
-
serial@13810000 {
status = "okay";
};
};
};
+&i2c_0 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx3>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-name = "VDD_ALIVE_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "VDDQ_VM1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VDDQ_MMC2_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VDDQ_MMC0/1/3_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "VMPLL_1.0V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VDD_MIPI/HDMI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VDD_MIPI/HDMI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "VDD_ABB1_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "VDD_UOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VDD_C2C_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VDD_ABB02_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VDD_HSIC/OTG_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VDD_HSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VDDQ_CAM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VDDQ_EMMC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "TFLASH_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VDDQ_EMMC_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "VDDQ_LCD_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "VDD_MIF_1.0V";
+ regulator-min-microvolt = <8500000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "VDD_ARM_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VDD_INT_1.1V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VDD_G3D_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VDDQ_AP_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "VCC_INL1/7_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "VCC_INL2/3/5_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "VCC_P3V3_2.85V";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
&sdhci2 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
};
aliases {
- i2c0 = "/i2c@13860000";
- i2c1 = "/i2c@13870000";
- i2c2 = "/i2c@13880000";
- i2c3 = "/i2c@13890000";
- i2c4 = "/i2c@138a0000";
- i2c5 = "/i2c@138b0000";
- i2c6 = "/i2c@138c0000";
- i2c7 = "/i2c@138d0000";
i2c8 = &i2c_fg;
i2c9 = &i2c_max77693;
serial0 = "/serial@13800000";
status = "okay";
};
- i2c@138d0000 {
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-slave-addr = <0x10>;
- samsung,i2c-max-bus-freq = <100000>;
- status = "okay";
-
- max77686_pmic@09 {
- compatible = "maxim,max77686";
- interrupts = <7 0>;
- reg = <0x09 0 0>;
- #clock-cells = <1>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-compatible = "LDO1";
- regulator-name = "VALIVE_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-compatible = "LDO2";
- regulator-name = "VM1M2_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-compatible = "LDO3";
- regulator-name = "VCC_1.8V_AP";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-compatible = "LDO4";
- regulator-name = "VCC_2.8V_AP";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo5_reg: LDO5 {
- regulator-compatible = "LDO5";
- regulator-name = "VCC_1.8V_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-compatible = "LDO6";
- regulator-name = "VMPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo7_reg: LDO7 {
- regulator-compatible = "LDO7";
- regulator-name = "VPLL_1.0V_AP";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-mem-on;
- };
-
- ldo8_reg: LDO8 {
- regulator-compatible = "LDO8";
- regulator-name = "VMIPI_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo9_reg: LDO9 {
- regulator-compatible = "LDO9";
- regulator-name = "CAM_ISP_MIPI_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo10_reg: LDO10 {
- regulator-compatible = "LDO10";
- regulator-name = "VMIPI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo11_reg: LDO11 {
- regulator-compatible = "LDO11";
- regulator-name = "VABB1_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo12_reg: LDO12 {
- regulator-compatible = "LDO12";
- regulator-name = "VUOTG_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-off;
- };
-
- ldo13_reg: LDO13 {
- regulator-compatible = "LDO13";
- regulator-name = "NFC_AVDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo14_reg: LDO14 {
- regulator-compatible = "LDO14";
- regulator-name = "VABB2_1.95V";
- regulator-min-microvolt = <1950000>;
- regulator-max-microvolt = <1950000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo15_reg: LDO15 {
- regulator-compatible = "LDO15";
- regulator-name = "VHSIC_1.0V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-mem-off;
- };
-
- ldo16_reg: LDO16 {
- regulator-compatible = "LDO16";
- regulator-name = "VHSIC_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-off;
- };
-
- ldo17_reg: LDO17 {
- regulator-compatible = "LDO17";
- regulator-name = "CAM_SENSOR_CORE_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-idle;
- };
-
- ldo18_reg: LDO18 {
- regulator-compatible = "LDO18";
- regulator-name = "CAM_ISP_SEN_IO_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo19_reg: LDO19 {
- regulator-compatible = "LDO19";
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo20_reg: LDO20 {
- regulator-compatible = "LDO20";
- regulator-name = "VDDQ_PRE_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo21_reg: LDO21 {
- regulator-compatible = "LDO21";
- regulator-name = "VTF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo22_reg: LDO22 {
- regulator-compatible = "LDO22";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- ldo23_reg: LDO23 {
- regulator-compatible = "LDO23";
- regulator-name = "TSP_AVDD_3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-mem-idle;
- };
-
- ldo24_reg: LDO24 {
- regulator-compatible = "LDO24";
- regulator-name = "TSP_VDD_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-mem-idle;
- };
-
- ldo25_reg: LDO25 {
- regulator-compatible = "LDO25";
- regulator-name = "LCD_VCC_3.3V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-mem-idle;
- };
-
- ldo26_reg: LDO26 {
- regulator-compatible = "LDO26";
- regulator-name = "MOTOR_VCC_3.0V";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-mem-idle;
- };
-
- buck1_reg: BUCK1 {
- regulator-compatible = "BUCK1";
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck2_reg: BUCK2 {
- regulator-compatible = "BUCK2";
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck3_reg: BUCK3 {
- regulator-compatible = "BUCK3";
- regulator-name = "vdd_int";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck4_reg: BUCK4 {
- regulator-compatible = "BUCK4";
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-mem-off;
- };
-
- buck5_reg: BUCK5 {
- regulator-compatible = "BUCK5";
- regulator-name = "VMEM_1.2V_AP";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- regulator-compatible = "BUCK6";
- regulator-name = "VCC_SUB_1.35V";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- buck7_reg: BUCK7 {
- regulator-compatible = "BUCK7";
- regulator-name = "VCC_SUB_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-compatible = "BUCK8";
- regulator-name = "VMEM_VDDF_3.0V";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- regulator-mem-off;
- };
-
- buck9_reg: BUCK9 {
- regulator-compatible = "BUCK9";
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- regulator-mem-off;
- };
- };
- };
- };
-
fimd@11c00000 {
compatible = "samsung,exynos-fimd";
reg = <0x11c00000 0xa4>;
};
};
+&i2c_7 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686: max77686_pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: LDO1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: LDO18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: LDO23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: LDO26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+};
+
&sdhci0 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
/ {
compatible = "samsung,exynos4412";
+};
- gic: interrupt-controller@10490000 {
- cpu-offset = <0x4000>;
- };
-
- interrupt-controller@10440000 {
- samsung,combiner-nr = <20>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
- };
-
+&combiner {
+ samsung,combiner-nr = <20>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+ <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+ <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+ <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 47 0>;
};
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
pinctrl_3: pinctrl@106E0000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 72 0>;
};
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
+ interrupt-parent = <&gic>;
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
--- /dev/null
+/*
+ * Device Tree Source for the Eagle board
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+
+/ {
+ model = "Renesas Eagle board based on r8a77970";
+ compatible = "renesas,eagle", "renesas,r8a77970";
+
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+
+ avb_pins: avb {
+ groups = "avb0_mdc";
+ function = "avb0";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a77970 SoC
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+ compatible = "renesas,r8a77970";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0>;
+ clocks = <&cpg CPG_CORE 0>;
+ power-domains = <&sysc 5>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller {
+ compatible = "cache";
+ power-domains = <&sysc 21>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1010000 0 0x1000>,
+ <0 0xf1020000 0 0x20000>,
+ <0 0xf1040000 0 0x20000>,
+ <0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77970-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77970-rst";
+ reg = <0 0xe6160000 0 0x200>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77970-sysc";
+ reg = <0 0xe6180000 0 0x440>;
+ #power-domain-cells = <1>;
+ };
+
+ pfc: pfc@e6060000 {
+ compatible = "renesas,pfc-r8a77970";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77970",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77970",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 96>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77970",
+ "renesas,rcar-gen3-hscif", "renesas,hscif";
+ reg = <0 0xe66a0000 0 96>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+ <&dmac2 0x37>, <&dmac2 0x36>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif",
+ "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+ <&dmac2 0x57>, <&dmac2 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77970",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE 9>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+ <&dmac2 0x59>, <&dmac2 0x58>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77970",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii-id";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77995.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Renesas Draak board based on r8a77995";
+ compatible = "renesas,draak", "renesas,r8a77995";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x18000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&pfc {
+ avb0_pins: avb {
+ mux {
+ groups = "avb0_link", "avb0_mdc", "avb0_mii";
+ function = "avb0";
+ };
+ };
+
+ pwm0_pins: pwm0 {
+ groups = "pwm0_c";
+ function = "pwm0";
+ };
+
+ pwm1_pins: pwm1 {
+ groups = "pwm1_c";
+ function = "pwm1";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data";
+ function = "scif2";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&avb {
+ pinctrl-0 = <&avb0_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for the r8a77995 SoC
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77995-sysc.h>
+
+/ {
+ compatible = "renesas,r8a77995";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a53_0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A77995_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77995-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77995-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a77995-rst";
+ reg = <0 0xe6160000 0 0x0200>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77995";
+ reg = <0 0xe6060000 0 0x508>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a77995-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 9>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a77995",
+ "renesas,rcar-gen3-gpio",
+ "renesas,gpio-rcar";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 14>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 906>;
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a77995",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii-txid";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ status = "disabled";
+ };
+
+ ehci0: usb@ee080100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ ohci0: usb@ee080000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a77995",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+#include <config.h>
+
+/ {
+ binman {
+ multiple-images;
+ image1 {
+ filename = "u-boot-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+
+ /* Same as image1 - some tools still expect the -dtb suffix */
+ image2 {
+ filename = "u-boot-dtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+
+ image3 {
+ filename = "u-boot-nodtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot-nodtb {
+ pos = <(CONFIG_SYS_TEXT_BASE -
+ CONFIG_SPL_TEXT_BASE)>;
+ };
+ };
+ };
+};
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "tegra-u-boot.dtsi"
+
/ {
host1x@50000000 {
u-boot,dm-pre-reloc;
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
-/ {
- host1x@50000000 {
- u-boot,dm-pre-reloc;
- dc@54200000 {
- u-boot,dm-pre-reloc;
- };
- };
-};
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
.rel.data : { *(.rel.data) *(.rel.data*) }
_data_size = . - _etext;
- . = ALIGN(4096);
- .dynsym : { *(.dynsym) }
- . = ALIGN(4096);
- .dynstr : { *(.dynstr) }
- . = ALIGN(4096);
- .note.gnu.build-id : { *(.note.gnu.build-id) }
/DISCARD/ : {
*(.rel.reloc)
*(.eh_frame)
*(.note.GNU-stack)
+ *(.dynsym)
+ *(.dynstr)
+ *(.note.gnu.build-id)
+ *(.comment)
}
- .comment 0 : { *(.comment) }
}
config R8A7796
bool "Renesas SoC R8A7796"
+config R8A77970
+ bool "Renesas SoC R8A77970"
+
+config R8A77995
+ bool "Renesas SoC R8A77995"
+
endchoice
choice
prompt "Renesus ARM64 SoCs board select"
optional
+config TARGET_DRAAK
+ bool "Draak board"
+ help
+ Support for Renesas R-Car Gen3 Draak platform
+
+config TARGET_EAGLE
+ bool "Eagle board"
+ help
+ Support for Renesas R-Car Gen3 Eagle platform
+
config TARGET_SALVATOR_X
bool "Salvator-X board"
help
config SYS_SOC
default "rmobile"
+source "board/renesas/draak/Kconfig"
+source "board/renesas/eagle/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
+ { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+ { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
};
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
#define RMOBILE_CPU_TYPE_R8A7796 0x52
+#define RMOBILE_CPU_TYPE_R8A77970 0x54
+#define RMOBILE_CPU_TYPE_R8A77995 0x58
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
}
};
+static struct mm_region r8a77970_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+static struct mm_region r8a77995_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
struct mm_region *mem_map = r8a7795_mem_map;
void rcar_gen3_memmap_fixup(void)
case RMOBILE_CPU_TYPE_R8A7796:
mem_map = r8a7796_mem_map;
break;
+ case RMOBILE_CPU_TYPE_R8A77970:
+ mem_map = r8a77970_mem_map;
+ break;
+ case RMOBILE_CPU_TYPE_R8A77995:
+ mem_map = r8a77995_mem_map;
+ break;
}
}
select OF_CONTROL
select VIDCONSOLE_AS_LCD if DM_VIDEO
select BOARD_EARLY_INIT_F
+ select BINMAN
imply CRC32_VERIFY
config TEGRA_NO_BPMP
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ no_match_by_nodename {
+ regulator-name = "buck_SUPPLY_1.5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
};
--- /dev/null
+if TARGET_DRAAK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "draak"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "draak"
+
+endif
--- /dev/null
+DRAAK BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/draak/
+F: include/configs/draak.h
+F: configs/r8a77995_draak_defconfig
--- /dev/null
+#
+# board/renesas/draak/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := draak.o
--- /dev/null
+/*
+ * board/renesas/draak/draak.c
+ * This file is Draak board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR 0xE6150904
+#define CPGWPR 0xE615090C
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ writel(0xA5A50000, CPGWPCR);
+ writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112 BIT(12) /* 3DG */
+#define TMU0_MSTP125 BIT(25) /* secure */
+#define TMU1_MSTP124 BIT(24) /* non-secure */
+#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
+#define DVFS_MSTP926 BIT(26)
+#define HSUSB_MSTP704 BIT(4) /* HSUSB */
+
+int board_early_init_f(void)
+{
+ /* TMU0,1 */ /* which use ? */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+ /* DVFS for reset */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+ return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define SYSC_PWRSR2 0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define SYSC_PWRONCR2 0xE618010C
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS 0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
+#define HSUSB_REG_UGCTRL2 0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ /* USB1 pull-up */
+ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+ /* Configure the HSUSB block */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ /* Choice USB0SEL */
+ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+ HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+ /* low power status */
+ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
--- /dev/null
+if TARGET_EAGLE
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "eagle"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "eagle"
+
+endif
--- /dev/null
+EAGLE BOARD
+M: Marek Vasut <marek.vasut+renesas@gmail.com>
+S: Maintained
+F: board/renesas/eagle/
+F: include/configs/eagle.h
+F: configs/r8a77970_eagle_defconfig
--- /dev/null
+#
+# board/renesas/eagle/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := eagle.o
--- /dev/null
+/*
+ * board/renesas/eagle/eagle.c
+ * This file is Eagle board support.
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR 0xE6150904
+#define CPGWPR 0xE615090C
+
+/* PLL */
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_OFFSET 24
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 0.8GHz */
+ stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+#define TMU0_MSTP125 BIT(25) /* secure */
+
+int board_early_init_f(void)
+{
+ writel(0xA5A5FFFF, CPGWPCR);
+ writel(0x5A5A0000, CPGWPR);
+
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_RSTOUTCR (RST_BASE + 0x58)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else if (cputype == 0xd07)
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+ else
+ hang();
+}
};
/**
- * Odroix XU3/4 board revisions:
+ * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf):
* Rev ADCmax Board
* 0.1 0 XU3 0.1
- * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
- * 0.3 1408 XU4 0.1
- * Use +10 % for ADC value tolerance.
+ * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231)
+ * 0.3 1280 XU4 0.1
+ * 0.4 739 XU4 0.2
+ * 0.5 1016 XU4+Air0.1 (Passive cooling)
+ * 0.6 1308 XU4S 0.1 (HC1)
+ * Use +1% for ADC value tolerance in the array below, the code loops until
+ * the measured ADC value is lower than then ADCmax from the array.
*/
struct odroid_rev_info odroid_info[] = {
{ EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" },
- { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" },
+ { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
+ { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
+ { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" },
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
goto rev_default;
for (i = 0; i < ARRAY_SIZE(odroid_info); i++) {
- /* ADC tolerance: +20 % */
+ /* ADC tolerance: +1% */
if (adcval < odroid_info[i].adc_val)
return odroid_info[i].board_type;
}
return false;
}
+bool board_is_odroidhc1(void)
+{
+ if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01)
+ return true;
+
+ return false;
+}
+
bool board_is_generic(void)
{
if (gd->board_type == EXYNOS5_BOARD_GENERIC)
{
char *info = "Not supported!";
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
return env_get("dfu_alt_system");
char *alt_boot;
int dev_num;
- if (board_is_odroidxu4())
+ if (board_is_odroidxu4() || board_is_odroidhc1())
return info;
dev_num = simple_strtoul(devstr, NULL, 10);
*/
#include <common.h>
+#include <binman_sym.h>
#include <dm.h>
#include <spl.h>
#include <asm/u-boot.h>
u32 *boot_params_ptr = NULL;
+/* See spl.h for information about this */
+binman_sym_declare(ulong, u_boot_any, pos);
+
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
spl_image->size = CONFIG_SYS_MONITOR_LEN;
- spl_image->entry_point = CONFIG_SYS_UBOOT_START;
- spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ if (u_boot_pos != BINMAN_SYM_MISSING) {
+ /* biman does not support separate entry addresses at present */
+ spl_image->entry_point = u_boot_pos;
+ spl_image->load_addr = u_boot_pos;
+ } else {
+ spl_image->entry_point = CONFIG_SYS_UBOOT_START;
+ spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ }
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
}
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <binman_sym.h>
+#include <mapmem.h>
#include <spl.h>
#include <libfdt.h>
load.read = spl_ram_load_read;
spl_load_simple_fit(spl_image, &load, 0, header);
} else {
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
debug("Legacy image\n");
/*
* Get the header. It will point to an address defined by
* handoff which will tell where the image located inside
- * the flash. For now, it will temporary fixed to address
- * pointed by U-Boot.
+ * the flash.
*/
- header = (struct image_header *)
- (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+ debug("u_boot_pos = %lx\n", u_boot_pos);
+ if (u_boot_pos == BINMAN_SYM_MISSING) {
+ /*
+ * No binman support or no information. For now, fix it
+ * to the address pointed to by U-Boot.
+ */
+ u_boot_pos = CONFIG_SYS_TEXT_BASE -
+ sizeof(struct image_header);
+ }
+ header = (struct image_header *)map_sysmem(u_boot_pos, 0);
spl_parse_image_header(spl_image, header);
}
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_EXYNOS5=y
-CONFIG_IDENT_STRING=" for ODROID-XU3"
+CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1"
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77970=y
+CONFIG_TARGET_EAGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77995=y
+CONFIG_TARGET_DRAAK=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_RENESAS_RPC_HF=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
Binding:
The regulator devices don't use the "compatible" property. The binding is done
-by the prefix of regulator node's name. Usually the pmic I/O driver will provide
+by the prefix of regulator node's name, or, if this fails, by the prefix of the
+regulator's "regulator-name" property. Usually the pmic I/O driver will provide
the array of 'struct pmic_child_info' with the prefixes and compatible drivers.
The bind is done by calling function: pmic_bind_childs().
Example drivers:
Example the prefix "ldo" will pass for: "ldo1", "ldo@1", "ldoreg@1, ...
+Binding by means of the node's name is preferred. However if the node names
+would produce ambiguous prefixes (like "regulator@1" and "regualtor@11") and you
+can't or do not want to change them then binding against the "regulator-name"
+property is possible. The syntax for the prefix of the "regulator-name" property
+is the same as the one for the regulator's node name.
+Use case: a regulator named "regulator@1" to be bound to a driver named
+"LDO_DRV" and a regulator named "regualator@11" to be bound to an other driver
+named "BOOST_DRV". Using prefix "regualtor@1" for driver matching would load
+the same driver for both regulators, hence the prefix is ambiguous.
+
Optional properties:
-- regulator-name: a string, required by the regulator uclass
+- regulator-name: a string, required by the regulator uclass, used for driver
+ binding if binding by node's name prefix fails
- regulator-min-microvolt: a minimum allowed Voltage value
- regulator-max-microvolt: a maximum allowed Voltage value
- regulator-min-microamp: a minimum allowed Current value
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <dm/uclass-internal.h>
static const char *if_typename_str[IF_TYPE_COUNT] = {
[IF_TYPE_IDE] = "ide",
struct blk_desc *desc;
int ret;
- ret = uclass_first_device(UCLASS_BLK, devp);
+ ret = uclass_find_first_device(UCLASS_BLK, devp);
if (ret)
return ret;
if (!*devp)
desc = dev_get_uclass_platdata(*devp);
if (desc->if_type == if_type)
return 0;
- ret = uclass_next_device(devp);
+ ret = uclass_find_next_device(devp);
if (ret)
return ret;
} while (*devp);
desc = dev_get_uclass_platdata(*devp);
if_type = desc->if_type;
do {
- ret = uclass_next_device(devp);
+ ret = uclass_find_next_device(devp);
if (ret)
return ret;
if (!*devp)
Enable support for clock present on Renesas RCar SoCs.
config CLK_RCAR_GEN3
- bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver"
+ bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
help
- Enable this to support the clocks on Renesas RCar Gen3
- R8A7795 and R8A7796 SoC.
+ Enable this to support the clocks on Renesas RCar Gen3 SoC.
/*
- * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
+ * Renesas RCar Gen3 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#define CPG_RST_MODEMR 0x0060
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
+ _div_clean) \
+ DEF_BASE(_name, _id, CLK_TYPE_FF, \
+ (_parent_clean), .div = (_div_clean), 1)
/*
* Definitions of Module Clocks
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R,
+ CLK_TYPE_GEN3_PE,
+ CLK_TYPE_GEN3_Z2,
};
struct rcar_gen3_cpg_pll_config {
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
+ CLK_PLL0D2,
+ CLK_PLL0D3,
+ CLK_PLL0D5,
+ CLK_PLL1D2,
+ CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
+ DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
+static const struct cpg_core_clk r8a77970_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
+
+ DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
+
+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+
+ /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+
+ DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+};
+
+static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+ DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
+ DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("thermal", 522, R8A77970_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
+ DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
+ DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
+ DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
+ DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
+ DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
+ DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
+ DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
+ DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
+ DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
+ DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
+ DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
+};
+
+static const struct cpg_core_clk r8a77995_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
+ DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
+ DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
+ DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
+ DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
+ DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
+ DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
+ DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
+ DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
+ DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
+
+ DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
+ DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+ DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+ DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+ DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
+};
+
+static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
+ DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
+ DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
+ DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
+ DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
+ DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
+ DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
+ DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("cmt3", 300, R8A77995_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77995_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77995_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77995_CLK_R),
+ DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
+ DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
+ DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
+ DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
+ DEF_MOD("rwdt", 402, R8A77995_CLK_R),
+ DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
+ DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
+ DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
+ DEF_MOD("thermal", 522, R8A77995_CLK_CP),
+ DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
+ DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
+ DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
+ DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
+ DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
+ DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
+ DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
+ DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
+ DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
+ DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
+ DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
+ DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
+ DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
+ DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
+ DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
+ DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
+ DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
+ DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
+ DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
+ DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+};
+
/*
* CPG Clock Data
*/
return rate;
case CLK_TYPE_FF:
+ case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
__func__, __LINE__,
enum gen3_clk_model {
CLK_R8A7795,
CLK_R8A7796,
+ CLK_R8A77970,
+ CLK_R8A77995,
};
static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
break;
+ case CLK_R8A77970:
+ priv->core_clk = r8a77970_core_clks;
+ priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
+ priv->mod_clk = r8a77970_mod_clks;
+ priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "renesas,r8a77970-rst");
+ if (ret < 0)
+ return ret;
+ break;
+ case CLK_R8A77995:
+ priv->core_clk = r8a77995_core_clks;
+ priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
+ priv->mod_clk = r8a77995_mod_clks;
+ priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
+ ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+ "renesas,r8a77995-rst");
+ if (ret < 0)
+ return ret;
+ break;
default:
return -EINVAL;
}
if (ret < 0)
return ret;
- ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
- if (ret < 0)
- return ret;
+ if (model != CLK_R8A77995) {
+ ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
+static struct mstp_stop_table r8a77970_mstp_table[] = {
+ { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
+static struct mstp_stop_table r8a77995_mstp_table[] = {
+ { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
+ { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
+ { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
+ { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
+ { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
+};
+
#define TSTR0 0x04
#define TSTR0_STR0 BIT(0)
tbl = r8a7796_mstp_table;
tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
break;
+ case CLK_R8A77970:
+ tbl = r8a77970_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
+ break;
+ case CLK_R8A77995:
+ tbl = r8a77995_mstp_table;
+ tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
+ break;
default:
return -EINVAL;
}
static const struct udevice_id gen3_clk_ids[] = {
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
+ { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
+ { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
{ }
};
static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a7795" },
{ .compatible = "renesas,gpio-r8a7796" },
+ { .compatible = "renesas,gpio-r8a77970" },
+ { .compatible = "renesas,gpio-r8a77995" },
+ { .compatible = "renesas,rcar-gen3-gpio" },
{ /* sentinel */ }
};
static const struct udevice_id uniphier_sd_match[] = {
{ .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
+ { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT },
+ { .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
{ /* sentinel */ }
};
static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-r8a7795" },
{ .compatible = "renesas,etheravb-r8a7796" },
+ { .compatible = "renesas,etheravb-r8a77970" },
+ { .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_PFC_R8A77970
+ bool "Renesas RCar Gen3 R8A77970 pin control driver"
+ def_bool y if R8A77970
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
+config PINCTRL_PFC_R8A77995
+ bool "Renesas RCar Gen3 R8A77995 pin control driver"
+ def_bool y if R8A77995
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
endif
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
--- /dev/null
+/*
+ * R8A77970 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
+ SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
+#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
+#define GPSR0_17 F_(DU_DB7, IP2_7_4)
+#define GPSR0_16 F_(DU_DB6, IP2_3_0)
+#define GPSR0_15 F_(DU_DB5, IP1_31_28)
+#define GPSR0_14 F_(DU_DB4, IP1_27_24)
+#define GPSR0_13 F_(DU_DB3, IP1_23_20)
+#define GPSR0_12 F_(DU_DB2, IP1_19_16)
+#define GPSR0_11 F_(DU_DG7, IP1_15_12)
+#define GPSR0_10 F_(DU_DG6, IP1_11_8)
+#define GPSR0_9 F_(DU_DG5, IP1_7_4)
+#define GPSR0_8 F_(DU_DG4, IP1_3_0)
+#define GPSR0_7 F_(DU_DG3, IP0_31_28)
+#define GPSR0_6 F_(DU_DG2, IP0_27_24)
+#define GPSR0_5 F_(DU_DR7, IP0_23_20)
+#define GPSR0_4 F_(DU_DR6, IP0_19_16)
+#define GPSR0_3 F_(DU_DR5, IP0_15_12)
+#define GPSR0_2 F_(DU_DR4, IP0_11_8)
+#define GPSR0_1 F_(DU_DR3, IP0_7_4)
+#define GPSR0_0 F_(DU_DR2, IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
+#define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
+#define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
+#define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
+#define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
+#define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
+#define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
+#define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
+#define GPSR1_19 FM(AVB0_AVTP_MATCH)
+#define GPSR1_18 FM(AVB0_LINK)
+#define GPSR1_17 FM(AVB0_PHY_INT)
+#define GPSR1_16 FM(AVB0_MAGIC)
+#define GPSR1_15 FM(AVB0_MDC)
+#define GPSR1_14 FM(AVB0_MDIO)
+#define GPSR1_13 FM(AVB0_TXCREFCLK)
+#define GPSR1_12 FM(AVB0_TD3)
+#define GPSR1_11 FM(AVB0_TD2)
+#define GPSR1_10 FM(AVB0_TD1)
+#define GPSR1_9 FM(AVB0_TD0)
+#define GPSR1_8 FM(AVB0_TXC)
+#define GPSR1_7 FM(AVB0_TX_CTL)
+#define GPSR1_6 FM(AVB0_RD3)
+#define GPSR1_5 FM(AVB0_RD2)
+#define GPSR1_4 FM(AVB0_RD1)
+#define GPSR1_3 FM(AVB0_RD0)
+#define GPSR1_2 FM(AVB0_RXC)
+#define GPSR1_1 FM(AVB0_RX_CTL)
+#define GPSR1_0 F_(IRQ0, IP2_27_24)
+
+/* GPSR2 */
+#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
+#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
+#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
+#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
+#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
+#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
+#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
+#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
+#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
+#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
+#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
+#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
+#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
+#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
+#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
+#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
+#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
+
+/* GPSR3 */
+#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
+#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
+#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
+#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
+#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
+#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
+#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
+#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
+#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
+#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
+#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
+#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
+#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
+#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
+#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
+#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
+#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
+
+/* GPSR4 */
+#define GPSR4_5 F_(SDA2, IP7_27_24)
+#define GPSR4_4 F_(SCL2, IP7_23_20)
+#define GPSR4_3 F_(SDA1, IP7_19_16)
+#define GPSR4_2 F_(SCL1, IP7_15_12)
+#define GPSR4_1 F_(SDA0, IP7_11_8)
+#define GPSR4_0 F_(SCL0, IP7_7_4)
+
+/* GPSR5 */
+#define GPSR5_14 FM(RPC_INT_N)
+#define GPSR5_13 FM(RPC_WP_N)
+#define GPSR5_12 FM(RPC_RESET_N)
+#define GPSR5_11 FM(QSPI1_SSL)
+#define GPSR5_10 FM(QSPI1_IO3)
+#define GPSR5_9 FM(QSPI1_IO2)
+#define GPSR5_8 FM(QSPI1_MISO_IO1)
+#define GPSR5_7 FM(QSPI1_MOSI_IO0)
+#define GPSR5_6 FM(QSPI1_SPCLK)
+#define GPSR5_5 FM(QSPI0_SSL)
+#define GPSR5_4 FM(QSPI0_IO3)
+#define GPSR5_3 FM(QSPI0_IO2)
+#define GPSR5_2 FM(QSPI0_MISO_IO1)
+#define GPSR5_1 FM(QSPI0_MOSI_IO0)
+#define GPSR5_0 FM(QSPI0_SPCLK)
+
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C */ /* D */ /* E */ /* F */
+#define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N_A26) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR1_27 \
+ GPSR1_26 \
+ GPSR1_25 \
+ GPSR1_24 \
+ GPSR1_23 \
+ GPSR1_22 \
+GPSR0_21 GPSR1_21 \
+GPSR0_20 GPSR1_20 \
+GPSR0_19 GPSR1_19 \
+GPSR0_18 GPSR1_18 \
+GPSR0_17 GPSR1_17 \
+GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
+GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
+GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
+GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
+GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
+GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
+GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
+GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 \
+FM(IP8_7_4) IP8_7_4 \
+FM(IP8_11_8) IP8_11_8 \
+FM(IP8_15_12) IP8_15_12 \
+FM(IP8_19_16) IP8_19_16 \
+FM(IP8_23_20) IP8_23_20 \
+FM(IP8_27_24) IP8_27_24 \
+FM(IP8_31_28) IP8_31_28
+
+/*
+ Set Value = H'0 Set Value = H'1
+Register Function Pin Function Pin
+------------------------------------------------------------
+sel_i2c3 SDA3_A VI0_DATA2 SDA3_B VI1_DATA10
+ SCL3_A VI0_DATA3 SCL3_B VI1_DATA9
+sel_hscif0 HSCIF0_A SCIF_CLK HSCIF0_B SCIF_CLK
+sel_scif1 SCIF1_A RX1 SCIF1_B TX1
+ SCIF1_A TX1 SCIF1_B RX1
+sel_canfd0 CANFD0_A CANFD0_TX CANFD0_B CANFD0_TX
+ CANFD0_A CANFD0_RX CANFD0_B CANFD0_RX
+ CANFD0_A CANFD_CLK CANFD0_B CANFD_CLK
+sel_pwm4 PWM4_A PWM4 PWM4_B PWM4
+sel_pwm3 PWM3_A PWM3 PWM3_B PWM3
+sel_pwm2 PWM2_A PWM2 PWM2_B PWM2
+sel_pwm1 PWM1_A PWM1 PWM1_B PWM1
+sel_pwm0 PWM0_A PWM0 PWM0_B PWM0
+sel_rfso RFSO_A FSO_CFE_0_N RFSO_B FSO_CFE_0_N
+ RFSO_A FSO_CFE_1_N RFSO_B FSO_CFE_1_N
+ RFSO_A FSO_TOE_N RFSO_B FSO_TOE_N
+sel_rsp RSP_A SPEEDIN RSP_B SPEEDIN
+sel_tmu TMU_A TCLK1 TMU_B TCLK1
+ TMU_A TCLK2 TMU_B TCLK2
+*/
+/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
+#define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
+#define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
+#define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
+#define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
+#define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
+#define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
+#define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
+#define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
+#define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
+#define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
+#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
+
+#define PINMUX_MOD_SELS \
+\
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_9 \
+MOD_SEL0_8 \
+MOD_SEL0_7 \
+MOD_SEL0_6 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_3 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(AVB0_RX_CTL),
+ PINMUX_SINGLE(AVB0_RXC),
+ PINMUX_SINGLE(AVB0_RD0),
+ PINMUX_SINGLE(AVB0_RD1),
+ PINMUX_SINGLE(AVB0_RD2),
+ PINMUX_SINGLE(AVB0_RD3),
+ PINMUX_SINGLE(AVB0_TX_CTL),
+ PINMUX_SINGLE(AVB0_TXC),
+ PINMUX_SINGLE(AVB0_TD0),
+ PINMUX_SINGLE(AVB0_TD1),
+ PINMUX_SINGLE(AVB0_TD2),
+ PINMUX_SINGLE(AVB0_TD3),
+ PINMUX_SINGLE(AVB0_TXCREFCLK),
+ PINMUX_SINGLE(AVB0_MDIO),
+ PINMUX_SINGLE(AVB0_MDC),
+ PINMUX_SINGLE(AVB0_MAGIC),
+ PINMUX_SINGLE(AVB0_PHY_INT),
+ PINMUX_SINGLE(AVB0_LINK),
+ PINMUX_SINGLE(AVB0_AVTP_MATCH),
+
+ PINMUX_SINGLE(QSPI0_SPCLK),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(RPC_WP_N),
+ PINMUX_SINGLE(RPC_INT_N),
+
+ /* IPSR0 */
+ PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
+ PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
+ PINMUX_IPSR_GPSR(IP0_3_0, A0),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
+ PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
+ PINMUX_IPSR_GPSR(IP0_7_4, A1),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
+ PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
+ PINMUX_IPSR_GPSR(IP0_11_8, A2),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
+ PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
+ PINMUX_IPSR_GPSR(IP0_15_12, A3),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
+ PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
+ PINMUX_IPSR_GPSR(IP0_19_16, A4),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
+ PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
+ PINMUX_IPSR_GPSR(IP0_23_20, A5),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
+ PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
+ PINMUX_IPSR_GPSR(IP0_27_24, A6),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
+ PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
+ PINMUX_IPSR_GPSR(IP0_31_28, A7),
+ PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
+ PINMUX_IPSR_GPSR(IP1_3_0, A8),
+ PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
+ PINMUX_IPSR_GPSR(IP1_7_4, A9),
+ PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
+ PINMUX_IPSR_GPSR(IP1_11_8, A10),
+ PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
+ PINMUX_IPSR_GPSR(IP1_15_12, A11),
+ PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
+ PINMUX_IPSR_GPSR(IP1_19_16, A12),
+ PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
+ PINMUX_IPSR_GPSR(IP1_23_20, A13),
+ PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
+ PINMUX_IPSR_GPSR(IP1_27_24, A14),
+ PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
+ PINMUX_IPSR_GPSR(IP1_31_28, A15),
+ PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
+ PINMUX_IPSR_GPSR(IP2_3_0, A16),
+ PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
+ PINMUX_IPSR_GPSR(IP2_7_4, A17),
+ PINMUX_IPSR_GPSR(IP2_7_4, STPWT_EXTFXR),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
+ PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
+ PINMUX_IPSR_GPSR(IP2_11_8, A18),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
+ PINMUX_IPSR_GPSR(IP2_15_12, A19),
+ PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
+ PINMUX_IPSR_GPSR(IP2_19_16, A20),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
+ PINMUX_IPSR_GPSR(IP2_23_20, A21),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
+ PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
+ PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
+ PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
+ PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
+ PINMUX_IPSR_GPSR(IP3_3_0, RX3),
+ PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
+ PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
+ PINMUX_IPSR_GPSR(IP3_7_4, TX3),
+ PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
+ PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
+ PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
+ PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
+ PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
+ PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
+ PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
+ PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_1),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
+ PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
+ PINMUX_IPSR_GPSR(IP3_23_20, SDA3_A),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
+ PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
+ PINMUX_IPSR_GPSR(IP3_27_24, SCL3_A),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
+ PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
+ PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
+ PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
+ PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
+ PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
+ PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
+ PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
+ PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
+ PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
+ PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
+ PINMUX_IPSR_GPSR(IP4_15_12, A22),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
+ PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
+ PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
+ PINMUX_IPSR_GPSR(IP4_19_16, A23),
+ PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
+ PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
+ PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
+ PINMUX_IPSR_GPSR(IP4_23_20, A24),
+ PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
+ PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
+ PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
+ PINMUX_IPSR_GPSR(IP4_27_24, A25),
+ PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
+ PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
+ PINMUX_IPSR_GPSR(IP4_31_28, CS1_N_A26),
+ PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
+ PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
+ PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
+ PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP5_7_4, D0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP5_11_8, D1),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
+ PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP5_15_12, D2),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
+ PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP5_19_16, D3),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
+ PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP5_23_20, D4),
+ PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
+ PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_27_24, D5),
+ PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
+ PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP5_31_28, D6),
+ PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
+ PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
+ PINMUX_IPSR_GPSR(IP6_3_0, D7),
+ PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
+ PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
+ PINMUX_IPSR_GPSR(IP6_7_4, D8),
+ PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
+ PINMUX_IPSR_GPSR(IP6_11_8, RX4),
+ PINMUX_IPSR_GPSR(IP6_11_8, D9),
+ PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
+ PINMUX_IPSR_GPSR(IP6_15_12, TX4),
+ PINMUX_IPSR_GPSR(IP6_15_12, D10),
+ PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
+ PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
+ PINMUX_IPSR_GPSR(IP6_19_16, D11),
+ PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
+ PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
+ PINMUX_IPSR_GPSR(IP6_23_20, D12),
+ PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
+ PINMUX_IPSR_GPSR(IP6_23_20, SCL3_B),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
+ PINMUX_IPSR_GPSR(IP6_27_24, D13),
+ PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
+ PINMUX_IPSR_GPSR(IP6_27_24, SDA3_B),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
+ PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
+ PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
+ PINMUX_IPSR_GPSR(IP6_31_28, D14),
+ PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
+ PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
+ PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
+ PINMUX_IPSR_GPSR(IP7_3_0, D15),
+ PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
+ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
+ PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
+ PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
+ PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
+ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
+ PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
+ PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
+ PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
+ PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
+ PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
+ PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
+ PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
+ PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
+ PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
+ PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
+ PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
+ PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
+ PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
+ PINMUX_IPSR_GPSR(IP7_23_20, RX0),
+ PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
+ PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
+ PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
+ PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
+ PINMUX_IPSR_GPSR(IP7_27_24, TX0),
+ PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
+ PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
+
+ /* IPSR8 */
+ PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
+ PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
+ PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
+ PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
+
+ PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
+
+ PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
+ PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
+ PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_0),
+ PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
+ PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
+ PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb0_rx_ctrl_pins[] = {
+ /* AVB0_RX_CTL */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int avb0_rx_ctrl_mux[] = {
+ AVB0_RX_CTL_MARK,
+};
+static const unsigned int avb0_rxc_pins[] = {
+ /* AVB0_RXC */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int avb0_rxc_mux[] = {
+ AVB0_RXC_MARK,
+};
+static const unsigned int avb0_rd0_pins[] = {
+ /* AVB0_RD[0] */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int avb0_rd0_mux[] = {
+ AVB0_RD0_MARK,
+};
+static const unsigned int avb0_rd1_pins[] = {
+ /* AVB0_RD[1] */
+ RCAR_GP_PIN(1, 4),
+};
+static const unsigned int avb0_rd1_mux[] = {
+ AVB0_RD1_MARK,
+};
+static const unsigned int avb0_rd2_pins[] = {
+ /* AVB0_RD[2] */
+ RCAR_GP_PIN(1, 5),
+};
+static const unsigned int avb0_rd2_mux[] = {
+ AVB0_RD2_MARK,
+};
+static const unsigned int avb0_rd3_pins[] = {
+ /* AVB0_RD[3] */
+ RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb0_rd3_mux[] = {
+ AVB0_RD3_MARK,
+};
+static const unsigned int avb0_rd4_pins[] = {
+ /* AVB0_RD[3:0] */
+ RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int avb0_rd4_mux[] = {
+ AVB0_RD0_MARK, AVB0_RD1_MARK,
+ AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_tx_ctrl_pins[] = {
+ /* AVB0_TX_CTL */
+ RCAR_GP_PIN(1, 7),
+};
+static const unsigned int avb0_tx_ctrl_mux[] = {
+ AVB0_TX_CTL_MARK,
+};
+static const unsigned int avb0_txc_pins[] = {
+ /* AVB0_TXC */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int avb0_txc_mux[] = {
+ AVB0_TXC_MARK,
+};
+static const unsigned int avb0_td0_pins[] = {
+ /* AVB0_TD[0] */
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int avb0_td0_mux[] = {
+ AVB0_TD0_MARK,
+};
+static const unsigned int avb0_td1_pins[] = {
+ /* AVB0_TD[1] */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int avb0_td1_mux[] = {
+ AVB0_TD1_MARK,
+};
+static const unsigned int avb0_td2_pins[] = {
+ /* AVB0_TD[2] */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int avb0_td2_mux[] = {
+ AVB0_TD2_MARK,
+};
+static const unsigned int avb0_td3_pins[] = {
+ /* AVB0_TD[3] */
+ RCAR_GP_PIN(1, 12),
+};
+static const unsigned int avb0_td3_mux[] = {
+ AVB0_TD3_MARK,
+};
+static const unsigned int avb0_td4_pins[] = {
+ /* AVB0_TD[3:0] */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
+ RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int avb0_td4_mux[] = {
+ AVB0_TD0_MARK, AVB0_TD1_MARK,
+ AVB0_TD2_MARK, AVB0_TD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDIO */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_mdc_pins[] = {
+ /* AVB0_MDC */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int avb0_mdc_mux[] = {
+ AVB0_MDC_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(1, 16),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(1, 18),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(1, 19),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(1, 20),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_a_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int canfd0_data_a_mux[] = {
+ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
+};
+static const unsigned int canfd_clk_a_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int canfd_clk_a_mux[] = {
+ CANFD_CLK_A_MARK,
+};
+static const unsigned int canfd0_data_b_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int canfd0_data_b_mux[] = {
+ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
+};
+static const unsigned int canfd_clk_b_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(3, 8),
+};
+static const unsigned int canfd_clk_b_mux[] = {
+ CANFD_CLK_B_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* TX, RX */
+ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+ /* R[7:0] */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+ RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+ /* G[7:0] */
+ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
+ /* B[7:0] */
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+ RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+};
+static const unsigned int du_rgb666_mux[] = {
+ DU_DR7_MARK, DU_DR6_MARK,
+ DU_DR5_MARK, DU_DR4_MARK,
+ DU_DR3_MARK, DU_DR2_MARK,
+ DU_DG7_MARK, DU_DG6_MARK,
+ DU_DG5_MARK, DU_DG4_MARK,
+ DU_DG3_MARK, DU_DG2_MARK,
+ DU_DB7_MARK, DU_DB6_MARK,
+ DU_DB5_MARK, DU_DB4_MARK,
+ DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_clk_out_0_pins[] = {
+ /* CLKOUT0 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_clk_out_1_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(0, 18), /* @@ */
+};
+static const unsigned int du_clk_out_1_mux[] = {
+ DU_DOTCLKOUT_MARK,
+};
+static const unsigned int du_sync_pins[] = {
+ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+ RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
+};
+static const unsigned int du_sync_mux[] = {
+ DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
+};
+static const unsigned int du_oddf_pins[] = {
+ /* EXDISP/EXODDF/EXCDE */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int du_oddf_mux[] = {
+ DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+ /* CDE */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int du_cde_mux[] = {
+ DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+ /* DISP */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int du_disp_mux[] = {
+ DU_DISP_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(0, 0),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int scif_clk_a_mux[] = {
+ SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif_clk_b_mux[] = {
+ SCIF_CLK_B_MARK,
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+static const unsigned int i2c3_pins[] = {
+ /* SDA3_A, SCL3_A */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_A_MARK, SCL3_A_MARK,
+};
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(0, 11),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(0, 19),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 2),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(4, 0),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 20),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* SYNC */
+ RCAR_GP_PIN(0, 21),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* SS1 */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* SS2 */
+ RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* TXD */
+ RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* RXD */
+ RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int pwm0_a_mux[] = {
+ PWM0_A_MARK,
+};
+static const unsigned int pwm0_b_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(1, 21),
+};
+static const unsigned int pwm0_b_mux[] = {
+ PWM0_B_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_a_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_a_mux[] = {
+ PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_a_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_a_mux[] = {
+ PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int pwm4_b_mux[] = {
+ PWM4_B_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_TANS_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_TANS_MARK, CTS4_N_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 6),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int mmc_cd_mux[] = {
+ MMC_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 15),
+};
+static const unsigned int mmc_wp_mux[] = {
+ MMC_WP_MARK,
+};
+
+/* - TMU -------------------------------------------------------------------- */
+static const unsigned int tmu_tclk1_a_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+ TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+ /* TCLK1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+ TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+ TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+ /* TCLK2 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+ TCLK2_B_MARK,
+};
+
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int vin0_data8_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+};
+static const unsigned int vin0_data10_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data10_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+};
+static const unsigned int vin0_data12_pins[] = {
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int vin0_data12_mux[] = {
+ VI0_DATA0_MARK, VI0_DATA1_MARK,
+ VI0_DATA2_MARK, VI0_DATA3_MARK,
+ VI0_DATA4_MARK, VI0_DATA5_MARK,
+ VI0_DATA6_MARK, VI0_DATA7_MARK,
+ VI0_DATA8_MARK, VI0_DATA9_MARK,
+ VI0_DATA10_MARK, VI0_DATA11_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+ /* VSYNC_N, HSYNC_N */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int vin0_sync_mux[] = {
+ VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
+};
+static const unsigned int vin0_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int vin0_field_mux[] = {
+ VI0_FIELD_MARK,
+};
+static const unsigned int vin0_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clkenb_mux[] = {
+ VI0_CLKENB_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin0_clk_mux[] = {
+ VI0_CLK_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int vin1_data8_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+};
+static const unsigned int vin1_data10_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int vin1_data10_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+};
+static const unsigned int vin1_data12_pins[] = {
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+ RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int vin1_data12_mux[] = {
+ VI1_DATA0_MARK, VI1_DATA1_MARK,
+ VI1_DATA2_MARK, VI1_DATA3_MARK,
+ VI1_DATA4_MARK, VI1_DATA5_MARK,
+ VI1_DATA6_MARK, VI1_DATA7_MARK,
+ VI1_DATA8_MARK, VI1_DATA9_MARK,
+ VI1_DATA10_MARK, VI1_DATA11_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+ /* VSYNC_N, HSYNC_N */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int vin1_sync_mux[] = {
+ VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
+};
+static const unsigned int vin1_field_pins[] = {
+ /* FIELD */
+ RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin1_field_mux[] = {
+ VI1_FIELD_MARK,
+};
+static const unsigned int vin1_clkenb_pins[] = {
+ /* CLKENB */
+ RCAR_GP_PIN(3, 1),
+};
+static const unsigned int vin1_clkenb_mux[] = {
+ VI1_CLKENB_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+ /* CLK */
+ RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_clk_mux[] = {
+ VI1_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_rx_ctrl),
+ SH_PFC_PIN_GROUP(avb0_rxc),
+ SH_PFC_PIN_GROUP(avb0_rd0),
+ SH_PFC_PIN_GROUP(avb0_rd1),
+ SH_PFC_PIN_GROUP(avb0_rd2),
+ SH_PFC_PIN_GROUP(avb0_rd3),
+ SH_PFC_PIN_GROUP(avb0_rd4),
+ SH_PFC_PIN_GROUP(avb0_tx_ctrl),
+ SH_PFC_PIN_GROUP(avb0_txc),
+ SH_PFC_PIN_GROUP(avb0_td0),
+ SH_PFC_PIN_GROUP(avb0_td1),
+ SH_PFC_PIN_GROUP(avb0_td2),
+ SH_PFC_PIN_GROUP(avb0_td3),
+ SH_PFC_PIN_GROUP(avb0_td4),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_mdc),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(canfd0_data_a),
+ SH_PFC_PIN_GROUP(canfd_clk_a),
+ SH_PFC_PIN_GROUP(canfd0_data_b),
+ SH_PFC_PIN_GROUP(canfd_clk_b),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(du_rgb666),
+ SH_PFC_PIN_GROUP(du_clk_out_0),
+ SH_PFC_PIN_GROUP(du_clk_out_1),
+ SH_PFC_PIN_GROUP(du_sync),
+ SH_PFC_PIN_GROUP(du_oddf),
+ SH_PFC_PIN_GROUP(du_cde),
+ SH_PFC_PIN_GROUP(du_disp),
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk_a),
+ SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm0_b),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_a),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
+ SH_PFC_PIN_GROUP(pwm4_a),
+ SH_PFC_PIN_GROUP(pwm4_b),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
+ SH_PFC_PIN_GROUP(vin0_data8),
+ SH_PFC_PIN_GROUP(vin0_data10),
+ SH_PFC_PIN_GROUP(vin0_data12),
+ SH_PFC_PIN_GROUP(vin0_sync),
+ SH_PFC_PIN_GROUP(vin0_field),
+ SH_PFC_PIN_GROUP(vin0_clkenb),
+ SH_PFC_PIN_GROUP(vin0_clk),
+ SH_PFC_PIN_GROUP(vin1_data8),
+ SH_PFC_PIN_GROUP(vin1_data10),
+ SH_PFC_PIN_GROUP(vin1_data12),
+ SH_PFC_PIN_GROUP(vin1_sync),
+ SH_PFC_PIN_GROUP(vin1_field),
+ SH_PFC_PIN_GROUP(vin1_clkenb),
+ SH_PFC_PIN_GROUP(vin1_clk),
+};
+
+static const char * const avb0_groups[] = {
+ "avb0_rx_ctrl",
+ "avb0_rxc",
+ "avb0_rd1",
+ "avb0_rd4",
+ "avb0_tx_ctrl",
+ "avb0_txc",
+ "avb0_td1",
+ "avb0_td4",
+ "avb0_txcrefclk",
+ "avb0_mdio",
+ "avb0_mdc",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_link",
+ "avb0_avtp_match",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data_a",
+ "canfd_clk_a",
+ "canfd0_data_b",
+ "canfd_clk_b",
+};
+
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const du_groups[] = {
+ "du_rgb666",
+ "du_clk_out_0",
+ "du_clk_out_1",
+ "du_sync",
+ "du_oddf",
+ "du_cde",
+ "du_disp",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk_a",
+ "scif_clk_b",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0_a",
+ "pwm0_b",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1_a",
+ "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2_a",
+ "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3_a",
+ "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4_a",
+ "pwm4_b",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+// "scif0_clk",
+// "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+};
+
+static const char * const tmu_groups[] = {
+ "tmu_tclk1_a",
+ "tmu_tclk1_b",
+ "tmu_tclk2_a",
+ "tmu_tclk2_b",
+};
+
+static const char * const vin0_groups[] = {
+ "vin0_data8",
+ "vin0_data10",
+ "vin0_data12",
+ "vin0_sync",
+ "vin0_field",
+ "vin0_clkenb",
+ "vin0_clk",
+};
+
+static const char * const vin1_groups[] = {
+ "vin1_data8",
+ "vin1_data10",
+ "vin1_data12",
+ "vin1_sync",
+ "vin1_field",
+ "vin1_clkenb",
+ "vin1_clk",
+};
+
+#define POCCTRL0 0x380
+#define POCCTRL1 0x384
+#define PIN2POCCTRL0_SHIFT(a) ({ \
+ int _gp = (a) >> 5; \
+ int _bit = (a) & 0x1f; \
+ ((_gp == 3) && (_bit < 17)) ? _bit + 7 : -1; \
+})
+
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(du),
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(intc_ex),
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(tmu),
+ SH_PFC_FUNCTION(vin0),
+ SH_PFC_FUNCTION(vin1),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_21_FN, GPSR0_21,
+ GP_0_20_FN, GPSR0_20,
+ GP_0_19_FN, GPSR0_19,
+ GP_0_18_FN, GPSR0_18,
+ GP_0_17_FN, GPSR0_17,
+ GP_0_16_FN, GPSR0_16,
+ GP_0_15_FN, GPSR0_15,
+ GP_0_14_FN, GPSR0_14,
+ GP_0_13_FN, GPSR0_13,
+ GP_0_12_FN, GPSR0_12,
+ GP_0_11_FN, GPSR0_11,
+ GP_0_10_FN, GPSR0_10,
+ GP_0_9_FN, GPSR0_9,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_16_FN, GPSR3_16,
+ GP_3_15_FN, GPSR3_15,
+ GP_3_14_FN, GPSR3_14,
+ GP_3_13_FN, GPSR3_13,
+ GP_3_12_FN, GPSR3_12,
+ GP_3_11_FN, GPSR3_11,
+ GP_3_10_FN, GPSR3_10,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) {
+ /* RESERVED 31..12 */
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MOD_SEL0_11
+ MOD_SEL0_10
+ MOD_SEL0_9
+ MOD_SEL0_8
+ MOD_SEL0_7
+ MOD_SEL0_6
+ MOD_SEL0_5
+ MOD_SEL0_4
+ MOD_SEL0_3
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 }
+ },
+ { },
+};
+
+static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = 0xe6060384;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+ bit = (pin & 0x1f) + 7;
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations pinmux_ops = {
+ .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a77970_pinmux_info = {
+ .name = "r8a77970_pfc",
+ .ops = &pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
--- /dev/null
+/*
+ * R8A77995 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_9(0, fn, sfx), \
+ PORT_GP_32(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_21(5, fn, sfx), \
+ PORT_GP_14(6, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
+#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
+#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
+#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
+#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
+#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
+#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
+#define GPSR0_1 FM(USB0_OVC)
+#define GPSR0_0 FM(USB0_PWEN)
+
+/* GPSR1 */
+#define GPSR1_31 F_(QPOLB, IP4_27_24)
+#define GPSR1_30 F_(QPOLA, IP4_23_20)
+#define GPSR1_29 F_(DU_CDE, IP4_19_16)
+#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
+#define GPSR1_27 F_(DU_DISP, IP4_11_8)
+#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
+#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
+#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
+#define GPSR1_23 F_(DU_DR7, IP3_27_24)
+#define GPSR1_22 F_(DU_DR6, IP3_23_20)
+#define GPSR1_21 F_(DU_DR5, IP3_19_16)
+#define GPSR1_20 F_(DU_DR4, IP3_15_12)
+#define GPSR1_19 F_(DU_DR3, IP3_11_8)
+#define GPSR1_18 F_(DU_DR2, IP3_7_4)
+#define GPSR1_17 F_(DU_DR1, IP3_3_0)
+#define GPSR1_16 F_(DU_DR0, IP2_31_28)
+#define GPSR1_15 F_(DU_DG7, IP2_27_24)
+#define GPSR1_14 F_(DU_DG6, IP2_23_20)
+#define GPSR1_13 F_(DU_DG5, IP2_19_16)
+#define GPSR1_12 F_(DU_DG4, IP2_15_12)
+#define GPSR1_11 F_(DU_DG3, IP2_11_8)
+#define GPSR1_10 F_(DU_DG2, IP2_7_4)
+#define GPSR1_9 F_(DU_DG1, IP2_3_0)
+#define GPSR1_8 F_(DU_DG0, IP1_31_28)
+#define GPSR1_7 F_(DU_DB7, IP1_27_24)
+#define GPSR1_6 F_(DU_DB6, IP1_23_20)
+#define GPSR1_5 F_(DU_DB5, IP1_19_16)
+#define GPSR1_4 F_(DU_DB4, IP1_15_12)
+#define GPSR1_3 F_(DU_DB3, IP1_11_8)
+#define GPSR1_2 F_(DU_DB2, IP1_7_4)
+#define GPSR1_1 F_(DU_DB1, IP1_3_0)
+#define GPSR1_0 F_(DU_DB0, IP0_31_28)
+
+/* GPSR2 */
+#define GPSR2_31 F_(NFCE_N, IP8_19_16)
+#define GPSR2_30 F_(NFCLE, IP8_15_12)
+#define GPSR2_29 F_(NFALE, IP8_11_8)
+#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
+#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
+#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
+#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
+#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
+#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
+#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
+#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
+#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
+#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
+#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
+#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
+#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
+#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
+#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
+#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
+#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
+#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
+#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
+#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
+#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
+#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
+#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
+#define GPSR2_5 FM(VI4_DATA4)
+#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
+#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
+#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
+#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
+#define GPSR2_0 FM(VI4_CLK)
+
+/* GPSR3 */
+#define GPSR3_9 F_(NFDATA7, IP9_31_28)
+#define GPSR3_8 F_(NFDATA6, IP9_27_24)
+#define GPSR3_7 F_(NFDATA5, IP9_23_20)
+#define GPSR3_6 F_(NFDATA4, IP9_19_16)
+#define GPSR3_5 F_(NFDATA3, IP9_15_12)
+#define GPSR3_4 F_(NFDATA2, IP9_11_8)
+#define GPSR3_3 F_(NFDATA1, IP9_7_4)
+#define GPSR3_2 F_(NFDATA0, IP9_3_0)
+#define GPSR3_1 F_(NFWE_N, IP8_31_28)
+#define GPSR3_0 F_(NFRE_N, IP8_27_24)
+
+/* GPSR4 */
+#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
+#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
+#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
+#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
+#define GPSR4_27 FM(TX2)
+#define GPSR4_26 FM(RX2)
+#define GPSR4_25 F_(SCK2, IP12_11_8)
+#define GPSR4_24 F_(TX1_A, IP12_7_4)
+#define GPSR4_23 F_(RX1_A, IP12_3_0)
+#define GPSR4_22 F_(SCK1_A, IP11_31_28)
+#define GPSR4_21 F_(TX0_A, IP11_27_24)
+#define GPSR4_20 F_(RX0_A, IP11_23_20)
+#define GPSR4_19 F_(SCK0_A, IP11_19_16)
+#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
+#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
+#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
+#define GPSR4_15 FM(MSIOF0_RXD)
+#define GPSR4_14 FM(MSIOF0_TXD)
+#define GPSR4_13 FM(MSIOF0_SYNC)
+#define GPSR4_12 FM(MSIOF0_SCK)
+#define GPSR4_11 F_(SDA1, IP11_3_0)
+#define GPSR4_10 F_(SCL1, IP10_31_28)
+#define GPSR4_9 FM(SDA0)
+#define GPSR4_8 FM(SCL0)
+#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
+#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
+#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
+#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
+#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
+#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
+#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
+#define GPSR4_0 F_(NFRB_N, IP8_23_20)
+
+/* GPSR5 */
+#define GPSR5_20 FM(AVB0_LINK)
+#define GPSR5_19 FM(AVB0_PHY_INT)
+#define GPSR5_18 FM(AVB0_MAGIC)
+#define GPSR5_17 FM(AVB0_MDC)
+#define GPSR5_16 FM(AVB0_MDIO)
+#define GPSR5_15 FM(AVB0_TXCREFCLK)
+#define GPSR5_14 FM(AVB0_TD3)
+#define GPSR5_13 FM(AVB0_TD2)
+#define GPSR5_12 FM(AVB0_TD1)
+#define GPSR5_11 FM(AVB0_TD0)
+#define GPSR5_10 FM(AVB0_TXC)
+#define GPSR5_9 FM(AVB0_TX_CTL)
+#define GPSR5_8 FM(AVB0_RD3)
+#define GPSR5_7 FM(AVB0_RD2)
+#define GPSR5_6 FM(AVB0_RD1)
+#define GPSR5_5 FM(AVB0_RD0)
+#define GPSR5_4 FM(AVB0_RXC)
+#define GPSR5_3 FM(AVB0_RX_CTL)
+#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
+#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
+#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
+
+/* GPSR6 */
+#define GPSR6_13 FM(RPC_INT_N)
+#define GPSR6_12 FM(RPC_RESET_N)
+#define GPSR6_11 FM(QSPI1_SSL)
+#define GPSR6_10 FM(QSPI1_IO3)
+#define GPSR6_9 FM(QSPI1_IO2)
+#define GPSR6_8 FM(QSPI1_MISO_IO1)
+#define GPSR6_7 FM(QSPI1_MOSI_IO0)
+#define GPSR6_6 FM(QSPI1_SPCLK)
+#define GPSR6_5 FM(QSPI0_SSL)
+#define GPSR6_4 FM(QSPI0_IO3)
+#define GPSR6_3 FM(QSPI0_IO2)
+#define GPSR6_2 FM(QSPI0_MISO_IO1)
+#define GPSR6_1 FM(QSPI0_MOSI_IO0)
+#define GPSR6_0 FM(QSPI0_SPCLK)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
+#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR \
+\
+ GPSR1_31 GPSR2_31 GPSR4_31 \
+ GPSR1_30 GPSR2_30 GPSR4_30 \
+ GPSR1_29 GPSR2_29 GPSR4_29 \
+ GPSR1_28 GPSR2_28 GPSR4_28 \
+ GPSR1_27 GPSR2_27 GPSR4_27 \
+ GPSR1_26 GPSR2_26 GPSR4_26 \
+ GPSR1_25 GPSR2_25 GPSR4_25 \
+ GPSR1_24 GPSR2_24 GPSR4_24 \
+ GPSR1_23 GPSR2_23 GPSR4_23 \
+ GPSR1_22 GPSR2_22 GPSR4_22 \
+ GPSR1_21 GPSR2_21 GPSR4_21 \
+ GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
+ GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
+ GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
+ GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
+ GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
+ GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
+ GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
+ GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
+ GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
+ GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
+ GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
+ GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
+GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
+GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
+GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
+GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
+GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
+GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
+GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
+GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
+GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
+
+#define PINMUX_IPSR \
+\
+FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
+FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
+FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
+FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
+FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
+FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
+FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
+FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
+\
+FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
+FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
+FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
+FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
+FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
+FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
+FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
+FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
+\
+FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
+FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
+FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
+FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
+FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
+FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
+FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
+FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
+\
+FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
+FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
+FM(IP12_11_8) IP12_11_8 \
+FM(IP12_15_12) IP12_15_12 \
+FM(IP12_19_16) IP12_19_16 \
+FM(IP12_23_20) IP12_23_20 \
+FM(IP12_27_24) IP12_27_24 \
+FM(IP12_31_28) IP12_31_28 \
+
+/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
+#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
+#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
+#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
+#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
+#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
+#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
+#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
+#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
+#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
+#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
+#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
+#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
+#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
+#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
+#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
+#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
+#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
+#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
+#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
+#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
+#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
+#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
+
+#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
+#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
+#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
+#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
+#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
+#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
+
+
+#define PINMUX_MOD_SELS \
+\
+ MOD_SEL1_31 \
+MOD_SEL0_30 MOD_SEL1_30 \
+MOD_SEL0_29 MOD_SEL1_29 \
+MOD_SEL0_28 MOD_SEL1_28 \
+MOD_SEL0_27 MOD_SEL1_27 \
+MOD_SEL0_26 MOD_SEL1_26 \
+MOD_SEL0_25 \
+MOD_SEL0_24_23 \
+MOD_SEL0_22_21 \
+MOD_SEL0_20_19 \
+MOD_SEL0_18_17 \
+MOD_SEL0_15 \
+MOD_SEL0_14 \
+MOD_SEL0_13 \
+MOD_SEL0_12 \
+MOD_SEL0_11 \
+MOD_SEL0_10 \
+MOD_SEL0_5 \
+MOD_SEL0_4 \
+MOD_SEL0_3 \
+MOD_SEL0_2 \
+MOD_SEL0_1 \
+MOD_SEL0_0
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x) FN_##x,
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x) x##_MARK,
+ PINMUX_MARK_BEGIN,
+ PINMUX_GPSR
+ PINMUX_IPSR
+ PINMUX_MOD_SELS
+ PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+ PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+ PINMUX_DATA(fn##_MARK, FN_##msel)
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(),
+
+ PINMUX_SINGLE(USB0_OVC),
+ PINMUX_SINGLE(USB0_PWEN),
+ PINMUX_SINGLE(VI4_DATA4),
+ PINMUX_SINGLE(VI4_CLK),
+ PINMUX_SINGLE(TX2),
+ PINMUX_SINGLE(RX2),
+ PINMUX_SINGLE(AVB0_LINK),
+ PINMUX_SINGLE(AVB0_PHY_INT),
+ PINMUX_SINGLE(AVB0_MAGIC),
+ PINMUX_SINGLE(AVB0_MDC),
+ PINMUX_SINGLE(AVB0_MDIO),
+ PINMUX_SINGLE(AVB0_TXCREFCLK),
+ PINMUX_SINGLE(AVB0_TD3),
+ PINMUX_SINGLE(AVB0_TD2),
+ PINMUX_SINGLE(AVB0_TD1),
+ PINMUX_SINGLE(AVB0_TD0),
+ PINMUX_SINGLE(AVB0_TXC),
+ PINMUX_SINGLE(AVB0_TX_CTL),
+ PINMUX_SINGLE(AVB0_RD3),
+ PINMUX_SINGLE(AVB0_RD2),
+ PINMUX_SINGLE(AVB0_RD1),
+ PINMUX_SINGLE(AVB0_RD0),
+ PINMUX_SINGLE(AVB0_RXC),
+ PINMUX_SINGLE(AVB0_RX_CTL),
+ PINMUX_SINGLE(RPC_INT_N),
+ PINMUX_SINGLE(RPC_RESET_N),
+ PINMUX_SINGLE(QSPI1_SSL),
+ PINMUX_SINGLE(QSPI1_IO3),
+ PINMUX_SINGLE(QSPI1_IO2),
+ PINMUX_SINGLE(QSPI1_MISO_IO1),
+ PINMUX_SINGLE(QSPI1_MOSI_IO0),
+ PINMUX_SINGLE(QSPI1_SPCLK),
+ PINMUX_SINGLE(QSPI0_SSL),
+ PINMUX_SINGLE(QSPI0_IO3),
+ PINMUX_SINGLE(QSPI0_IO2),
+ PINMUX_SINGLE(QSPI0_MISO_IO1),
+ PINMUX_SINGLE(QSPI0_MOSI_IO0),
+ PINMUX_SINGLE(QSPI0_SPCLK),
+
+ /* IPSR0 */
+ PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
+ PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
+ PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
+
+ PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
+ PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
+
+ PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
+ PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
+
+ PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
+ PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
+
+ PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
+ PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
+ PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
+
+ PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
+ PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
+ PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
+
+ PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
+ PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
+ PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
+ PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
+
+ PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
+ PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
+ PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
+
+ /* IPSR1 */
+ PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
+ PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
+ PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
+ PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
+ PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
+
+ PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
+ PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
+ PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
+ PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
+ PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
+ PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
+ PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
+
+ PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
+ PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
+ PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
+ PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
+ PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
+ PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
+ PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
+
+ /* IPSR2 */
+ PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
+ PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
+ PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
+ PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
+
+ PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
+ PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
+ PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
+
+ PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
+ PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
+ PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
+ PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
+ PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
+ PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
+ PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
+ PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
+ PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
+
+ PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
+ PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
+ PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
+
+ /* IPSR3 */
+ PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
+ PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
+ PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
+
+ PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
+ PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
+ PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
+
+ PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
+ PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
+ PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
+
+ PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
+ PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
+ PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
+
+ PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
+ PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
+ PINMUX_IPSR_GPSR(IP3_19_16, NMI),
+
+ PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
+ PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
+ PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
+
+ PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
+ PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
+ PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
+
+ PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
+ PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
+
+ /* IPSR4 */
+ PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
+ PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
+ PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
+
+ PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
+ PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
+ PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
+
+ PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
+ PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
+ PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
+
+ PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
+ PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
+ PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
+ PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
+
+ PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
+ PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
+ PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
+ PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
+ PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
+
+ PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
+ PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
+
+ /* IPSR5 */
+ PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
+ PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
+
+ PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
+ PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
+
+ PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
+ PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
+
+ PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
+ PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
+ PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
+
+ PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
+ PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
+
+ PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
+
+ PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
+ PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
+
+ /* IPSR6 */
+ PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
+ PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
+ PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
+
+ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
+ PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
+
+ PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
+ PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
+
+ PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
+ PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
+ PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
+
+ PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
+ PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
+
+ PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
+ PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
+
+ PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
+ PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
+
+ /* IPSR7 */
+ PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
+ PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
+ PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
+ PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
+
+ PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
+ PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
+ PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
+ PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
+ PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
+ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
+ PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
+ PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
+
+ PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
+
+ PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
+ PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
+
+ PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
+ PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
+
+ /* IPSR8 */
+ PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
+ PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
+ PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
+ PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
+ PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
+
+ PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
+ PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
+ PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
+
+ PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
+ PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
+ PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
+
+ PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
+ PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
+ PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
+
+ PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
+ PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
+
+ PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
+ PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
+ PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
+
+ PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
+ PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
+
+ PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
+ PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
+
+ /* IPSR9 */
+ PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
+ PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
+
+ PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
+ PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
+
+ PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
+ PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
+
+ PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
+ PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
+
+ PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
+ PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
+
+ PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
+ PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
+
+ PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
+ PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
+
+ PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
+ PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
+
+ /* IPSR10 */
+ PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
+ PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
+
+ PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
+ PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
+ PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
+ PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
+
+ PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
+ PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
+ PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
+
+ PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
+ PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
+
+ PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
+ PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
+ PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
+ PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
+
+ PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
+ PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
+
+ /* IPSR11 */
+ PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
+ PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
+
+ PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
+ PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
+ PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
+ PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
+
+ PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
+ PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
+ PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
+ PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
+ PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
+
+ PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
+ PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
+
+ /* IPSR12 */
+ PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
+ PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
+
+ PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
+ PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
+ PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
+
+ PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
+ PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
+
+ PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
+ PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
+
+ PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
+ PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
+
+ PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
+ PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
+ PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
+
+ PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
+ PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
+
+ PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
+ PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
+ PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
+
+ /* IPSR13 */
+ PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
+
+ PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
+ PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+static const unsigned int i2c0_mux[] = {
+ SCL0_MARK, SDA0_MARK,
+};
+static const unsigned int i2c1_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int i2c1_mux[] = {
+ SCL1_MARK, SDA1_MARK,
+};
+static const unsigned int i2c2_a_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+};
+static const unsigned int i2c2_a_mux[] = {
+ SCL2_A_MARK, SDA2_A_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
+};
+static const unsigned int i2c2_b_mux[] = {
+ SCL2_B_MARK, SDA2_B_MARK,
+};
+static const unsigned int i2c3_a_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int i2c3_a_mux[] = {
+ SCL3_A_MARK, SDA3_A_MARK,
+};
+static const unsigned int i2c3_b_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int i2c3_b_mux[] = {
+ SCL3_B_MARK, SDA3_B_MARK,
+};
+
+/* - MMC ------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 2),
+};
+static const unsigned int mmc_data1_mux[] = {
+ MMC_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int mmc_data4_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int mmc_data8_mux[] = {
+ MMC_D0_MARK, MMC_D1_MARK,
+ MMC_D2_MARK, MMC_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_CLK_MARK, MMC_CMD_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scif0_data_a_mux[] = {
+ RX0_A_MARK, TX0_A_MARK,
+};
+static const unsigned int scif0_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 19),
+};
+static const unsigned int scif0_clk_a_mux[] = {
+ SCK0_A_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif0_clk_b_mux[] = {
+ SCK0_B_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scif1_data_a_mux[] = {
+ RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 22),
+};
+static const unsigned int scif1_clk_a_mux[] = {
+ SCK1_A_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 25),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCK1_B_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(4, 25),
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
+};
+static const unsigned int scif3_data_a_mux[] = {
+ RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 30),
+};
+static const unsigned int scif3_clk_a_mux[] = {
+ SCK3_A_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 29),
+};
+static const unsigned int scif3_clk_b_mux[] = {
+ SCK3_B_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scif4_data_a_mux[] = {
+ RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 6),
+};
+static const unsigned int scif4_clk_a_mux[] = {
+ SCK4_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scif4_clk_b_mux[] = {
+ SCK4_B_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif5_data_a_mux[] = {
+ RX5_A_MARK, TX5_A_MARK,
+};
+static const unsigned int scif5_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int scif5_clk_a_mux[] = {
+ SCK5_A_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif5_clk_b_mux[] = {
+ SCK5_B_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(2, 27),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2_a),
+ SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3_a),
+ SH_PFC_PIN_GROUP(i2c3_b),
+ SH_PFC_PIN_GROUP(mmc_data1),
+ SH_PFC_PIN_GROUP(mmc_data4),
+ SH_PFC_PIN_GROUP(mmc_data8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_a),
+ SH_PFC_PIN_GROUP(scif0_clk_a),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_clk_b),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_a),
+ SH_PFC_PIN_GROUP(scif1_clk_a),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif3_data_a),
+ SH_PFC_PIN_GROUP(scif3_clk_a),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data_a),
+ SH_PFC_PIN_GROUP(scif4_clk_a),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif5_data_a),
+ SH_PFC_PIN_GROUP(scif5_clk_a),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif_clk),
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_a",
+ "i2c2_b",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_a",
+ "i2c3_b",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data_a",
+ "scif0_clk_a",
+ "scif0_data_b",
+ "scif0_clk_b",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data_a",
+ "scif1_clk_a",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_ctrl",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data_a",
+ "scif3_clk_a",
+ "scif3_data_b",
+ "scif3_clk_b",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data_a",
+ "scif4_clk_a",
+ "scif4_data_b",
+ "scif4_clk_b",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data_a",
+ "scif5_clk_a",
+ "scif5_data_b",
+ "scif5_clk_b",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(mmc),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(scif_clk),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y) FN_##y
+#define FM(x) FN_##x
+ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_0_8_FN, GPSR0_8,
+ GP_0_7_FN, GPSR0_7,
+ GP_0_6_FN, GPSR0_6,
+ GP_0_5_FN, GPSR0_5,
+ GP_0_4_FN, GPSR0_4,
+ GP_0_3_FN, GPSR0_3,
+ GP_0_2_FN, GPSR0_2,
+ GP_0_1_FN, GPSR0_1,
+ GP_0_0_FN, GPSR0_0, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+ GP_1_31_FN, GPSR1_31,
+ GP_1_30_FN, GPSR1_30,
+ GP_1_29_FN, GPSR1_29,
+ GP_1_28_FN, GPSR1_28,
+ GP_1_27_FN, GPSR1_27,
+ GP_1_26_FN, GPSR1_26,
+ GP_1_25_FN, GPSR1_25,
+ GP_1_24_FN, GPSR1_24,
+ GP_1_23_FN, GPSR1_23,
+ GP_1_22_FN, GPSR1_22,
+ GP_1_21_FN, GPSR1_21,
+ GP_1_20_FN, GPSR1_20,
+ GP_1_19_FN, GPSR1_19,
+ GP_1_18_FN, GPSR1_18,
+ GP_1_17_FN, GPSR1_17,
+ GP_1_16_FN, GPSR1_16,
+ GP_1_15_FN, GPSR1_15,
+ GP_1_14_FN, GPSR1_14,
+ GP_1_13_FN, GPSR1_13,
+ GP_1_12_FN, GPSR1_12,
+ GP_1_11_FN, GPSR1_11,
+ GP_1_10_FN, GPSR1_10,
+ GP_1_9_FN, GPSR1_9,
+ GP_1_8_FN, GPSR1_8,
+ GP_1_7_FN, GPSR1_7,
+ GP_1_6_FN, GPSR1_6,
+ GP_1_5_FN, GPSR1_5,
+ GP_1_4_FN, GPSR1_4,
+ GP_1_3_FN, GPSR1_3,
+ GP_1_2_FN, GPSR1_2,
+ GP_1_1_FN, GPSR1_1,
+ GP_1_0_FN, GPSR1_0, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+ GP_2_31_FN, GPSR2_31,
+ GP_2_30_FN, GPSR2_30,
+ GP_2_29_FN, GPSR2_29,
+ GP_2_28_FN, GPSR2_28,
+ GP_2_27_FN, GPSR2_27,
+ GP_2_26_FN, GPSR2_26,
+ GP_2_25_FN, GPSR2_25,
+ GP_2_24_FN, GPSR2_24,
+ GP_2_23_FN, GPSR2_23,
+ GP_2_22_FN, GPSR2_22,
+ GP_2_21_FN, GPSR2_21,
+ GP_2_20_FN, GPSR2_20,
+ GP_2_19_FN, GPSR2_19,
+ GP_2_18_FN, GPSR2_18,
+ GP_2_17_FN, GPSR2_17,
+ GP_2_16_FN, GPSR2_16,
+ GP_2_15_FN, GPSR2_15,
+ GP_2_14_FN, GPSR2_14,
+ GP_2_13_FN, GPSR2_13,
+ GP_2_12_FN, GPSR2_12,
+ GP_2_11_FN, GPSR2_11,
+ GP_2_10_FN, GPSR2_10,
+ GP_2_9_FN, GPSR2_9,
+ GP_2_8_FN, GPSR2_8,
+ GP_2_7_FN, GPSR2_7,
+ GP_2_6_FN, GPSR2_6,
+ GP_2_5_FN, GPSR2_5,
+ GP_2_4_FN, GPSR2_4,
+ GP_2_3_FN, GPSR2_3,
+ GP_2_2_FN, GPSR2_2,
+ GP_2_1_FN, GPSR2_1,
+ GP_2_0_FN, GPSR2_0, }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_3_9_FN, GPSR3_9,
+ GP_3_8_FN, GPSR3_8,
+ GP_3_7_FN, GPSR3_7,
+ GP_3_6_FN, GPSR3_6,
+ GP_3_5_FN, GPSR3_5,
+ GP_3_4_FN, GPSR3_4,
+ GP_3_3_FN, GPSR3_3,
+ GP_3_2_FN, GPSR3_2,
+ GP_3_1_FN, GPSR3_1,
+ GP_3_0_FN, GPSR3_0, }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+ GP_4_31_FN, GPSR4_31,
+ GP_4_30_FN, GPSR4_30,
+ GP_4_29_FN, GPSR4_29,
+ GP_4_28_FN, GPSR4_28,
+ GP_4_27_FN, GPSR4_27,
+ GP_4_26_FN, GPSR4_26,
+ GP_4_25_FN, GPSR4_25,
+ GP_4_24_FN, GPSR4_24,
+ GP_4_23_FN, GPSR4_23,
+ GP_4_22_FN, GPSR4_22,
+ GP_4_21_FN, GPSR4_21,
+ GP_4_20_FN, GPSR4_20,
+ GP_4_19_FN, GPSR4_19,
+ GP_4_18_FN, GPSR4_18,
+ GP_4_17_FN, GPSR4_17,
+ GP_4_16_FN, GPSR4_16,
+ GP_4_15_FN, GPSR4_15,
+ GP_4_14_FN, GPSR4_14,
+ GP_4_13_FN, GPSR4_13,
+ GP_4_12_FN, GPSR4_12,
+ GP_4_11_FN, GPSR4_11,
+ GP_4_10_FN, GPSR4_10,
+ GP_4_9_FN, GPSR4_9,
+ GP_4_8_FN, GPSR4_8,
+ GP_4_7_FN, GPSR4_7,
+ GP_4_6_FN, GPSR4_6,
+ GP_4_5_FN, GPSR4_5,
+ GP_4_4_FN, GPSR4_4,
+ GP_4_3_FN, GPSR4_3,
+ GP_4_2_FN, GPSR4_2,
+ GP_4_1_FN, GPSR4_1,
+ GP_4_0_FN, GPSR4_0, }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_20_FN, GPSR5_20,
+ GP_5_19_FN, GPSR5_19,
+ GP_5_18_FN, GPSR5_18,
+ GP_5_17_FN, GPSR5_17,
+ GP_5_16_FN, GPSR5_16,
+ GP_5_15_FN, GPSR5_15,
+ GP_5_14_FN, GPSR5_14,
+ GP_5_13_FN, GPSR5_13,
+ GP_5_12_FN, GPSR5_12,
+ GP_5_11_FN, GPSR5_11,
+ GP_5_10_FN, GPSR5_10,
+ GP_5_9_FN, GPSR5_9,
+ GP_5_8_FN, GPSR5_8,
+ GP_5_7_FN, GPSR5_7,
+ GP_5_6_FN, GPSR5_6,
+ GP_5_5_FN, GPSR5_5,
+ GP_5_4_FN, GPSR5_4,
+ GP_5_3_FN, GPSR5_3,
+ GP_5_2_FN, GPSR5_2,
+ GP_5_1_FN, GPSR5_1,
+ GP_5_0_FN, GPSR5_0, }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_13_FN, GPSR6_13,
+ GP_6_12_FN, GPSR6_12,
+ GP_6_11_FN, GPSR6_11,
+ GP_6_10_FN, GPSR6_10,
+ GP_6_9_FN, GPSR6_9,
+ GP_6_8_FN, GPSR6_8,
+ GP_6_7_FN, GPSR6_7,
+ GP_6_6_FN, GPSR6_6,
+ GP_6_5_FN, GPSR6_5,
+ GP_6_4_FN, GPSR6_4,
+ GP_6_3_FN, GPSR6_3,
+ GP_6_2_FN, GPSR6_2,
+ GP_6_1_FN, GPSR6_1,
+ GP_6_0_FN, GPSR6_0, }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+ IP0_31_28
+ IP0_27_24
+ IP0_23_20
+ IP0_19_16
+ IP0_15_12
+ IP0_11_8
+ IP0_7_4
+ IP0_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+ IP1_31_28
+ IP1_27_24
+ IP1_23_20
+ IP1_19_16
+ IP1_15_12
+ IP1_11_8
+ IP1_7_4
+ IP1_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+ IP2_31_28
+ IP2_27_24
+ IP2_23_20
+ IP2_19_16
+ IP2_15_12
+ IP2_11_8
+ IP2_7_4
+ IP2_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+ IP3_31_28
+ IP3_27_24
+ IP3_23_20
+ IP3_19_16
+ IP3_15_12
+ IP3_11_8
+ IP3_7_4
+ IP3_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+ IP4_31_28
+ IP4_27_24
+ IP4_23_20
+ IP4_19_16
+ IP4_15_12
+ IP4_11_8
+ IP4_7_4
+ IP4_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+ IP5_31_28
+ IP5_27_24
+ IP5_23_20
+ IP5_19_16
+ IP5_15_12
+ IP5_11_8
+ IP5_7_4
+ IP5_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+ IP6_31_28
+ IP6_27_24
+ IP6_23_20
+ IP6_19_16
+ IP6_15_12
+ IP6_11_8
+ IP6_7_4
+ IP6_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+ IP7_31_28
+ IP7_27_24
+ IP7_23_20
+ IP7_19_16
+ IP7_15_12
+ IP7_11_8
+ IP7_7_4
+ IP7_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+ IP8_31_28
+ IP8_27_24
+ IP8_23_20
+ IP8_19_16
+ IP8_15_12
+ IP8_11_8
+ IP8_7_4
+ IP8_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+ IP9_31_28
+ IP9_27_24
+ IP9_23_20
+ IP9_19_16
+ IP9_15_12
+ IP9_11_8
+ IP9_7_4
+ IP9_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+ IP10_31_28
+ IP10_27_24
+ IP10_23_20
+ IP10_19_16
+ IP10_15_12
+ IP10_11_8
+ IP10_7_4
+ IP10_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+ IP11_31_28
+ IP11_27_24
+ IP11_23_20
+ IP11_19_16
+ IP11_15_12
+ IP11_11_8
+ IP11_7_4
+ IP11_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+ IP12_31_28
+ IP12_27_24
+ IP12_23_20
+ IP12_19_16
+ IP12_15_12
+ IP12_11_8
+ IP12_7_4
+ IP12_3_0 }
+ },
+ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+ /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ IP13_7_4
+ IP13_3_0 }
+ },
+#undef F_
+#undef FM
+
+#define F_(x, y) x,
+#define FM(x) FN_##x,
+ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+ 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
+ 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
+ /* RESERVED 31 */
+ 0, 0,
+ MOD_SEL0_30
+ MOD_SEL0_29
+ MOD_SEL0_28
+ MOD_SEL0_27
+ MOD_SEL0_26
+ MOD_SEL0_25
+ MOD_SEL0_24_23
+ MOD_SEL0_22_21
+ MOD_SEL0_20_19
+ MOD_SEL0_18_17
+ /* RESERVED 16 */
+ 0, 0,
+ MOD_SEL0_15
+ MOD_SEL0_14
+ MOD_SEL0_13
+ MOD_SEL0_12
+ MOD_SEL0_11
+ MOD_SEL0_10
+ /* RESERVED 9, 8, 7, 6 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ MOD_SEL0_5
+ MOD_SEL0_4
+ MOD_SEL0_3
+ MOD_SEL0_2
+ MOD_SEL0_1
+ MOD_SEL0_0 }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
+ 1, 1, 1, 1, 1, 1, 2, 4, 4,
+ 4, 4, 4, 4) {
+ MOD_SEL1_31
+ MOD_SEL1_30
+ MOD_SEL1_29
+ MOD_SEL1_28
+ MOD_SEL1_27
+ MOD_SEL1_26
+ /* RESERVED 25, 24 */
+ 0, 0, 0, 0,
+ /* RESERVED 23, 22, 21, 20 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 19, 18, 17, 16 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 15, 14, 13, 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 11, 10, 9, 8 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 7, 6, 5, 4 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 3, 2, 1, 0 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ { },
+};
+
+static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = 0xe6060380;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
+ bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
+ .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
+};
+
+const struct sh_pfc_soc_info r8a77995_pinmux_info = {
+ .name = "r8a77995_pfc",
+ .ops = &r8a77995_pinmux_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
enum sh_pfc_model {
SH_PFC_R8A7795 = 0,
SH_PFC_R8A7796,
+ SH_PFC_R8A77970,
+ SH_PFC_R8A77995,
};
struct sh_pfc_pin_config {
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77970
+ if (model == SH_PFC_R8A77970)
+ priv->pfc.info = &r8a77970_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77995
+ if (model == SH_PFC_R8A77995)
+ priv->pfc.info = &r8a77995_pinmux_info;
+#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
.compatible = "renesas,pfc-r8a7796",
.data = SH_PFC_R8A7796,
},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77970
+ {
+ .compatible = "renesas,pfc-r8a77970",
+ .data = SH_PFC_R8A77970,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77995
+ {
+ .compatible = "renesas,pfc-r8a77995",
+ .data = SH_PFC_R8A77995,
+ },
#endif
{ },
};
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
+#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_4(bank, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
+#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
+
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
+#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_18(bank, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
+#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
+
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
The MC34VR500 is used in conjunction with the FSL T1 and LS1 series
SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed
via an I2C interface.
+
+config DM_PMIC_TPS65910
+ bool "Enable driver for Texas Instruments TPS65910 PMIC"
+ depends on DM_PMIC
+ ---help---
+ The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
+ DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
+ pmic children.
obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
+obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
struct driver *drv;
struct udevice *child;
const char *node_name;
+ const char *reg_name;
int bind_count = 0;
ofnode node;
int prefix_len;
debug(" - compatible prefix: '%s'\n", info->prefix);
prefix_len = strlen(info->prefix);
- if (strncmp(info->prefix, node_name, prefix_len))
- continue;
+ if (strncmp(info->prefix, node_name, prefix_len)) {
+ reg_name = ofnode_read_string(node,
+ "regulator-name");
+ if (!reg_name)
+ continue;
+ if (strncmp(info->prefix, reg_name, prefix_len))
+ continue;
+ }
drv = lists_driver_lookup_name(info->driver);
if (!drv) {
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65910_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER },
+ { .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER },
+ { .prefix = "boost_", .driver = TPS65910_BOOST_DRIVER },
+ { },
+};
+
+static int pmic_tps65910_reg_count(struct udevice *dev)
+{
+ return TPS65910_NUM_REGS;
+}
+
+static int pmic_tps65910_write(struct udevice *dev, uint reg, const u8 *buffer,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buffer, len);
+ if (ret)
+ error("%s write error on register %02x\n", dev->name, reg);
+
+ return ret;
+}
+
+static int pmic_tps65910_read(struct udevice *dev, uint reg, u8 *buffer,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buffer, len);
+ if (ret)
+ error("%s read error on register %02x\n", dev->name, reg);
+
+ return ret;
+}
+
+static int pmic_tps65910_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s regulators subnode not found\n", dev->name);
+ return -EINVAL;
+ }
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s has no children (regulators)\n", dev->name);
+
+ return 0;
+}
+
+static int pmic_tps65910_probe(struct udevice *dev)
+{
+ /* use I2C control interface instead of I2C smartreflex interface to
+ * access smartrefelex registers VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG
+ * and VDD2_SR_REG
+ */
+ return pmic_clrsetbits(dev, TPS65910_REG_DEVICE_CTRL, 0,
+ TPS65910_I2C_SEL_MASK);
+}
+
+static struct dm_pmic_ops pmic_tps65910_ops = {
+ .reg_count = pmic_tps65910_reg_count,
+ .read = pmic_tps65910_read,
+ .write = pmic_tps65910_write,
+};
+
+static const struct udevice_id pmic_tps65910_match[] = {
+ { .compatible = "ti,tps65910" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pmic_tps65910) = {
+ .name = "pmic_tps65910",
+ .id = UCLASS_PMIC,
+ .of_match = pmic_tps65910_match,
+ .bind = pmic_tps65910_bind,
+ .probe = pmic_tps65910_probe,
+ .ops = &pmic_tps65910_ops,
+};
LP87565 series of PMICs have 4 single phase BUCKs that can also
be configured in multi phase modes. The driver implements
get/set api for value and enable.
+
+config DM_REGULATOR_TPS65910
+ bool "Enable driver for TPS65910 PMIC regulators"
+ depends on DM_PMIC_TPS65910
+ ---help---
+ The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all
+ regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
+ the get/set api for value and enable.
obj-$(CONFIG_$(SPL_)DM_REGULATOR_PBIAS) += pbias_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
+obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65910_pmic.h>
+
+#define VOUT_CHOICE_COUNT 4
+
+/*
+ * struct regulator_props - Properties of a LDO and VIO SMPS regulator
+ *
+ * All of these regulators allow setting one out of four output voltages.
+ * These output voltages are only achievable when supplying the regulator
+ * with a minimum input voltage.
+ *
+ * @vin_min[]: minimum supply input voltage in uV required to achieve the
+ * corresponding vout[] voltage
+ * @vout[]: regulator output voltage in uV
+ * @reg: I2C register used to set regulator voltage
+ */
+struct regulator_props {
+ int vin_min[VOUT_CHOICE_COUNT];
+ int vout[VOUT_CHOICE_COUNT];
+ int reg;
+};
+
+static const struct regulator_props ldo_props_vdig1 = {
+ .vin_min = { 1700000, 2100000, 2700000, 3200000 },
+ .vout = { 1200000, 1500000, 1800000, 2700000 },
+ .reg = TPS65910_REG_VDIG1
+};
+
+static const struct regulator_props ldo_props_vdig2 = {
+ .vin_min = { 1700000, 1700000, 1700000, 2700000 },
+ .vout = { 1000000, 1100000, 1200000, 1800000 },
+ .reg = TPS65910_REG_VDIG2
+};
+
+static const struct regulator_props ldo_props_vpll = {
+ .vin_min = { 2700000, 2700000, 2700000, 3000000 },
+ .vout = { 1000000, 1100000, 1800000, 2500000 },
+ .reg = TPS65910_REG_VPLL
+};
+
+static const struct regulator_props ldo_props_vdac = {
+ .vin_min = { 2700000, 3000000, 3200000, 3200000 },
+ .vout = { 1800000, 2600000, 2800000, 2850000 },
+ .reg = TPS65910_REG_VDAC
+};
+
+static const struct regulator_props ldo_props_vaux1 = {
+ .vin_min = { 2700000, 3200000, 3200000, 3200000 },
+ .vout = { 1800000, 2500000, 2800000, 2850000 },
+ .reg = TPS65910_REG_VAUX1
+};
+
+static const struct regulator_props ldo_props_vaux2 = {
+ .vin_min = { 2700000, 3200000, 3200000, 3600000 },
+ .vout = { 1800000, 2800000, 2900000, 3300000 },
+ .reg = TPS65910_REG_VAUX2
+};
+
+static const struct regulator_props ldo_props_vaux33 = {
+ .vin_min = { 2700000, 2700000, 3200000, 3600000 },
+ .vout = { 1800000, 2000000, 2800000, 3300000 },
+ .reg = TPS65910_REG_VAUX33
+};
+
+static const struct regulator_props ldo_props_vmmc = {
+ .vin_min = { 2700000, 3200000, 3200000, 3600000 },
+ .vout = { 1800000, 2800000, 3000000, 3300000 },
+ .reg = TPS65910_REG_VMMC
+};
+
+static const struct regulator_props smps_props_vio = {
+ .vin_min = { 3200000, 3200000, 4000000, 4400000 },
+ .vout = { 1500000, 1800000, 2500000, 3300000 },
+ .reg = TPS65910_REG_VIO
+};
+
+/* lookup table of control registers indexed by regulator unit number */
+static const int ctrl_regs[] = {
+ TPS65910_REG_VRTC,
+ TPS65910_REG_VIO,
+ TPS65910_REG_VDD1,
+ TPS65910_REG_VDD2,
+ TPS65910_REG_VDD3,
+ TPS65910_REG_VDIG1,
+ TPS65910_REG_VDIG2,
+ TPS65910_REG_VPLL,
+ TPS65910_REG_VDAC,
+ TPS65910_REG_VAUX1,
+ TPS65910_REG_VAUX2,
+ TPS65910_REG_VAUX33,
+ TPS65910_REG_VMMC
+};
+
+/* supply names as used in DT */
+static const char * const supply_names[] = {
+ "vccio-supply",
+ "vcc1-supply",
+ "vcc2-supply",
+ "vcc3-supply",
+ "vcc4-supply",
+ "vcc5-supply",
+ "vcc6-supply",
+ "vcc7-supply"
+};
+
+/* lookup table of regulator supplies indexed by regulator unit number */
+static const int regulator_supplies[] = {
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_SUPPLY_VCCIO,
+ TPS65910_SUPPLY_VCC1,
+ TPS65910_SUPPLY_VCC2,
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC3,
+ TPS65910_SUPPLY_VCC3
+};
+
+static int get_ctrl_reg_from_unit_addr(const uint unit_addr)
+{
+ if (unit_addr < ARRAY_SIZE(ctrl_regs))
+ return ctrl_regs[unit_addr];
+ return -ENXIO;
+}
+
+static int tps65910_regulator_get_value(struct udevice *dev,
+ const struct regulator_props *rgp)
+{
+ int sel, val, vout;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin = pdata->supply;
+
+ val = pmic_reg_read(dev->parent, rgp->reg);
+ if (val < 0)
+ return val;
+ sel = (val & TPS65910_SEL_MASK) >> 2;
+ vout = (vin >= *(rgp->vin_min + sel)) ? *(rgp->vout + sel) : 0;
+ vout = ((val & TPS65910_SUPPLY_STATE_MASK) == 1) ? vout : 0;
+
+ return vout;
+}
+
+static int tps65910_ldo_get_value(struct udevice *dev)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin;
+
+ if (!pdata)
+ return 0;
+ vin = pdata->supply;
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VRTC:
+ /* VRTC is fixed and can't be turned off */
+ return (vin >= 2500000) ? 1830000 : 0;
+ case TPS65910_UNIT_VDIG1:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdig1);
+ case TPS65910_UNIT_VDIG2:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdig2);
+ case TPS65910_UNIT_VPLL:
+ return tps65910_regulator_get_value(dev, &ldo_props_vpll);
+ case TPS65910_UNIT_VDAC:
+ return tps65910_regulator_get_value(dev, &ldo_props_vdac);
+ case TPS65910_UNIT_VAUX1:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux1);
+ case TPS65910_UNIT_VAUX2:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux2);
+ case TPS65910_UNIT_VAUX33:
+ return tps65910_regulator_get_value(dev, &ldo_props_vaux33);
+ case TPS65910_UNIT_VMMC:
+ return tps65910_regulator_get_value(dev, &ldo_props_vmmc);
+ default:
+ return 0;
+ }
+}
+
+static int tps65910_regulator_set_value(struct udevice *dev,
+ const struct regulator_props *ldo,
+ int uV)
+{
+ int val;
+ int sel = 0;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ do {
+ /* we only allow exact voltage matches */
+ if (uV == *(ldo->vout + sel))
+ break;
+ } while (++sel < VOUT_CHOICE_COUNT);
+ if (sel == VOUT_CHOICE_COUNT)
+ return -EINVAL;
+ if (pdata->supply < *(ldo->vin_min + sel))
+ return -EINVAL;
+
+ val = pmic_reg_read(dev->parent, ldo->reg);
+ if (val < 0)
+ return val;
+ val &= ~TPS65910_SEL_MASK;
+ val |= sel << 2;
+ return pmic_reg_write(dev->parent, ldo->reg, val);
+}
+
+static int tps65910_ldo_set_value(struct udevice *dev, int uV)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+ int vin = pdata->supply;
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VRTC:
+ /* VRTC is fixed to 1.83V and can't be turned off */
+ if (vin < 2500000)
+ return -EINVAL;
+ return 0;
+ case TPS65910_UNIT_VDIG1:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdig1, uV);
+ case TPS65910_UNIT_VDIG2:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdig2, uV);
+ case TPS65910_UNIT_VPLL:
+ return tps65910_regulator_set_value(dev, &ldo_props_vpll, uV);
+ case TPS65910_UNIT_VDAC:
+ return tps65910_regulator_set_value(dev, &ldo_props_vdac, uV);
+ case TPS65910_UNIT_VAUX1:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux1, uV);
+ case TPS65910_UNIT_VAUX2:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux2, uV);
+ case TPS65910_UNIT_VAUX33:
+ return tps65910_regulator_set_value(dev, &ldo_props_vaux33, uV);
+ case TPS65910_UNIT_VMMC:
+ return tps65910_regulator_set_value(dev, &ldo_props_vmmc, uV);
+ default:
+ return 0;
+ }
+}
+
+static int tps65910_get_enable(struct udevice *dev)
+{
+ int reg, val;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ reg = get_ctrl_reg_from_unit_addr(pdata->unit);
+ if (reg < 0)
+ return reg;
+
+ val = pmic_reg_read(dev->parent, reg);
+ if (val < 0)
+ return val;
+
+ /* bits 1:0 of regulator control register define state */
+ return ((val & TPS65910_SUPPLY_STATE_MASK) == 1);
+}
+
+static int tps65910_set_enable(struct udevice *dev, bool enable)
+{
+ int reg;
+ uint clr, set;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ reg = get_ctrl_reg_from_unit_addr(pdata->unit);
+ if (reg < 0)
+ return reg;
+
+ if (enable) {
+ clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_ON;
+ set = TPS65910_SUPPLY_STATE_MASK & TPS65910_SUPPLY_STATE_ON;
+ } else {
+ clr = TPS65910_SUPPLY_STATE_MASK & ~TPS65910_SUPPLY_STATE_OFF;
+ set = TPS65910_SUPPLY_STATE_MASK & TPS65910_SUPPLY_STATE_OFF;
+ }
+ return pmic_clrsetbits(dev->parent, reg, clr, set);
+}
+
+static int buck_get_vdd1_vdd2_value(struct udevice *dev, int reg_vdd)
+{
+ int gain;
+ int val = pmic_reg_read(dev, reg_vdd);
+
+ if (val < 0)
+ return val;
+ gain = (val & TPS65910_GAIN_SEL_MASK) >> 6;
+ gain = (gain == 0) ? 1 : gain;
+ val = pmic_reg_read(dev, reg_vdd + 1);
+ if (val < 0)
+ return val;
+ if (val & TPS65910_VDD_SR_MASK)
+ /* use smart reflex value instead */
+ val = pmic_reg_read(dev, reg_vdd + 2);
+ if (val < 0)
+ return val;
+ return (562500 + (val & TPS65910_VDD_SEL_MASK) * 12500) * gain;
+}
+
+static int tps65910_buck_get_value(struct udevice *dev)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VIO:
+ return tps65910_regulator_get_value(dev, &smps_props_vio);
+ case TPS65910_UNIT_VDD1:
+ return buck_get_vdd1_vdd2_value(dev->parent, TPS65910_REG_VDD1);
+ case TPS65910_UNIT_VDD2:
+ return buck_get_vdd1_vdd2_value(dev->parent, TPS65910_REG_VDD2);
+ default:
+ return 0;
+ }
+}
+
+static int buck_set_vdd1_vdd2_value(struct udevice *dev, int uV)
+{
+ int ret, reg_vdd, gain;
+ int val;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ switch (pdata->unit) {
+ case TPS65910_UNIT_VDD1:
+ reg_vdd = TPS65910_REG_VDD1;
+ break;
+ case TPS65910_UNIT_VDD2:
+ reg_vdd = TPS65910_REG_VDD2;
+ break;
+ default:
+ return -EINVAL;
+ }
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ /* check setpoint is within limits */
+ if (uV < uc_pdata->min_uV) {
+ error("voltage %duV for %s too low\n", uV, dev->name);
+ return -EINVAL;
+ }
+ if (uV > uc_pdata->max_uV) {
+ error("voltage %duV for %s too high\n", uV, dev->name);
+ return -EINVAL;
+ }
+
+ val = pmic_reg_read(dev->parent, reg_vdd);
+ if (val < 0)
+ return val;
+ gain = (val & TPS65910_GAIN_SEL_MASK) >> 6;
+ gain = (gain == 0) ? 1 : gain;
+ val = ((uV / gain) - 562500) / 12500;
+ if (val < TPS65910_VDD_SEL_MIN || val > TPS65910_VDD_SEL_MAX)
+ /*
+ * Neither do we change the gain, nor do we allow shutdown or
+ * any approximate value (for now)
+ */
+ return -EPERM;
+ val &= TPS65910_VDD_SEL_MASK;
+ ret = pmic_reg_write(dev->parent, reg_vdd + 1, val);
+ if (ret)
+ return ret;
+ return 0;
+}
+
+static int tps65910_buck_set_value(struct udevice *dev, int uV)
+{
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ if (pdata->unit == TPS65910_UNIT_VIO)
+ return tps65910_regulator_set_value(dev, &smps_props_vio, uV);
+
+ return buck_set_vdd1_vdd2_value(dev, uV);
+}
+
+static int tps65910_boost_get_value(struct udevice *dev)
+{
+ int vout;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ vout = (pdata->supply >= 3000000) ? 5000000 : 0;
+ return vout;
+}
+
+static int tps65910_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct udevice *supply;
+ int ret;
+ const char *supply_name;
+ struct tps65910_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->unit = dev_get_driver_data(dev);
+ if (pdata->unit > TPS65910_UNIT_VMMC)
+ return -EINVAL;
+ supply_name = supply_names[regulator_supplies[pdata->unit]];
+
+ debug("Looking up supply power %s\n", supply_name);
+ ret = device_get_supply_regulator(dev->parent, supply_name, &supply);
+ if (ret) {
+ debug(" missing supply power %s\n", supply_name);
+ return ret;
+ }
+ pdata->supply = regulator_get_value(supply);
+ if (pdata->supply < 0) {
+ debug(" invalid supply voltage for regulator %s\n",
+ supply->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops tps65910_boost_ops = {
+ .get_value = tps65910_boost_get_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_boost) = {
+ .name = TPS65910_BOOST_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_boost_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
+
+static const struct dm_regulator_ops tps65910_buck_ops = {
+ .get_value = tps65910_buck_get_value,
+ .set_value = tps65910_buck_set_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_buck) = {
+ .name = TPS65910_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_buck_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
+
+static const struct dm_regulator_ops tps65910_ldo_ops = {
+ .get_value = tps65910_ldo_get_value,
+ .set_value = tps65910_ldo_set_value,
+ .get_enable = tps65910_get_enable,
+ .set_enable = tps65910_set_enable,
+};
+
+U_BOOT_DRIVER(tps65910_ldo) = {
+ .name = TPS65910_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65910_ldo_ops,
+ .platdata_auto_alloc_size = sizeof(struct tps65910_regulator_pdata),
+ .ofdata_to_platdata = tps65910_regulator_ofdata_to_platdata,
+};
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- sysreset_walk_halt(SYSRESET_WARM);
+ sysreset_walk_halt(SYSRESET_COLD);
return 0;
}
#include <console.h>
#include <usb.h>
#include <asm/io.h>
+#include <linux/iopoll.h>
#include "r8a66597.h"
int timeout = 3000;
#if defined(CONFIG_RZA_USB)
u16 dcpctr;
- int timeout2 = 10000;
#endif
u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
#if defined(CONFIG_RZA_USB)
dcpctr = r8a66597_read(r8a66597, DCPCTR);
if ((dcpctr & PID) == PID_BUF) {
- timeout2 = 10000;
- while (!(dcpctr & BSTS)) {
- dcpctr = r8a66597_read(r8a66597, DCPCTR);
- if (timeout2-- < 0) {
- printf("DCPCTR clear timeout!\n");
- break;
- }
+ if (readw_poll_timeout(r8a66597->reg + DCPCTR, dcpctr,
+ dcpctr & BSTS, 1000) < 0) {
+ printf("DCPCTR BSTS timeout!\n");
+ return -ETIMEDOUT;
}
}
#endif
--- /dev/null
+/*
+ * Symbol access for symbols set up by binman as part of the build.
+ *
+ * This allows C code to access the position of a particular part of the image
+ * assembled by binman.
+ *
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BINMAN_SYM_H
+#define __BINMAN_SYM_H
+
+#define BINMAN_SYM_MISSING (-1UL)
+
+#ifdef CONFIG_BINMAN
+
+/**
+ * binman_symname() - Internal fnuction to get a binman symbol name
+ *
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns name of the symbol for that entry and property
+ */
+#define binman_symname(_entry_name, _prop_name) \
+ _binman_ ## _entry_name ## _prop_ ## _prop_name
+
+/**
+ * binman_sym_declare() - Declare a symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare(_type, _entry_name, _prop_name) \
+ _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_extern() - Declare a extern symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_extern(_type, _entry_name, _prop_name) \
+ extern _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_declare_optional() - Declare an optional symbol
+ *
+ * If this symbol cannot be provided by binman, an error will not be generated.
+ * Instead the image will be assigned the value BINMAN_SYM_MISSING.
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name) \
+ _type binman_symname(_entry_name, _prop_name) \
+ __attribute__((aligned(4), weak, unused, \
+ section(".binman_sym")))
+
+/**
+ * binman_sym() - Access a previously declared symbol
+ *
+ * This is used to get the value of a symbol. E.g.:
+ *
+ * ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns value of that property (filled in by binman)
+ */
+#define binman_sym(_type, _entry_name, _prop_name) \
+ (*(_type *)&binman_symname(_entry_name, _prop_name))
+
+#else /* !BINMAN */
+
+#define binman_sym_declare(_type, _entry_name, _prop_name)
+
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name)
+
+#define binman_sym_extern(_type, _entry_name, _prop_name)
+
+#define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING
+
+#endif /* BINMAN */
+
+#endif
--- /dev/null
+/*
+ * include/configs/draak.h
+ * This file is Draak board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DRAAK_H
+#define __DRAAK_H
+
+#undef DEBUG
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CONFIG_CMD_CACHE
+
+#endif /* __DRAAK_H */
--- /dev/null
+/*
+ * include/configs/eagle.h
+ * This file is Eagle board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EAGLE_H
+#define __EAGLE_H
+
+#undef DEBUG
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ 33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+#endif /* __EAGLE_H */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* MEMORY */
+#if defined(CONFIG_R8A77970)
+#define CONFIG_SYS_TEXT_BASE 0x58280000
+#else
#define CONFIG_SYS_TEXT_BASE 0x50000000
+#endif
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_DENALI_ECC_SIZE 512
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2 0
+#define R8A77970_CLK_ZR 1
+#define R8A77970_CLK_ZTR 2
+#define R8A77970_CLK_ZTRD2 3
+#define R8A77970_CLK_ZT 4
+#define R8A77970_CLK_ZX 5
+#define R8A77970_CLK_S1D1 6
+#define R8A77970_CLK_S1D2 7
+#define R8A77970_CLK_S1D4 8
+#define R8A77970_CLK_S2D1 9
+#define R8A77970_CLK_S2D2 10
+#define R8A77970_CLK_S2D4 11
+#define R8A77970_CLK_LB 12
+#define R8A77970_CLK_CL 13
+#define R8A77970_CLK_ZB3 14
+#define R8A77970_CLK_ZB3D2 15
+#define R8A77970_CLK_DDR 16
+#define R8A77970_CLK_CR 17
+#define R8A77970_CLK_CRD2 18
+#define R8A77970_CLK_SD0H 19
+#define R8A77970_CLK_SD0 20
+#define R8A77970_CLK_RPC 21
+#define R8A77970_CLK_RPCD2 22
+#define R8A77970_CLK_MSO 23
+#define R8A77970_CLK_CANFD 24
+#define R8A77970_CLK_CSI0 25
+#define R8A77970_CLK_FRAY 26
+#define R8A77970_CLK_CP 27
+#define R8A77970_CLK_CPEX 28
+#define R8A77970_CLK_R 29
+#define R8A77970_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2 0
+#define R8A77995_CLK_ZG 1
+#define R8A77995_CLK_ZTR 2
+#define R8A77995_CLK_ZT 3
+#define R8A77995_CLK_ZX 4
+#define R8A77995_CLK_S0D1 5
+#define R8A77995_CLK_S1D1 6
+#define R8A77995_CLK_S1D2 7
+#define R8A77995_CLK_S1D4 8
+#define R8A77995_CLK_S2D1 9
+#define R8A77995_CLK_S2D2 10
+#define R8A77995_CLK_S2D4 11
+#define R8A77995_CLK_S3D1 12
+#define R8A77995_CLK_S3D2 13
+#define R8A77995_CLK_S3D4 14
+#define R8A77995_CLK_S1D4C 15
+#define R8A77995_CLK_S3D1C 16
+#define R8A77995_CLK_S3D2C 17
+#define R8A77995_CLK_S3D4C 18
+#define R8A77995_CLK_LB 19
+#define R8A77995_CLK_CL 20
+#define R8A77995_CLK_ZB3 21
+#define R8A77995_CLK_ZB3D2 22
+#define R8A77995_CLK_CR 23
+#define R8A77995_CLK_CRD2 24
+#define R8A77995_CLK_SD0H 25
+#define R8A77995_CLK_SD0 26
+#define R8A77995_CLK_SSP2 27
+#define R8A77995_CLK_SSP1 28
+#define R8A77995_CLK_RPC 29
+#define R8A77995_CLK_RPCD2 30
+#define R8A77995_CLK_ZA2 31
+#define R8A77995_CLK_ZA8 32
+#define R8A77995_CLK_Z2D 33
+#define R8A77995_CLK_CANFD 34
+#define R8A77995_CLK_MSO 35
+#define R8A77995_CLK_R 36
+#define R8A77995_CLK_OSC 37
+#define R8A77995_CLK_LV0 38
+#define R8A77995_CLK_LV1 39
+#define R8A77995_CLK_CP 40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77970_PD_CA53_CPU0 5
+#define R8A77970_PD_CA53_CPU1 6
+#define R8A77970_PD_CR7 13
+#define R8A77970_PD_CA53_SCU 21
+#define R8A77970_PD_A2IR0 23
+#define R8A77970_PD_A3IR 24
+#define R8A77970_PD_A2IR1 27
+#define R8A77970_PD_A2IR2 28
+#define R8A77970_PD_A2IR3 29
+#define R8A77970_PD_A2SC0 30
+#define R8A77970_PD_A2SC1 31
+
+/* Always-on power area */
+#define R8A77970_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77995_PD_CA53_CPU0 5
+#define R8A77995_PD_CA53_SCU 21
+
+/* Always-on power area */
+#define R8A77995_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
void efi_add_handle(struct efi_object *obj);
/* Create handle */
efi_status_t efi_create_handle(void **handle);
+/* Delete handle */
+void efi_delete_handle(struct efi_object *obj);
/* Call this to validate a handle and find the EFI object for it */
struct efi_object *efi_search_obj(const void *handle);
/* Find a protocol on a handle */
int efi_memory_init(void);
/* Adds new or overrides configuration table entry to the system table */
efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table);
-void efi_setup_loaded_image(struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path);
+/* Sets up a loaded image */
+efi_status_t efi_setup_loaded_image(
+ struct efi_loaded_image *info, struct efi_object *obj,
+ struct efi_device_path *device_path,
+ struct efi_device_path *file_path);
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
void **buffer);
#define SANDBOX_BUCK_DRIVER "sandbox_buck"
#define SANDBOX_OF_BUCK_PREFIX "buck"
-#define SANDBOX_BUCK_COUNT 2
+#define SANDBOX_BUCK_COUNT 3
#define SANDBOX_LDO_COUNT 2
/*
* Sandbox PMIC registers:
#define SANDBOX_BUCK1_PLATNAME "SUPPLY_1.2V"
#define SANDBOX_BUCK2_DEVNAME "buck2"
#define SANDBOX_BUCK2_PLATNAME "SUPPLY_3.3V"
+/* BUCK3: for testing fallback regulator prefix matching during bind */
+#define SANDBOX_BUCK3_DEVNAME "no_match_by_nodename"
+#define SANDBOX_BUCK3_PLATNAME "buck_SUPPLY_1.5V"
/* LDO names */
#define SANDBOX_LDO1_DEVNAME "ldo1"
#define SANDBOX_LDO1_PLATNAME "VDD_EMMC_1.8V"
--- /dev/null
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TPS65910_PMIC_H_
+#define __TPS65910_PMIC_H_
+
+#define TPS65910_I2C_SEL_MASK (0x1 << 4)
+#define TPS65910_VDD_SR_MASK (0x1 << 7)
+#define TPS65910_GAIN_SEL_MASK (0x3 << 6)
+#define TPS65910_VDD_SEL_MASK 0x7f
+#define TPS65910_VDD_SEL_MIN 3
+#define TPS65910_VDD_SEL_MAX 75
+#define TPS65910_SEL_MASK (0x3 << 2)
+#define TPS65910_SUPPLY_STATE_MASK 0x3
+#define TPS65910_SUPPLY_STATE_OFF 0x0
+#define TPS65910_SUPPLY_STATE_ON 0x1
+
+/* i2c registers */
+enum {
+ TPS65910_REG_RTC_SEC = 0x00,
+ TPS65910_REG_RTC_MIN,
+ TPS65910_REG_RTC_HOUR,
+ TPS65910_REG_RTC_DAY,
+ TPS65910_REG_RTC_MONTH,
+ TPS65910_REG_RTC_YEAR,
+ TPS65910_REG_RTC_WEEK,
+ TPS65910_REG_RTC_ALARM_SEC = 0x08,
+ TPS65910_REG_RTC_ALARM_MIN,
+ TPS65910_REG_RTC_ALARM_HOUR,
+ TPS65910_REG_RTC_ALARM_DAY,
+ TPS65910_REG_RTC_ALARM_MONTH,
+ TPS65910_REG_RTC_ALARM_YEAR,
+ TPS65910_REG_RTC_CTRL = 0x10,
+ TPS65910_REG_RTC_STAT,
+ TPS65910_REG_RTC_INT,
+ TPS65910_REG_RTC_COMP_LSB,
+ TPS65910_REG_RTC_COMP_MSB,
+ TPS65910_REG_RTC_RESISTOR_PRG,
+ TPS65910_REG_RTC_RESET_STAT,
+ TPS65910_REG_BACKUP1,
+ TPS65910_REG_BACKUP2,
+ TPS65910_REG_BACKUP3,
+ TPS65910_REG_BACKUP4,
+ TPS65910_REG_BACKUP5,
+ TPS65910_REG_PUADEN,
+ TPS65910_REG_REF,
+ TPS65910_REG_VRTC,
+ TPS65910_REG_VIO = 0x20,
+ TPS65910_REG_VDD1,
+ TPS65910_REG_VDD1_VAL,
+ TPS65910_REG_VDD1_VAL_SR,
+ TPS65910_REG_VDD2,
+ TPS65910_REG_VDD2_VAL,
+ TPS65910_REG_VDD2_VAL_SR,
+ TPS65910_REG_VDD3,
+ TPS65910_REG_VDIG1 = 0x30,
+ TPS65910_REG_VDIG2,
+ TPS65910_REG_VAUX1,
+ TPS65910_REG_VAUX2,
+ TPS65910_REG_VAUX33,
+ TPS65910_REG_VMMC,
+ TPS65910_REG_VPLL,
+ TPS65910_REG_VDAC,
+ TPS65910_REG_THERM,
+ TPS65910_REG_BATTERY_BACKUP_CHARGE,
+ TPS65910_REG_DCDC_CTRL = 0x3e,
+ TPS65910_REG_DEVICE_CTRL,
+ TPS65910_REG_DEVICE_CTRL2,
+ TPS65910_REG_SLEEP_KEEP_LDO_ON,
+ TPS65910_REG_SLEEP_KEEP_RES_ON,
+ TPS65910_REG_SLEEP_SET_LDO_OFF,
+ TPS65910_REG_SLEEP_SET_RES_OFF,
+ TPS65910_REG_EN1_LDO_ASS,
+ TPS65910_REG_EM1_SMPS_ASS,
+ TPS65910_REG_EN2_LDO_ASS,
+ TPS65910_REG_EM2_SMPS_ASS,
+ TPS65910_REG_INT_STAT = 0x50,
+ TPS65910_REG_INT_MASK,
+ TPS65910_REG_INT_STAT2,
+ TPS65910_REG_INT_MASK2,
+ TPS65910_REG_GPIO = 0x60,
+ TPS65910_REG_JTAGREVNUM = 0x80,
+ TPS65910_NUM_REGS
+};
+
+/* chip supplies */
+enum {
+ TPS65910_SUPPLY_VCCIO = 0x00,
+ TPS65910_SUPPLY_VCC1,
+ TPS65910_SUPPLY_VCC2,
+ TPS65910_SUPPLY_VCC3,
+ TPS65910_SUPPLY_VCC4,
+ TPS65910_SUPPLY_VCC5,
+ TPS65910_SUPPLY_VCC6,
+ TPS65910_SUPPLY_VCC7,
+ TPS65910_NUM_SUPPLIES
+};
+
+/* regulator unit numbers */
+enum {
+ TPS65910_UNIT_VRTC = 0x00,
+ TPS65910_UNIT_VIO,
+ TPS65910_UNIT_VDD1,
+ TPS65910_UNIT_VDD2,
+ TPS65910_UNIT_VDD3,
+ TPS65910_UNIT_VDIG1,
+ TPS65910_UNIT_VDIG2,
+ TPS65910_UNIT_VPLL,
+ TPS65910_UNIT_VDAC,
+ TPS65910_UNIT_VAUX1,
+ TPS65910_UNIT_VAUX2,
+ TPS65910_UNIT_VAUX33,
+ TPS65910_UNIT_VMMC,
+};
+
+/* platform data */
+struct tps65910_regulator_pdata {
+ u32 supply; /* regulator supply voltage in uV */
+ uint unit; /* unit-address according to DT */
+};
+
+/* driver names */
+#define TPS65910_BUCK_DRIVER "tps65910_buck"
+#define TPS65910_BOOST_DRIVER "tps65910_boost"
+#define TPS65910_LDO_DRIVER "tps65910_ldo"
+
+#endif /* __TPS65910_PMIC_H_ */
EXYNOS5_BOARD_ODROID_XU3_REV01,
EXYNOS5_BOARD_ODROID_XU3_REV02,
EXYNOS5_BOARD_ODROID_XU4_REV01,
+ EXYNOS5_BOARD_ODROID_HC1_REV01,
EXYNOS5_BOARD_ODROID_UNKNOWN,
EXYNOS5_BOARD_COUNT,
bool board_is_generic(void);
bool board_is_odroidxu3(void);
bool board_is_odroidxu4(void);
+bool board_is_odroidhc1(void);
#endif
#ifndef _SPL_H_
#define _SPL_H_
+#include <binman_sym.h>
+
/* Platform-specific defines */
#include <linux/compiler.h>
#include <asm/spl.h>
void *buf);
};
+/*
+ * We need to know the position of U-Boot in memory so we can jump to it. We
+ * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
+ * u-boot.img), hence the '_any'. These is no checking here that the correct
+ * image is found. For * example if u-boot.img is used we don't check that
+ * spl_parse_image_header() can parse a valid header.
+ */
+binman_sym_extern(ulong, u_boot_any, pos);
+
/**
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
return r;
}
+/*
+ * Find a protocol on a handle.
+ *
+ * @handle handle
+ * @protocol_guid GUID of the protocol
+ * @handler reference to the protocol
+ * @return status code
+ */
+efi_status_t efi_search_protocol(const void *handle,
+ const efi_guid_t *protocol_guid,
+ struct efi_handler **handler)
+{
+ struct efi_object *efiobj;
+ struct list_head *lhandle;
+
+ if (!handle || !protocol_guid)
+ return EFI_INVALID_PARAMETER;
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_INVALID_PARAMETER;
+ list_for_each(lhandle, &efiobj->protocols) {
+ struct efi_handler *protocol;
+
+ protocol = list_entry(lhandle, struct efi_handler, link);
+ if (!guidcmp(protocol->guid, protocol_guid)) {
+ if (handler)
+ *handler = protocol;
+ return EFI_SUCCESS;
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+/*
+ * Delete protocol from a handle.
+ *
+ * @handle handle from which the protocol shall be deleted
+ * @protocol GUID of the protocol to be deleted
+ * @protocol_interface interface of the protocol implementation
+ * @return status code
+ */
+efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
+ void *protocol_interface)
+{
+ struct efi_handler *handler;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(handle, protocol, &handler);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ if (guidcmp(handler->guid, protocol))
+ return EFI_INVALID_PARAMETER;
+ list_del(&handler->link);
+ free(handler);
+ return EFI_SUCCESS;
+}
+
+/*
+ * Delete all protocols from a handle.
+ *
+ * @handle handle from which the protocols shall be deleted
+ * @return status code
+ */
+efi_status_t efi_remove_all_protocols(const void *handle)
+{
+ struct efi_object *efiobj;
+ struct list_head *lhandle;
+ struct list_head *pos;
+
+ efiobj = efi_search_obj(handle);
+ if (!efiobj)
+ return EFI_INVALID_PARAMETER;
+ list_for_each_safe(lhandle, pos, &efiobj->protocols) {
+ struct efi_handler *protocol;
+ efi_status_t ret;
+
+ protocol = list_entry(lhandle, struct efi_handler, link);
+
+ ret = efi_remove_protocol(handle, protocol->guid,
+ protocol->protocol_interface);
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Delete handle.
+ *
+ * @handle handle to delete
+ */
+void efi_delete_handle(struct efi_object *obj)
+{
+ if (!obj)
+ return;
+ efi_remove_all_protocols(obj->handle);
+ list_del(&obj->link);
+ free(obj);
+}
+
/*
* Our event capabilities are very limited. Only a small limited
* number of events is allowed to coexist.
return NULL;
}
-/*
- * Find a protocol on a handle.
- *
- * @handle handle
- * @protocol_guid GUID of the protocol
- * @handler reference to the protocol
- * @return status code
- */
-efi_status_t efi_search_protocol(const void *handle,
- const efi_guid_t *protocol_guid,
- struct efi_handler **handler)
-{
- struct efi_object *efiobj;
- struct list_head *lhandle;
-
- if (!handle || !protocol_guid)
- return EFI_INVALID_PARAMETER;
- efiobj = efi_search_obj(handle);
- if (!efiobj)
- return EFI_INVALID_PARAMETER;
- list_for_each(lhandle, &efiobj->protocols) {
- struct efi_handler *protocol;
-
- protocol = list_entry(lhandle, struct efi_handler, link);
- if (!guidcmp(protocol->guid, protocol_guid)) {
- if (handler)
- *handler = protocol;
- return EFI_SUCCESS;
- }
- }
- return EFI_NOT_FOUND;
-}
-
/*
* Install new protocol on a handle.
*
return EFI_SUCCESS;
}
-/*
- * Delete protocol from a handle.
- *
- * @handle handle from which the protocol shall be deleted
- * @protocol GUID of the protocol to be deleted
- * @protocol_interface interface of the protocol implementation
- * @return status code
- */
-efi_status_t efi_remove_protocol(const void *handle, const efi_guid_t *protocol,
- void *protocol_interface)
-{
- struct efi_handler *handler;
- efi_status_t ret;
-
- ret = efi_search_protocol(handle, protocol, &handler);
- if (ret != EFI_SUCCESS)
- return ret;
- if (guidcmp(handler->guid, protocol))
- return EFI_INVALID_PARAMETER;
- list_del(&handler->link);
- free(handler);
- return EFI_SUCCESS;
-}
-
-/*
- * Delete all protocols from a handle.
- *
- * @handle handle from which the protocols shall be deleted
- * @return status code
- */
-efi_status_t efi_remove_all_protocols(const void *handle)
-{
- struct efi_object *efiobj;
- struct list_head *lhandle;
- struct list_head *pos;
-
- efiobj = efi_search_obj(handle);
- if (!efiobj)
- return EFI_INVALID_PARAMETER;
- list_for_each_safe(lhandle, pos, &efiobj->protocols) {
- struct efi_handler *protocol;
- efi_status_t ret;
-
- protocol = list_entry(lhandle, struct efi_handler, link);
-
- ret = efi_remove_protocol(handle, protocol->guid,
- protocol->protocol_interface);
- if (ret != EFI_SUCCESS)
- return ret;
- }
- return EFI_SUCCESS;
-}
-
/*
* Install protocol interface.
*
* @obj internal object associated with the loaded image
* @device_path device path of the loaded image
* @file_path file path of the loaded image
+ * @return status code
*/
-void efi_setup_loaded_image(struct efi_loaded_image *info, struct efi_object *obj,
- struct efi_device_path *device_path,
- struct efi_device_path *file_path)
+efi_status_t efi_setup_loaded_image(
+ struct efi_loaded_image *info, struct efi_object *obj,
+ struct efi_device_path *device_path,
+ struct efi_device_path *file_path)
{
efi_status_t ret;
if (ret != EFI_SUCCESS)
goto failure;
- return;
+ return ret;
failure:
printf("ERROR: Failure to install protocols for loaded image\n");
+ return ret;
}
/*
{
struct efi_loaded_image *info;
struct efi_object *obj;
+ efi_status_t ret;
EFI_ENTRY("%d, %p, %p, %p, %ld, %p", boot_policy, parent_image,
file_path, source_buffer, source_size, image_handle);
if (!source_buffer) {
struct efi_device_path *dp, *fp;
- efi_status_t ret;
ret = efi_load_image_from_path(file_path, &source_buffer);
- if (ret != EFI_SUCCESS) {
- free(info);
- free(obj);
- return EFI_EXIT(ret);
- }
-
+ if (ret != EFI_SUCCESS)
+ goto failure;
/*
* split file_path which contains both the device and
* file parts:
*/
efi_dp_split_file_path(file_path, &dp, &fp);
-
- efi_setup_loaded_image(info, obj, dp, fp);
+ ret = efi_setup_loaded_image(info, obj, dp, fp);
+ if (ret != EFI_SUCCESS)
+ goto failure;
} else {
/* In this case, file_path is the "device" path, ie.
* something like a HARDWARE_DEVICE:MEMORY_MAPPED
*/
- efi_setup_loaded_image(info, obj, file_path, NULL);
+ ret = efi_setup_loaded_image(info, obj, file_path, NULL);
+ if (ret != EFI_SUCCESS)
+ goto failure;
}
-
info->reserved = efi_load_pe(source_buffer, info);
if (!info->reserved) {
- free(info);
- free(obj);
- return EFI_EXIT(EFI_UNSUPPORTED);
+ ret = EFI_UNSUPPORTED;
+ goto failure;
}
-
info->system_table = &systab;
info->parent_handle = parent_image;
*image_handle = obj->handle;
-
return EFI_EXIT(EFI_SUCCESS);
+failure:
+ free(info);
+ efi_delete_handle(obj);
+ return EFI_EXIT(ret);
}
/*
.guid = U_BOOT_GUID,
};
+#if defined(CONFIG_DM_MMC) && defined(CONFIG_MMC)
+/*
+ * Determine if an MMC device is an SD card.
+ *
+ * @desc block device descriptor
+ * @return true if the device is an SD card
+ */
+static bool is_sd(struct blk_desc *desc)
+{
+ struct mmc *mmc = find_mmc_device(desc->devnum);
+
+ if (!mmc)
+ return false;
+
+ return IS_SD(mmc) != 0U;
+}
+#endif
+
static void *dp_alloc(size_t sz)
{
void *buf;
struct efi_device_path **rem)
{
struct efi_object *efiobj;
+ unsigned int dp_size = efi_dp_size(dp);
list_for_each_entry(efiobj, &efi_obj_list, link) {
struct efi_handler *handler;
do {
if (efi_dp_match(dp, obj_dp) == 0) {
if (rem) {
+ /*
+ * Allow partial matches, but inform
+ * the caller.
+ */
*rem = ((void *)dp) +
efi_dp_size(obj_dp);
+ return efiobj;
+ } else {
+ /* Only return on exact matches */
+ if (efi_dp_size(obj_dp) == dp_size)
+ return efiobj;
}
- return efiobj;
}
obj_dp = shorten_path(efi_dp_next(obj_dp));
{
struct efi_object *efiobj;
- efiobj = find_obj(dp, false, rem);
+ /* Search for an exact match first */
+ efiobj = find_obj(dp, false, NULL);
+
+ /* Then for a fuzzy match */
+ if (!efiobj)
+ efiobj = find_obj(dp, false, rem);
+ /* And now for a fuzzy short match */
if (!efiobj)
efiobj = find_obj(dp, true, rem);
struct blk_desc *desc = mmc_get_blk_desc(mmc);
sddp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
- sddp->dp.sub_type = (desc->if_type == IF_TYPE_MMC) ?
- DEVICE_PATH_SUB_TYPE_MSG_MMC :
- DEVICE_PATH_SUB_TYPE_MSG_SD;
+ sddp->dp.sub_type = is_sd(desc) ?
+ DEVICE_PATH_SUB_TYPE_MSG_SD :
+ DEVICE_PATH_SUB_TYPE_MSG_MMC;
sddp->dp.length = sizeof(*sddp);
sddp->slot_number = dev->seq;
return dpsize;
}
+/*
+ * Create a device path for a block device or one of its partitions.
+ *
+ * @buf buffer to which the device path is wirtten
+ * @desc block device descriptor
+ * @part partition number, 0 identifies a block device
+ */
static void *dp_part_fill(void *buf, struct blk_desc *desc, int part)
{
disk_partition_t info;
* and handling all the different cases like we do for non-
* legacy (ie CONFIG_BLK=y) case. But most important thing
* is just to have a unique device-path for if_type+devnum.
- * So map things to a fictional USB device:
+ * So map things to a fictitious USB device.
*/
struct efi_device_path_usb *udp;
if (desc->part_type == PART_TYPE_ISO) {
struct efi_device_path_cdrom_path *cddp = buf;
- cddp->boot_entry = part - 1;
+ cddp->boot_entry = part;
cddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
cddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_CDROM_PATH;
cddp->dp.length = sizeof(*cddp);
hddp->dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
hddp->dp.sub_type = DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH;
hddp->dp.length = sizeof(*hddp);
- hddp->partition_number = part - 1;
+ hddp->partition_number = part;
hddp->partition_start = info.start;
hddp->partition_end = info.size;
if (desc->part_type == PART_TYPE_EFI)
case DEVICE_PATH_SUB_TYPE_MSG_USB: {
struct efi_device_path_usb *udp =
(struct efi_device_path_usb *)dp;
- s += sprintf(s, "Usb(0x%x,0x%x)", udp->parent_port_number,
+ s += sprintf(s, "USB(0x%x,0x%x)", udp->parent_port_number,
udp->usb_interface);
break;
}
case DEVICE_PATH_SUB_TYPE_MSG_MMC: {
const char *typename =
(dp->sub_type == DEVICE_PATH_SUB_TYPE_MSG_SD) ?
- "SDCard" : "MMC";
+ "SD" : "eMMC";
struct efi_device_path_sd_mmc_path *sddp =
(struct efi_device_path_sd_mmc_path *)dp;
- s += sprintf(s, "%s(Slot%u)", typename, sddp->slot_number);
+ s += sprintf(s, "%s(%u)", typename, sddp->slot_number);
break;
}
default:
return s;
}
+/*
+ * Convert a media device path node to text.
+ *
+ * @s output buffer
+ * @dp device path node
+ * @return next unused buffer address
+ */
static char *dp_media(char *s, struct efi_device_path *dp)
{
switch (dp->sub_type) {
struct efi_device_path_hard_drive_path *hddp =
(struct efi_device_path_hard_drive_path *)dp;
void *sig = hddp->partition_signature;
+ u64 start;
+ u64 end;
+
+ /* Copy from packed structure to aligned memory */
+ memcpy(&start, &hddp->partition_start, sizeof(start));
+ memcpy(&end, &hddp->partition_end, sizeof(end));
switch (hddp->signature_type) {
- case SIG_TYPE_MBR:
- s += sprintf(s, "HD(Part%d,Sig%08x)",
- hddp->partition_number,
- *(uint32_t *)sig);
+ case SIG_TYPE_MBR: {
+ u32 signature;
+
+ memcpy(&signature, sig, sizeof(signature));
+ s += sprintf(
+ s, "HD(%d,MBR,0x%08x,0x%llx,0x%llx)",
+ hddp->partition_number, signature, start, end);
break;
+ }
case SIG_TYPE_GUID:
- s += sprintf(s, "HD(Part%d,Sig%pUl)",
- hddp->partition_number, sig);
+ s += sprintf(
+ s, "HD(%d,GPT,%pUl,0x%llx,0x%llx)",
+ hddp->partition_number, sig, start, end);
break;
default:
- s += sprintf(s, "HD(Part%d,MBRType=%02x,SigType=%02x)",
- hddp->partition_number, hddp->partmap_type,
- hddp->signature_type);
+ s += sprintf(
+ s, "HD(%d,0x%02x,0,0x%llx,0x%llx)",
+ hddp->partition_number, hddp->partmap_type,
+ start, end);
break;
}
#include <common.h>
#include <efi_api.h>
+static const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
+
/*
* Entry point of the EFI application.
*
struct efi_simple_text_output_protocol *con_out = systable->con_out;
struct efi_boot_services *boottime = systable->boottime;
struct efi_loaded_image *loaded_image;
- const efi_guid_t loaded_image_guid = LOADED_IMAGE_GUID;
efi_status_t ret;
con_out->output_string(con_out, L"Hello, world!\n");
enum {
BUCK1,
BUCK2,
+ BUCK3,
LDO1,
LDO2,
OUTPUT_COUNT,
/* devname, platname */
{ SANDBOX_BUCK1_DEVNAME, SANDBOX_BUCK1_PLATNAME },
{ SANDBOX_BUCK2_DEVNAME, SANDBOX_BUCK2_PLATNAME },
+ { SANDBOX_BUCK3_DEVNAME, SANDBOX_BUCK3_PLATNAME },
{ SANDBOX_LDO1_DEVNAME, SANDBOX_LDO1_PLATNAME},
{ SANDBOX_LDO2_DEVNAME, SANDBOX_LDO2_PLATNAME},
};
an entry containing a hash of the contents of some other entries. At this
stage the position and size of entries should not be adjusted.
+6. WriteEntryInfo()
+
7. BuildImage() - builds the image and writes it to a file. This is the final
step.
# u_boot_dtsi_options_debug = $(u_boot_dtsi_options_raw)
+Access to binman entry positions at run time
+--------------------------------------------
+
+Binman assembles images and determines where each entry is placed in the image.
+This information may be useful to U-Boot at run time. For example, in SPL it
+is useful to be able to find the location of U-Boot so that it can be executed
+when SPL is finished.
+
+Binman allows you to declare symbols in the SPL image which are filled in
+with their correct values during the build. For example:
+
+ binman_sym_declare(ulong, u_boot_any, pos);
+
+declares a ulong value which will be assigned to the position of any U-Boot
+image (u-boot.bin, u-boot.img, u-boot-nodtb.bin) that is present in the image.
+You can access this value with something like:
+
+ ulong u_boot_pos = binman_sym(ulong, u_boot_any, pos);
+
+Thus u_boot_pos will be set to the position of U-Boot in memory, assuming that
+the whole image has been loaded, or is available in flash. You can then jump to
+that address to start U-Boot.
+
+At present this feature is only supported in SPL. In principle it is possible
+to fill in such symbols in U-Boot proper, as well.
+
+
Code coverage
-------------
Some ideas:
- Fill out the device tree to include the final position and size of each
- entry (since the input file may not always specify these)
+ entry (since the input file may not always specify these). See also
+ 'Access to binman entry positions at run time' above
- Use of-platdata to make the information available to code that is unable
to use device tree (such as a very small SPL image)
- Write an image map to a text file
import command
import control
-def RunTests():
+def RunTests(debug):
"""Run the functional tests and any embedded doctests"""
+ import elf_test
import entry_test
import fdt_test
import ftest
+ import image_test
import test
import doctest
suite.run(result)
sys.argv = [sys.argv[0]]
+ if debug:
+ sys.argv.append('-D')
# Run the entry tests first ,since these need to be the first to import the
# 'entry' module.
suite = unittest.TestLoader().loadTestsFromTestCase(entry_test.TestEntry)
suite.run(result)
- for module in (ftest.TestFunctional, fdt_test.TestFdt):
+ for module in (ftest.TestFunctional, fdt_test.TestFdt, elf_test.TestElf,
+ image_test.TestImage):
suite = unittest.TestLoader().loadTestsFromTestCase(module)
suite.run(result)
sys.tracebacklimit = 0
if options.test:
- ret_code = RunTests()
+ ret_code = RunTests(options.debug)
elif options.test_coverage:
RunTestCoverage()
import tools
import command
+import elf
import fdt
import fdt_util
from image import Image
try:
tout.Init(options.verbosity)
+ elf.debug = options.debug
try:
tools.SetInputDirs(options.indir)
tools.PrepareOutputDir(options.outdir, options.preserve)
image.CheckSize()
image.CheckEntries()
image.ProcessEntryContents()
+ image.WriteSymbols()
image.BuildImage()
finally:
tools.FinaliseOutputDir()
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Handle various things related to ELF images
+#
+
+from collections import namedtuple, OrderedDict
+import command
+import os
+import re
+import struct
+
+import tools
+
+# This is enabled from control.py
+debug = False
+
+Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak'])
+
+
+def GetSymbols(fname, patterns):
+ """Get the symbols from an ELF file
+
+ Args:
+ fname: Filename of the ELF file to read
+ patterns: List of regex patterns to search for, each a string
+
+ Returns:
+ None, if the file does not exist, or Dict:
+ key: Name of symbol
+ value: Hex value of symbol
+ """
+ stdout = command.Output('objdump', '-t', fname, raise_on_error=False)
+ lines = stdout.splitlines()
+ if patterns:
+ re_syms = re.compile('|'.join(patterns))
+ else:
+ re_syms = None
+ syms = {}
+ syms_started = False
+ for line in lines:
+ if not line or not syms_started:
+ if 'SYMBOL TABLE' in line:
+ syms_started = True
+ line = None # Otherwise code coverage complains about 'continue'
+ continue
+ if re_syms and not re_syms.search(line):
+ continue
+
+ space_pos = line.find(' ')
+ value, rest = line[:space_pos], line[space_pos + 1:]
+ flags = rest[:7]
+ parts = rest[7:].split()
+ section, size = parts[:2]
+ if len(parts) > 2:
+ name = parts[2]
+ syms[name] = Symbol(section, int(value, 16), int(size,16),
+ flags[1] == 'w')
+ return syms
+
+def GetSymbolAddress(fname, sym_name):
+ """Get a value of a symbol from an ELF file
+
+ Args:
+ fname: Filename of the ELF file to read
+ patterns: List of regex patterns to search for, each a string
+
+ Returns:
+ Symbol value (as an integer) or None if not found
+ """
+ syms = GetSymbols(fname, [sym_name])
+ sym = syms.get(sym_name)
+ if not sym:
+ return None
+ return sym.address
+
+def LookupAndWriteSymbols(elf_fname, entry, image):
+ """Replace all symbols in an entry with their correct values
+
+ The entry contents is updated so that values for referenced symbols will be
+ visible at run time. This is done by finding out the symbols positions in
+ the entry (using the ELF file) and replacing them with values from binman's
+ data structures.
+
+ Args:
+ elf_fname: Filename of ELF image containing the symbol information for
+ entry
+ entry: Entry to process
+ image: Image which can be used to lookup symbol values
+ """
+ fname = tools.GetInputFilename(elf_fname)
+ syms = GetSymbols(fname, ['image', 'binman'])
+ if not syms:
+ return
+ base = syms.get('__image_copy_start')
+ if not base:
+ return
+ for name, sym in syms.iteritems():
+ if name.startswith('_binman'):
+ msg = ("Image '%s': Symbol '%s'\n in entry '%s'" %
+ (image.GetPath(), name, entry.GetPath()))
+ offset = sym.address - base.address
+ if offset < 0 or offset + sym.size > entry.contents_size:
+ raise ValueError('%s has offset %x (size %x) but the contents '
+ 'size is %x' % (entry.GetPath(), offset,
+ sym.size, entry.contents_size))
+ if sym.size == 4:
+ pack_string = '<I'
+ elif sym.size == 8:
+ pack_string = '<Q'
+ else:
+ raise ValueError('%s has size %d: only 4 and 8 are supported' %
+ (msg, sym.size))
+
+ # Look up the symbol in our entry tables.
+ value = image.LookupSymbol(name, sym.weak, msg)
+ if value is not None:
+ value += base.address
+ else:
+ value = -1
+ pack_string = pack_string.lower()
+ value_bytes = struct.pack(pack_string, value)
+ if debug:
+ print('%s:\n insert %s, offset %x, value %x, length %d' %
+ (msg, name, offset, value, len(value_bytes)))
+ entry.data = (entry.data[:offset] + value_bytes +
+ entry.data[offset + sym.size:])
--- /dev/null
+#
+# Copyright (c) 2017 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the elf module
+
+from contextlib import contextmanager
+import os
+import sys
+import unittest
+
+try:
+ from StringIO import StringIO
+except ImportError:
+ from io import StringIO
+
+import elf
+
+binman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
+
+# Use this to suppress stdout/stderr output:
+# with capture_sys_output() as (stdout, stderr)
+# ...do something...
+@contextmanager
+def capture_sys_output():
+ capture_out, capture_err = StringIO(), StringIO()
+ old_out, old_err = sys.stdout, sys.stderr
+ try:
+ sys.stdout, sys.stderr = capture_out, capture_err
+ yield capture_out, capture_err
+ finally:
+ sys.stdout, sys.stderr = old_out, old_err
+
+
+class FakeEntry:
+ def __init__(self, contents_size):
+ self.contents_size = contents_size
+ self.data = 'a' * contents_size
+
+ def GetPath(self):
+ return 'entry_path'
+
+class FakeImage:
+ def __init__(self, sym_value=1):
+ self.sym_value = sym_value
+
+ def GetPath(self):
+ return 'image_path'
+
+ def LookupSymbol(self, name, weak, msg):
+ return self.sym_value
+
+class TestElf(unittest.TestCase):
+ def testAllSymbols(self):
+ fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
+ syms = elf.GetSymbols(fname, [])
+ self.assertIn('.ucode', syms)
+
+ def testRegexSymbols(self):
+ fname = os.path.join(binman_dir, 'test', 'u_boot_ucode_ptr')
+ syms = elf.GetSymbols(fname, ['ucode'])
+ self.assertIn('.ucode', syms)
+ syms = elf.GetSymbols(fname, ['missing'])
+ self.assertNotIn('.ucode', syms)
+ syms = elf.GetSymbols(fname, ['missing', 'ucode'])
+ self.assertIn('.ucode', syms)
+
+ def testMissingFile(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols('missing-file', entry, image)
+ self.assertIn("Filename 'missing-file' not found in input path",
+ str(e.exception))
+
+ def testOutsideFile(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertIn('entry_path has offset 4 (size 8) but the contents size '
+ 'is a', str(e.exception))
+
+ def testMissingImageStart(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_bad')
+ self.assertEqual(elf.LookupAndWriteSymbols(elf_fname, entry, image),
+ None)
+
+ def testBadSymbolSize(self):
+ entry = FakeEntry(10)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms_size')
+ with self.assertRaises(ValueError) as e:
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertIn('has size 1: only 4 and 8 are supported',
+ str(e.exception))
+
+ def testNoValue(self):
+ entry = FakeEntry(20)
+ image = FakeImage(sym_value=None)
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ self.assertEqual(chr(255) * 16 + 'a' * 4, entry.data)
+
+ def testDebug(self):
+ elf.debug = True
+ entry = FakeEntry(20)
+ image = FakeImage()
+ elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms')
+ with capture_sys_output() as (stdout, stderr):
+ syms = elf.LookupAndWriteSymbols(elf_fname, entry, image)
+ elf.debug = False
+ self.assertTrue(len(stdout.getvalue()) > 0)
+
+
+if __name__ == '__main__':
+ unittest.main()
def ProcessContents(self):
pass
+
+ def WriteSymbols(self, image):
+ """Write symbol values into binary files for access at run time
+
+ Args:
+ image: Image containing the entry
+ """
+ pass
# Entry-type module for spl/u-boot-spl.bin
#
+import elf
+
from entry import Entry
from blob import Entry_blob
class Entry_u_boot_spl(Entry_blob):
def __init__(self, image, etype, node):
Entry_blob.__init__(self, image, etype, node)
+ self.elf_fname = 'spl/u-boot-spl'
def GetDefaultFilename(self):
return 'spl/u-boot-spl.bin'
+
+ def WriteSymbols(self, image):
+ elf.LookupAndWriteSymbols(self.elf_fname, self, image)
#
import command
+import elf
from entry import Entry
from blob import Entry_blob
import tools
def ObtainContents(self):
fname = tools.GetInputFilename('spl/u-boot-spl')
- args = [['nm', fname], ['grep', '__bss_size']]
- out = command.RunPipe(args, capture=True).stdout.splitlines()
- bss_size = int(out[0].split()[0], 16)
+ bss_size = elf.GetSymbolAddress(fname, '__bss_size')
+ if not bss_size:
+ self.Raise('Expected __bss_size symbol in spl/u-boot-spl')
self.data = chr(0) * bss_size
self.contents_size = bss_size
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for U-Boot device tree
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl_dtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl.dtb'
--- /dev/null
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for 'u-boot-nodtb.bin'
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_u_boot_spl_nodtb(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
+
+ def GetDefaultFilename(self):
+ return 'spl/u-boot-spl-nodtb.bin'
import struct
import command
+import elf
from entry import Entry
from blob import Entry_blob
import fdt_util
def ObtainContents(self):
# Figure out where to put the microcode pointer
fname = tools.GetInputFilename(self.elf_fname)
- args = [['nm', fname], ['grep', '-w', '_dt_ucode_base_size']]
- out = (command.RunPipe(args, capture=True, raise_on_error=False).
- stdout.splitlines())
- if len(out) == 1:
- self.target_pos = int(out[0].split()[0], 16)
+ sym = elf.GetSymbolAddress(fname, '_dt_ucode_base_size')
+ if sym:
+ self.target_pos = sym
elif not fdt_util.GetBool(self._node, 'optional-ucode'):
self.Raise('Cannot locate _dt_ucode_base_size symbol in u-boot')
import cmdline
import command
import control
+import elf
import fdt
import fdt_util
import tools
# Contents of test files, corresponding to different entry types
U_BOOT_DATA = '1234'
U_BOOT_IMG_DATA = 'img'
-U_BOOT_SPL_DATA = '567'
+U_BOOT_SPL_DATA = '56780123456789abcde'
BLOB_DATA = '89'
ME_DATA = '0abcd'
VGA_DATA = 'vga'
U_BOOT_DTB_DATA = 'udtb'
+U_BOOT_SPL_DTB_DATA = 'spldtb'
X86_START16_DATA = 'start16'
X86_START16_SPL_DATA = 'start16spl'
U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
TestFunctional._MakeInputFile('me.bin', ME_DATA)
TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
TestFunctional._MakeInputFile('u-boot.dtb', U_BOOT_DTB_DATA)
+ TestFunctional._MakeInputFile('spl/u-boot-spl.dtb', U_BOOT_SPL_DTB_DATA)
TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin',
X86_START16_SPL_DATA)
Returns:
Return value (0 for success)
"""
- (options, args) = cmdline.ParseArgs(list(args))
+ args = list(args)
+ if '-D' in sys.argv:
+ args = args + ['-D']
+ (options, args) = cmdline.ParseArgs(args)
options.pager = 'binman-invalid-pager'
options.build_dir = self._indir
# options.verbosity = tout.DEBUG
return control.Binman(options, args)
- def _DoTestFile(self, fname):
+ def _DoTestFile(self, fname, debug=False):
"""Run binman with a given test file
Args:
fname: Device tree source filename to use (e.g. 05_simple.dts)
"""
- return self._DoBinman('-p', '-I', self._indir,
- '-d', self.TestFile(fname))
+ args = ['-p', '-I', self._indir, '-d', self.TestFile(fname)]
+ if debug:
+ args.append('-D')
+ return self._DoBinman(*args)
def _SetupDtb(self, fname, outfile='u-boot.dtb'):
"""Set up a new test device-tree file
self.assertEqual(0, len(result.stderr))
self.assertEqual(0, result.return_code)
- # Not yet available.
def testBoard(self):
"""Test that we can run it with a specific board"""
self._SetupDtb('05_simple.dts', 'sandbox/u-boot.dtb')
data = self._DoReadFile('05_simple.dts')
self.assertEqual(U_BOOT_DATA, data)
+ def testSimpleDebug(self):
+ """Test a simple binman run with debugging enabled"""
+ data = self._DoTestFile('05_simple.dts', debug=True)
+
def testDual(self):
"""Test that we can handle creating two images
def testImagePadByte(self):
"""Test that the image pad byte can be specified"""
+ with open(self.TestFile('bss_data')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
data = self._DoReadFile('21_image_pad.dts')
- self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 9) + U_BOOT_DATA, data)
+ self.assertEqual(U_BOOT_SPL_DATA + (chr(0xff) * 1) + U_BOOT_DATA, data)
def testImageName(self):
"""Test that image files can be named"""
def testPackSorted(self):
"""Test that entries can be sorted"""
data = self._DoReadFile('24_sorted.dts')
- self.assertEqual(chr(0) * 5 + U_BOOT_SPL_DATA + chr(0) * 2 +
+ self.assertEqual(chr(0) * 1 + U_BOOT_SPL_DATA + chr(0) * 2 +
U_BOOT_DATA, data)
def testPackZeroPosition(self):
with self.assertRaises(ValueError) as e:
self._DoTestFile('28_pack_4gb_outside.dts')
self.assertIn("Node '/binman/u-boot': Position 0x0 (0) is outside "
- "the image starting at 0xfffffff0 (4294967280)",
+ "the image starting at 0xffffffe0 (4294967264)",
str(e.exception))
def testPackX86Rom(self):
"""Test that a basic x86 ROM can be created"""
data = self._DoReadFile('29_x86-rom.dts')
- self.assertEqual(U_BOOT_DATA + chr(0) * 3 + U_BOOT_SPL_DATA +
- chr(0) * 6, data)
+ self.assertEqual(U_BOOT_DATA + chr(0) * 7 + U_BOOT_SPL_DATA +
+ chr(0) * 2, data)
def testPackX86RomMeNoDesc(self):
"""Test that an invalid Intel descriptor entry is detected"""
data = self._DoReadFile('47_spl_bss_pad.dts')
self.assertEqual(U_BOOT_SPL_DATA + (chr(0) * 10) + U_BOOT_DATA, data)
+ with open(self.TestFile('u_boot_ucode_ptr')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ with self.assertRaises(ValueError) as e:
+ data = self._DoReadFile('47_spl_bss_pad.dts')
+ self.assertIn('Expected __bss_size symbol in spl/u-boot-spl',
+ str(e.exception))
+
def testPackStart16Spl(self):
"""Test that an image with an x86 start16 region can be created"""
data = self._DoReadFile('48_x86-start16-spl.dts')
data = self._DoReadFile('50_intel_mrc.dts')
self.assertEqual(MRC_DATA, data[:len(MRC_DATA)])
+ def testSplDtb(self):
+ """Test that an image with spl/u-boot-spl.dtb can be created"""
+ data = self._DoReadFile('51_u_boot_spl_dtb.dts')
+ self.assertEqual(U_BOOT_SPL_DTB_DATA, data[:len(U_BOOT_SPL_DTB_DATA)])
+
+ def testSplNoDtb(self):
+ """Test that an image with spl/u-boot-spl-nodtb.bin can be created"""
+ data = self._DoReadFile('52_u_boot_spl_nodtb.dts')
+ self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)])
+
+ def testSymbols(self):
+ """Test binman can assign symbols embedded in U-Boot"""
+ elf_fname = self.TestFile('u_boot_binman_syms')
+ syms = elf.GetSymbols(elf_fname, ['binman', 'image'])
+ addr = elf.GetSymbolAddress(elf_fname, '__image_copy_start')
+ self.assertEqual(syms['_binman_u_boot_spl_prop_pos'].address, addr)
+
+ with open(self.TestFile('u_boot_binman_syms')) as fd:
+ TestFunctional._MakeInputFile('spl/u-boot-spl', fd.read())
+ data = self._DoReadFile('53_symbols.dts')
+ sym_values = struct.pack('<LQL', 0x24 + 0, 0x24 + 24, 0x24 + 20)
+ expected = (sym_values + U_BOOT_SPL_DATA[16:] + chr(0xff) +
+ U_BOOT_DATA +
+ sym_values + U_BOOT_SPL_DATA[16:])
+ self.assertEqual(expected, data)
+
if __name__ == "__main__":
unittest.main()
# Class for an image, the output of binman
#
+from __future__ import print_function
+
from collections import OrderedDict
from operator import attrgetter
+import re
+import sys
import fdt_util
import tools
address.
_entries: OrderedDict() of entries
"""
- def __init__(self, name, node):
+ def __init__(self, name, node, test=False):
global entry
global Entry
import entry
self._end_4gb = False
self._entries = OrderedDict()
- self._ReadNode()
- self._ReadEntries()
+ if not test:
+ self._ReadNode()
+ self._ReadEntries()
def _ReadNode(self):
"""Read properties from the image node"""
"""
raise ValueError("Image '%s': %s" % (self._node.path, msg))
+ def GetPath(self):
+ """Get the path of an image (in the FDT)
+
+ Returns:
+ Full path of the node for this image
+ """
+ return self._node.path
+
def _ReadEntries(self):
for node in self._node.subnodes:
self._entries[node.name] = Entry.Create(self, node)
for entry in self._entries.values():
entry.ProcessContents()
+ def WriteSymbols(self):
+ """Write symbol values into binary files for access at run time"""
+ for entry in self._entries.values():
+ entry.WriteSymbols(self)
+
def BuildImage(self):
"""Write the image to a file"""
fname = tools.GetOutputFilename(self._filename)
data = entry.GetData()
fd.seek(self._pad_before + entry.pos - self._skip_at_start)
fd.write(data)
+
+ def LookupSymbol(self, sym_name, optional, msg):
+ """Look up a symbol in an ELF file
+
+ Looks up a symbol in an ELF file. Only entry types which come from an
+ ELF image can be used by this function.
+
+ At present the only entry property supported is pos.
+
+ Args:
+ sym_name: Symbol name in the ELF file to look up in the format
+ _binman_<entry>_prop_<property> where <entry> is the name of
+ the entry and <property> is the property to find (e.g.
+ _binman_u_boot_prop_pos). As a special case, you can append
+ _any to <entry> to have it search for any matching entry. E.g.
+ _binman_u_boot_any_prop_pos will match entries called u-boot,
+ u-boot-img and u-boot-nodtb)
+ optional: True if the symbol is optional. If False this function
+ will raise if the symbol is not found
+ msg: Message to display if an error occurs
+
+ Returns:
+ Value that should be assigned to that symbol, or None if it was
+ optional and not found
+
+ Raises:
+ ValueError if the symbol is invalid or not found, or references a
+ property which is not supported
+ """
+ m = re.match(r'^_binman_(\w+)_prop_(\w+)$', sym_name)
+ if not m:
+ raise ValueError("%s: Symbol '%s' has invalid format" %
+ (msg, sym_name))
+ entry_name, prop_name = m.groups()
+ entry_name = entry_name.replace('_', '-')
+ entry = self._entries.get(entry_name)
+ if not entry:
+ if entry_name.endswith('-any'):
+ root = entry_name[:-4]
+ for name in self._entries:
+ if name.startswith(root):
+ rest = name[len(root):]
+ if rest in ['', '-img', '-nodtb']:
+ entry = self._entries[name]
+ if not entry:
+ err = ("%s: Entry '%s' not found in list (%s)" %
+ (msg, entry_name, ','.join(self._entries.keys())))
+ if optional:
+ print('Warning: %s' % err, file=sys.stderr)
+ return None
+ raise ValueError(err)
+ if prop_name == 'pos':
+ return entry.pos
+ else:
+ raise ValueError("%s: No such property '%s'" % (msg, prop_name))
--- /dev/null
+#
+# Copyright (c) 2017 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Test for the image module
+
+import unittest
+
+from image import Image
+from elf_test import capture_sys_output
+
+class TestImage(unittest.TestCase):
+ def testInvalidFormat(self):
+ image = Image('name', 'node', test=True)
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_something_prop_', False, 'msg')
+ self.assertIn(
+ "msg: Symbol '_binman_something_prop_' has invalid format",
+ str(e.exception))
+
+ def testMissingSymbol(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {}
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_type_prop_pname', False, 'msg')
+ self.assertIn("msg: Entry 'type' not found in list ()",
+ str(e.exception))
+
+ def testMissingSymbolOptional(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {}
+ with capture_sys_output() as (stdout, stderr):
+ val = image.LookupSymbol('_binman_type_prop_pname', True, 'msg')
+ self.assertEqual(val, None)
+ self.assertEqual("Warning: msg: Entry 'type' not found in list ()\n",
+ stderr.getvalue())
+ self.assertEqual('', stdout.getvalue())
+
+ def testBadProperty(self):
+ image = Image('name', 'node', test=True)
+ image._entries = {'u-boot': 1}
+ with self.assertRaises(ValueError) as e:
+ image.LookupSymbol('_binman_u_boot_prop_bad', False, 'msg')
+ self.assertIn("msg: No such property 'bad", str(e.exception))
};
u-boot {
- pos = <12>;
+ pos = <20>;
};
};
};
binman {
sort-by-pos;
u-boot {
- pos = <10>;
+ pos = <22>;
};
u-boot-spl {
- pos = <5>;
+ pos = <1>;
};
};
};
binman {
sort-by-pos;
end-at-4gb;
- size = <16>;
+ size = <32>;
u-boot {
pos = <0>;
};
u-boot-spl {
- pos = <0xfffffff7>;
+ pos = <0xffffffeb>;
};
};
};
binman {
sort-by-pos;
end-at-4gb;
- size = <16>;
+ size = <32>;
u-boot {
- pos = <0xfffffff0>;
+ pos = <0xffffffe0>;
};
u-boot-spl {
- pos = <0xfffffff7>;
+ pos = <0xffffffeb>;
};
};
};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ u-boot-spl-dtb {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-spl-nodtb {
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+
+ u-boot {
+ pos = <20>;
+ };
+
+ u-boot-spl2 {
+ type = "u-boot-spl";
+ };
+ };
+};
CFLAGS := -march=i386 -m32 -nostdlib -I ../../../include
LDS_UCODE := -T u_boot_ucode_ptr.lds
+LDS_BINMAN := -T u_boot_binman_syms.lds
+LDS_BINMAN_BAD := -T u_boot_binman_syms_bad.lds
-TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data
+TARGETS = u_boot_ucode_ptr u_boot_no_ucode_ptr bss_data \
+ u_boot_binman_syms u_boot_binman_syms.bin u_boot_binman_syms_bad \
+ u_boot_binman_syms_size
all: $(TARGETS)
bss_data: CFLAGS += bss_data.lds
bss_data: bss_data.c
+u_boot_binman_syms.bin: u_boot_binman_syms
+ objcopy -O binary $< -R .note.gnu.build-id $@
+
+u_boot_binman_syms: CFLAGS += $(LDS_BINMAN)
+u_boot_binman_syms: u_boot_binman_syms.c
+
+u_boot_binman_syms_bad: CFLAGS += $(LDS_BINMAN_BAD)
+u_boot_binman_syms_bad: u_boot_binman_syms_bad.c
+
+u_boot_binman_syms_size: CFLAGS += $(LDS_BINMAN)
+u_boot_binman_syms_size: u_boot_binman_syms_size.c
+
clean:
rm -f $(TARGETS)
* SPDX-License-Identifier: GPL-2.0+
*
* Simple program to create a _dt_ucode_base_size symbol which can be read
- * by 'nm'. This is used by binman tests.
+ * by binutils. This is used by binman tests.
*/
int bss_data[10];
--- /dev/null
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create some binman symbols. This is used by binman tests.
+ */
+
+#define CONFIG_BINMAN
+#include <binman_sym.h>
+
+binman_sym_declare(unsigned long, u_boot_spl, pos);
+binman_sym_declare(unsigned long long, u_boot_spl2, pos);
+binman_sym_declare(unsigned long, u_boot_any, pos);
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
+}
--- /dev/null
+u_boot_binman_syms.c
\ No newline at end of file
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x00000000;
+ _start = .;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .binman_sym_table : {
+ __binman_sym_start = .;
+ KEEP(*(SORT(.binman_sym*)));
+ __binman_sym_end = .;
+ }
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Simple program to create some binman symbols. This is used by binman tests.
+ */
+
+#define CONFIG_BINMAN
+#include <binman_sym.h>
+
+binman_sym_declare(char, u_boot_spl, pos);
* SPDX-License-Identifier: GPL-2.0+
*
* Simple program to create a _dt_ucode_base_size symbol which can be read
- * by 'nm'. This is used by binman tests.
+ * by binutils. This is used by binman tests.
*/
static unsigned long _dt_ucode_base_size[2]
projects / u-boot / commitdiff