The following erratum :
"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"
only applies to mx51, so restrict its usage for this SoC only.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
int ipu_probe(void)
{
unsigned long ipu_base;
+#if defined CONFIG_MX51
u32 temp;
u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
+#endif
ipu_base = IPU_CTRL_BASE_ADDR;
ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);