/* SDHI CMD VALUE */
#define CMD_MASK 0x0000ffff
#define SDHI_APP 0x0040
+#define SDHI_MMC_SEND_OP_COND 0x0701
#define SDHI_SD_APP_SEND_SCR 0x0073
#define SDHI_SD_SWITCH 0x1C06
+#define SDHI_MMC_SEND_EXT_CSD 0x1C08
/* SDHI_PORTSEL */
#define USE_1PORT (1 << 8) /* 1 port */
#define CLK_ENABLE (1 << 8)
/* SDHI_OPTION */
-#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */
+#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */
+#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */
+#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */
+#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */
/* SDHI_ERR_STS1 */
#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
else /* SD_SWITCH */
opc = SDHI_SD_SWITCH;
break;
+ case MMC_CMD_SEND_OP_COND:
+ opc = SDHI_MMC_SEND_OP_COND;
+ break;
+ case MMC_CMD_SEND_EXT_CSD:
+ if (data)
+ opc = SDHI_MMC_SEND_EXT_CSD;
+ break;
default:
break;
}
case MMC_CMD_READ_SINGLE_BLOCK:
case SDHI_SD_APP_SEND_SCR:
case SDHI_SD_SWITCH: /* SD_SWITCH */
+ case SDHI_MMC_SEND_EXT_CSD:
ret = sh_sdhi_single_read(host, data);
break;
default:
if (ret)
return -EINVAL;
- if (mmc->bus_width == 4)
- sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 &
- sh_sdhi_readw(host, SDHI_OPTION));
+ if (mmc->bus_width == 8)
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
+ else if (mmc->bus_width == 4)
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
else
- sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 |
- sh_sdhi_readw(host, SDHI_OPTION));
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);