]> git.sur5r.net Git - u-boot/commitdiff
ARM: OMAP4+: Cleanup header files
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 30 May 2013 02:54:30 +0000 (02:54 +0000)
committerTom Rini <trini@ti.com>
Mon, 10 Jun 2013 12:43:09 +0000 (08:43 -0400)
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
13 files changed:
arch/arm/cpu/armv7/omap4/prcm-regs.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap4/clocks.h
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap5/clocks.h
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/omap_common.h
board/ti/omap5_uevm/evm.c
board/ti/panda/panda.c
board/ti/sdp4430/sdp.c
drivers/usb/musb/omap3.c

index 7225a301b1ef3335f934d2824aea952d0306de06..7e71ca0a264ffe0672b8a049b86658d1fc79f95e 100644 (file)
@@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
        .control_ldosram_iva_voltage_ctrl       = 0x4A002320,
        .control_ldosram_mpu_voltage_ctrl       = 0x4A002324,
        .control_ldosram_core_voltage_ctrl      = 0x4A002328,
+       .control_usbotghs_ctrl                  = 0x4A00233C,
+       .control_padconf_core_base              = 0x4A100000,
        .control_pbiaslite                      = 0x4A100600,
        .control_lpddr2io1_0                    = 0x4A100638,
        .control_lpddr2io1_1                    = 0x4A10063C,
@@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
        .control_lpddr2io2_3                    = 0x4A100654,
        .control_efuse_1                        = 0x4A100700,
        .control_efuse_2                        = 0x4A100704,
+       .control_padconf_wkup_base              = 0x4A31E000,
 };
index 501073902496b81895768ac1dc356c6eacba6fe6..f3b31551635d95cf23c8ec416b1e5cac0d9a8ec1 100644 (file)
@@ -313,6 +313,7 @@ struct prcm_regs const omap5_es1_prcm = {
 struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
        .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
+       .control_padconf_core_base              = 0x4A002800,
        .control_paconf_global                  = 0x4A002DA0,
        .control_paconf_mode                    = 0x4A002DA4,
        .control_smart1io_padconf_0             = 0x4A002DA8,
@@ -361,6 +362,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_emif1_sdram_config_ext         = 0x4AE0C144,
        .control_emif2_sdram_config_ext         = 0x4AE0C148,
        .control_wkup_ldovbb_mpu_voltage_ctrl   = 0x4AE0C318,
+       .control_padconf_wkup_base              = 0x4AE0C800,
        .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
        .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
        .control_padconf_mode                   = 0x4AE0CDA8,
index ed7a1c8be7a3282dcf2e32201e41d032bff4a73a..f544edfbd0afa3e3ace5055a8a1f744ece35d330 100644 (file)
  */
 #define LDELAY         1000000
 
-#define CM_CLKMODE_DPLL_CORE           0x4A004120
-#define CM_CLKMODE_DPLL_PER            0x4A008140
-#define CM_CLKMODE_DPLL_MPU            0x4A004160
-#define CM_CLKSEL_CORE                 0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL                0
-#define CM_IDLEST_DPLL         0x4
-#define CM_AUTOIDLE_DPLL       0x8
-#define CM_CLKSEL_DPLL         0xC
-#define CM_DIV_M2_DPLL         0x10
-#define CM_DIV_M3_DPLL         0x14
-#define CM_DIV_M4_DPLL         0x18
-#define CM_DIV_M5_DPLL         0x1C
-#define CM_DIV_M6_DPLL         0x20
-#define CM_DIV_M7_DPLL         0x24
-
-#define DPLL_CLKOUT_DIV_MASK   0x1F /* post-divider mask */
-
 /* CM_DLL_CTRL */
 #define CM_DLL_CTRL_OVERRIDE_SHIFT     0
 #define CM_DLL_CTRL_OVERRIDE_MASK      (1 << 0)
@@ -94,8 +75,6 @@
 #define CM_CLKSEL_DCC_EN_SHIFT                 22
 #define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
-#define OMAP4_DPLL_MAX_N       127
-
 /* CM_SYS_CLKSEL */
 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK   (1 << 25)
 
 /* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ     38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ      6
-#define OMAP_32K_CLK_FREQ              32768
 
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 
 #define ALTCLKSRC_MODE_ACTIVE          1
 
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0           0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ       1000
-
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
index 3a0bfbf0c612a052296756aecceb4af72ac4b956..311c6ff522ced4ad0ad9368e9bb9b1d106dd9d46 100644 (file)
@@ -115,18 +115,6 @@ struct watchdog {
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
-#define SYSCLKDIV_1            (0x1 << 6)
-#define SYSCLKDIV_2            (0x1 << 7)
-
-#define CLKSEL_GPT1            (0x1 << 0)
-
-#define EN_GPT1                        (0x1 << 0)
-#define EN_32KSYNC             (0x1 << 2)
-
-#define ST_WDT2                        (0x1 << 5)
-
-#define RESETDONE              (0x1 << 0)
-
 #define TCLR_ST                        (0x1 << 0)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
index 55a07605b81a13e91eead5e23363b76467d4b2bc..66afd924927a4bdcf8a1a3ed43d18b95b7c0e33b 100644 (file)
 #define DRAM_ADDR_SPACE_START  OMAP44XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP44XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE              (OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE   (OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP   (OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE    0x4A100638
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE                0x4A002204
 
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE     (OMAP44XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP44XX_GPMC_BASE     0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE      0x4A002000
-
 /*
  * Hardware Register Details
  */
index 68afa7669602300a16a317a150c33b103fa8b714..6673a025f5d58441fd4e960a8be0d61167eddbe8 100644 (file)
  */
 #define LDELAY         1000000
 
-#define CM_CLKMODE_DPLL_CORE           (OMAP54XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER            (OMAP54XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU            (OMAP54XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE                 (OMAP54XX_L4_CORE_BASE + 0x4100)
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL                0
-#define CM_IDLEST_DPLL         0x4
-#define CM_AUTOIDLE_DPLL       0x8
-#define CM_CLKSEL_DPLL         0xC
-
-#define DPLL_CLKOUT_DIV_MASK   0x1F /* post-divider mask */
-
 /* CM_DLL_CTRL */
 #define CM_DLL_CTRL_OVERRIDE_SHIFT             0
 #define CM_DLL_CTRL_OVERRIDE_MASK              (1 << 0)
@@ -93,8 +80,6 @@
 #define CM_CLKSEL_DCC_EN_SHIFT                 22
 #define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
-#define OMAP4_DPLL_MAX_N       127
-
 /* CM_SYS_CLKSEL */
 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 #define RSTTIME1_MASK                          (0x3ff << 0)
 
 /* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ     38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ      6
-#define OMAP_32K_CLK_FREQ              32768
 
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 #define TPS62361_BASE_VOLT_MV  500
 #define TPS62361_VSEL0_GPIO    7
 
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0           0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ       1000
-
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
index 044ab5581ad0a5dd3d1db89228701aaa83bafdc3..4753f4624ec499d1728859a71c7c8e43c26156a2 100644 (file)
@@ -119,18 +119,6 @@ struct watchdog {
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
-#define SYSCLKDIV_1            (0x1 << 6)
-#define SYSCLKDIV_2            (0x1 << 7)
-
-#define CLKSEL_GPT1            (0x1 << 0)
-
-#define EN_GPT1                        (0x1 << 0)
-#define EN_32KSYNC             (0x1 << 2)
-
-#define ST_WDT2                        (0x1 << 5)
-
-#define RESETDONE              (0x1 << 0)
-
 #define TCLR_ST                        (0x1 << 0)
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
index 1c1a64bd234e95a2b7393327da360d3c37dd2da1..4fcd99f9925e2eee15540a3d1852540328caef12 100644 (file)
 #define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE              (OMAP54XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE   (CTRL_BASE + 0x0800)
-#define CONTROL_PADCONF_WKUP   (OMAP54XX_L4_WKUP_BASE + 0xc800)
-
-/* LPDDR2 IO regs. To be verified */
-#define LPDDR2_IO_REGS_BASE    0x4A100638
-
 /* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE                (CTRL_BASE + 0x204)
+#define CONTROL_ID_CODE                0x4A002204
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0         0x0B94202F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
 
-/* STD_FUSE_PROD_ID_1 */
-#define STD_FUSE_PROD_ID_1             (CTRL_BASE + 0x218)
-#define PROD_ID_1_SILICON_TYPE_SHIFT   16
-#define PROD_ID_1_SILICON_TYPE_MASK    (3 << 16)
-
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE             (OMAP54XX_L4_PER_BASE + 0x6c000)
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP54XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE     (OMAP54XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP54XX_GPMC_BASE     0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE      0x4A002000
-
 /*
  * Hardware Register Details
  */
@@ -191,16 +172,6 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4031F000
 
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID    0xFFFFFFFF
-#define OMAP4430_ES1_0 0x44300100
-#define OMAP4430_ES2_0 0x44300200
-#define OMAP4430_ES2_1 0x44300210
-#define OMAP4430_ES2_2 0x44300220
-#define OMAP4430_ES2_3 0x44300230
-#define OMAP4460_ES1_0 0x44600100
-#define OMAP4460_ES1_1 0x44600110
-
 /* CONTROL_SRCOMP_XXX_SIDE */
 #define OVERRIDE_XS_SHIFT              30
 #define OVERRIDE_XS_MASK               (1 << 30)
index f8f3719bd6fe758ef1205dffbe68ad2f85dab773..712d78b0a6145141cdb8368a124f161f6d71f775 100644 (file)
@@ -367,6 +367,7 @@ struct omap_sys_ctrl_regs {
        u32 control_ldosram_iva_voltage_ctrl;
        u32 control_ldosram_mpu_voltage_ctrl;
        u32 control_ldosram_core_voltage_ctrl;
+       u32 control_usbotghs_ctrl;
        u32 control_padconf_core_base;
        u32 control_paconf_global;
        u32 control_paconf_mode;
@@ -555,9 +556,6 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
               u32 txdone, u32 txdone_mask, u32 opp);
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
-/* Max value for DPLL multiplier M */
-#define OMAP_DPLL_MAX_N        127
-
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL                  0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR       1
index 46db1bfe6640b4569d2789a6d5da2ab2a748ca19..90046e896e6c29cd30c81c929084e59214eef950 100644 (file)
@@ -71,22 +71,26 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_essential,
                   sizeof(core_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_essential,
                   sizeof(wkup_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 }
 
 void set_muxconf_regs_non_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_non_essential,
                   sizeof(core_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_non_essential,
                   sizeof(wkup_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 }
index 2bbe392d8113fd0b5dd459f988a24e84afd6fa3a..4335259e58a67ce4f346c2220b9a13c1f97aade3 100644 (file)
@@ -139,16 +139,18 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_essential,
                   sizeof(core_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_essential,
                   sizeof(wkup_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 
        if (omap_revision() >= OMAP4460_ES1_0)
-               do_set_mux(CONTROL_PADCONF_WKUP,
+               do_set_mux((*ctrl)->control_padconf_wkup_base,
                                 wkup_padconf_array_essential_4460,
                                 sizeof(wkup_padconf_array_essential_4460) /
                                 sizeof(struct pad_conf_entry));
@@ -156,27 +158,29 @@ void set_muxconf_regs_essential(void)
 
 void set_muxconf_regs_non_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_non_essential,
                   sizeof(core_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 
        if (omap_revision() < OMAP4460_ES1_0)
-               do_set_mux(CONTROL_PADCONF_CORE,
+               do_set_mux((*ctrl)->control_padconf_core_base,
                                core_padconf_array_non_essential_4430,
                                sizeof(core_padconf_array_non_essential_4430) /
                                sizeof(struct pad_conf_entry));
        else
-               do_set_mux(CONTROL_PADCONF_CORE,
+               do_set_mux((*ctrl)->control_padconf_core_base,
                                core_padconf_array_non_essential_4460,
                                sizeof(core_padconf_array_non_essential_4460) /
                                sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_non_essential,
                   sizeof(wkup_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 
        if (omap_revision() < OMAP4460_ES1_0)
-               do_set_mux(CONTROL_PADCONF_WKUP,
+               do_set_mux((*ctrl)->control_padconf_wkup_base,
                                wkup_padconf_array_non_essential_4430,
                                sizeof(wkup_padconf_array_non_essential_4430) /
                                sizeof(struct pad_conf_entry));
index 4c1a4f7e78625b83b8ab7f79de6865f644a331e0..5dd1ba3cb43739e3c196f899474a3692bc6ed034 100644 (file)
@@ -72,16 +72,18 @@ int misc_init_r(void)
 
 void set_muxconf_regs_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_essential,
                   sizeof(core_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_essential,
                   sizeof(wkup_padconf_array_essential) /
                   sizeof(struct pad_conf_entry));
 
        if (omap_revision() >= OMAP4460_ES1_0)
-               do_set_mux(CONTROL_PADCONF_WKUP,
+               do_set_mux((*ctrl)->control_padconf_wkup_base,
                                 wkup_padconf_array_essential_4460,
                                 sizeof(wkup_padconf_array_essential_4460) /
                                 sizeof(struct pad_conf_entry));
@@ -89,16 +91,18 @@ void set_muxconf_regs_essential(void)
 
 void set_muxconf_regs_non_essential(void)
 {
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_core_base,
+                  core_padconf_array_non_essential,
                   sizeof(core_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+       do_set_mux((*ctrl)->control_padconf_wkup_base,
+                  wkup_padconf_array_non_essential,
                   sizeof(wkup_padconf_array_non_essential) /
                   sizeof(struct pad_conf_entry));
 
        if (omap_revision() < OMAP4460_ES1_0) {
-               do_set_mux(CONTROL_PADCONF_WKUP,
+               do_set_mux((*ctrl)->control_padconf_wkup_base,
                        wkup_padconf_array_non_essential_4430,
                        sizeof(wkup_padconf_array_non_essential_4430) /
                        sizeof(struct pad_conf_entry));
index c7876ed094b1a8bd02eb552babea20db4fe61487..a395ebcc67e9685a138f8e6b3e1937b891db29a3 100644 (file)
@@ -30,6 +30,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/omap_common.h>
 #include <twl4030.h>
 #include <twl6030.h>
 #include "omap3.h"
@@ -135,7 +136,8 @@ int musb_platform_init(void)
 #endif
 
 #ifdef CONFIG_OMAP4430
-               u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C);
+               u32 *usbotghs_control =
+                       (u32 *)((*ctrl)->control_usbotghs_ctrl);
                *usbotghs_control = 0x15;
 #endif
                platform_needs_initialization = 0;