--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V5.00\r
+ * @date 02. March 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * http://www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
+\r
+\r
+#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ uint32_t result;\r
+\r
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* The MPU version of port.c includes and excludes functions depending on the\r
+settings within this file. Therefore, to ensure all the functions in port.c\r
+build, this configuration file has all options turned on. */\r
+ \r
+#define configUSE_PREEMPTION 1\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ 48000000\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 5\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 1\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 2\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#define portGET_RUN_TIME_COUNTER_VALUE()\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 1\r
+#define INCLUDE_xTaskGetHandle 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle 1\r
+#define INCLUDE_xTaskAbortDelay 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_xTaskGetIdleTaskHandle 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 7 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* LED not used at present, so just increment a variable to keep a count of the\r
+number of times the LED would otherwise have been toggled. */\r
+#define configTOGGLE_LED() ulLED++\r
+\r
+/* Definitions for the messages that can be sent to the check task. */\r
+#define configREG_TEST_1_STILL_EXECUTING ( 0 )\r
+#define configREG_TEST_2_STILL_EXECUTING ( 1 )\r
+#define configTIMER_STILL_EXECUTING ( 2 )\r
+#define configPRINT_SYSTEM_STATUS ( 3 )\r
+\r
+/* Parameters that are passed into the third and fourth register check tasks\r
+solely for the purpose of ensuring parameters are passed into tasks correctly. */\r
+#define configREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x11112222 )\r
+#define configREG_TEST_TASK_3_PARAMETER ( ( void * ) 0x12345678 )\r
+#define configREG_TEST_TASK_4_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">\r
+\r
+ <SchemaVersion>1.0</SchemaVersion>\r
+\r
+ <Header>### uVision Project, (C) Keil Software</Header>\r
+\r
+ <Extensions>\r
+ <cExt>*.c;*.S</cExt>\r
+ <aExt></aExt>\r
+ <oExt>*.obj</oExt>\r
+ <lExt>*.lib</lExt>\r
+ <tExt>*.txt; *.h; *.inc</tExt>\r
+ <pExt>*.plm</pExt>\r
+ <CppX>*.cpp</CppX>\r
+ <nMigrate>0</nMigrate>\r
+ </Extensions>\r
+\r
+ <DaveTm>\r
+ <dwLowDateTime>0</dwLowDateTime>\r
+ <dwHighDateTime>0</dwHighDateTime>\r
+ </DaveTm>\r
+\r
+ <Target>\r
+ <TargetName>RTOSDemo_GCC_MPU</TargetName>\r
+ <ToolsetNumber>0x3</ToolsetNumber>\r
+ <ToolsetName>ARM-GNU</ToolsetName>\r
+ <TargetOption>\r
+ <CLKARM>12000000</CLKARM>\r
+ <OPTTT>\r
+ <gFlags>1</gFlags>\r
+ <BeepAtEnd>1</BeepAtEnd>\r
+ <RunSim>0</RunSim>\r
+ <RunTarget>1</RunTarget>\r
+ <RunAbUc>0</RunAbUc>\r
+ </OPTTT>\r
+ <OPTHX>\r
+ <HexSelection>1</HexSelection>\r
+ <FlashByte>65535</FlashByte>\r
+ <HexRangeLowAddress>0</HexRangeLowAddress>\r
+ <HexRangeHighAddress>0</HexRangeHighAddress>\r
+ <HexOffset>0</HexOffset>\r
+ </OPTHX>\r
+ <OPTLEX>\r
+ <PageWidth>120</PageWidth>\r
+ <PageLength>65</PageLength>\r
+ <TabStop>8</TabStop>\r
+ <ListingPath>.\Listings\</ListingPath>\r
+ </OPTLEX>\r
+ <ListingPage>\r
+ <CreateCListing>1</CreateCListing>\r
+ <CreateAListing>1</CreateAListing>\r
+ <CreateLListing>1</CreateLListing>\r
+ <CreateIListing>0</CreateIListing>\r
+ <AsmCond>1</AsmCond>\r
+ <AsmSymb>1</AsmSymb>\r
+ <AsmXref>0</AsmXref>\r
+ <CCond>1</CCond>\r
+ <CCode>0</CCode>\r
+ <CListInc>0</CListInc>\r
+ <CSymb>0</CSymb>\r
+ <LinkerCodeListing>0</LinkerCodeListing>\r
+ </ListingPage>\r
+ <OPTXL>\r
+ <LMap>1</LMap>\r
+ <LComments>1</LComments>\r
+ <LGenerateSymbols>1</LGenerateSymbols>\r
+ <LLibSym>1</LLibSym>\r
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+ <LPubSym>1</LPubSym>\r
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+ <LExpSel>0</LExpSel>\r
+ </OPTXL>\r
+ <OPTFL>\r
+ <tvExp>1</tvExp>\r
+ <tvExpOptDlg>0</tvExpOptDlg>\r
+ <IsCurrentTarget>1</IsCurrentTarget>\r
+ </OPTFL>\r
+ <CpuCode>7</CpuCode>\r
+ <DebugOpt>\r
+ <uSim>0</uSim>\r
+ <uTrg>1</uTrg>\r
+ <sLdApp>1</sLdApp>\r
+ <sGomain>1</sGomain>\r
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+ <sRunDeb>0</sRunDeb>\r
+ <sLrtime>0</sLrtime>\r
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+ <sDll></sDll>\r
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+ <sDlgDll></sDlgDll>\r
+ <sDlgPa></sDlgPa>\r
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+ <tDll></tDll>\r
+ <tDllPa></tDllPa>\r
+ <tDlgDll></tDlgDll>\r
+ <tDlgPa></tDlgPa>\r
+ <tIfile>init_app.ini</tIfile>\r
+ <pMon>BIN\UL2CM3.DLL</pMon>\r
+ </DebugOpt>\r
+ <TargetDriverDllRegistry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>JL2CM3</Key>\r
+ <Name>-U59101789 -O3047 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8006 -TDT0 -TDC1F -TIE1 -TIP8 -TB1 -TFE0 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>DLGDARM</Key>\r
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>ARMRTXEVENTFLAGS</Key>\r
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>DLGTARM</Key>\r
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=1377,131,1842,431,0)</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>ARMDBGFLAGS</Key>\r
+ <Name>-T0</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>DLGUARM</Key>\r
+ <Name>(105=-1,-1,-1,-1,0)</Name>\r
+ </SetRegEntry>\r
+ <SetRegEntry>\r
+ <Number>0</Number>\r
+ <Key>UL2CM3</Key>\r
+ <Name>-UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>\r
+ </SetRegEntry>\r
+ </TargetDriverDllRegistry>\r
+ <Breakpoint>\r
+ <Bp>\r
+ <Number>0</Number>\r
+ <Type>0</Type>\r
+ <LineNumber>2428</LineNumber>\r
+ <EnabledFlag>1</EnabledFlag>\r
+ <Address>926184</Address>\r
+ <ByteObject>0</ByteObject>\r
+ <HtxType>0</HtxType>\r
+ <ManyObjects>0</ManyObjects>\r
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+ <BreakIfRCount>1</BreakIfRCount>\r
+ <Filename>C:\E\Dev\FreeRTOS\Trial\Active\Microchip_CEC1302\WorkingCopy\Source\tasks.c</Filename>\r
+ <ExecCommand></ExecCommand>\r
+ <Expression>\\RTOSDemo\../../../Source/tasks.c\2428</Expression>\r
+ </Bp>\r
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+ <ExecCommand></ExecCommand>\r
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+ </Bp>\r
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+ <ExecCommand></ExecCommand>\r
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+ </Bp>\r
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+ <ExecCommand></ExecCommand>\r
+ <Expression>\\RTOSDemo\../main.c\916</Expression>\r
+ </Bp>\r
+ </Breakpoint>\r
+ <WatchWindow1>\r
+ <Ww>\r
+ <count>0</count>\r
+ <WinNumber>1</WinNumber>\r
+ <ItemText>xTickCount</ItemText>\r
+ </Ww>\r
+ <Ww>\r
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+ <ItemText>pxCurrentTCB</ItemText>\r
+ </Ww>\r
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+ <ItemText>*pcString</ItemText>\r
+ </Ww>\r
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+ </Ww>\r
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+ <ItemText>xSchedulerRunning</ItemText>\r
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+ </MemoryWindow1>\r
+ <Tracepoint>\r
+ <THDelay>0</THDelay>\r
+ </Tracepoint>\r
+ <DebugFlag>\r
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+ </DebugFlag>\r
+ <LintExecutable></LintExecutable>\r
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+ <Enable>1</Enable>\r
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+ <DbgClock>10000000</DbgClock>\r
+ </DebugDescription>\r
+ </TargetOption>\r
+ </Target>\r
+\r
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--- /dev/null
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+ <Header>### uVision Project, (C) Keil Software</Header>\r
+\r
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+ <FileName>btimer_api.c</FileName>\r
+ <FileType>1</FileType>\r
+ <FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>\r
+ </File>\r
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+ <FilePath>..\peripheral_library\system_internal.c</FilePath>\r
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+ </Files>\r
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+ </Groups>\r
+ </Target>\r
+ </Targets>\r
+\r
+</Project>\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+\r
+/*\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ */\r
+\r
+void vRegTest1Implementation( void *pvParameters );\r
+void vRegTest2Implementation( void *pvParameters );\r
+void vRegTest3Implementation( void ) __attribute__ ((naked));\r
+void vRegTest4Implementation( void ) __attribute__ ((naked));\r
+\r
+/*\r
+ * Used as an easy way of deleting a task from inline assembly.\r
+ */\r
+extern void vMainDeleteMe( void ) __attribute__((noinline));\r
+\r
+/*\r
+ * Used by the first two reg test tasks and a software timer callback function\r
+ * to send messages to the check task. The message just lets the check task\r
+ * know that the tasks and timer are still functioning correctly. If a reg test\r
+ * task detects an error it will delete itself, and in so doing prevent itself\r
+ * from sending any more 'I'm Alive' messages to the check task.\r
+ */\r
+extern void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber );\r
+\r
+/* The queue used to send a message to the check task. */\r
+extern QueueHandle_t xGlobalScopeCheckQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest1Implementation( void *pvParameters )\r
+{\r
+/* This task is created in privileged mode so can access the file scope\r
+queue variable. Take a stack copy of this before the task is set into user\r
+mode. Once this task is in user mode the file scope queue variable will no\r
+longer be accessible but the stack copy will. */\r
+QueueHandle_t xQueue = xGlobalScopeCheckQueue;\r
+\r
+ /* Now the queue handle has been obtained the task can switch to user\r
+ mode. This is just one method of passing a handle into a protected\r
+ task, the other reg test task uses the task parameter instead. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* First check that the parameter value is as expected. */\r
+ if( pvParameters != ( void * ) configREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Error detected. Delete the task so it stops communicating with\r
+ the check task. */\r
+ vMainDeleteMe();\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile\r
+ (\r
+ " MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #105 \n"\r
+ " MOV R6, #106 \n"\r
+ " MOV R8, #108 \n"\r
+ " MOV R9, #109 \n"\r
+ " MOV R10, #110 \n"\r
+ " MOV R11, #111 \n"\r
+ "reg1loop: \n"\r
+ " MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #101 \n"\r
+ " MOV R2, #102 \n"\r
+ " MOV R3, #103 \n"\r
+ " MOV R12, #112 \n"\r
+ " SVC #1 \n" /* Yield just to increase test coverage. */\r
+ " CMP R0, #100 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */\r
+ " CMP R1, #101 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R2, #102 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R3, #103 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R4, #104 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R5, #105 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R6, #106 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R8, #108 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R9, #109 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R10, #110 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R11, #111 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R12, #112 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"\r
+ );\r
+\r
+ /* Send configREG_TEST_1_STILL_EXECUTING to the check task to indicate that this\r
+ task is still functioning. */\r
+ vMainSendImAlive( xQueue, configREG_TEST_1_STILL_EXECUTING );\r
+\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg1loop " );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Implementation( void *pvParameters )\r
+{\r
+/* The queue handle is passed in as the task parameter. This is one method of\r
+passing data into a protected task, the other reg test task uses a different\r
+method. */\r
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile\r
+ (\r
+ " MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #5 \n"\r
+ " MOV R6, #6 \n"\r
+ " MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */\r
+ " MOV R9, #9 \n"\r
+ " MOV R10, 10 \n"\r
+ " MOV R11, #11 \n"\r
+ "reg2loop: \n"\r
+ " MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #1 \n"\r
+ " MOV R2, #2 \n"\r
+ " MOV R3, #3 \n"\r
+ " MOV R12, #12 \n"\r
+ " CMP R0, #13 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */\r
+ " CMP R1, #1 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R2, #2 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R3, #3 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R4, #4 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R5, #5 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R6, #6 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R8, #8 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R9, #9 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R10, #10 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R11, #11 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R12, #12 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"\r
+ );\r
+\r
+ /* Send configREG_TEST_2_STILL_EXECUTING to the check task to indicate that this\r
+ task is still functioning. */\r
+ vMainSendImAlive( xQueue, configREG_TEST_2_STILL_EXECUTING );\r
+\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg2loop " );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest3Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern pulRegTest3LoopCounter \n"\r
+ "/* Fill the core registers with known values. */ \n"\r
+ "mov r0, #100 \n"\r
+ "mov r1, #101 \n"\r
+ "mov r2, #102 \n"\r
+ "mov r3, #103 \n"\r
+ "mov r4, #104 \n"\r
+ "mov r5, #105 \n"\r
+ "mov r6, #106 \n"\r
+ "mov r7, #107 \n"\r
+ "mov r8, #108 \n"\r
+ "mov r9, #109 \n"\r
+ "mov r10, #110 \n"\r
+ "mov r11, #111 \n"\r
+ "mov r12, #112 \n"\r
+\r
+ "/* Fill the VFP registers with known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg1_loop: \n"\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg1_loopf_pass \n"\r
+\r
+ "reg1_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be incorrect. */ \n"\r
+ "b reg1_error_loopf \n"\r
+\r
+ "reg1_loopf_pass: \n"\r
+\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r2, #102 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r3, #103 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r4, #104 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r5, #105 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r6, #106 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r7, #107 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r8, #108 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r9, #109 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r10, #110 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r11, #111 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r12, #112 \n"\r
+ "bne reg1_error_loop \n"\r
+\r
+ "/* Everything passed, increment the loop counter. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =pulRegTest3LoopCounter \n"\r
+ "ldr r0, [r0] \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg1_loop \n"\r
+\r
+ "reg1_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "The loop ensures the loop counter stops incrementing. */ \n"\r
+ "b reg1_error_loop \n"\r
+ "nop "\r
+ ); /* __asm volatile. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest4Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern pulRegTest4LoopCounter \n"\r
+ "/* Set all the core registers to known values. */ \n"\r
+ "mov r0, #-1 \n"\r
+ "mov r1, #1 \n"\r
+ "mov r2, #2 \n"\r
+ "mov r3, #3 \n"\r
+ "mov r4, #4 \n"\r
+ "mov r5, #5 \n"\r
+ "mov r6, #6 \n"\r
+ "mov r7, #7 \n"\r
+ "mov r8, #8 \n"\r
+ "mov r9, #9 \n"\r
+ "mov r10, #10 \n"\r
+ "mov r11, #11 \n"\r
+ "mov r12, #12 \n"\r
+\r
+ "/* Set all the VFP to known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg2_loop: \n"\r
+\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg2_loopf_pass \n"\r
+\r
+ "reg2_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be \n"\r
+ "incorrect. */ \n"\r
+ "b reg2_error_loopf \n"\r
+\r
+ "reg2_loopf_pass: \n"\r
+\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r2, #2 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r3, #3 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r4, #4 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r5, #5 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r6, #6 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r7, #7 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r8, #8 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r9, #9 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r10, #10 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r11, #11 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r12, #12 \n"\r
+ "bne reg2_error_loop \n"\r
+\r
+ "/* Increment the loop counter so the check task knows this task is \n"\r
+ "still running. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =pulRegTest4LoopCounter \n"\r
+ "ldr r0, [r0] \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Yield to increase test coverage. */ \n"\r
+ "SVC #1 \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg2_loop \n"\r
+\r
+ "reg2_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "This loop ensures the loop counter variable stops incrementing. */ \n"\r
+ "b reg2_error_loop \n"\r
+ ); /* __asm volatile */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Fault handlers are here for convenience as they use compiler specific syntax\r
+and this file is specific to the GCC compiler. */\r
+void hard_fault_handler( uint32_t * hardfault_args )\r
+{\r
+volatile uint32_t stacked_r0;\r
+volatile uint32_t stacked_r1;\r
+volatile uint32_t stacked_r2;\r
+volatile uint32_t stacked_r3;\r
+volatile uint32_t stacked_r12;\r
+volatile uint32_t stacked_lr;\r
+volatile uint32_t stacked_pc;\r
+volatile uint32_t stacked_psr;\r
+\r
+ stacked_r0 = ((uint32_t) hardfault_args[ 0 ]);\r
+ stacked_r1 = ((uint32_t) hardfault_args[ 1 ]);\r
+ stacked_r2 = ((uint32_t) hardfault_args[ 2 ]);\r
+ stacked_r3 = ((uint32_t) hardfault_args[ 3 ]);\r
+\r
+ stacked_r12 = ((uint32_t) hardfault_args[ 4 ]);\r
+ stacked_lr = ((uint32_t) hardfault_args[ 5 ]);\r
+ stacked_pc = ((uint32_t) hardfault_args[ 6 ]);\r
+ stacked_psr = ((uint32_t) hardfault_args[ 7 ]);\r
+\r
+ /* Inspect stacked_pc to locate the offending instruction. */\r
+ for( ;; );\r
+\r
+ ( void ) stacked_psr;\r
+ ( void ) stacked_pc;\r
+ ( void ) stacked_lr;\r
+ ( void ) stacked_r12;\r
+ ( void ) stacked_r0;\r
+ ( void ) stacked_r1;\r
+ ( void ) stacked_r2;\r
+ ( void ) stacked_r3;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void HardFault_Handler( void ) __attribute__((naked));\r
+void HardFault_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, [r0, #24] \n"\r
+ " ldr r2, handler_address_const \n"\r
+ " bx r2 \n"\r
+ " handler_address_const: .word hard_fault_handler \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void ) __attribute__((naked));\r
+void MemManage_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, [r0, #24] \n"\r
+ " ldr r2, handler2_address_const \n"\r
+ " bx r2 \n"\r
+ " handler2_address_const: .word hard_fault_handler \n"\r
+ );\r
+}/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+//Initialization file for the application code\r
+RESET\r
+T\r
+T\r
+T\r
+//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine\r
+eval PC = Reset_Handler;\r
+T\r
--- /dev/null
+//Initialization file for the application code\r
+//RESET\r
+//T\r
+//T\r
+//T\r
+//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine\r
+MAP 0xE0000, 0x118000 Read // map ROM\r
+MAP 0x118000, 0x120000 Read WRITE // map RAM\r
+eval PC = Reset_Handler;\r
+//T\r
--- /dev/null
+/*\r
+ * Memory Spaces Definitions.\r
+ *\r
+ * Need modifying for a specific board.\r
+ * FLASH.ORIGIN: starting address of flash\r
+ * FLASH.LENGTH: length of flash\r
+ * RAM.ORIGIN: starting address of RAM bank 0\r
+ * RAM.LENGTH: length of RAM bank 0\r
+ *\r
+ * The values below can be addressed in further linker scripts\r
+ * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\r
+ */\r
+\r
+MEMORY\r
+{\r
+ /* Due to restrictions in the MPU, the size of memory regions must be a power\r
+ of two, and start on a boundary equal to their size. */\r
+ ROM (rx) : ORIGIN = 0xE0000, LENGTH = 0x20000\r
+ RAM (rw) : ORIGIN = 0x100000, LENGTH = 0x20000\r
+}\r
+\r
+/* Variables used by FreeRTOS-MPU. */\r
+_Privileged_Functions_Region_Size = 32K;\r
+_Privileged_Data_Region_Size = 512;\r
+\r
+__FLASH_segment_start__ = ORIGIN( ROM );\r
+__FLASH_segment_end__ = __FLASH_segment_start__ + LENGTH( ROM );\r
+\r
+__privileged_functions_start__ = ORIGIN( ROM );\r
+__privileged_functions_end__ = __privileged_functions_start__ + _Privileged_Functions_Region_Size;\r
+\r
+__SRAM_segment_start__ = ORIGIN( RAM );\r
+__SRAM_segment_end__ = __SRAM_segment_start__ + LENGTH( RAM );\r
+\r
+__privileged_data_start__ = ORIGIN( RAM );\r
+__privileged_data_end__ = ORIGIN( RAM ) + _Privileged_Data_Region_Size;\r
+\r
+\r
+/*\r
+ * The '__stack' definition is required by crt0, do not remove it.\r
+ */\r
+__stack = ORIGIN(RAM) + LENGTH(RAM);\r
+_estack = __stack;\r
+\r
+/*\r
+ * Default stack sizes.\r
+ * These are used by the startup in order to allocate stacks\r
+ * for the different modes.\r
+ */\r
+\r
+__Main_Stack_Size = 2048 ;\r
+\r
+PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;\r
+\r
+__Main_Stack_Limit = __stack - __Main_Stack_Size ;\r
+\r
+/*"PROVIDE" allows to easily override these values from an object file or the command line. */\r
+PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;\r
+\r
+/*\r
+ * There will be a link error if there is not this amount of\r
+ * RAM free at the end.\r
+ */\r
+_Minimum_Stack_Size = 1024 ;\r
+\r
+/*\r
+ * Default heap definitions.\r
+ * The heap start immediately after the last statically allocated\r
+ * .sbss/.noinit section, and extends up to the main stack limit.\r
+ */\r
+PROVIDE ( _Heap_Begin = _end_noinit ) ;\r
+PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;\r
+\r
+/*\r
+ * The entry point is informative, for debuggers and simulators,\r
+ * since the Cortex-M vector points to it anyway.\r
+ */\r
+ENTRY(_start)\r
+\r
+/* Sections Definitions */\r
+\r
+SECTIONS\r
+{\r
+ /*\r
+ * For Cortex-M devices, the beginning of the startup code is stored in\r
+ * the .isr_vector section, which goes to ROM\r
+ */\r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ _isr_vector = .;\r
+ KEEP(*(.isr_vector))\r
+ } >ROM\r
+\r
+ privileged_functions :\r
+ {\r
+ . = ALIGN(4);\r
+ *(privileged_functions)\r
+ \r
+ /* Non privileged code is after _Privileged_Functions_Region_Size. */\r
+ __privileged_functions_actual_end__ = .;\r
+ . = _Privileged_Functions_Region_Size;\r
+ } > ROM\r
+\r
+\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+\r
+\r
+ /*\r
+ * This section is here for convenience, to store the\r
+ * startup code at the beginning of the flash area, hoping that\r
+ * this will increase the readability of the listing.\r
+ */\r
+ KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * These are the old initialisation sections, intended to contain\r
+ * naked code, with the prologue/epilogue added by crti.o/crtn.o\r
+ * when linking with startup files. The standalone startup code\r
+ * currently does not run these, better use the init arrays below.\r
+ */\r
+ KEEP(*(.init))\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The preinit code, i.e. an array of pointers to initialisation\r
+ * functions to be performed before constructors.\r
+ */\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+\r
+ /*\r
+ * Used to run the SystemInit() before anything else.\r
+ */\r
+ KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\r
+\r
+ /*\r
+ * Used for other platform inits.\r
+ */\r
+ KEEP(*(.preinit_array_platform .preinit_array_platform.*))\r
+\r
+ /*\r
+ * The application inits. If you need to enforce some order in\r
+ * execution, create new sections, as before.\r
+ */\r
+ KEEP(*(.preinit_array .preinit_array.*))\r
+\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The init code, i.e. an array of pointers to static constructors.\r
+ */\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP(*(SORT(.init_array.*)))\r
+ KEEP(*(.init_array))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The fini code, i.e. an array of pointers to static destructors.\r
+ */\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP(*(SORT(.fini_array.*)))\r
+ KEEP(*(.fini_array))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+ . = ALIGN(4);\r
+\r
+ . = ALIGN(4);\r
+\r
+ *(.text*) /* all remaining code */\r
+\r
+ *(vtable) /* C++ virtual tables */\r
+\r
+ } >ROM\r
+\r
+ .rodata :\r
+ {\r
+ *(.rodata*) /* read-only data (constants) */\r
+ } >ROM\r
+\r
+ .glue :\r
+ {\r
+ KEEP(*(.eh_frame*))\r
+\r
+ /*\r
+ * Stub sections generated by the linker, to glue together\r
+ * ARM and Thumb code. .glue_7 is used for ARM code calling\r
+ * Thumb code, and .glue_7t is used for Thumb code calling\r
+ * ARM code. Apparently always generated by the linker, for some\r
+ * architectures, so better leave them here.\r
+ */\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >ROM\r
+\r
+ /* ARM magic sections */\r
+ .ARM.extab :\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > ROM\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > ROM\r
+ __exidx_end = .;\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+ __etext = .;\r
+\r
+ /*\r
+ * This address is used by the startup code to\r
+ * initialise the .data section.\r
+ */\r
+ _sidata = _etext;\r
+\r
+ /* MEMORY_ARRAY */\r
+ /*\r
+ .ROarraySection :\r
+ {\r
+ *(.ROarraySection .ROarraySection.*)\r
+ } >MEMORY_ARRAY\r
+ */\r
+\r
+\r
+ privileged_data :\r
+ {\r
+ *(privileged_data)\r
+ /* Non kernel data is kept out of the first _Privileged_Data_Region_Size\r
+ bytes of SRAM. */\r
+ __privileged_data_actual_end__ = .;\r
+ . = _Privileged_Data_Region_Size;\r
+ } > RAM\r
+\r
+ /*\r
+ * The initialised data section.\r
+ * The program executes knowing that the data is in the RAM\r
+ * but the loader puts the initial values in the ROM (inidata).\r
+ * It is one task of the startup to copy the initial values from\r
+ * ROM to RAM.\r
+ */\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
+\r
+ /* This is used by the startup code to initialise the .data section */\r
+ _sdata = . ; /* STM specific definition */\r
+ __data_start__ = . ;\r
+ *(.data_begin .data_begin.*)\r
+\r
+ *(.data .data.*)\r
+\r
+ *(.data_end .data_end.*)\r
+ . = ALIGN(4);\r
+\r
+ /* This is used by the startup code to initialise the .data section */\r
+ _edata = . ; /* STM specific definition */\r
+ __data_end__ = . ;\r
+\r
+ } >RAM\r
+\r
+\r
+ /*\r
+ * The uninitialised data section. NOLOAD is used to avoid\r
+ * the "section `.bss' type changed to PROGBITS" warning\r
+ */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ __bss_start__ = .; /* standard newlib definition */\r
+ _sbss = .; /* STM specific definition */\r
+ *(.bss_begin .bss_begin.*)\r
+\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+\r
+ *(.bss_end .bss_end.*)\r
+ . = ALIGN(4);\r
+ __bss_end__ = .; /* standard newlib definition */\r
+ _ebss = . ; /* STM specific definition */\r
+ } >RAM\r
+\r
+ .noinit (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _noinit = .;\r
+\r
+ *(.noinit .noinit.*)\r
+\r
+ . = ALIGN(4) ;\r
+ _end_noinit = .;\r
+ } > RAM\r
+\r
+ /* Mandatory to be word aligned, _sbrk assumes this */\r
+ PROVIDE ( end = _end_noinit ); /* was _ebss */\r
+ PROVIDE ( _end = _end_noinit );\r
+ PROVIDE ( __end = _end_noinit );\r
+ PROVIDE ( __end__ = _end_noinit );\r
+ PROVIDE ( ROM_DATA_START = __data_start__ );\r
+\r
+ /*\r
+ * Used for validation only, do not allocate anything here!\r
+ *\r
+ * This is just to check that there is enough RAM left for the Main\r
+ * stack. It should generate an error if it's full.\r
+ */\r
+ ._check_stack :\r
+ {\r
+ . = ALIGN(4);\r
+\r
+ . = . + _Minimum_Stack_Size ;\r
+\r
+ . = ALIGN(4);\r
+ } >RAM\r
+\r
+ /* After that there are only debugging sections. */\r
+\r
+ /* This can remove the debugging information from the standard libraries */\r
+ /*\r
+ DISCARD :\r
+ {\r
+ libc.a ( * )\r
+ libm.a ( * )\r
+ libgcc.a ( * )\r
+ }\r
+ */\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /*\r
+ * DWARF debug sections.\r
+ * Symbols in the DWARF debugging sections are relative to the beginning\r
+ * of the section so we begin them at 0.\r
+ */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+/* File: startup_ARMCM4.S\r
+ * Purpose: startup file for Cortex-M4 devices. Should use with\r
+ * GCC for ARM Embedded Processors\r
+ * Version: V2.0\r
+ * Date: 16 August 2013\r
+ *\r
+/* Copyright (c) 2011 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+ .syntax unified\r
+ .arch armv7e-m\r
+\r
+ .extern __SRAM_segment_end__\r
+\r
+ .section .isr_vector,"a",%progbits\r
+ .align 4\r
+ .globl __isr_vector\r
+ .global __Vectors\r
+\r
+__Vectors:\r
+__isr_vector:\r
+ .long __SRAM_segment_end__ - 4 /* Top of Stack at top of RAM*/\r
+ .long Reset_Handler /* Reset Handler */\r
+ .long NMI_Handler /* NMI Handler */\r
+ .long HardFault_Handler /* Hard Fault Handler */\r
+ .long MemManage_Handler /* MPU Fault Handler */\r
+ .long BusFault_Handler /* Bus Fault Handler */\r
+ .long UsageFault_Handler /* Usage Fault Handler */\r
+ .long 0 /* Reserved */\r
+ .long 0 /* Reserved */\r
+ .long 0 /* Reserved */\r
+ .long 0 /* Reserved */\r
+ .long SVC_Handler /* SVCall Handler */\r
+ .long DebugMon_Handler /* Debug Monitor Handler */\r
+ .long 0 /* Reserved */\r
+ .long PendSV_Handler /* PendSV Handler */\r
+ .long SysTick_Handler /* SysTick Handler */\r
+\r
+ /* External interrupts */\r
+ .long NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08\r
+ .long NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09\r
+ .long NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10\r
+ .long NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11\r
+ .long NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12\r
+ .long NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13\r
+ .long NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14\r
+ .long NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15\r
+ .long NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16\r
+ .long NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17\r
+ .long NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18\r
+ .long NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19\r
+ .long NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20\r
+ .long NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21\r
+ .long NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23\r
+ .long NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24\r
+ .long NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25\r
+ .long NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26\r
+ .long 0 // 88h: 18, RSVD\r
+ .long 0 // 8Ch: 19, RSVD\r
+ .long NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0\r
+ .long NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1\r
+ .long NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2\r
+ .long NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3\r
+ .long NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0\r
+ .long NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1\r
+ .long NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2\r
+ .long NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3\r
+ .long NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4\r
+ .long NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5\r
+ .long NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6\r
+ .long NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7\r
+ .long NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8\r
+ .long NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9\r
+ .long NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10\r
+ .long NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11\r
+ .long NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12\r
+ .long NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13\r
+ .long 0 // D8h: 38, Unused\r
+ .long 0 // DCh: 39, Unused\r
+ .long NVIC_Handler_UART0 // E0h: 40, UART0\r
+ .long NVIC_Handler_UART1 // E4h: 41, UART1\r
+ .long NVIC_Handler_EMI0 // E8h: 42, EMI0\r
+ .long NVIC_Handler_EMI1 // ECh: 43, EMI0\r
+ .long NVIC_Handler_EMI2 // F0h: 44, EMI0\r
+ .long NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF\r
+ .long NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF\r
+ .long NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF\r
+ .long NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF\r
+ .long NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF\r
+ .long NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF\r
+ .long NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF\r
+ .long NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF\r
+ .long NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF\r
+ .long NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF\r
+ .long NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL\r
+ .long NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN\r
+ .long NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS\r
+ .long NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF\r
+ .long NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF\r
+ .long NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC\r
+ .long NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data\r
+ .long NVIC_Handler_P80A // 138h: 62, Port 80h A\r
+ .long NVIC_Handler_P80B // 13Ch: 63, Port 80h B\r
+ .long 0 // 140h: 64, Reserved\r
+ .long NVIC_Handler_PKE_ERR // 144h: 65, PKE Error\r
+ .long NVIC_Handler_PKE_END // 148h: 66, PKE End\r
+ .long NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen\r
+ .long NVIC_Handler_AES // 150h: 68, AES\r
+ .long NVIC_Handler_HASH // 154h: 69, HASH\r
+ .long NVIC_Handler_PECI // 158h: 70, PECI\r
+ .long NVIC_Handler_TACH0 // 15Ch: 71, TACH0\r
+ .long NVIC_Handler_TACH1 // 160h: 72, TACH1\r
+ .long NVIC_Handler_TACH2 // 164h: 73, TACH2\r
+ .long NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail\r
+ .long NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall\r
+ .long NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail\r
+ .long NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall\r
+ .long NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL\r
+ .long NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT\r
+ .long NVIC_Handler_RCID0 // 180h: 80, RCID 0\r
+ .long NVIC_Handler_RCID1 // 184h: 81, RCID 1\r
+ .long NVIC_Handler_RCID2 // 188h: 82, RCID 2\r
+ .long NVIC_Handler_LED0 // 18Ch: 83, LED0\r
+ .long NVIC_Handler_LED1 // 190h: 84, LED1\r
+ .long NVIC_Handler_LED2 // 194h: 85, LED2\r
+ .long NVIC_Handler_LED3 // 198h: 86, LED2\r
+ .long NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor\r
+ .long NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status\r
+ .long NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status\r
+ .long NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error\r
+ .long NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0\r
+ .long NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX\r
+ .long NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX\r
+ .long NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX\r
+ .long NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX\r
+ .long NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear\r
+ .long NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error\r
+ .long NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear\r
+ .long NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error\r
+ .long NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0\r
+ .long NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1\r
+ .long NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2\r
+ .long NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan\r
+ .long NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1\r
+ .long NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2\r
+ .long NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR\r
+ .long NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1\r
+ .long NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2\r
+ .long NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan\r
+ .long NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset\r
+ .long NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer\r
+ .long NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0\r
+ .long NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1\r
+ .long NVIC_Handler_WK // 208h: 114, Week Alarm\r
+ .long NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week\r
+ .long NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec\r
+ .long NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec\r
+ .long NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin\r
+ .long NVIC_Handler_RTC // 21Ch: 119, RTC\r
+ .long NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM\r
+ .long NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input\r
+ .long NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0\r
+ .long NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1\r
+ .long NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2\r
+ .long NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3\r
+ .long NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4\r
+ .long NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5\r
+ .long NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6\r
+ .long NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake\r
+ .long NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake\r
+ .long NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake\r
+ .long NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake\r
+ .long NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake\r
+ .long NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor\r
+ .long NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan\r
+ .long NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0\r
+ .long NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1\r
+ .long NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2\r
+ .long NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3\r
+ .long NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0\r
+ .long NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1\r
+ .long NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0\r
+ .long NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1\r
+ .long NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2\r
+ .long NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3\r
+ .long NVIC_Handler_CAPTMR // 288h: 146, Capture Timer\r
+ .long NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event\r
+ .long NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event\r
+ .long NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event\r
+ .long NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event\r
+ .long NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event\r
+ .long NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event\r
+ .long NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event\r
+ .long NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event\r
+\r
+\r
+ .text\r
+ .thumb\r
+ .thumb_func\r
+ .align 2\r
+ .globl _start\r
+ .extern main\r
+ .globl Reset_Handler\r
+ .type Reset_Handler, %function\r
+_start:\r
+Reset_Handler:\r
+/* Firstly it copies data from read only memory to RAM. There are two schemes\r
+ * to copy. One can copy more than one sections. Another can only copy\r
+ * one section. The former scheme needs more instructions and read-only\r
+ * data to implement than the latter.\r
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */\r
+\r
+/* Single section scheme.\r
+ *\r
+ * The ranges of copy from/to are specified by following symbols\r
+ * __etext: LMA of start of the section to copy from. Usually end of text\r
+ * __data_start__: VMA of start of the section to copy to\r
+ * __data_end__: VMA of end of the section to copy to\r
+ *\r
+ * All addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr sp, =__SRAM_segment_end__\r
+ sub sp, sp, #4\r
+\r
+ ldr r1, =__etext\r
+ ldr r2, =__data_start__\r
+ ldr r3, =__data_end__\r
+\r
+.L_loop1:\r
+ cmp r2, r3\r
+ ittt lt\r
+ ldrlt r0, [r1], #4\r
+ strlt r0, [r2], #4\r
+ blt .L_loop1\r
+\r
+/* This part of work usually is done in C library startup code. Otherwise,\r
+ * define this macro to enable it in this startup.\r
+ *\r
+ * There are two schemes too. One can clear multiple BSS sections. Another\r
+ * can only clear one section. The former is more size expensive than the\r
+ * latter.\r
+ *\r
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.\r
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.\r
+ */\r
+\r
+ /* Single BSS section scheme.\r
+ *\r
+ * The BSS section is specified by following symbols\r
+ * __bss_start__: start of the BSS section.\r
+ * __bss_end__: end of the BSS section.\r
+ *\r
+ * Both addresses must be aligned to 4 bytes boundary.\r
+ */\r
+ ldr r1, =__bss_start__\r
+ ldr r2, =__bss_end__\r
+\r
+ movs r0, 0\r
+.L_loop3:\r
+ cmp r1, r2\r
+ itt lt\r
+ strlt r0, [r1], #4\r
+ blt .L_loop3\r
+\r
+#ifndef __NO_SYSTEM_INIT\r
+/* bl SystemInit */\r
+#endif\r
+\r
+ bl main\r
+\r
+ .pool\r
+ .size Reset_Handler, . - Reset_Handler\r
+\r
+ .align 1\r
+ .thumb_func\r
+ .weak Default_Handler\r
+ .type Default_Handler, %function\r
+Default_Handler:\r
+ b .\r
+ .size Default_Handler, . - Default_Handler\r
+\r
+/* Macro to define default handlers. Default handler\r
+ * will be weak symbol and just dead loops. They can be\r
+ * overwritten by other handlers */\r
+ .macro def_irq_handler handler_name\r
+ .weak \handler_name\r
+ .set \handler_name, Default_Handler\r
+ .endm\r
+\r
+ def_irq_handler NMI_Handler\r
+ def_irq_handler HardFault_Handler\r
+ def_irq_handler MemManage_Handler\r
+ def_irq_handler BusFault_Handler\r
+ def_irq_handler UsageFault_Handler\r
+/* def_irq_handler SVC_Handler */\r
+ def_irq_handler DebugMon_Handler\r
+/* def_irq_handler PendSV_Handler */\r
+/* def_irq_handler SysTick_Handler */\r
+ def_irq_handler DEF_IRQHandler\r
+\r
+ def_irq_handler NVIC_Handler_GIRQ08 // 40h: 0, GIRQ08\r
+ def_irq_handler NVIC_Handler_GIRQ09 // 44h: 1, GIRQ09\r
+ def_irq_handler NVIC_Handler_GIRQ10 // 48h: 2, GIRQ10\r
+ def_irq_handler NVIC_Handler_GIRQ11 // 4Ch: 3, GIRQ11\r
+ def_irq_handler NVIC_Handler_GIRQ12 // 50h: 4, GIRQ12\r
+ def_irq_handler NVIC_Handler_GIRQ13 // 54h: 5, GIRQ13\r
+ def_irq_handler NVIC_Handler_GIRQ14 // 58h: 6, GIRQ14\r
+ def_irq_handler NVIC_Handler_GIRQ15 // 5Ch: 7, GIRQ15\r
+ def_irq_handler NVIC_Handler_GIRQ16 // 60h: 8, GIRQ16\r
+ def_irq_handler NVIC_Handler_GIRQ17 // 64h: 9, GIRQ17\r
+ def_irq_handler NVIC_Handler_GIRQ18 // 68h: 10, GIRQ18\r
+ def_irq_handler NVIC_Handler_GIRQ19 // 6Ch: 11, GIRQ19\r
+ def_irq_handler NVIC_Handler_GIRQ20 // 70h: 12, GIRQ20\r
+ def_irq_handler NVIC_Handler_GIRQ21 // 74h: 13, GIRQ21\r
+ def_irq_handler NVIC_Handler_GIRQ23 // 78h: 14, GIRQ23\r
+ def_irq_handler NVIC_Handler_GIRQ24 // 7Ch: 15, GIRQ24\r
+ def_irq_handler NVIC_Handler_GIRQ25 // 80h: 16, GIRQ25\r
+ def_irq_handler NVIC_Handler_GIRQ26 // 84h: 17, GIRQ26\r
+ def_irq_handler NVIC_Handler_I2C0 // 90h: 20, I2C/SMBus 0\r
+ def_irq_handler NVIC_Handler_I2C1 // 94h: 21, I2C/SMBus 1\r
+ def_irq_handler NVIC_Handler_I2C2 // 98h: 22, I2C/SMBus 2\r
+ def_irq_handler NVIC_Handler_I2C3 // 9Ch: 23, I2C/SMBus 3\r
+ def_irq_handler NVIC_Handler_DMA0 // A0h: 24, DMA Channel 0\r
+ def_irq_handler NVIC_Handler_DMA1 // A4h: 25, DMA Channel 1\r
+ def_irq_handler NVIC_Handler_DMA2 // A8h: 26, DMA Channel 2\r
+ def_irq_handler NVIC_Handler_DMA3 // ACh: 27, DMA Channel 3\r
+ def_irq_handler NVIC_Handler_DMA4 // B0h: 28, DMA Channel 4\r
+ def_irq_handler NVIC_Handler_DMA5 // B4h: 29, DMA Channel 5\r
+ def_irq_handler NVIC_Handler_DMA6 // B8h: 30, DMA Channel 6\r
+ def_irq_handler NVIC_Handler_DMA7 // BCh: 31, DMA Channel 7\r
+ def_irq_handler NVIC_Handler_DMA8 // C0h: 32, DMA Channel 8\r
+ def_irq_handler NVIC_Handler_DMA9 // C4h: 33, DMA Channel 9\r
+ def_irq_handler NVIC_Handler_DMA10 // C8h: 34, DMA Channel 10\r
+ def_irq_handler NVIC_Handler_DMA11 // CCh: 35, DMA Channel 11\r
+ def_irq_handler NVIC_Handler_DMA12 // D0h: 36, DMA Channel 12\r
+ def_irq_handler NVIC_Handler_DMA13 // D4h: 37, DMA Channel 13\r
+ def_irq_handler NVIC_Handler_UART0 // E0h: 40, UART0\r
+ def_irq_handler NVIC_Handler_UART1 // E4h: 41, UART1\r
+ def_irq_handler NVIC_Handler_EMI0 // E8h: 42, EMI0\r
+ def_irq_handler NVIC_Handler_EMI1 // ECh: 43, EMI0\r
+ def_irq_handler NVIC_Handler_EMI2 // F0h: 44, EMI0\r
+ def_irq_handler NVIC_Handler_ACPI_EC0_IBF // F4h: 45, ACPI_EC0_IBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC0_OBF // F8h: 46, ACPI_EC0_OBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC1_IBF // FCh: 47, ACPI_EC1_IBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC1_OBF // 100h: 48, ACPI_EC1_OBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC2_IBF // 104h: 49, ACPI_EC0_IBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC2_OBF // 108h: 50, ACPI_EC0_OBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC3_IBF // 10Ch: 51, ACPI_EC1_IBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC3_OBF // 110h: 52, ACPI_EC1_OBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC4_IBF // 114h: 53, ACPI_EC0_IBF\r
+ def_irq_handler NVIC_Handler_ACPI_EC4_OBF // 118h: 54, ACPI_EC0_OBF\r
+ def_irq_handler NVIC_Handler_PM1_CTL // 11Ch: 55, ACPI_PM1_CTL\r
+ def_irq_handler NVIC_Handler_PM1_EN // 120h: 56, ACPI_PM1_EN\r
+ def_irq_handler NVIC_Handler_PM1_STS // 124h: 57, ACPI_PM1_STS\r
+ def_irq_handler NVIC_Handler_MIF8042_OBF // 128h: 58, MIF8042_OBF\r
+ def_irq_handler NVIC_Handler_MIF8042_IBF // 12Ch: 59, MIF8042_IBF\r
+ def_irq_handler NVIC_Handler_MB_H2EC // 130h: 60, Mailbox Host to EC\r
+ def_irq_handler NVIC_Handler_MB_DATA // 134h: 61, Mailbox Host Data\r
+ def_irq_handler NVIC_Handler_P80A // 138h: 62, Port 80h A\r
+ def_irq_handler NVIC_Handler_P80B // 13Ch: 63, Port 80h B\r
+ def_irq_handler NVIC_Handler_PKE_ERR // 144h: 65, PKE Error\r
+ def_irq_handler NVIC_Handler_PKE_END // 148h: 66, PKE End\r
+ def_irq_handler NVIC_Handler_TRNG // 14Ch: 67, Random Num Gen\r
+ def_irq_handler NVIC_Handler_AES // 150h: 68, AES\r
+ def_irq_handler NVIC_Handler_HASH // 154h: 69, HASH\r
+ def_irq_handler NVIC_Handler_PECI // 158h: 70, PECI\r
+ def_irq_handler NVIC_Handler_TACH0 // 15Ch: 71, TACH0\r
+ def_irq_handler NVIC_Handler_TACH1 // 160h: 72, TACH1\r
+ def_irq_handler NVIC_Handler_TACH2 // 164h: 73, TACH2\r
+ def_irq_handler NVIC_Handler_R2P0_FAIL // 168h: 74, RPM2PWM 0 Fan Fail\r
+ def_irq_handler NVIC_Handler_R2P0_STALL // 16Ch: 75, RPM2PWM 0 Fan Stall\r
+ def_irq_handler NVIC_Handler_R2P1_FAIL // 170h: 76, RPM2PWM 1 Fan Fail\r
+ def_irq_handler NVIC_Handler_R2P1_STALL // 174h: 77, RPM2PWM 1 Fan Stall\r
+ def_irq_handler NVIC_Handler_ADC_SNGL // 178h: 78, ADC_SNGL\r
+ def_irq_handler NVIC_Handler_ADC_RPT // 17Ch: 79, ADC_RPT\r
+ def_irq_handler NVIC_Handler_RCID0 // 180h: 80, RCID 0\r
+ def_irq_handler NVIC_Handler_RCID1 // 184h: 81, RCID 1\r
+ def_irq_handler NVIC_Handler_RCID2 // 188h: 82, RCID 2\r
+ def_irq_handler NVIC_Handler_LED0 // 18Ch: 83, LED0\r
+ def_irq_handler NVIC_Handler_LED1 // 190h: 84, LED1\r
+ def_irq_handler NVIC_Handler_LED2 // 194h: 85, LED2\r
+ def_irq_handler NVIC_Handler_LED3 // 198h: 86, LED2\r
+ def_irq_handler NVIC_Handler_PHOT // 19Ch: 87, ProcHot Monitor\r
+ def_irq_handler NVIC_Handler_PWRGD0 // 1A0h: 88, PowerGuard 0 Status\r
+ def_irq_handler NVIC_Handler_PWRGD1 // 1A4h: 89, PowerGuard 1 Status\r
+ def_irq_handler NVIC_Handler_LPCBERR // 1A8h: 90, LPC Bus Error\r
+ def_irq_handler NVIC_Handler_QMSPI0 // 1ACh: 91, QMSPI 0\r
+ def_irq_handler NVIC_Handler_GPSPI0_TX // 1B0h: 92, GP-SPI0 TX\r
+ def_irq_handler NVIC_Handler_GPSPI0_RX // 1B4h: 93, GP-SPI0 RX\r
+ def_irq_handler NVIC_Handler_GPSPI1_TX // 1B8h: 94, GP-SPI1 TX\r
+ def_irq_handler NVIC_Handler_GPSPI1_RX // 1BCh: 95, GP-SPI1 RX\r
+ def_irq_handler NVIC_Handler_BC0_BUSY // 1C0h: 96, BC-Link0 Busy-Clear\r
+ def_irq_handler NVIC_Handler_BC0_ERR // 1C4h: 97, BC-Link0 Error\r
+ def_irq_handler NVIC_Handler_BC1_BUSY // 1C8h: 98, BC-Link1 Busy-Clear\r
+ def_irq_handler NVIC_Handler_BC1_ERR // 1CCh: 99, BC-Link1 Error\r
+ def_irq_handler NVIC_Handler_PS2_0 // 1D0h: 100, PS2_0\r
+ def_irq_handler NVIC_Handler_PS2_1 // 1D4h: 101, PS2_1\r
+ def_irq_handler NVIC_Handler_PS2_2 // 1D8h: 102, PS2_2\r
+ def_irq_handler NVIC_Handler_ESPI_PC // 1DCh: 103, eSPI Periph Chan\r
+ def_irq_handler NVIC_Handler_ESPI_BM1 // 1E0h: 104, eSPI Bus Master 1\r
+ def_irq_handler NVIC_Handler_ESPI_BM2 // 1E4h: 105, eSPI Bus Master 2\r
+ def_irq_handler NVIC_Handler_ESPI_LTR // 1E8h: 106, eSPI LTR\r
+ def_irq_handler NVIC_Handler_ESPI_OOB_UP // 1ECh: 107, eSPI Bus Master 1\r
+ def_irq_handler NVIC_Handler_ESPI_OOB_DN // 1F0h: 108, eSPI Bus Master 2\r
+ def_irq_handler NVIC_Handler_ESPI_FLASH // 1F4h: 109, eSPI Flash Chan\r
+ def_irq_handler NVIC_Handler_ESPI_RESET // 1F8h: 110, eSPI Reset\r
+ def_irq_handler NVIC_Handler_RTMR // 1FCh: 111, RTOS Timer\r
+ def_irq_handler NVIC_Handler_HTMR0 // 200h: 112, Hibernation Timer 0\r
+ def_irq_handler NVIC_Handler_HTMR1 // 204h: 113, Hibernation Timer 1\r
+ def_irq_handler NVIC_Handler_WK // 208h: 114, Week Alarm\r
+ def_irq_handler NVIC_Handler_WKSUB // 20Ch: 115, Week Alarm, sub week\r
+ def_irq_handler NVIC_Handler_WKSEC // 210h: 116, Week Alarm, one sec\r
+ def_irq_handler NVIC_Handler_WKSUBSEC // 214h: 117, Week Alarm, sub sec\r
+ def_irq_handler NVIC_Handler_SYSPWR // 218h: 118, System Power Present pin\r
+ def_irq_handler NVIC_Handler_RTC // 21Ch: 119, RTC\r
+ def_irq_handler NVIC_Handler_RTC_ALARM // 220h: 120, RTC_ALARM\r
+ def_irq_handler NVIC_Handler_VCI_OVRD_IN // 224h: 121, VCI Override Input\r
+ def_irq_handler NVIC_Handler_VCI_IN0 // 228h: 122, VCI Input 0\r
+ def_irq_handler NVIC_Handler_VCI_IN1 // 22Ch: 123, VCI Input 1\r
+ def_irq_handler NVIC_Handler_VCI_IN2 // 230h: 124, VCI Input 2\r
+ def_irq_handler NVIC_Handler_VCI_IN3 // 234h: 125, VCI Input 3\r
+ def_irq_handler NVIC_Handler_VCI_IN4 // 238h: 126, VCI Input 4\r
+ def_irq_handler NVIC_Handler_VCI_IN5 // 23Ch: 127, VCI Input 5\r
+ def_irq_handler NVIC_Handler_VCI_IN6 // 240h: 128, VCI Input 6\r
+ def_irq_handler NVIC_Handler_PS20A_WAKE // 244h: 129, PS2 Port 0A Wake\r
+ def_irq_handler NVIC_Handler_PS20B_WAKE // 248h: 130, PS2 Port 0B Wake\r
+ def_irq_handler NVIC_Handler_PS21A_WAKE // 24Ch: 131, PS2 Port 1A Wake\r
+ def_irq_handler NVIC_Handler_PS21B_WAKE // 250h: 132, PS2 Port 1B Wake\r
+ def_irq_handler NVIC_Handler_PS21_WAKE // 254h: 133, PS2 Port 1 Wake\r
+ def_irq_handler NVIC_Handler_ENVMON // 258h: 134, Thernal Monitor\r
+ def_irq_handler NVIC_Handler_KEYSCAN // 25Ch: 135, Key Scan\r
+ def_irq_handler NVIC_Handler_BTMR16_0 // 260h: 136, 16-bit Basic Timer 0\r
+ def_irq_handler NVIC_Handler_BTMR16_1 // 264h: 137, 16-bit Basic Timer 1\r
+ def_irq_handler NVIC_Handler_BTMR16_2 // 268h: 138, 16-bit Basic Timer 2\r
+ def_irq_handler NVIC_Handler_BTMR16_3 // 26Ch: 139, 16-bit Basic Timer 3\r
+ def_irq_handler NVIC_Handler_BTMR32_0 // 270h: 140, 32-bit Basic Timer 0\r
+ def_irq_handler NVIC_Handler_BTMR32_1 // 274h: 141, 32-bit Basic Timer 1\r
+ def_irq_handler NVIC_Handler_EVTMR0 // 278h: 142, Event Counter/Timer 0\r
+ def_irq_handler NVIC_Handler_EVTMR1 // 27Ch: 143, Event Counter/Timer 1\r
+ def_irq_handler NVIC_Handler_EVTMR2 // 280h: 144, Event Counter/Timer 2\r
+ def_irq_handler NVIC_Handler_EVTMR3 // 284h: 145, Event Counter/Timer 3\r
+ def_irq_handler NVIC_Handler_CAPTMR // 288h: 146, Capture Timer\r
+ def_irq_handler NVIC_Handler_CAP0 // 28Ch: 147, Capture 0 Event\r
+ def_irq_handler NVIC_Handler_CAP1 // 290h: 148, Capture 1 Event\r
+ def_irq_handler NVIC_Handler_CAP2 // 294h: 149, Capture 2 Event\r
+ def_irq_handler NVIC_Handler_CAP3 // 298h: 150, Capture 3 Event\r
+ def_irq_handler NVIC_Handler_CAP4 // 29Ch: 151, Capture 4 Event\r
+ def_irq_handler NVIC_Handler_CAP5 // 2A0h: 152, Capture 5 Event\r
+ def_irq_handler NVIC_Handler_CMP0 // 2A4h: 153, Compare 0 Event\r
+ def_irq_handler NVIC_Handler_CMP1 // 2A8h: 154, Compare 1 Event\r
+\r
+ .end\r
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup pwm pwm_c_wrapper\r
+ * @{\r
+ */\r
+/** @file pwm_c_wrapper.cpp\r
+ \brief the pwm component C wrapper \r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/GCC_Specific/system.c $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2016/09/22 08:03:49 $\r
+ * AUTHOR: $Author: pramans $\r
+ *\r
+ * Revision history (latest first):\r
+ * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
+ * #2 2011/03/25 martin_y support FPGA build 058 apps\r
+ * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
+ ***********************************************************************************\r
+ */\r
+/* Imported Header File */\r
+//#include "common.h"\r
+//#include "build.h"\r
+#include <stdint.h>\r
+\r
+#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
+#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
+#define CPU_CLOCK_DIVIDER 1\r
+\r
+/******************************************************************************/\r
+/** system_set_ec_clock\r
+* Set CPU speed\r
+* @param void\r
+* @return void\r
+*******************************************************************************/\r
+\r
+void system_set_ec_clock(void)\r
+{\r
+\r
+ /* Set ARC CPU Clock Divider to determine the CPU speed */\r
+ /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */\r
+ MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;\r
+\r
+} /* End system_set_ec_clock() */\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
+; *************************************************************\r
+\r
+\r
+LR_IROM1 0xE0000 0x40000 ; load region size_region\r
+{\r
+ ER_PRIVILEGED_FUNCTIONS 0xE0000 0x8000 {\r
+ *.o (RESET, +First)\r
+ startup_MPS_CM4.o\r
+ *(InRoot$$Sections)\r
+ *( privileged_functions )\r
+ }\r
+\r
+ ER_UNPRIVILEGED_FUNCTIONS 0xE8000 0x18000 {\r
+ .ANY (+RO)\r
+ }\r
+\r
+ RW_PRIVILEGED_DATA 0x100000 0x200 {\r
+ *( privileged_data )\r
+ }\r
+\r
+ RW_UNPRIVILEGED_DATA 0x100200 0x1FE00 {\r
+ .ANY (+RW +ZI)\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>RTOSDemo</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>48000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile>init_app.ini</tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMRTXEVENTFLAGS</Key>
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=1199,245,1664,545,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UV1115SAE -O3047 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC48000000 -TP21 -TDS8028 -TDT0 -TDC1F -TIE1 -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0E0000 -FL038000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <WatchWindow1>
+ <Ww>
+ <count>0</count>
+ <WinNumber>1</WinNumber>
+ <ItemText>pxCurrentTCB</ItemText>
+ </Ww>
+ </WatchWindow1>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>2</SubType>
+ <ItemText>0xe000e284</ItemText>
+ <AccSizeX>4</AccSizeX>
+ </Mm>
+ </MemoryWindow1>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>1</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_MPS_CM4.S</PathWithFileName>
+ <FilenameWithoutPath>startup_MPS_CM4.S</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>main_and_config</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>..\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\FreeRTOSConfig.h</PathWithFileName>
+ <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
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+ </File>
+ <File>
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+ <FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
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+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
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+ <FilenameWithoutPath>list.c</FilenameWithoutPath>
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+ </File>
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+ </File>
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+ <File>
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+ <FilenameWithoutPath>mpu_wrappers.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>peripheral_library</GroupName>
+ <tvExp>1</tvExp>
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+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
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+ <FilenameWithoutPath>interrupt_api.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\peripheral_library\interrupt\interrupt_ecia_perphl.c</PathWithFileName>
+ <FilenameWithoutPath>interrupt_ecia_perphl.c</FilenameWithoutPath>
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+ <bShared>0</bShared>
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+ <File>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\peripheral_library\interrupt\interrupt_nvic_perphl.c</PathWithFileName>
+ <FilenameWithoutPath>interrupt_nvic_perphl.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
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+ <tvExpOptDlg>0</tvExpOptDlg>
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+ <PathWithFileName>..\peripheral_library\basic_timer\btimer_api.c</PathWithFileName>
+ <FilenameWithoutPath>btimer_api.c</FilenameWithoutPath>
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+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\peripheral_library\pcr\pcr_api.c</PathWithFileName>
+ <FilenameWithoutPath>pcr_api.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>19</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\peripheral_library\pcr\pcr_perphl.c</PathWithFileName>
+ <FilenameWithoutPath>pcr_perphl.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>20</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\peripheral_library\system_internal.c</PathWithFileName>
+ <FilenameWithoutPath>system_internal.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>RTOSDemo</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Objects\</OutputDirectory>
+ <OutputName>RTOSDemo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>1</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\Listings\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>1</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>init_app.ini</InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>1</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0xe0000</StartAddress>
+ <Size>0x38000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x118000</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4_MPU;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full;..\peripheral_library\interrupt</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>RTOSDemo.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_MPS_CM4.S</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_MPS_CM4.S</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_and_config</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\RVDS\ARM_CM4_MPU\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>mpu_wrappers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\Common\mpu_wrappers.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>peripheral_library</GroupName>
+ <Files>
+ <File>
+ <FileName>interrupt_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\interrupt\interrupt_api.c</FilePath>
+ </File>
+ <File>
+ <FileName>interrupt_ecia_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\interrupt\interrupt_ecia_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>interrupt_nvic_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\interrupt\interrupt_nvic_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>btimer_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>
+ </File>
+ <File>
+ <FileName>btimer_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>pcr_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\pcr\pcr_api.c</FilePath>
+ </File>
+ <File>
+ <FileName>pcr_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\pcr\pcr_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>system_internal.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\system_internal.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/*\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ */\r
+\r
+void vRegTest1Implementation( void *pvParameters );\r
+void vRegTest2Implementation( void *pvParameters );\r
+void vRegTest3Implementation( void );\r
+void vRegTest4Implementation( void );\r
+\r
+/*\r
+ * Used as an easy way of deleting a task from inline assembly.\r
+ */\r
+extern void vMainDeleteMe( void ) __attribute__((noinline));\r
+\r
+/*\r
+ * Used by the first two reg test tasks and a software timer callback function\r
+ * to send messages to the check task. The message just lets the check task\r
+ * know that the tasks and timer are still functioning correctly. If a reg test\r
+ * task detects an error it will delete itself, and in so doing prevent itself\r
+ * from sending any more 'I'm Alive' messages to the check task.\r
+ */\r
+extern void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber );\r
+\r
+/* The queue used to send a message to the check task. */\r
+extern QueueHandle_t xGlobalScopeCheckQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest1Implementation( void *pvParameters )\r
+{\r
+/* This task is created in privileged mode so can access the file scope\r
+queue variable. Take a stack copy of this before the task is set into user\r
+mode. Once this task is in user mode the file scope queue variable will no\r
+longer be accessible but the stack copy will. */\r
+QueueHandle_t xQueue = xGlobalScopeCheckQueue;\r
+const TickType_t xDelayTime = pdMS_TO_TICKS( 100UL );\r
+\r
+ /* Now the queue handle has been obtained the task can switch to user\r
+ mode. This is just one method of passing a handle into a protected\r
+ task, the other reg test task uses the task parameter instead. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* First check that the parameter value is as expected. */\r
+ if( pvParameters != ( void * ) configREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Error detected. Delete the task so it stops communicating with\r
+ the check task. */\r
+ vMainDeleteMe();\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ #if defined ( __GNUC__ )\r
+ {\r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile\r
+ (\r
+ " MOV R4, #104 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #105 \n"\r
+ " MOV R6, #106 \n"\r
+ " MOV R8, #108 \n"\r
+ " MOV R9, #109 \n"\r
+ " MOV R10, #110 \n"\r
+ " MOV R11, #111 \n"\r
+ "reg1loop: \n"\r
+ " MOV R0, #100 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #101 \n"\r
+ " MOV R2, #102 \n"\r
+ " MOV R3, #103 \n"\r
+ " MOV R12, #112 \n"\r
+ " SVC #1 \n" /* Yield just to increase test coverage. */\r
+ " CMP R0, #100 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task. */\r
+ " CMP R1, #101 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R2, #102 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R3, #103 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R4, #104 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R5, #105 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R6, #106 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R8, #108 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R9, #109 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R10, #110 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R11, #111 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R12, #112 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"\r
+ );\r
+ }\r
+ #endif /* __GNUC__ */\r
+\r
+ /* Send configREG_TEST_1_STILL_EXECUTING to the check task to indicate that this\r
+ task is still functioning. */\r
+ vMainSendImAlive( xQueue, configREG_TEST_1_STILL_EXECUTING );\r
+ vTaskDelay( xDelayTime );\r
+\r
+ #if defined ( __GNUC__ )\r
+ {\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg1loop " );\r
+ }\r
+ #endif /* __GNUC__ */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Implementation( void *pvParameters )\r
+{\r
+/* The queue handle is passed in as the task parameter. This is one method of\r
+passing data into a protected task, the other reg test task uses a different\r
+method. */\r
+QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;\r
+const TickType_t xDelayTime = pdMS_TO_TICKS( 100UL );\r
+\r
+ for( ;; )\r
+ {\r
+ #if defined ( __GNUC__ )\r
+ {\r
+ /* This task tests the kernel context switch mechanism by reading and\r
+ writing directly to registers - which requires the test to be written\r
+ in assembly code. */\r
+ __asm volatile\r
+ (\r
+ " MOV R4, #4 \n" /* Set registers to a known value. R0 to R1 are done in the loop below. */\r
+ " MOV R5, #5 \n"\r
+ " MOV R6, #6 \n"\r
+ " MOV R8, #8 \n" /* Frame pointer is omitted as it must not be changed. */\r
+ " MOV R9, #9 \n"\r
+ " MOV R10, 10 \n"\r
+ " MOV R11, #11 \n"\r
+ "reg2loop: \n"\r
+ " MOV R0, #13 \n" /* Set the scratch registers to known values - done inside the loop as they get clobbered. */\r
+ " MOV R1, #1 \n"\r
+ " MOV R2, #2 \n"\r
+ " MOV R3, #3 \n"\r
+ " MOV R12, #12 \n"\r
+ " CMP R0, #13 \n" /* Check all the registers still contain their expected values. */\r
+ " BNE vMainDeleteMe \n" /* Value was not as expected, delete the task so it stops communicating with the check task */\r
+ " CMP R1, #1 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R2, #2 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R3, #3 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R4, #4 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R5, #5 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R6, #6 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R8, #8 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R9, #9 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R10, #10 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R11, #11 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ " CMP R12, #12 \n"\r
+ " BNE vMainDeleteMe \n"\r
+ :::"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r10", "r11", "r12"\r
+ );\r
+ }\r
+ #endif /* __GNUC__ */\r
+\r
+ /* Send configREG_TEST_2_STILL_EXECUTING to the check task to indicate\r
+ that this task is still functioning. */\r
+ vMainSendImAlive( xQueue, configREG_TEST_2_STILL_EXECUTING );\r
+ vTaskDelay( xDelayTime );\r
+\r
+ #if defined ( __GNUC__ )\r
+ {\r
+ /* Go back to check all the register values again. */\r
+ __asm volatile( " B reg2loop " );\r
+ }\r
+ #endif /* __GNUC__ */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vRegTest3Implementation( void )\r
+{\r
+ extern pulRegTest3LoopCounter\r
+\r
+ PRESERVE8\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =pulRegTest3LoopCounter\r
+ ldr r0, [r0]\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vRegTest4Implementation( void )\r
+{\r
+ extern pulRegTest4LoopCounter;\r
+\r
+ PRESERVE8\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+\r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+\r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+\r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+\r
+ /* Increment the loop counter so the check task knows this task is\r
+ still running. */\r
+ push { r0-r1 }\r
+ ldr r0, =pulRegTest4LoopCounter\r
+ ldr r0, [r0]\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+\r
+ /* Yield to increase test coverage. */\r
+ SVC #1\r
+\r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Fault handlers are here for convenience as they use compiler specific syntax\r
+and this file is specific to the Keil compiler. */\r
+void hard_fault_handler( uint32_t * hardfault_args )\r
+{\r
+volatile uint32_t stacked_r0;\r
+volatile uint32_t stacked_r1;\r
+volatile uint32_t stacked_r2;\r
+volatile uint32_t stacked_r3;\r
+volatile uint32_t stacked_r12;\r
+volatile uint32_t stacked_lr;\r
+volatile uint32_t stacked_pc;\r
+volatile uint32_t stacked_psr;\r
+\r
+ stacked_r0 = ((uint32_t) hardfault_args[ 0 ]);\r
+ stacked_r1 = ((uint32_t) hardfault_args[ 1 ]);\r
+ stacked_r2 = ((uint32_t) hardfault_args[ 2 ]);\r
+ stacked_r3 = ((uint32_t) hardfault_args[ 3 ]);\r
+\r
+ stacked_r12 = ((uint32_t) hardfault_args[ 4 ]);\r
+ stacked_lr = ((uint32_t) hardfault_args[ 5 ]);\r
+ stacked_pc = ((uint32_t) hardfault_args[ 6 ]);\r
+ stacked_psr = ((uint32_t) hardfault_args[ 7 ]);\r
+\r
+ /* Inspect stacked_pc to locate the offending instruction. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void HardFault_Handler( void );\r
+__asm void HardFault_Handler( void )\r
+{\r
+ extern hard_fault_handler\r
+\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ ldr r1, [r0, #24]\r
+ ldr r2, hard_fault_handler\r
+ bx r2\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void );\r
+__asm void MemManage_Handler( void )\r
+{\r
+ extern hard_fault_handler\r
+\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ ldr r1, [r0, #24]\r
+ ldr r2, hard_fault_handler\r
+ bx r2\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+//Initialization file for the application code\r
+RESET\r
+T\r
+T\r
+T\r
+eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine\r
+T\r
--- /dev/null
+;/*****************************************************************************\r
+; * @file: startup_MPS_CM4.s\r
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File\r
+; * for the ARM 'Microcontroller Prototyping System'\r
+; * @version: V1.00\r
+; * @date: 1. Jun. 2010\r
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+; *\r
+; * Copyright (C) 2008-2010 ARM Limited. All rights reserved.\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M4\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ****************************************************************************/\r
+\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+Stack_Size EQU 0x00000800\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD NVIC_Handler_GIRQ08 ; 40h: 0, GIRQ08\r
+ DCD NVIC_Handler_GIRQ09 ; 44h: 1, GIRQ09\r
+ DCD NVIC_Handler_GIRQ10 ; 48h: 2, GIRQ10\r
+ DCD NVIC_Handler_GIRQ11 ; 4Ch: 3, GIRQ11\r
+ DCD NVIC_Handler_GIRQ12 ; 50h: 4, GIRQ12\r
+ DCD NVIC_Handler_GIRQ13 ; 54h: 5, GIRQ13\r
+ DCD NVIC_Handler_GIRQ14 ; 58h: 6, GIRQ14\r
+ DCD NVIC_Handler_GIRQ15 ; 5Ch: 7, GIRQ15\r
+ DCD NVIC_Handler_GIRQ16 ; 60h: 8, GIRQ16\r
+ DCD NVIC_Handler_GIRQ17 ; 64h: 9, GIRQ17\r
+ DCD NVIC_Handler_GIRQ18 ; 68h: 10, GIRQ18\r
+ DCD NVIC_Handler_GIRQ19 ; 6Ch: 11, GIRQ19\r
+ DCD NVIC_Handler_GIRQ20 ; 70h: 12, GIRQ20\r
+ DCD NVIC_Handler_GIRQ21 ; 74h: 13, GIRQ21\r
+ DCD NVIC_Handler_GIRQ23 ; 78h: 14, GIRQ23\r
+ DCD NVIC_Handler_GIRQ24 ; 7Ch: 15, GIRQ24\r
+ DCD NVIC_Handler_GIRQ25 ; 80h: 16, GIRQ25\r
+ DCD NVIC_Handler_GIRQ26 ; 84h: 17, GIRQ26\r
+ DCD 0 ; 88h: 18, RSVD\r
+ DCD 0 ; 8Ch: 19, RSVD\r
+ DCD NVIC_Handler_I2C0 ; 90h: 20, I2C/SMBus 0\r
+ DCD NVIC_Handler_I2C1 ; 94h: 21, I2C/SMBus 1\r
+ DCD NVIC_Handler_I2C2 ; 98h: 22, I2C/SMBus 2\r
+ DCD NVIC_Handler_I2C3 ; 9Ch: 23, I2C/SMBus 3\r
+ DCD NVIC_Handler_DMA0 ; A0h: 24, DMA Channel 0\r
+ DCD NVIC_Handler_DMA1 ; A4h: 25, DMA Channel 1\r
+ DCD NVIC_Handler_DMA2 ; A8h: 26, DMA Channel 2\r
+ DCD NVIC_Handler_DMA3 ; ACh: 27, DMA Channel 3\r
+ DCD NVIC_Handler_DMA4 ; B0h: 28, DMA Channel 4\r
+ DCD NVIC_Handler_DMA5 ; B4h: 29, DMA Channel 5\r
+ DCD NVIC_Handler_DMA6 ; B8h: 30, DMA Channel 6\r
+ DCD NVIC_Handler_DMA7 ; BCh: 31, DMA Channel 7\r
+ DCD NVIC_Handler_DMA8 ; C0h: 32, DMA Channel 8\r
+ DCD NVIC_Handler_DMA9 ; C4h: 33, DMA Channel 9\r
+ DCD NVIC_Handler_DMA10 ; C8h: 34, DMA Channel 10\r
+ DCD NVIC_Handler_DMA11 ; CCh: 35, DMA Channel 11\r
+ DCD NVIC_Handler_DMA12 ; D0h: 36, DMA Channel 12\r
+ DCD NVIC_Handler_DMA13 ; D4h: 37, DMA Channel 13\r
+ DCD 0 ; D8h: 38, Unused\r
+ DCD 0 ; DCh: 39, Unused\r
+ DCD NVIC_Handler_UART0 ; E0h: 40, UART0\r
+ DCD NVIC_Handler_UART1 ; E4h: 41, UART1\r
+ DCD NVIC_Handler_EMI0 ; E8h: 42, EMI0\r
+ DCD NVIC_Handler_EMI1 ; ECh: 43, EMI0\r
+ DCD NVIC_Handler_EMI2 ; F0h: 44, EMI0\r
+ DCD NVIC_Handler_ACPI_EC0_IBF ; F4h: 45, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC0_OBF ; F8h: 46, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_ACPI_EC1_IBF ; FCh: 47, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_ACPI_EC1_OBF ; 100h: 48, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_ACPI_EC2_IBF ; 104h: 49, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC2_OBF ; 108h: 50, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_ACPI_EC3_IBF ; 10Ch: 51, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_ACPI_EC3_OBF ; 110h: 52, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_ACPI_EC4_IBF ; 114h: 53, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_ACPI_EC4_OBF ; 118h: 54, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_PM1_CTL ; 11Ch: 55, ACPI_PM1_CTL\r
+ DCD NVIC_Handler_PM1_EN ; 120h: 56, ACPI_PM1_EN\r
+ DCD NVIC_Handler_PM1_STS ; 124h: 57, ACPI_PM1_STS\r
+ DCD NVIC_Handler_MIF8042_OBF ; 128h: 58, MIF8042_OBF\r
+ DCD NVIC_Handler_MIF8042_IBF ; 12Ch: 59, MIF8042_IBF\r
+ DCD NVIC_Handler_MB_H2EC ; 130h: 60, Mailbox Host to EC\r
+ DCD NVIC_Handler_MB_DATA ; 134h: 61, Mailbox Host Data\r
+ DCD NVIC_Handler_P80A ; 138h: 62, Port 80h A\r
+ DCD NVIC_Handler_P80B ; 13Ch: 63, Port 80h B\r
+ DCD 0 ; 140h: 64, Reserved\r
+ DCD NVIC_Handler_PKE_ERR ; 144h: 65, PKE Error\r
+ DCD NVIC_Handler_PKE_END ; 148h: 66, PKE End\r
+ DCD NVIC_Handler_TRNG ; 14Ch: 67, Random Num Gen\r
+ DCD NVIC_Handler_AES ; 150h: 68, AES\r
+ DCD NVIC_Handler_HASH ; 154h: 69, HASH\r
+ DCD NVIC_Handler_PECI ; 158h: 70, PECI\r
+ DCD NVIC_Handler_TACH0 ; 15Ch: 71, TACH0\r
+ DCD NVIC_Handler_TACH1 ; 160h: 72, TACH1\r
+ DCD NVIC_Handler_TACH2 ; 164h: 73, TACH2\r
+ DCD NVIC_Handler_R2P0_FAIL ; 168h: 74, RPM2PWM 0 Fan Fail\r
+ DCD NVIC_Handler_R2P0_STALL ; 16Ch: 75, RPM2PWM 0 Fan Stall\r
+ DCD NVIC_Handler_R2P1_FAIL ; 170h: 76, RPM2PWM 1 Fan Fail\r
+ DCD NVIC_Handler_R2P1_STALL ; 174h: 77, RPM2PWM 1 Fan Stall\r
+ DCD NVIC_Handler_ADC_SNGL ; 178h: 78, ADC_SNGL\r
+ DCD NVIC_Handler_ADC_RPT ; 17Ch: 79, ADC_RPT\r
+ DCD NVIC_Handler_RCID0 ; 180h: 80, RCID 0\r
+ DCD NVIC_Handler_RCID1 ; 184h: 81, RCID 1\r
+ DCD NVIC_Handler_RCID2 ; 188h: 82, RCID 2\r
+ DCD NVIC_Handler_LED0 ; 18Ch: 83, LED0\r
+ DCD NVIC_Handler_LED1 ; 190h: 84, LED1\r
+ DCD NVIC_Handler_LED2 ; 194h: 85, LED2\r
+ DCD NVIC_Handler_LED3 ; 198h: 86, LED2\r
+ DCD NVIC_Handler_PHOT ; 19Ch: 87, ProcHot Monitor\r
+ DCD NVIC_Handler_PWRGD0 ; 1A0h: 88, PowerGuard 0 Status\r
+ DCD NVIC_Handler_PWRGD1 ; 1A4h: 89, PowerGuard 1 Status\r
+ DCD NVIC_Handler_LPCBERR ; 1A8h: 90, LPC Bus Error\r
+ DCD NVIC_Handler_QMSPI0 ; 1ACh: 91, QMSPI 0\r
+ DCD NVIC_Handler_GPSPI0_TX ; 1B0h: 92, GP-SPI0 TX\r
+ DCD NVIC_Handler_GPSPI0_RX ; 1B4h: 93, GP-SPI0 RX\r
+ DCD NVIC_Handler_GPSPI1_TX ; 1B8h: 94, GP-SPI1 TX\r
+ DCD NVIC_Handler_GPSPI1_RX ; 1BCh: 95, GP-SPI1 RX\r
+ DCD NVIC_Handler_BC0_BUSY ; 1C0h: 96, BC-Link0 Busy-Clear\r
+ DCD NVIC_Handler_BC0_ERR ; 1C4h: 97, BC-Link0 Error\r
+ DCD NVIC_Handler_BC1_BUSY ; 1C8h: 98, BC-Link1 Busy-Clear\r
+ DCD NVIC_Handler_BC1_ERR ; 1CCh: 99, BC-Link1 Error\r
+ DCD NVIC_Handler_PS2_0 ; 1D0h: 100, PS2_0\r
+ DCD NVIC_Handler_PS2_1 ; 1D4h: 101, PS2_1\r
+ DCD NVIC_Handler_PS2_2 ; 1D8h: 102, PS2_2\r
+ DCD NVIC_Handler_ESPI_PC ; 1DCh: 103, eSPI Periph Chan\r
+ DCD NVIC_Handler_ESPI_BM1 ; 1E0h: 104, eSPI Bus Master 1\r
+ DCD NVIC_Handler_ESPI_BM2 ; 1E4h: 105, eSPI Bus Master 2\r
+ DCD NVIC_Handler_ESPI_LTR ; 1E8h: 106, eSPI LTR\r
+ DCD NVIC_Handler_ESPI_OOB_UP ; 1ECh: 107, eSPI Bus Master 1\r
+ DCD NVIC_Handler_ESPI_OOB_DN ; 1F0h: 108, eSPI Bus Master 2\r
+ DCD NVIC_Handler_ESPI_FLASH ; 1F4h: 109, eSPI Flash Chan\r
+ DCD NVIC_Handler_ESPI_RESET ; 1F8h: 110, eSPI Reset\r
+ DCD NVIC_Handler_RTMR ; 1FCh: 111, RTOS Timer\r
+ DCD NVIC_Handler_HTMR0 ; 200h: 112, Hibernation Timer 0\r
+ DCD NVIC_Handler_HTMR1 ; 204h: 113, Hibernation Timer 1\r
+ DCD NVIC_Handler_WK ; 208h: 114, Week Alarm\r
+ DCD NVIC_Handler_WKSUB ; 20Ch: 115, Week Alarm, sub week\r
+ DCD NVIC_Handler_WKSEC ; 210h: 116, Week Alarm, one sec\r
+ DCD NVIC_Handler_WKSUBSEC ; 214h: 117, Week Alarm, sub sec\r
+ DCD NVIC_Handler_SYSPWR ; 218h: 118, System Power Present pin\r
+ DCD NVIC_Handler_RTC ; 21Ch: 119, RTC\r
+ DCD NVIC_Handler_RTC_ALARM ; 220h: 120, RTC_ALARM\r
+ DCD NVIC_Handler_VCI_OVRD_IN ; 224h: 121, VCI Override Input\r
+ DCD NVIC_Handler_VCI_IN0 ; 228h: 122, VCI Input 0\r
+ DCD NVIC_Handler_VCI_IN1 ; 22Ch: 123, VCI Input 1\r
+ DCD NVIC_Handler_VCI_IN2 ; 230h: 124, VCI Input 2\r
+ DCD NVIC_Handler_VCI_IN3 ; 234h: 125, VCI Input 3\r
+ DCD NVIC_Handler_VCI_IN4 ; 238h: 126, VCI Input 4\r
+ DCD NVIC_Handler_VCI_IN5 ; 23Ch: 127, VCI Input 5\r
+ DCD NVIC_Handler_VCI_IN6 ; 240h: 128, VCI Input 6\r
+ DCD NVIC_Handler_PS20A_WAKE ; 244h: 129, PS2 Port 0A Wake\r
+ DCD NVIC_Handler_PS20B_WAKE ; 248h: 130, PS2 Port 0B Wake\r
+ DCD NVIC_Handler_PS21A_WAKE ; 24Ch: 131, PS2 Port 1A Wake\r
+ DCD NVIC_Handler_PS21B_WAKE ; 250h: 132, PS2 Port 1B Wake\r
+ DCD NVIC_Handler_PS21_WAKE ; 254h: 133, PS2 Port 1 Wake\r
+ DCD NVIC_Handler_ENVMON ; 258h: 134, Thernal Monitor\r
+ DCD NVIC_Handler_KEYSCAN ; 25Ch: 135, Key Scan\r
+ DCD NVIC_Handler_BTMR16_0 ; 260h: 136, 16-bit Basic Timer 0\r
+ DCD NVIC_Handler_BTMR16_1 ; 264h: 137, 16-bit Basic Timer 1\r
+ DCD NVIC_Handler_BTMR16_2 ; 268h: 138, 16-bit Basic Timer 2\r
+ DCD NVIC_Handler_BTMR16_3 ; 26Ch: 139, 16-bit Basic Timer 3\r
+ DCD NVIC_Handler_BTMR32_0 ; 270h: 140, 32-bit Basic Timer 0\r
+ DCD NVIC_Handler_BTMR32_1 ; 274h: 141, 32-bit Basic Timer 1\r
+ DCD NVIC_Handler_EVTMR0 ; 278h: 142, Event Counter/Timer 0\r
+ DCD NVIC_Handler_EVTMR1 ; 27Ch: 143, Event Counter/Timer 1\r
+ DCD NVIC_Handler_EVTMR2 ; 280h: 144, Event Counter/Timer 2\r
+ DCD NVIC_Handler_EVTMR3 ; 284h: 145, Event Counter/Timer 3\r
+ DCD NVIC_Handler_CAPTMR ; 288h: 146, Capture Timer\r
+ DCD NVIC_Handler_CAP0 ; 28Ch: 147, Capture 0 Event\r
+ DCD NVIC_Handler_CAP1 ; 290h: 148, Capture 1 Event\r
+ DCD NVIC_Handler_CAP2 ; 294h: 149, Capture 2 Event\r
+ DCD NVIC_Handler_CAP3 ; 298h: 150, Capture 3 Event\r
+ DCD NVIC_Handler_CAP4 ; 29Ch: 151, Capture 4 Event\r
+ DCD NVIC_Handler_CAP5 ; 2A0h: 152, Capture 5 Event\r
+ DCD NVIC_Handler_CMP0 ; 2A4h: 153, Compare 0 Event\r
+ DCD NVIC_Handler_CMP1 ; 2A8h: 154, Compare 1 Event\r
+ ; Project build information\r
+\r
+ AREA |.text|, CODE, READONLY\r
+; AREA RESET, CODE, READONLY\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ; Remap vector table\r
+ LDR R0, =__Vectors\r
+ LDR R1, =0xE000ED08\r
+ STR R0, [r1]\r
+ NOP\r
+\r
+ IF {CPU} = "Cortex-M4.fp"\r
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
+ LDR R1,[R0]\r
+ ORR R1,R1,#(0xF << 20)\r
+ STR R1,[R0]\r
+ ENDIF\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT NVIC_Handler_GIRQ08 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ09 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ10 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ11 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ12 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ13 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ14 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ15 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ16 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ17 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ18 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ19 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ20 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ21 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ23 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ24 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ25 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ26 [WEAK]\r
+\r
+ EXPORT NVIC_Handler_I2C0 [WEAK]\r
+ EXPORT NVIC_Handler_I2C1 [WEAK]\r
+ EXPORT NVIC_Handler_I2C2 [WEAK]\r
+ EXPORT NVIC_Handler_I2C3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA0 [WEAK]\r
+ EXPORT NVIC_Handler_DMA1 [WEAK]\r
+ EXPORT NVIC_Handler_DMA2 [WEAK]\r
+ EXPORT NVIC_Handler_DMA3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA4 [WEAK]\r
+ EXPORT NVIC_Handler_DMA5 [WEAK]\r
+ EXPORT NVIC_Handler_DMA6 [WEAK]\r
+ EXPORT NVIC_Handler_DMA7 [WEAK]\r
+ EXPORT NVIC_Handler_DMA8 [WEAK]\r
+ EXPORT NVIC_Handler_DMA9 [WEAK]\r
+ EXPORT NVIC_Handler_DMA10 [WEAK]\r
+ EXPORT NVIC_Handler_DMA11 [WEAK]\r
+ EXPORT NVIC_Handler_DMA12 [WEAK]\r
+ EXPORT NVIC_Handler_DMA13 [WEAK]\r
+\r
+ EXPORT NVIC_Handler_UART0 [WEAK]\r
+ EXPORT NVIC_Handler_UART1 [WEAK]\r
+ EXPORT NVIC_Handler_EMI0 [WEAK]\r
+ EXPORT NVIC_Handler_EMI1 [WEAK]\r
+ EXPORT NVIC_Handler_EMI2 [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC0_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC0_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC1_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC1_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC2_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC2_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC3_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC3_OBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC4_IBF [WEAK]\r
+ EXPORT NVIC_Handler_ACPI_EC4_OBF [WEAK]\r
+ EXPORT NVIC_Handler_PM1_CTL [WEAK]\r
+ EXPORT NVIC_Handler_PM1_EN [WEAK]\r
+ EXPORT NVIC_Handler_PM1_STS [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_OBF [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_IBF [WEAK]\r
+ EXPORT NVIC_Handler_MB_H2EC [WEAK]\r
+ EXPORT NVIC_Handler_MB_DATA [WEAK]\r
+ EXPORT NVIC_Handler_P80A [WEAK]\r
+ EXPORT NVIC_Handler_P80B [WEAK]\r
+\r
+ EXPORT NVIC_Handler_PKE_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PKE_END [WEAK]\r
+ EXPORT NVIC_Handler_TRNG [WEAK]\r
+ EXPORT NVIC_Handler_AES [WEAK]\r
+ EXPORT NVIC_Handler_HASH [WEAK]\r
+ EXPORT NVIC_Handler_PECI [WEAK]\r
+ EXPORT NVIC_Handler_TACH0 [WEAK]\r
+ EXPORT NVIC_Handler_TACH1 [WEAK]\r
+ EXPORT NVIC_Handler_TACH2 [WEAK]\r
+ EXPORT NVIC_Handler_R2P0_FAIL [WEAK]\r
+ EXPORT NVIC_Handler_R2P0_STALL [WEAK]\r
+ EXPORT NVIC_Handler_R2P1_FAIL [WEAK]\r
+ EXPORT NVIC_Handler_R2P1_STALL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_SNGL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_RPT [WEAK]\r
+ EXPORT NVIC_Handler_RCID0 [WEAK]\r
+ EXPORT NVIC_Handler_RCID1 [WEAK]\r
+ EXPORT NVIC_Handler_RCID2 [WEAK]\r
+ EXPORT NVIC_Handler_LED0 [WEAK]\r
+ EXPORT NVIC_Handler_LED1 [WEAK]\r
+ EXPORT NVIC_Handler_LED2 [WEAK]\r
+ EXPORT NVIC_Handler_LED3 [WEAK]\r
+ EXPORT NVIC_Handler_PHOT [WEAK]\r
+ EXPORT NVIC_Handler_PWRGD0 [WEAK]\r
+ EXPORT NVIC_Handler_PWRGD1 [WEAK]\r
+ EXPORT NVIC_Handler_LPCBERR [WEAK]\r
+ EXPORT NVIC_Handler_QMSPI0 [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI0_TX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI0_RX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI1_TX [WEAK]\r
+ EXPORT NVIC_Handler_GPSPI1_RX [WEAK]\r
+ EXPORT NVIC_Handler_BC0_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_BC0_ERR [WEAK]\r
+ EXPORT NVIC_Handler_BC1_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_BC1_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PS2_0 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_2 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_PC [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_BM1 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_BM2 [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_LTR [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_OOB_UP [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_OOB_DN [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_FLASH [WEAK]\r
+ EXPORT NVIC_Handler_ESPI_RESET [WEAK]\r
+ EXPORT NVIC_Handler_RTMR [WEAK]\r
+ EXPORT NVIC_Handler_HTMR0 [WEAK]\r
+ EXPORT NVIC_Handler_HTMR1 [WEAK]\r
+ EXPORT NVIC_Handler_WK [WEAK]\r
+ EXPORT NVIC_Handler_WKSUB [WEAK]\r
+ EXPORT NVIC_Handler_WKSEC [WEAK]\r
+ EXPORT NVIC_Handler_WKSUBSEC [WEAK]\r
+ EXPORT NVIC_Handler_SYSPWR [WEAK]\r
+ EXPORT NVIC_Handler_RTC [WEAK]\r
+ EXPORT NVIC_Handler_RTC_ALARM [WEAK]\r
+ EXPORT NVIC_Handler_VCI_OVRD_IN [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN0 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN1 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN2 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN3 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN4 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN5 [WEAK]\r
+ EXPORT NVIC_Handler_VCI_IN6 [WEAK]\r
+ EXPORT NVIC_Handler_PS20A_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS20B_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21A_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21B_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_PS21_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_ENVMON [WEAK]\r
+ EXPORT NVIC_Handler_KEYSCAN [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_0 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_1 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_2 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR16_3 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR32_0 [WEAK]\r
+ EXPORT NVIC_Handler_BTMR32_1 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR0 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR1 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR2 [WEAK]\r
+ EXPORT NVIC_Handler_EVTMR3 [WEAK]\r
+ EXPORT NVIC_Handler_CAPTMR [WEAK]\r
+ EXPORT NVIC_Handler_CAP0 [WEAK]\r
+ EXPORT NVIC_Handler_CAP1 [WEAK]\r
+ EXPORT NVIC_Handler_CAP2 [WEAK]\r
+ EXPORT NVIC_Handler_CAP3 [WEAK]\r
+ EXPORT NVIC_Handler_CAP4 [WEAK]\r
+ EXPORT NVIC_Handler_CAP5 [WEAK]\r
+ EXPORT NVIC_Handler_CMP0 [WEAK]\r
+ EXPORT NVIC_Handler_CMP1 [WEAK]\r
+\r
+NVIC_Handler_GIRQ08\r
+NVIC_Handler_GIRQ09\r
+NVIC_Handler_GIRQ10\r
+NVIC_Handler_GIRQ11\r
+NVIC_Handler_GIRQ12\r
+NVIC_Handler_GIRQ13\r
+NVIC_Handler_GIRQ14\r
+NVIC_Handler_GIRQ15\r
+NVIC_Handler_GIRQ16\r
+NVIC_Handler_GIRQ17\r
+NVIC_Handler_GIRQ18\r
+NVIC_Handler_GIRQ19\r
+NVIC_Handler_GIRQ20\r
+NVIC_Handler_GIRQ21\r
+NVIC_Handler_GIRQ23\r
+NVIC_Handler_GIRQ24\r
+NVIC_Handler_GIRQ25\r
+NVIC_Handler_GIRQ26\r
+\r
+NVIC_Handler_I2C0\r
+NVIC_Handler_I2C1\r
+NVIC_Handler_I2C2\r
+NVIC_Handler_I2C3\r
+NVIC_Handler_DMA0\r
+NVIC_Handler_DMA1\r
+NVIC_Handler_DMA2\r
+NVIC_Handler_DMA3\r
+NVIC_Handler_DMA4\r
+NVIC_Handler_DMA5\r
+NVIC_Handler_DMA6\r
+NVIC_Handler_DMA7\r
+NVIC_Handler_DMA8\r
+NVIC_Handler_DMA9\r
+NVIC_Handler_DMA10\r
+NVIC_Handler_DMA11\r
+NVIC_Handler_DMA12\r
+NVIC_Handler_DMA13\r
+\r
+NVIC_Handler_UART0\r
+NVIC_Handler_UART1\r
+NVIC_Handler_EMI0\r
+NVIC_Handler_EMI1\r
+NVIC_Handler_EMI2\r
+NVIC_Handler_ACPI_EC0_IBF\r
+NVIC_Handler_ACPI_EC0_OBF\r
+NVIC_Handler_ACPI_EC1_IBF\r
+NVIC_Handler_ACPI_EC1_OBF\r
+NVIC_Handler_ACPI_EC2_IBF\r
+NVIC_Handler_ACPI_EC2_OBF\r
+NVIC_Handler_ACPI_EC3_IBF\r
+NVIC_Handler_ACPI_EC3_OBF\r
+NVIC_Handler_ACPI_EC4_IBF\r
+NVIC_Handler_ACPI_EC4_OBF\r
+NVIC_Handler_PM1_CTL\r
+NVIC_Handler_PM1_EN\r
+NVIC_Handler_PM1_STS\r
+NVIC_Handler_MIF8042_OBF\r
+NVIC_Handler_MIF8042_IBF\r
+NVIC_Handler_MB_H2EC\r
+NVIC_Handler_MB_DATA\r
+NVIC_Handler_P80A\r
+NVIC_Handler_P80B\r
+\r
+NVIC_Handler_PKE_ERR\r
+NVIC_Handler_PKE_END\r
+NVIC_Handler_TRNG\r
+NVIC_Handler_AES\r
+NVIC_Handler_HASH\r
+NVIC_Handler_PECI\r
+NVIC_Handler_TACH0\r
+NVIC_Handler_TACH1\r
+NVIC_Handler_TACH2\r
+NVIC_Handler_R2P0_FAIL\r
+NVIC_Handler_R2P0_STALL\r
+NVIC_Handler_R2P1_FAIL\r
+NVIC_Handler_R2P1_STALL\r
+NVIC_Handler_ADC_SNGL\r
+NVIC_Handler_ADC_RPT\r
+NVIC_Handler_RCID0\r
+NVIC_Handler_RCID1\r
+NVIC_Handler_RCID2\r
+NVIC_Handler_LED0\r
+NVIC_Handler_LED1\r
+NVIC_Handler_LED2\r
+NVIC_Handler_LED3\r
+NVIC_Handler_PHOT\r
+NVIC_Handler_PWRGD0\r
+NVIC_Handler_PWRGD1\r
+NVIC_Handler_LPCBERR\r
+NVIC_Handler_QMSPI0\r
+NVIC_Handler_GPSPI0_TX\r
+NVIC_Handler_GPSPI0_RX\r
+NVIC_Handler_GPSPI1_TX\r
+NVIC_Handler_GPSPI1_RX\r
+NVIC_Handler_BC0_BUSY\r
+NVIC_Handler_BC0_ERR\r
+NVIC_Handler_BC1_BUSY\r
+NVIC_Handler_BC1_ERR\r
+NVIC_Handler_PS2_0\r
+NVIC_Handler_PS2_1\r
+NVIC_Handler_PS2_2\r
+NVIC_Handler_ESPI_PC\r
+NVIC_Handler_ESPI_BM1\r
+NVIC_Handler_ESPI_BM2\r
+NVIC_Handler_ESPI_LTR\r
+NVIC_Handler_ESPI_OOB_UP\r
+NVIC_Handler_ESPI_OOB_DN\r
+NVIC_Handler_ESPI_FLASH\r
+NVIC_Handler_ESPI_RESET\r
+NVIC_Handler_RTMR\r
+NVIC_Handler_HTMR0\r
+NVIC_Handler_HTMR1\r
+NVIC_Handler_WK\r
+NVIC_Handler_WKSUB\r
+NVIC_Handler_WKSEC\r
+NVIC_Handler_WKSUBSEC\r
+NVIC_Handler_SYSPWR\r
+NVIC_Handler_RTC\r
+NVIC_Handler_RTC_ALARM\r
+NVIC_Handler_VCI_OVRD_IN\r
+NVIC_Handler_VCI_IN0\r
+NVIC_Handler_VCI_IN1\r
+NVIC_Handler_VCI_IN2\r
+NVIC_Handler_VCI_IN3\r
+NVIC_Handler_VCI_IN4\r
+NVIC_Handler_VCI_IN5\r
+NVIC_Handler_VCI_IN6\r
+NVIC_Handler_PS20A_WAKE\r
+NVIC_Handler_PS20B_WAKE\r
+NVIC_Handler_PS21A_WAKE\r
+NVIC_Handler_PS21B_WAKE\r
+NVIC_Handler_PS21_WAKE\r
+NVIC_Handler_ENVMON\r
+NVIC_Handler_KEYSCAN\r
+NVIC_Handler_BTMR16_0\r
+NVIC_Handler_BTMR16_1\r
+NVIC_Handler_BTMR16_2\r
+NVIC_Handler_BTMR16_3\r
+NVIC_Handler_BTMR32_0\r
+NVIC_Handler_BTMR32_1\r
+NVIC_Handler_EVTMR0\r
+NVIC_Handler_EVTMR1\r
+NVIC_Handler_EVTMR2\r
+NVIC_Handler_EVTMR3\r
+NVIC_Handler_CAPTMR\r
+NVIC_Handler_CAP0\r
+NVIC_Handler_CAP1\r
+NVIC_Handler_CAP2\r
+NVIC_Handler_CAP3\r
+NVIC_Handler_CAP4\r
+NVIC_Handler_CAP5\r
+NVIC_Handler_CMP0\r
+NVIC_Handler_CMP1\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+/*\r
+ * This file demonstrates the use of FreeRTOS-MPU. It creates tasks in both\r
+ * User mode and Privileged mode, and using both the xTaskCreate() and\r
+ * xTaskCreateRestricted() API functions. The purpose of each created task is\r
+ * documented in the comments above the task function prototype (in this file),\r
+ * with the task behaviour demonstrated and documented within the task function\r
+ * itself.\r
+ *\r
+ * In addition a queue is used to demonstrate passing data between\r
+ * protected/restricted tasks as well as passing data between an interrupt and\r
+ * a protected/restricted task. A software timer is also used.\r
+ *\r
+ * The system status is printed to ITM channel 0, where it can be viewed in the\r
+ * Keil serial/debug window (a compatible SW debug interface is required).\r
+ */\r
+\r
+/* Microchip includes. */\r
+#include "common.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "timers.h"\r
+#include "event_groups.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc constants. */\r
+#define mainDONT_BLOCK ( 0 )\r
+\r
+/* GCC specifics. */\r
+#define mainALIGN_TO( x ) __attribute__((aligned(x)))\r
+\r
+/* Hardware register addresses. */\r
+#define mainVTOR ( * ( volatile uint32_t * ) 0xE000ED08 )\r
+\r
+/* The period of the timer must be less than the rate at which\r
+configPRINT_SYSTEM_STATUS messages are sent to the check task - otherwise the\r
+check task will think the timer has stopped. */\r
+#define mainTIMER_PERIOD pdMS_TO_TICKS( 200 )\r
+\r
+/* The name of the task that is deleted by the Idle task is used in a couple of\r
+places, so is #defined. */\r
+#define mainTASK_TO_DELETE_NAME "DeleteMe"\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Prototypes for functions that implement tasks. -----------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * NOTE: The filling and checking of the registers in the following two tasks\r
+ * is only actually performed when the GCC compiler is used. Use of the\r
+ * queue to communicate with the check task is done with all compilers.\r
+ *\r
+ * Prototype for the first two register test tasks, which execute in User mode.\r
+ * Amongst other things, these fill the CPU registers (other than the FPU\r
+ * registers) with known values before checking that the registers still contain\r
+ * the expected values. Each of the two tasks use different values so an error\r
+ * in the context switch mechanism can be caught. Both tasks execute at the\r
+ * idle priority so will get preempted regularly. Each task repeatedly sends a\r
+ * message on a queue to a 'check' task so the check task knows the register\r
+ * check task is still executing and has not detected any errors. If an error\r
+ * is detected within the task the task is simply deleted so it no longer sends\r
+ * messages.\r
+ *\r
+ * For demonstration and test purposes, both tasks obtain access to the queue\r
+ * handle in different ways; vRegTest1Implementation() is created in Privileged\r
+ * mode and copies the queue handle to its local stack before setting itself to\r
+ * User mode, and vRegTest2Implementation() receives the task handle using its\r
+ * parameter.\r
+ */\r
+extern void vRegTest1Implementation( void *pvParameters );\r
+extern void vRegTest2Implementation( void *pvParameters );\r
+\r
+/*\r
+ * The second two register test tasks are similar to the first two, but do test\r
+ * the floating point registers, execute in Privileged mode, and signal their\r
+ * execution status to the 'check' task by incrementing a loop counter on each\r
+ * iteration instead of sending a message on a queue. The loop counters use a\r
+ * memory region to which the User mode 'check' task has read access.\r
+ *\r
+ * The functions ending 'Implementation' are called by the register check tasks.\r
+ */\r
+static void prvRegTest3Task( void *pvParameters );\r
+extern void vRegTest3Implementation( void );\r
+static void prvRegTest4Task( void *pvParameters );\r
+extern void vRegTest4Implementation( void );\r
+\r
+/*\r
+ * Prototype for the check task. The check task demonstrates various features\r
+ * of the MPU before entering a loop where it waits for messages to arrive on a\r
+ * queue.\r
+ *\r
+ * Two types of messages can be processes:\r
+ *\r
+ * 1) "I'm Alive" messages sent from the first two register test tasks and a\r
+ * software timer callback, as described above.\r
+ *\r
+ * 2) "Print Status commands" sent periodically by the tick hook function (and\r
+ * therefore from within an interrupt) which commands the check task to write\r
+ * either pass or fail to the terminal, depending on the status of the reg\r
+ * test tasks.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Prototype for a task created in User mode using the original vTaskCreate()\r
+ * API function. The task demonstrates the characteristics of such a task,\r
+ * before simply deleting itself.\r
+ */\r
+static void prvOldStyleUserModeTask( void *pvParameters );\r
+\r
+/*\r
+ * Prototype for a task created in Privileged mode using the original\r
+ * vTaskCreate() API function. The task demonstrates the characteristics of\r
+ * such a task, before simply deleting itself.\r
+ */\r
+static void prvOldStylePrivilegedModeTask( void *pvParameters );\r
+\r
+/*\r
+ * A task that exercises the API of various RTOS objects before being deleted by\r
+ * the Idle task. This is done for MPU API code coverage test purposes.\r
+ */\r
+static void prvTaskToDelete( void *pvParameters );\r
+\r
+/*\r
+ * Functions called by prvTaskToDelete() to exercise the MPU API.\r
+ */\r
+static void prvExerciseEventGroupAPI( void );\r
+static void prvExerciseSemaphoreAPI( void );\r
+static void prvExerciseTaskNotificationAPI( void );\r
+\r
+/*\r
+ * Just configures any clocks and IO necessary.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Simply deletes the calling task. The function is provided only because it\r
+ * is simpler to call from asm code than the normal vTaskDelete() API function.\r
+ * It has the noinline attribute because it is called from asm code.\r
+ */\r
+void vMainDeleteMe( void ) __attribute__((noinline));\r
+\r
+/*\r
+ * Used by the first two reg test tasks and a software timer callback function\r
+ * to send messages to the check task. The message just lets the check task\r
+ * know that the tasks and timer are still functioning correctly. If a reg test\r
+ * task detects an error it will delete itself, and in so doing prevent itself\r
+ * from sending any more 'I'm Alive' messages to the check task.\r
+ */\r
+void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber );\r
+\r
+/*\r
+ * The check task is created with access to three memory regions (plus its\r
+ * stack). Each memory region is configured with different parameters and\r
+ * prvTestMemoryRegions() demonstrates what can and cannot be accessed for each\r
+ * region. prvTestMemoryRegions() also demonstrates a task that was created\r
+ * as a privileged task settings its own privilege level down to that of a user\r
+ * task.\r
+ */\r
+static void prvTestMemoryRegions( void );\r
+\r
+/*\r
+ * Callback function used with the timer that uses the queue to send messages\r
+ * to the check task.\r
+ */\r
+static void prvTimerCallback( TimerHandle_t xExpiredTimer );\r
+\r
+/*\r
+ * Simple routine to print a string to ITM for viewing in the Keil serial debug\r
+ * viewer.\r
+ */\r
+static void prvITMPrintString( const char *pcString );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The handle of the queue used to communicate between tasks and between tasks\r
+and interrupts. Note that this is a global scope variable that falls outside of\r
+any MPU region. As such other techniques have to be used to allow the tasks\r
+to gain access to the queue. See the comments in the tasks themselves for\r
+further information. */\r
+QueueHandle_t xGlobalScopeCheckQueue = NULL;\r
+\r
+/* Holds the handle of a task that is deleted in the idle task hook - this is\r
+done for code coverage test purposes only. */\r
+static TaskHandle_t xTaskToDelete = NULL;\r
+\r
+/* The timer that periodically sends data to the check task on the queue. */\r
+static TimerHandle_t xTimer = NULL;\r
+\r
+#if defined ( __GNUC__ )\r
+ extern uint32_t __FLASH_segment_start__[];\r
+ extern uint32_t __FLASH_segment_end__[];\r
+ extern uint32_t __SRAM_segment_start__[];\r
+ extern uint32_t __SRAM_segment_end__[];\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __privileged_data_start__[];\r
+ extern uint32_t __privileged_data_end__[];\r
+ extern uint32_t __privileged_functions_actual_end__[];\r
+ extern uint32_t __privileged_data_actual_end__[];\r
+#else\r
+ const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0xE0000UL;\r
+ const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x100000UL;\r
+ const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x100000UL;\r
+ const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x120000;\r
+ const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0xE0000UL;\r
+ const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0xE4000UL;\r
+ const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x100000UL;\r
+ const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x100200UL;\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+/* Data used by the 'check' task. ---------------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define the constants used to allocate the check task stack. Note that the\r
+stack size is defined in words, not bytes. */\r
+#define mainCHECK_TASK_STACK_SIZE_WORDS 128\r
+#define mainCHECK_TASK_STACK_ALIGNMENT ( mainCHECK_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) )\r
+\r
+/* Declare the stack that will be used by the check task. The kernel will\r
+ automatically create an MPU region for the stack. The stack alignment must\r
+ match its size, so if 128 words are reserved for the stack then it must be\r
+ aligned to ( 128 * 4 ) bytes. */\r
+static portSTACK_TYPE xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainCHECK_TASK_STACK_ALIGNMENT );\r
+\r
+/* Declare three arrays - an MPU region will be created for each array\r
+using the TaskParameters_t structure below. THIS IS JUST TO DEMONSTRATE THE\r
+MPU FUNCTIONALITY, the data is not used by the check tasks primary function\r
+of monitoring the reg test tasks and printing out status information.\r
+\r
+Note that the arrays allocate slightly more RAM than is actually assigned to\r
+the MPU region. This is to permit writes off the end of the array to be\r
+detected even when the arrays are placed in adjacent memory locations (with no\r
+gaps between them). The align size must be a power of two. */\r
+#define mainREAD_WRITE_ARRAY_SIZE 130\r
+#define mainREAD_WRITE_ALIGN_SIZE 128\r
+char cReadWriteArray[ mainREAD_WRITE_ARRAY_SIZE ] mainALIGN_TO( mainREAD_WRITE_ALIGN_SIZE );\r
+\r
+#define mainREAD_ONLY_ARRAY_SIZE 260\r
+#define mainREAD_ONLY_ALIGN_SIZE 256\r
+char cReadOnlyArray[ mainREAD_ONLY_ARRAY_SIZE ] mainALIGN_TO( mainREAD_ONLY_ALIGN_SIZE );\r
+\r
+#define mainPRIVILEGED_ONLY_ACCESS_ARRAY_SIZE 130\r
+#define mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE 128\r
+char cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] mainALIGN_TO( mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE );\r
+\r
+/* The following two variables are used to communicate the status of the second\r
+two register check tasks (tasks 3 and 4) to the check task. If the variables\r
+keep incrementing, then the register check tasks have not discovered any errors.\r
+If a variable stops incrementing, then an error has been found. The variables\r
+overlay the array that the check task has access to so they can be read by the\r
+check task without causing a memory fault. The check task has the highest\r
+priority so will have finished with the array before the register test tasks\r
+start to access it. */\r
+volatile uint32_t *pulRegTest3LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulRegTest4LoopCounter = ( uint32_t * ) &( cReadWriteArray[ 4 ] );\r
+\r
+/* Fill in a TaskParameters_t structure to define the check task - this is the\r
+structure passed to the xTaskCreateRestricted() function. */\r
+static const TaskParameters_t xCheckTaskParameters =\r
+{\r
+ prvCheckTask, /* pvTaskCode - the function that implements the task. */\r
+ "Check", /* pcName */\r
+ mainCHECK_TASK_STACK_SIZE_WORDS, /* usStackDepth - defined in words, not bytes. */\r
+ ( void * ) 0x12121212, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */\r
+ ( tskIDLE_PRIORITY + 1 ) | portPRIVILEGE_BIT,/* uxPriority - this is the highest priority task in the system. The task is created in privileged mode to demonstrate accessing the privileged only data. */\r
+ xCheckTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+\r
+ /* xRegions - In this case the xRegions array is used to create MPU regions\r
+ for all three of the arrays declared directly above. Each MPU region is\r
+ created with different parameters. Again, THIS IS JUST TO DEMONSTRATE THE\r
+ MPU FUNCTIONALITY, the data is not used by the check tasks primary function\r
+ of monitoring the reg test tasks and printing out status information.*/\r
+ {\r
+ /* Base address Length Parameters */\r
+ { cReadWriteArray, mainREAD_WRITE_ALIGN_SIZE, portMPU_REGION_READ_WRITE },\r
+ { cReadOnlyArray, mainREAD_ONLY_ALIGN_SIZE, portMPU_REGION_READ_ONLY },\r
+ { cPrivilegedOnlyAccessArray, mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE }\r
+ }\r
+};\r
+\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Data used by the 'reg test' tasks. -----------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define the constants used to allocate the reg test task stacks. Note that\r
+that stack size is defined in words, not bytes. */\r
+#define mainREG_TEST_STACK_SIZE_WORDS 128\r
+#define mainREG_TEST_STACK_ALIGNMENT ( mainREG_TEST_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) )\r
+\r
+/* Declare the stacks that will be used by the reg test tasks. The kernel will\r
+automatically create an MPU region for the stack. The stack alignment must\r
+match its size, so if 128 words are reserved for the stack then it must be\r
+aligned to ( 128 * 4 ) bytes. */\r
+static portSTACK_TYPE xRegTest1Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT );\r
+static portSTACK_TYPE xRegTest2Stack[ mainREG_TEST_STACK_SIZE_WORDS ] mainALIGN_TO( mainREG_TEST_STACK_ALIGNMENT );\r
+\r
+/* Fill in a TaskParameters_t structure per reg test task to define the tasks. */\r
+static const TaskParameters_t xRegTest1Parameters =\r
+{\r
+ vRegTest1Implementation, /* pvTaskCode - the function that implements the task. */\r
+ "RegTest1", /* pcName */\r
+ mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */\r
+ ( void * ) configREG_TEST_TASK_1_PARAMETER, /* pvParameters - this value is just to test that the parameter is being passed into the task correctly. */\r
+ tskIDLE_PRIORITY | portPRIVILEGE_BIT, /* uxPriority - note that this task is created with privileges to demonstrate one method of passing a queue handle into the task. */\r
+ xRegTest1Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+ { /* xRegions - this task does not use any non-stack data hence all members are zero. */\r
+ /* Base address Length Parameters */\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 }\r
+ }\r
+};\r
+/*-----------------------------------------------------------*/\r
+\r
+static TaskParameters_t xRegTest2Parameters =\r
+{\r
+ vRegTest2Implementation, /* pvTaskCode - the function that implements the task. */\r
+ "RegTest2", /* pcName */\r
+ mainREG_TEST_STACK_SIZE_WORDS, /* usStackDepth */\r
+ ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */\r
+ tskIDLE_PRIORITY, /* uxPriority */\r
+ xRegTest2Stack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+ { /* xRegions - this task does not use any non-stack data hence all members are zero. */\r
+ /* Base address Length Parameters */\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 }\r
+ }\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*-----------------------------------------------------------*/\r
+/* Configures the task that is deleted. ---------------------*/\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define the constants used to allocate the stack of the task that is\r
+deleted. Note that that stack size is defined in words, not bytes. */\r
+#define mainDELETE_TASK_STACK_SIZE_WORDS 128\r
+#define mainTASK_TO_DELETE_STACK_ALIGNMENT ( mainDELETE_TASK_STACK_SIZE_WORDS * sizeof( portSTACK_TYPE ) )\r
+\r
+/* Declare the stack that will be used by the task that gets deleted. The\r
+kernel will automatically create an MPU region for the stack. The stack\r
+alignment must match its size, so if 128 words are reserved for the stack\r
+then it must be aligned to ( 128 * 4 ) bytes. */\r
+static portSTACK_TYPE xDeleteTaskStack[ mainDELETE_TASK_STACK_SIZE_WORDS ] mainALIGN_TO( mainTASK_TO_DELETE_STACK_ALIGNMENT );\r
+\r
+static TaskParameters_t xTaskToDeleteParameters =\r
+{\r
+ prvTaskToDelete, /* pvTaskCode - the function that implements the task. */\r
+ mainTASK_TO_DELETE_NAME, /* pcName */\r
+ mainDELETE_TASK_STACK_SIZE_WORDS, /* usStackDepth */\r
+ ( void * ) NULL, /* pvParameters - this task uses the parameter to pass in a queue handle, but the queue is not created yet. */\r
+ tskIDLE_PRIORITY + 1, /* uxPriority */\r
+ xDeleteTaskStack, /* puxStackBuffer - the array to use as the task stack, as declared above. */\r
+ { /* xRegions - this task does not use any non-stack data hence all members are zero. */\r
+ /* Base address Length Parameters */\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 },\r
+ { 0x00, 0x00, 0x00 }\r
+ }\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ prvITMPrintString( "Starting\r\n" );\r
+\r
+ /* Create the queue used to pass "I'm alive" messages to the check task. */\r
+ xGlobalScopeCheckQueue = xQueueCreate( 1, sizeof( uint32_t ) );\r
+\r
+ /* One check task uses the task parameter to receive the queue handle.\r
+ This allows the file scope variable to be accessed from within the task.\r
+ The pvParameters member of xRegTest2Parameters can only be set after the\r
+ queue has been created so is set here. */\r
+ xRegTest2Parameters.pvParameters = xGlobalScopeCheckQueue;\r
+\r
+ /* Create three test tasks. Handles to the created tasks are not required,\r
+ hence the second parameter is NULL. */\r
+ xTaskCreateRestricted( &xRegTest1Parameters, NULL );\r
+ xTaskCreateRestricted( &xRegTest2Parameters, NULL );\r
+ xTaskCreateRestricted( &xCheckTaskParameters, NULL );\r
+\r
+ /* Create a task that does nothing but ensure some of the MPU API functions\r
+ can be called correctly, then get deleted. This is done for code coverage\r
+ test purposes only. The task's handle is saved in xTaskToDelete so it can\r
+ get deleted in the idle task hook. */\r
+ xTaskCreateRestricted( &xTaskToDeleteParameters, &xTaskToDelete );\r
+\r
+ /* Create the tasks that are created using the original xTaskCreate() API\r
+ function. */\r
+ xTaskCreate( prvOldStyleUserModeTask, /* The function that implements the task. */\r
+ "Task1", /* Text name for the task. */\r
+ 100, /* Stack depth in words. */\r
+ NULL, /* Task parameters. */\r
+ 3, /* Priority and mode (user in this case). */\r
+ NULL /* Handle. */\r
+ );\r
+\r
+ xTaskCreate( prvOldStylePrivilegedModeTask, /* The function that implements the task. */\r
+ "Task2", /* Text name for the task. */\r
+ 100, /* Stack depth in words. */\r
+ NULL, /* Task parameters. */\r
+ ( 3 | portPRIVILEGE_BIT ), /* Priority and mode. */\r
+ NULL /* Handle. */\r
+ );\r
+\r
+ /* Create the third and fourth register check tasks, as described at the top\r
+ of this file. */\r
+ xTaskCreate( prvRegTest3Task, "Reg3", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_3_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest4Task, "Reg4", configMINIMAL_STACK_SIZE, configREG_TEST_TASK_4_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create and start the software timer. */\r
+ xTimer = xTimerCreate( "Timer", /* Test name for the timer. */\r
+ mainTIMER_PERIOD, /* Period of the timer. */\r
+ pdTRUE, /* The timer will auto-reload itself. */\r
+ ( void * ) 0, /* The timer's ID is used to count the number of times it expires - initialise this to 0. */\r
+ prvTimerCallback ); /* The function called when the timer expires. */\r
+ configASSERT( xTimer );\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+/* This task is created in privileged mode so can access the file scope\r
+queue variable. Take a stack copy of this before the task is set into user\r
+mode. Once that task is in user mode the file scope queue variable will no\r
+longer be accessible but the stack copy will. */\r
+QueueHandle_t xQueue = xGlobalScopeCheckQueue;\r
+int32_t lMessage;\r
+uint32_t ulStillAliveCounts[ 3 ] = { 0 };\r
+const char *pcStatusMessage = "PASS\r\n";\r
+uint32_t ulLastRegTest3CountValue = 0, ulLastRegTest4Value = 0;\r
+\r
+/* The register test tasks that also test the floating point registers increment\r
+a counter on each iteration of their loop. The counters are inside the array\r
+that this task has access to. */\r
+volatile uint32_t *pulOverlaidCounter3 = ( uint32_t * ) &( cReadWriteArray[ 0 ] ), *pulOverlaidCounter4 = ( uint32_t * ) &( cReadWriteArray[ 4 ] );\r
+\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Demonstrate how the various memory regions can and can't be accessed.\r
+ The task privilege level is set down to user mode within this function. */\r
+ prvTestMemoryRegions();\r
+\r
+ /* Clear overlaid reg test counters before entering the loop below. */\r
+ *pulOverlaidCounter3 = 0UL;\r
+ *pulOverlaidCounter4 = 0UL;\r
+\r
+ /* This loop performs the main function of the task, which is blocking\r
+ on a message queue then processing each message as it arrives. */\r
+ for( ;; )\r
+ {\r
+ /* Wait for the next message to arrive. */\r
+ xQueueReceive( xQueue, &lMessage, portMAX_DELAY );\r
+\r
+ switch( lMessage )\r
+ {\r
+ case configREG_TEST_1_STILL_EXECUTING :\r
+ case configREG_TEST_2_STILL_EXECUTING :\r
+ case configTIMER_STILL_EXECUTING :\r
+ /* Message from the first or second register check task, or\r
+ the timer callback function. Increment the count of the\r
+ number of times the message source has sent the message as\r
+ the message source must still be executed. */\r
+ ( ulStillAliveCounts[ lMessage ] )++;\r
+ break;\r
+\r
+ case configPRINT_SYSTEM_STATUS :\r
+ /* Message from tick hook, time to print out the system\r
+ status. If messages have stopped arriving from either of\r
+ the first two reg test task or the timer callback then the\r
+ status must be set to fail. */\r
+ if( ( ulStillAliveCounts[ 0 ] == 0 ) || ( ulStillAliveCounts[ 1 ] == 0 ) || ( ulStillAliveCounts[ 2 ] == 0 ) )\r
+ {\r
+ /* One or both of the test tasks are no longer sending\r
+ 'still alive' messages. */\r
+ pcStatusMessage = "FAIL\r\n";\r
+ }\r
+ else\r
+ {\r
+ /* Reset the count of 'still alive' messages. */\r
+ memset( ( void * ) ulStillAliveCounts, 0x00, sizeof( ulStillAliveCounts ) );\r
+ }\r
+\r
+ /* Check that the register test 3 task is still incrementing\r
+ its counter, and therefore still running. */\r
+ if( ulLastRegTest3CountValue == *pulOverlaidCounter3 )\r
+ {\r
+ pcStatusMessage = "FAIL\r\n";\r
+ }\r
+ ulLastRegTest3CountValue = *pulOverlaidCounter3;\r
+\r
+ /* Check that the register test 4 task is still incrementing\r
+ its counter, and therefore still running. */\r
+ if( ulLastRegTest4Value == *pulOverlaidCounter4 )\r
+ {\r
+ pcStatusMessage = "FAIL\r\n";\r
+ }\r
+ ulLastRegTest4Value = *pulOverlaidCounter4;\r
+\r
+ /**** print pcStatusMessage here. ****/\r
+ prvITMPrintString( pcStatusMessage );\r
+ break;\r
+\r
+ default :\r
+ /* Something unexpected happened. Delete this task so the\r
+ error is apparent (no output will be displayed). */\r
+ vMainDeleteMe();\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTestMemoryRegions( void )\r
+{\r
+int32_t x;\r
+char cTemp;\r
+\r
+ /* The check task (from which this function is called) is created in the\r
+ Privileged mode. The privileged array can be both read from and written\r
+ to while this task is privileged. */\r
+ cPrivilegedOnlyAccessArray[ 0 ] = 'a';\r
+ if( cPrivilegedOnlyAccessArray[ 0 ] != 'a' )\r
+ {\r
+ /* Something unexpected happened. Delete this task so the error is\r
+ apparent (no output will be displayed). */\r
+ vMainDeleteMe();\r
+ }\r
+\r
+ /* Writing off the end of the RAM allocated to this task will *NOT* cause a\r
+ protection fault because the task is still executing in a privileged mode.\r
+ Uncomment the following to test. */\r
+ /*cPrivilegedOnlyAccessArray[ mainPRIVILEGED_ONLY_ACCESS_ALIGN_SIZE ] = 'a';*/\r
+\r
+ /* Now set the task into user mode. */\r
+ portSWITCH_TO_USER_MODE();\r
+\r
+ /* Accessing the privileged only array will now cause a fault. Uncomment\r
+ the following line to test. */\r
+ /*cPrivilegedOnlyAccessArray[ 0 ] = 'a';*/\r
+\r
+ /* The read/write array can still be successfully read and written. */\r
+ for( x = 0; x < mainREAD_WRITE_ALIGN_SIZE; x++ )\r
+ {\r
+ cReadWriteArray[ x ] = 'a';\r
+ if( cReadWriteArray[ x ] != 'a' )\r
+ {\r
+ /* Something unexpected happened. Delete this task so the error is\r
+ apparent (no output will be displayed). */\r
+ vMainDeleteMe();\r
+ }\r
+ }\r
+\r
+ /* But attempting to read or write off the end of the RAM allocated to this\r
+ task will cause a fault. Uncomment either of the following two lines to\r
+ test. */\r
+ /* cReadWriteArray[ 0 ] = cReadWriteArray[ -1 ]; */\r
+ /* cReadWriteArray[ mainREAD_WRITE_ALIGN_SIZE ] = 0x00; */\r
+\r
+ /* The read only array can be successfully read... */\r
+ for( x = 0; x < mainREAD_ONLY_ALIGN_SIZE; x++ )\r
+ {\r
+ cTemp = cReadOnlyArray[ x ];\r
+ }\r
+\r
+ /* ...but cannot be written. Uncomment the following line to test. */\r
+ /* cReadOnlyArray[ 0 ] = 'a'; */\r
+\r
+ /* Writing to the first and last locations in the stack array should not\r
+ cause a protection fault. Note that doing this will cause the kernel to\r
+ detect a stack overflow if configCHECK_FOR_STACK_OVERFLOW is greater than\r
+ 1, hence the test is commented out by default. */\r
+ /* xCheckTaskStack[ 0 ] = 0;\r
+ xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS - 1 ] = 0; */\r
+\r
+ /* Writing off either end of the stack array should cause a protection\r
+ fault, uncomment either of the following two lines to test. */\r
+ /* xCheckTaskStack[ -1 ] = 0; */\r
+ /* xCheckTaskStack[ mainCHECK_TASK_STACK_SIZE_WORDS ] = 0; */\r
+\r
+ ( void ) cTemp;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExerciseEventGroupAPI( void )\r
+{\r
+EventGroupHandle_t xEventGroup;\r
+EventBits_t xBits;\r
+const EventBits_t xBitsToWaitFor = ( EventBits_t ) 0xff, xBitToClear = ( EventBits_t ) 0x01;\r
+\r
+ /* Exercise some event group functions. */\r
+ xEventGroup = xEventGroupCreate();\r
+ configASSERT( xEventGroup );\r
+\r
+ /* No bits should be set. */\r
+ xBits = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdFALSE, mainDONT_BLOCK );\r
+ configASSERT( xBits == ( EventBits_t ) 0 );\r
+\r
+ /* Set bits and read back to ensure the bits were set. */\r
+ xEventGroupSetBits( xEventGroup, xBitsToWaitFor );\r
+ xBits = xEventGroupGetBits( xEventGroup );\r
+ configASSERT( xBits == xBitsToWaitFor );\r
+\r
+ /* Clear a bit and read back again using a different API function. */\r
+ xEventGroupClearBits( xEventGroup, xBitToClear );\r
+ xBits = xEventGroupSync( xEventGroup, 0x00, xBitsToWaitFor, mainDONT_BLOCK );\r
+ configASSERT( xBits == ( xBitsToWaitFor & ~xBitToClear ) );\r
+\r
+ /* Finished with the event group. */\r
+ vEventGroupDelete( xEventGroup );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExerciseSemaphoreAPI( void )\r
+{\r
+SemaphoreHandle_t xSemaphore;\r
+const UBaseType_t uxMaxCount = 5, uxInitialCount = 0;\r
+\r
+ /* Most of the semaphore API is common to the queue API and is already being\r
+ used. This function uses a few semaphore functions that are unique to the\r
+ RTOS objects, rather than generic and used by queues also.\r
+\r
+ First create and use a counting semaphore. */\r
+ xSemaphore = xSemaphoreCreateCounting( uxMaxCount, uxInitialCount );\r
+ configASSERT( xSemaphore );\r
+\r
+ /* Give the semaphore a couple of times and ensure the count is returned\r
+ correctly. */\r
+ xSemaphoreGive( xSemaphore );\r
+ xSemaphoreGive( xSemaphore );\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 2 );\r
+ vSemaphoreDelete( xSemaphore );\r
+\r
+ /* Create a recursive mutex, and ensure the mutex holder and count are\r
+ returned returned correctly. */\r
+ xSemaphore = xSemaphoreCreateRecursiveMutex();\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 );\r
+ configASSERT( xSemaphore );\r
+ xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK );\r
+ xSemaphoreTakeRecursive( xSemaphore, mainDONT_BLOCK );\r
+ configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() );\r
+ configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetHandle( mainTASK_TO_DELETE_NAME ) );\r
+ xSemaphoreGiveRecursive( xSemaphore );\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );\r
+ xSemaphoreGiveRecursive( xSemaphore );\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 );\r
+ configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL );\r
+ vSemaphoreDelete( xSemaphore );\r
+\r
+ /* Create a normal mutex, and sure the mutex holder and count are returned\r
+ returned correctly. */\r
+ xSemaphore = xSemaphoreCreateMutex();\r
+ configASSERT( xSemaphore );\r
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );\r
+ xSemaphoreTake( xSemaphore, mainDONT_BLOCK );\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 ); /* Not recursive so can only be 1. */\r
+ configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == xTaskGetCurrentTaskHandle() );\r
+ xSemaphoreGive( xSemaphore );\r
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 1 );\r
+ configASSERT( xSemaphoreGetMutexHolder( xSemaphore ) == NULL );\r
+ vSemaphoreDelete( xSemaphore );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvExerciseTaskNotificationAPI( void )\r
+{\r
+uint32_t ulNotificationValue;\r
+BaseType_t xReturned;\r
+\r
+ /* The task should not yet have a notification pending. */\r
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK );\r
+ configASSERT( xReturned == pdFAIL );\r
+ configASSERT( ulNotificationValue == 0UL );\r
+\r
+ /* Exercise the 'give' and 'take' versions of the notification API. */\r
+ xTaskNotifyGive( xTaskGetCurrentTaskHandle() );\r
+ xTaskNotifyGive( xTaskGetCurrentTaskHandle() );\r
+ ulNotificationValue = ulTaskNotifyTake( pdTRUE, mainDONT_BLOCK );\r
+ configASSERT( ulNotificationValue == 2 );\r
+\r
+ /* Exercise the 'notify' and 'clear' API. */\r
+ ulNotificationValue = 20;\r
+ xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite );\r
+ ulNotificationValue = 0;\r
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, mainDONT_BLOCK );\r
+ configASSERT( xReturned == pdPASS );\r
+ configASSERT( ulNotificationValue == 20 );\r
+ xTaskNotify( xTaskGetCurrentTaskHandle(), ulNotificationValue, eSetValueWithOverwrite );\r
+ xReturned = xTaskNotifyStateClear( NULL );\r
+ configASSERT( xReturned == pdTRUE ); /* First time a notification was pending. */\r
+ xReturned = xTaskNotifyStateClear( NULL );\r
+ configASSERT( xReturned == pdFALSE ); /* Second time the notification was already clear. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskToDelete( void *pvParameters )\r
+{\r
+ /* Remove compiler warnings about unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Check the enter and exit critical macros are working correctly. If the\r
+ SVC priority is below configMAX_SYSCALL_INTERRUPT_PRIORITY then this will\r
+ fault. */\r
+ taskENTER_CRITICAL();\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Exercise the API of various RTOS objects. */\r
+ prvExerciseEventGroupAPI();\r
+ prvExerciseSemaphoreAPI();\r
+ prvExerciseTaskNotificationAPI();\r
+\r
+ /* For code coverage test purposes it is deleted by the Idle task. */\r
+ configASSERT( uxTaskGetStackHighWaterMark( NULL ) > 0 );\r
+ vTaskSuspend( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile const uint32_t *pul;\r
+volatile uint32_t ulReadData;\r
+\r
+ /* The idle task, and therefore this function, run in Supervisor mode and\r
+ can therefore access all memory. Try reading from corners of flash and\r
+ RAM to ensure a memory fault does not occur.\r
+\r
+ Start with the edges of the privileged data area. */\r
+ pul = __privileged_data_start__;\r
+ ulReadData = *pul;\r
+ pul = __privileged_data_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Next the standard SRAM area. */\r
+ pul = __SRAM_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* And the standard Flash area - the start of which is marked for\r
+ privileged access only. */\r
+ pul = __FLASH_segment_start__;\r
+ ulReadData = *pul;\r
+ pul = __FLASH_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Reading off the end of Flash or SRAM space should cause a fault.\r
+ Uncomment one of the following two pairs of lines to test. */\r
+\r
+ /* pul = __FLASH_segment_end__ + 4;\r
+ ulReadData = *pul; */\r
+\r
+ /* pul = __SRAM_segment_end__ + 1;\r
+ ulReadData = *pul; */\r
+\r
+ /* One task is created purely so it can be deleted - done for code coverage\r
+ test purposes. */\r
+ if( xTaskToDelete != NULL )\r
+ {\r
+ vTaskDelete( xTaskToDelete );\r
+ xTaskToDelete = NULL;\r
+ }\r
+\r
+ ( void ) ulReadData;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvOldStyleUserModeTask( void *pvParameters )\r
+{\r
+const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;\r
+volatile const uint32_t *pul;\r
+volatile uint32_t ulReadData;\r
+\r
+/* The following lines are commented out to prevent the unused variable\r
+compiler warnings when the tests that use the variable are also commented out. */\r
+/* extern uint32_t __privileged_functions_start__[]; */\r
+/* const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; */\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* This task is created in User mode using the original xTaskCreate() API\r
+ function. It should have access to all Flash and RAM except that marked\r
+ as Privileged access only. Reading from the start and end of the non-\r
+ privileged RAM should not cause a problem (the privileged RAM is the first\r
+ block at the bottom of the RAM memory). */\r
+ pul = __privileged_data_end__ + 1;\r
+ ulReadData = *pul;\r
+ pul = __SRAM_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Likewise reading from the start and end of the non-privileged Flash\r
+ should not be a problem (the privileged Flash is the first block at the\r
+ bottom of the Flash memory). */\r
+ pul = __privileged_functions_end__ + 1;\r
+ ulReadData = *pul;\r
+ pul = __FLASH_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Standard peripherals are accessible. */\r
+ ulReadData = *pulStandardPeripheralRegister;\r
+\r
+ /* System peripherals are not accessible. Uncomment the following line\r
+ to test. Also uncomment the declaration of pulSystemPeripheralRegister\r
+ at the top of this function.\r
+ ulReadData = *pulSystemPeripheralRegister; */\r
+\r
+ /* Reading from anywhere inside the privileged Flash or RAM should cause a\r
+ fault. This can be tested by uncommenting any of the following pairs of\r
+ lines. Also uncomment the declaration of __privileged_functions_start__\r
+ at the top of this function. */\r
+\r
+ /* pul = __privileged_functions_start__;\r
+ ulReadData = *pul; */\r
+\r
+ /*pul = __privileged_functions_end__ - 1;\r
+ ulReadData = *pul;*/\r
+\r
+ /*pul = __privileged_data_start__;\r
+ ulReadData = *pul;*/\r
+\r
+ /*pul = __privileged_data_end__ - 1;\r
+ ulReadData = *pul;*/\r
+\r
+ /* Must not just run off the end of a task function, so delete this task.\r
+ Note that because this task was created using xTaskCreate() the stack was\r
+ allocated dynamically and I have not included any code to free it again. */\r
+ vTaskDelete( NULL );\r
+\r
+ ( void ) ulReadData;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvOldStylePrivilegedModeTask( void *pvParameters )\r
+{\r
+volatile const uint32_t *pul;\r
+volatile uint32_t ulReadData;\r
+const volatile uint32_t *pulSystemPeripheralRegister = ( volatile uint32_t * ) 0xe000e014; /* Systick */\r
+/*const volatile uint32_t *pulStandardPeripheralRegister = ( volatile uint32_t * ) 0x40000000;*/\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* This task is created in Privileged mode using the original xTaskCreate()\r
+ API function. It should have access to all Flash and RAM including that\r
+ marked as Privileged access only. So reading from the start and end of the\r
+ non-privileged RAM should not cause a problem (the privileged RAM is the\r
+ first block at the bottom of the RAM memory). */\r
+ pul = __privileged_data_end__ + 1;\r
+ ulReadData = *pul;\r
+ pul = __SRAM_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Likewise reading from the start and end of the non-privileged Flash\r
+ should not be a problem (the privileged Flash is the first block at the\r
+ bottom of the Flash memory). */\r
+ pul = __privileged_functions_end__ + 1;\r
+ ulReadData = *pul;\r
+ pul = __FLASH_segment_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Reading from anywhere inside the privileged Flash or RAM should also\r
+ not be a problem. */\r
+ pul = __privileged_functions_start__;\r
+ ulReadData = *pul;\r
+ pul = __privileged_functions_end__ - 1;\r
+ ulReadData = *pul;\r
+ pul = __privileged_data_start__;\r
+ ulReadData = *pul;\r
+ pul = __privileged_data_end__ - 1;\r
+ ulReadData = *pul;\r
+\r
+ /* Finally, accessing both System and normal peripherals should both be\r
+ possible. */\r
+ ulReadData = *pulSystemPeripheralRegister;\r
+ /*ulReadData = *pulStandardPeripheralRegister;*/\r
+\r
+ /* Must not just run off the end of a task function, so delete this task.\r
+ Note that because this task was created using xTaskCreate() the stack was\r
+ allocated dynamically and I have not included any code to free it again. */\r
+ vTaskDelete( NULL );\r
+\r
+ ( void ) ulReadData;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMainDeleteMe( void )\r
+{\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMainSendImAlive( QueueHandle_t xHandle, uint32_t ulTaskNumber )\r
+{\r
+ if( xHandle != NULL )\r
+ {\r
+ xQueueSend( xHandle, &ulTaskNumber, mainDONT_BLOCK );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ extern void SystemInit( void );\r
+ extern uint32_t __Vectors[];\r
+\r
+ /* Assuming downloading code via the debugger - so ensure the hardware\r
+ is using the vector table downloaded with the application. */\r
+ mainVTOR = ( uint32_t ) __Vectors;\r
+\r
+ #if ( ( configASSERT_DEFINED == 1 ) && ( defined ( __GNUC__ ) ) )\r
+ {\r
+ /* Sanity check linker configuration sizes sections adequately. */\r
+ const uint32_t ulPrivilegedFunctionsActualEnd = ( uint32_t ) __privileged_functions_actual_end__;\r
+ const uint32_t ulPrivilegedDataActualEnd = ( uint32_t ) __privileged_data_actual_end__;\r
+ const uint32_t ulPrivilegedFunctionsEnd = ( uint32_t ) __privileged_functions_end__;\r
+ const uint32_t ulPrivilegedDataEnd = ( uint32_t ) __privileged_data_end__;\r
+\r
+ configASSERT( ulPrivilegedFunctionsActualEnd < ulPrivilegedFunctionsEnd );\r
+ configASSERT( ulPrivilegedDataActualEnd < ulPrivilegedDataEnd );\r
+\r
+ /* Clear the privileged data to 0 as the C start up code is only set to\r
+ clear the non-privileged bss. */\r
+ memset( ( void * ) __privileged_data_start__, 0x00, ( size_t ) __privileged_data_actual_end__ - ( size_t ) __privileged_data_start__ );\r
+ }\r
+ #endif\r
+\r
+ SystemInit();\r
+ SystemCoreClockUpdate();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+static uint32_t ulCallCount = 0;\r
+const uint32_t ulCallsBetweenSends = pdMS_TO_TICKS( 5000 );\r
+const uint32_t ulMessage = configPRINT_SYSTEM_STATUS;\r
+portBASE_TYPE xDummy;\r
+\r
+ /* If configUSE_TICK_HOOK is set to 1 then this function will get called\r
+ from each RTOS tick. It is called from the tick interrupt and therefore\r
+ will be executing in the privileged state. */\r
+\r
+ ulCallCount++;\r
+\r
+ /* Is it time to print out the pass/fail message again? */\r
+ if( ulCallCount >= ulCallsBetweenSends )\r
+ {\r
+ ulCallCount = 0;\r
+\r
+ /* Send a message to the check task to command it to check that all\r
+ the tasks are still running then print out the status.\r
+\r
+ This is running in an ISR so has to use the "FromISR" version of\r
+ xQueueSend(). Because it is in an ISR it is running with privileges\r
+ so can access xGlobalScopeCheckQueue directly. */\r
+ xQueueSendFromISR( xGlobalScopeCheckQueue, &ulMessage, &xDummy );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ /* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this\r
+ function will automatically get called if a task overflows its stack. */\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will\r
+ be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()\r
+ is called automatically when a task, queue or semaphore is created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTimerCallback( TaskHandle_t xExpiredTimer )\r
+{\r
+uint32_t ulCount;\r
+\r
+ /* The count of the number of times this timer has expired is saved in the\r
+ timer's ID. Obtain the current count. */\r
+ ulCount = ( uint32_t ) pvTimerGetTimerID( xTimer );\r
+\r
+ /* Increment the count, and save it back into the timer's ID. */\r
+ ulCount++;\r
+ vTimerSetTimerID( xTimer, ( void * ) ulCount );\r
+\r
+ /* Let the check task know the timer is still running. */\r
+ vMainSendImAlive( xGlobalScopeCheckQueue, configTIMER_STILL_EXECUTING );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
+used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+ state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Timer task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xTimerTaskTCB;\r
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvITMPrintString( const char *pcString )\r
+{\r
+ while( *pcString != 0x00 )\r
+ {\r
+ ITM_SendChar( *pcString );\r
+ pcString++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest3Task( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == configREG_TEST_TASK_3_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest3Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest4Task( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == configREG_TEST_TASK_4_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest4Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * ARM_REG.h\r
+ * This is the header to define Cortex-M3 system control & status registers\r
+ **********************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/ARM_REG.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2016/09/22 08:03:49 $\r
+ * AUTHOR: $Author: pramans $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+/******************************************************************************/\r
+/** @defgroup ARM_REG ARM_REG\r
+ * @{\r
+ */\r
+\r
+/** @file ARM_REG.h\r
+* \brief ARM Cortex-M3 registers header file\r
+* \author KBCEC Team\r
+* \r
+* This file contains ARM Cortex-M3 system control & status registers.\r
+******************************************************************************/ \r
+#ifndef ARM_REG_H_\r
+#define ARM_REG_H_\r
+\r
+#define REG8(x) (*((volatile unsigned char *)(x)))\r
+#define REG16(x) (*((volatile unsigned short *)(x)))\r
+#define REG32(x) (*((volatile unsigned long *)(x)))\r
+\r
+/* NVIC Registers */\r
+#define NVIC_INT_TYPE REG32(0xE000E004)\r
+#define NVIC_AUX_ACTLR REG32(0xE000E008)\r
+ #define WR_BUF_DISABLE (1 << 1)\r
+#define NVIC_ST_CTRL REG32(0xE000E010)\r
+ #define ST_ENABLE (1 << 0)\r
+ #define ST_TICKINT (1 << 1)\r
+ #define ST_CLKSOURCE (1 << 2)\r
+ #define ST_COUNTFLAG (1 << 3)\r
+#define NVIC_ST_RELOAD REG32(0xE000E014)\r
+#define NVIC_ST_CURRENT REG32(0xE000E018)\r
+#define NVIC_ST_CALIB REG32(0xE000E01C)\r
+#define NVIC_ENABLE0 REG32(0xE000E100)\r
+#define NVIC_ENABLE1 REG32(0xE000E104)\r
+#define NVIC_ENABLE2 REG32(0xE000E108)\r
+#define NVIC_ENABLE3 REG32(0xE000E10C)\r
+#define NVIC_ENABLE4 REG32(0xE000E110)\r
+#define NVIC_ENABLE5 REG32(0xE000E114)\r
+#define NVIC_ENABLE6 REG32(0xE000E118)\r
+#define NVIC_ENABLE7 REG32(0xE000E11C)\r
+#define NVIC_DISABLE0 REG32(0xE000E180)\r
+#define NVIC_DISABLE1 REG32(0xE000E184)\r
+#define NVIC_DISABLE2 REG32(0xE000E188)\r
+#define NVIC_DISABLE3 REG32(0xE000E18C)\r
+#define NVIC_DISABLE4 REG32(0xE000E190)\r
+#define NVIC_DISABLE5 REG32(0xE000E194)\r
+#define NVIC_DISABLE6 REG32(0xE000E198)\r
+#define NVIC_DISABLE7 REG32(0xE000E19C)\r
+#define NVIC_PEND0 REG32(0xE000E200)\r
+#define NVIC_PEND1 REG32(0xE000E204)\r
+#define NVIC_PEND2 REG32(0xE000E208)\r
+#define NVIC_PEND3 REG32(0xE000E20C)\r
+#define NVIC_PEND4 REG32(0xE000E210)\r
+#define NVIC_PEND5 REG32(0xE000E214)\r
+#define NVIC_PEND6 REG32(0xE000E218)\r
+#define NVIC_PEND7 REG32(0xE000E21C)\r
+#define NVIC_UNPEND0 REG32(0xE000E280)\r
+#define NVIC_UNPEND1 REG32(0xE000E284)\r
+#define NVIC_UNPEND2 REG32(0xE000E288)\r
+#define NVIC_UNPEND3 REG32(0xE000E28C)\r
+#define NVIC_UNPEND4 REG32(0xE000E290)\r
+#define NVIC_UNPEND5 REG32(0xE000E294)\r
+#define NVIC_UNPEND6 REG32(0xE000E298)\r
+#define NVIC_UNPEND7 REG32(0xE000E29C)\r
+#define NVIC_ACTIVE0 REG32(0xE000E300)\r
+#define NVIC_ACTIVE1 REG32(0xE000E304)\r
+#define NVIC_ACTIVE2 REG32(0xE000E308)\r
+#define NVIC_ACTIVE3 REG32(0xE000E30C)\r
+#define NVIC_ACTIVE4 REG32(0xE000E310)\r
+#define NVIC_ACTIVE5 REG32(0xE000E314)\r
+#define NVIC_ACTIVE6 REG32(0xE000E318)\r
+#define NVIC_ACTIVE7 REG32(0xE000E31C)\r
+#define NVIC_PRI0 REG32(0xE000E400)\r
+#define NVIC_PRI1 REG32(0xE000E404)\r
+#define NVIC_PRI2 REG32(0xE000E408)\r
+#define NVIC_PRI3 REG32(0xE000E40C)\r
+#define NVIC_PRI4 REG32(0xE000E410)\r
+#define NVIC_PRI5 REG32(0xE000E414)\r
+#define NVIC_PRI6 REG32(0xE000E418)\r
+#define NVIC_PRI7 REG32(0xE000E41C)\r
+#define NVIC_PRI8 REG32(0xE000E420)\r
+#define NVIC_PRI9 REG32(0xE000E424)\r
+#define NVIC_PRI10 REG32(0xE000E428)\r
+#define NVIC_PRI11 REG32(0xE000E42C)\r
+#define NVIC_PRI12 REG32(0xE000E430)\r
+#define NVIC_PRI13 REG32(0xE000E434)\r
+#define NVIC_PRI14 REG32(0xE000E438)\r
+#define NVIC_PRI15 REG32(0xE000E43C)\r
+#define NVIC_PRI16 REG32(0xE000E440)\r
+#define NVIC_PRI17 REG32(0xE000E444)\r
+#define NVIC_PRI18 REG32(0xE000E448)\r
+#define NVIC_PRI19 REG32(0xE000E44C)\r
+#define NVIC_PRI20 REG32(0xE000E450)\r
+#define NVIC_PRI21 REG32(0xE000E454)\r
+#define NVIC_PRI22 REG32(0xE000E458)\r
+#define NVIC_PRI23 REG32(0xE000E45C)\r
+#define NVIC_PRI24 REG32(0xE000E460)\r
+#define NVIC_PRI25 REG32(0xE000E464)\r
+#define NVIC_PRI26 REG32(0xE000E468)\r
+#define NVIC_PRI27 REG32(0xE000E46C)\r
+#define NVIC_PRI28 REG32(0xE000E470)\r
+#define NVIC_PRI29 REG32(0xE000E474)\r
+#define NVIC_PRI30 REG32(0xE000E478)\r
+#define NVIC_PRI31 REG32(0xE000E47C)\r
+#define NVIC_PRI32 REG32(0xE000E480)\r
+#define NVIC_PRI33 REG32(0xE000E484)\r
+#define NVIC_PRI34 REG32(0xE000E488)\r
+#define NVIC_PRI35 REG32(0xE000E48C)\r
+#define NVIC_PRI36 REG32(0xE000E490)\r
+#define NVIC_PRI37 REG32(0xE000E494)\r
+#define NVIC_PRI38 REG32(0xE000E498)\r
+#define NVIC_PRI39 REG32(0xE000E49C)\r
+#define NVIC_PRI40 REG32(0xE000E4A0)\r
+#define NVIC_PRI41 REG32(0xE000E4A4)\r
+#define NVIC_PRI42 REG32(0xE000E4A8)\r
+#define NVIC_PRI43 REG32(0xE000E4AC)\r
+#define NVIC_PRI44 REG32(0xE000E4B0)\r
+#define NVIC_PRI45 REG32(0xE000E4B4)\r
+#define NVIC_PRI46 REG32(0xE000E4B8)\r
+#define NVIC_PRI47 REG32(0xE000E4BC)\r
+#define NVIC_PRI48 REG32(0xE000E4C0)\r
+#define NVIC_PRI49 REG32(0xE000E4C4)\r
+#define NVIC_PRI50 REG32(0xE000E4C8)\r
+#define NVIC_PRI51 REG32(0xE000E4CC)\r
+#define NVIC_PRI52 REG32(0xE000E4D0)\r
+#define NVIC_PRI53 REG32(0xE000E4D4)\r
+#define NVIC_PRI54 REG32(0xE000E4D8)\r
+#define NVIC_PRI55 REG32(0xE000E4DC)\r
+#define NVIC_PRI56 REG32(0xE000E4E0)\r
+#define NVIC_PRI57 REG32(0xE000E4E4)\r
+#define NVIC_PRI58 REG32(0xE000E4E8)\r
+#define NVIC_PRI59 REG32(0xE000E4EC)\r
+#define NVIC_CPUID REG32(0xE000ED00)\r
+#define NVIC_INT_CTRL REG32(0xE000ED04)\r
+#define NVIC_VECT_TABLE REG32(0xE000ED08)\r
+#define NVIC_AP_INT_RST REG32(0xE000ED0C)\r
+#define NVIC_SYS_CTRL REG32(0xE000ED10)\r
+#define NVIC_CFG_CTRL REG32(0xE000ED14)\r
+#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)\r
+#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)\r
+#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)\r
+#define NVIC_SYS_H_CTRL REG32(0xE000ED24)\r
+#define NVIC_FAULT_STA REG32(0xE000ED28)\r
+#define NVIC_HARD_F_STA REG32(0xE000ED2C)\r
+#define NVIC_DBG_F_STA REG32(0xE000ED30)\r
+#define NVIC_MM_F_ADR REG32(0xE000ED34)\r
+#define NVIC_BUS_F_ADR REG32(0xE000ED38)\r
+#define NVIC_SW_TRIG REG32(0xE000EF00)\r
+\r
+/* MPU Registers */\r
+#define MPU_TYPE REG32(0xE000ED90)\r
+#define MPU_CTRL REG32(0xE000ED94)\r
+#define MPU_RG_NUM REG32(0xE000ED98)\r
+#define MPU_RG_ADDR REG32(0xE000ED9C)\r
+#define MPU_RG_AT_SZ REG32(0xE000EDA0)\r
+\r
+\r
+#endif /* #ifndef ARM_REG_H_ */\r
+\r
+/** @}\r
+ */\r
--- /dev/null
+\r
+/****************************************************************************************************//**\r
+ * @file MCHP_device_header.h\r
+ *\r
+ * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
+ * MCHP_device_header from Microchip Technology Inc..\r
+ *\r
+ * @version V1.0\r
+ * @date 5. November 2015\r
+ *\r
+ * @note Generated with SVDConv V2.87e \r
+ * from CMSIS SVD File 'MCHP_device_header.svd' Version 1.0,\r
+ *\r
+ * @par ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontroller, but can be equally used for other\r
+ * suitable processor architectures. This file can be freely distributed.\r
+ * Modifications to this file shall be clearly marked.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. \r
+ *\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Microchip Technology Inc.\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MCHP_device_header\r
+ * @{\r
+ */\r
+\r
+#ifndef MCHP_DEVICE_HEADER_H\r
+#define MCHP_DEVICE_HEADER_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* ------------------------- Interrupt Number Definition ------------------------ */\r
+\r
+typedef enum {\r
+/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */\r
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation\r
+ and No Match */\r
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
+ related Fault */\r
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+/* ----------------Device Specific Interrupt Numbers---------------- */\r
+ GPIO_140_176_IRQn = 0, /*!< 0 GPIO[140:176], GIRQ08 */\r
+ GPIO_100_137_IRQn = 1, /*!< 1 GPIO[100:137], GIRQ09 */\r
+ GPIO_040_076_IRQn = 2, /*!< 2 GPIO[040:076], GIRQ10 */\r
+ GPIO_000_036_IRQn = 3, /*!< 3 GPIO[000:036], GIRQ11 */\r
+ GPIO_200_236_IRQn = 4, /*!< 4 GPIO[200:236], GIRQ12 */\r
+ MSVW00_06_IRQn = 15, /*!< 15 MSVW[00:06]_SRC[0:3], GIRQ 24 */\r
+ MSVW07_10_IRQn = 16, /*!< 16 MSVW[07:10]_SRC[0:3], GIRQ 25 */\r
+ GPIO_240_257_IRQn = 17, /*!< 17 GPIO[240:257], GIRQ26 */\r
+ SMB0_IRQn = 20, /*!< 20 SMB0, GIRQ 13.0 */\r
+ SMB1_IRQn = 21, /*!< 21 SMB1 */\r
+ SMB2_IRQn = 22, /*!< 22 SMB2 */\r
+ SMB3_IRQn = 23, /*!< 23 SMB3 */\r
+ DMA0_IRQn = 24, /*!< 24 DMA0, GIRQ14.0 */\r
+ DMA1_IRQn = 25, /*!< 25 DMA1 */\r
+ DMA2_IRQn = 26, /*!< 26 DMA2 */\r
+ DMA3_IRQn = 27, /*!< 27 DMA3 */\r
+ DMA4_IRQn = 28, /*!< 28 DMA4 */\r
+ DMA5_IRQn = 29, /*!< 29 DMA5 */\r
+ DMA6_IRQn = 30, /*!< 30 DMA6 */\r
+ DMA7_IRQn = 31, /*!< 31 DMA7 */\r
+ DMA8_IRQn = 32, /*!< 32 DMA8 */\r
+ DMA9_IRQn = 33, /*!< 33 DMA9 */\r
+ DMA10_IRQn = 34, /*!< 34 DMA10 */\r
+ DMA11_IRQn = 35, /*!< 35 DMA11 */\r
+ DMA12_IRQn = 36, /*!< 36 DMA12 */\r
+ DMA13_IRQn = 37, /*!< 37 DMA13 */\r
+ UART_0_IRQn = 40, /*!< 40 UART 0, GIRQ 15.0 */\r
+ UART_1_IRQn = 41, /*!< 41 UART 1, GIRQ 15.1 */\r
+ EMI_0_IRQn = 42, /*!< 42 EMI_0, GIRQ 15.2 */\r
+ EMI_1_IRQn = 43, /*!< 43 EMI_1, GIRQ 15.3 */\r
+ EMI_2_IRQn = 44, /*!< 44 EMI_2, GIRQ 15.4 */\r
+ ACPIEC0_IBF_IRQn = 45, /*!< 45 ACPIEC[0] IBF, GIRQ 15.5 */\r
+ ACPIEC0_OBF_IRQn = 46, /*!< 46 ACPIEC[0] OBF, GIRQ 15.6 */\r
+ ACPIEC1_IBF_IRQn = 47, /*!< 47 ACPIEC[1] IBF, GIRQ 15.7 */\r
+ ACPIEC1_OBF_IRQn = 48, /*!< 48 ACPIEC[1] OBF, GIRQ 15.8 */\r
+ ACPIEC2_IBF_IRQn = 49, /*!< 49 ACPIEC[2] IBF, GIRQ 15.9 */\r
+ ACPIEC2_OBF_IRQn = 50, /*!< 50 ACPIEC[2] OBF, GIRQ 15.10 */\r
+ ACPIEC3_IBF_IRQn = 51, /*!< 51 ACPIEC[3] IBF, GIRQ 15.11 */\r
+ ACPIEC3_OBF_IRQn = 52, /*!< 52 ACPIEC[3] OBF, GIRQ 15.12 */\r
+ ACPIEC4_IBF_IRQn = 53, /*!< 53 ACPIEC[4] IBF, GIRQ 15.13 */\r
+ ACPIEC4_OBF_IRQn = 54, /*!< 54 ACPIEC[4] OBF, GIRQ 15.14 */\r
+ ACPIPM1_CTL_IRQn = 55, /*!< 55 ACPIPM1_CTL, GIRQ 15.10 */\r
+ ACPIPM1_EN_IRQn = 56, /*!< 56 ACPIPM1_EN, GIRQ 15.11 */\r
+ ACPIPM1_STS_IRQn = 57, /*!< 57 ACPIPM1_STS, GIRQ 15.12 */\r
+ KBC8042_OBF_IRQn = 58, /*!< 58 8042EM OBF, GIRQ 15.18 */\r
+ KBC8042_IBF_IRQn = 59, /*!< 59 8042EM IBF, GIRQ 15.19 */\r
+ MAILBOX_IRQn = 60, /*!< 60 MAILBOX, GIRQ 15.20 */\r
+ MAILBOX_DATA_IRQn = 61, /*!< 61 MAILBOX DATA, GIRQ 15.21 */\r
+ PORT80_DEBUG_0_IRQn = 62, /*!< 62 PORT80_DEBUG_0, GIRQ 15.22 */\r
+ PORT80_DEBUG_1_IRQn = 63, /*!< 63 PORT80_DEBUG_1, GIRQ 15.23 */\r
+ ASIF_INT_IRQn = 64, /*!< 64 ASIF_INT, GIRQ 15.24 */\r
+ PECIHOST_IRQn = 70, /*!< 70 PECIHOST, GIRQ 17.0 */\r
+ TACH_0_IRQn = 71, /*!< 71 TACH_0, GIRQ 17.1 */\r
+ TACH_1_IRQn = 72, /*!< 72 TACH_1, GIRQ 17.2 */\r
+ TACH_2_IRQn = 73, /*!< 73 TACH_2, GIRQ 17.3 */\r
+ RPM2PWM_0_FAIL_IRQn = 74, /*!< 74 RPM2PWM_0 Fail, GIRQ 17.4 */\r
+ RPM2PWM_0_STALL_IRQn = 75, /*!< 75 RPM2PWM_0 Stall, GIRQ 17.5 */\r
+ RPM2PWM_1_FAIL_IRQn = 76, /*!< 76 RPM2PWM_1 Fail, GIRQ 17.6 */\r
+ RPM2PWM_1_STALL_IRQn = 77, /*!< 77 RPM2PWM_1 Stall, GIRQ 17.7 */\r
+ ADC_SNGL_IRQn = 78, /*!< 78 ADC_SNGL, GIRQ 17.8 */\r
+ ADC_RPT_IRQn = 79, /*!< 79 ADC_RPT, GIRQ 17.9 */\r
+ RC_ID_0_IRQn = 80, /*!< 80 RC_ID_0, GIRQ 17.10 */\r
+ RC_ID_1_IRQn = 81, /*!< 81 RC_ID_1, GIRQ 17.11 */\r
+ RC_ID_2_IRQn = 82, /*!< 82 RC_ID_2, GIRQ 17.12 */\r
+ LED_0_IRQn = 83, /*!< 83 Breathing LED 0, GIRQ 17.13 */\r
+ LED_1_IRQn = 84, /*!< 84 Breathing LED 1, GIRQ 17.14 */\r
+ LED_2_IRQn = 85, /*!< 85 Breathing LED 2, GIRQ 17.15 */\r
+ LED_3_IRQn = 86, /*!< 86 Breathing LED 3, GIRQ 17.16 */\r
+ PROCHOT_MON_IRQn = 87, /*!< 87 PROCHOT_MON, GIRQ 17.17 */\r
+ POWERGUARD_0_IRQn = 88, /*!< 88 POWERGUARD_0, GIRQ 17.18 */\r
+ POWERGUARD_1_IRQn = 89, /*!< 89 POWERGUARD_1, GIRQ 17.19 */\r
+ LPC_IRQn = 90, /*!< 90 LPC (GIRQ 18.0) */\r
+ QMSPI_IRQn = 91, /*!< 91 QMSPI, GIRQ 18.1 */\r
+ SPI0_TX_IRQn = 92, /*!< 92 SPI0 TX, GIRQ 18.2 */\r
+ SPI0_RX_IRQn = 93, /*!< 93 SPI0 RX, GIRQ 18.3 */\r
+ SPI1_TX_IRQn = 94, /*!< 94 SPI1 TX, GIRQ 18.4 */\r
+ SPI1_RX_IRQn = 95, /*!< 95 SPI1 RX, GIRQ 18.5 */\r
+ BCM_BUSY_CLR_0_IRQn = 96, /*!< 96 BCM_BUSY_CLR_0, GIRQ 18.6 */\r
+ BCM_ERR_0_IRQn = 97, /*!< 97 BCM_ERR_0, GIRQ 18.7 */\r
+ BCM_BUSY_CLR_1_IRQn = 98, /*!< 98 BCM_BUSY_CLR_1, GIRQ 18.8 */\r
+ BCM_ERR_1_IRQn = 99, /*!< 99 BCM_ERR_1, GIRQ 18.9 */\r
+ PS2_0_ACT_IRQn = 100, /*!< 100 PS2 Controller 0 Activity, GIRQ 17.14 */\r
+ PS2_1_ACT_IRQn = 101, /*!< 101 PS2 Controller 1 Activity, GIRQ 17.15 */\r
+ PS2_2_ACT_IRQn = 102, /*!< 102 PS2 Controller 2 Activity, GIRQ 17.16 */\r
+ INTR_PC_IRQn = 103, /*!< 103 PC, GIRQ 19.0 */\r
+ INTR_BM1_IRQn = 104, /*!< 104 BM1, GIRQ 19.1 */\r
+ INTR_BM2_IRQn = 105, /*!< 105 BM2, GIRQ 19.2 */\r
+ INTR_LTR_IRQn = 106, /*!< 106 LTR, GIRQ 19.3 */\r
+ INTR_OOB_UP_IRQn = 107, /*!< 107 OOB_UP, GIRQ 19.4 */\r
+ INTR_OOB_DOWN_IRQn = 108, /*!< 108 OOB_DOWN, GIRQ 19.5 */\r
+ INTR_FLASH_IRQn = 109, /*!< 109 FLASH, GIRQ 19.6 */\r
+ ESPI_RESET_IRQn = 110, /*!< 110 ESPI_RESET, GIRQ 19.7 */\r
+ RTOS_TIMER_IRQn = 111, /*!< 111 RTOS_TIMER, GIRQ 21.0 */\r
+ HTIMER0_IRQn = 112, /*!< 112 HTIMER0, GIRQ 21.1 */\r
+ HTIMER1_IRQn = 113, /*!< 113 HTIMER1, GIRQ 21.2 */\r
+ WEEK_ALARM_IRQn = 114, /*!< 114 WEEK_ALARM_INT, GIRQ 21.3 */\r
+ SUB_WEEK_ALARM_IRQn = 115, /*!< 115 SUB_WEEK_ALARM_INT, GIRQ 21.4 */\r
+ ONE_SECOND_IRQn = 116, /*!< 116 ONE_SECOND, GIRQ 21.5 */\r
+ SUB_SECOND_IRQn = 117, /*!< 117 SUB_SECOND, GIRQ 21.6 */\r
+ SYSPWR_PRES_IRQn = 118, /*!< 118 SYSPWR_PRES, GIRQ 21.7 */\r
+ RTC_IRQn = 119, /*!< 119 RTC, GIRQ 21.8 */\r
+ RTC_ALARM_IRQn = 120, /*!< 120 RTC ALARM, GIRQ 21.9 */\r
+ VCI_OVRD_IN_IRQn = 121, /*!< 121 VCI_OVRD_IN, GIRQ 21.10 */\r
+ VCI_IN0_IRQn = 122, /*!< 122 VCI_IN0, GIRQ 21.11 */\r
+ VCI_IN1_IRQn = 123, /*!< 123 VCI_IN1, GIRQ 21.12 */\r
+ VCI_IN2_IRQn = 124, /*!< 124 VCI_IN2, GIRQ 21.13 */\r
+ VCI_IN3_IRQn = 125, /*!< 125 VCI_IN3, GIRQ 21.14 */\r
+ VCI_IN4_IRQn = 126, /*!< 126 VCI_IN4, GIRQ 21.15 */\r
+ VCI_IN5_IRQn = 127, /*!< 127 VCI_IN5, GIRQ 21.16 */\r
+ VCI_IN6_IRQn = 128, /*!< 128 VCI_IN6, GIRQ 21.17 */\r
+ PS2_0A_WK_IRQn = 129, /*!< 129 PS2 Controller 0 Port A Wake, GIRQ 21.18 */\r
+ PS2_0B_WK_IRQn = 130, /*!< 130 PS2 Controller 0 Port B Wake, GIRQ 21.19 */\r
+ PS2_1A_WK_IRQn = 131, /*!< 131 PS2 Controller 1 Port A Wake, GIRQ 21.20 */\r
+ PS2_1B_WK_IRQn = 132, /*!< 132 PS2 Controller 1 Port B Wake, GIRQ 21.21 */\r
+ PS2_2_WK_IRQn = 133, /*!< 133 PS2 Controller 2 Wake, GIRQ 21.22 */\r
+ KSC_INT_IRQn = 135, /*!< 135 KSC, GIRQ 21.25 */\r
+ TIMER0_IRQn = 136, /*!< 136 TIMER_16_0, GIRQ 23.0 */\r
+ TIMER1_IRQn = 137, /*!< 137 TIMER_16_1, GIRQ 23.1 */\r
+ TIMER2_IRQn = 138, /*!< 138 TIMER_16_2, GIRQ 23.2 */\r
+ TIMER3_IRQn = 139, /*!< 139 TIMER_16_3, GIRQ 23.3 */\r
+ TIMER4_IRQn = 140, /*!< 140 TIMER_32_0, GIRQ 23.4 */\r
+ TIMER5_IRQn = 141, /*!< 141 TIMER_32_1, GIRQ 23.5 */\r
+ COUNTER_TIMER_0_IRQn = 142, /*!< 142 COUNTER_TIMER_0, GIRQ 23.6 */\r
+ COUNTER_TIMER_1_IRQn = 143, /*!< 143 COUNTER_TIMER_1, GIRQ 23.7 */\r
+ COUNTER_TIMER_2_IRQn = 144, /*!< 144 COUNTER_TIMER_2, GIRQ 23.8 */\r
+ COUNTER_TIMER_3_IRQn = 145, /*!< 145 COUNTER_TIMER_3, GIRQ 23.9 */\r
+ CAPTURE_TIMER_IRQn = 146, /*!< 146 CAPTURE_TIMER, GIRQ 23.10 */\r
+ CAPTURE_0_IRQn = 147, /*!< 147 CAPTURE_0, GIRQ 23.11 */\r
+ CAPTURE_1_IRQn = 148, /*!< 148 CAPTURE_1, GIRQ 23.12 */\r
+ CAPTURE_2_IRQn = 149, /*!< 149 CAPTURE_2, GIRQ 23.13 */\r
+ CAPTURE_3_IRQn = 150, /*!< 150 CAPTURE_3, GIRQ 23.14 */\r
+ CAPTURE_4_IRQn = 151, /*!< 151 CAPTURE_4, GIRQ 23.15 */\r
+ CAPTURE_5_IRQn = 152, /*!< 152 CAPTURE_5, GIRQ 23.16 */\r
+ COMPARE_0_IRQn = 153, /*!< 153 COMPARE_0, GIRQ 23.17 */\r
+ COMPARE_1_IRQn = 154, /*!< 154 COMPARE_1, GIRQ 23.18 */\r
+ EEPROM_IRQn = 155, /*!< 155 EEPROM, GIRQ 18.13 */\r
+ VWIRE_ENABLE_IRQn = 156, /*!< 156 VWIRE_ENABLE, GIRQ 19.8 */\r
+ MAX_IRQn\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+ * @{\r
+ */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Processor and Core Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
+#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */\r
+#define __MPU_PRESENT 1 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present or not */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
+\r
+/* ================================================================================ */\r
+/* ================ Custom Defines (added manually) ================ */\r
+/* ================================================================================ */\r
+\r
+/* Register Union */\r
+typedef union\r
+{\r
+ uint32_t w;\r
+ uint16_t h[2];\r
+ uint8_t b[4];\r
+} REG32_U;\r
+\r
+/* ================================================================================ */\r
+/* ================ Device Specific Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+ * @{\r
+ */\r
+\r
+\r
+/* ------------------- Start of section using anonymous unions ------------------ */\r
+#if defined(__CC_ARM)\r
+ #pragma push\r
+ #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+ #pragma language=extended\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning 586\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PCR ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Power, Clocks, and Resets (PCR) Section identifies all the power supplies,\r
+ clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40080100) PCR Structure */\r
+ \r
+ union {\r
+ __IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control */\r
+ \r
+ struct {\r
+ __IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode */\r
+ uint32_t : 1;\r
+ __IO uint32_t TEST : 1; /*!< [2..2] Test bit */\r
+ __IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode */\r
+ } SYS_SLP_CNTRL_b; /*!< [4] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Register [7:0] Processor\r
+ Clock Divide Value (PROC_DIV)\r
+ 1: divide 48 MHz Ring Oscillator by 1.\r
+ 2: divide 48 MHz Ring Oscillator by 2.\r
+ 3: divide 48 MHz Ring Oscillator by 3.\r
+ 4: divide 48 MHz Ring Oscillator by 4.\r
+ 16: divide 48 MHz Ring Oscillator by 16.\r
+ 48: divide 48 MHz Ring Oscillator by 48.\r
+ No other values are supported. */\r
+ \r
+ struct {\r
+ __IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate */\r
+ } PROC_CLK_CNTRL_b; /*!< [8] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock domain */\r
+ \r
+ struct {\r
+ __IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Clock off */\r
+ } SLOW_CLK_CNTRL_b; /*!< [10] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register */\r
+ \r
+ struct {\r
+ __IO uint32_t TEST : 8; /*!< [0..7] Test bits */\r
+ __IO uint32_t PLL_LOCK : 1; /*!< [8..8] PLL Lock Status */\r
+ } OSC_ID_b; /*!< [9] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t PCR_PWR_RST_STS; /*!< (@ 0x40080110) PCR Power Reset Status Register */\r
+ \r
+ struct {\r
+ uint32_t : 2;\r
+ __I uint32_t VCC_PWRGD_STATUS: 1; /*!< [2..2] Indicates the status of VCC_PWRGD. 0 = PWRGD not asserted.\r
+ 1 = PWRGD asserte. */\r
+ __I uint32_t RESET_HOST_STATUS: 1; /*!< [3..3] Indicates the status of RESET_VCC. 0 = reset active.\r
+ 1 = reset not active. */\r
+ uint32_t : 1;\r
+ __IO uint32_t VBAT_RESET_STATUS: 1; /*!< [5..5] VBAT reset status 0 = No reset occurred while VTR was\r
+ off or since the last time this bit was cleared. 1 = A reset\r
+ occurred.(R/WC) */\r
+ __IO uint32_t VTR_RESET_STATUS: 1; /*!< [6..6] Indicates the status of VTR_RESET.(R/WC)\r
+ 0 = No reset occurred since the last time this bit was cleared.\r
+ 1 = A reset occurred. */\r
+ __IO uint32_t JTAG_RESET_STATUS: 1; /*!< [7..7] Indicates s RESET_SYS was triggered by a JTAG action.(R/WC)\r
+ 0 = No JTAG reset occurred since the last time this bit was\r
+ cleared.\r
+ 1 = A reset occurred because of a JATAG command. */\r
+ uint32_t : 2;\r
+ __I uint32_t _32K_ACTIVE: 1; /*!< [10..10] 32K_ACTIVE (32K_ACTIVE) */\r
+ __I uint32_t PCICLK_ACTIVE: 1; /*!< [11..11] PCICLK_ACTIVE (PCICLK_ACTIVE) */\r
+ __I uint32_t ESPI_CLK_ACTIVE: 1; /*!< [12..12] ESPI_CLK_ACTIVE */\r
+ } PCR_PWR_RST_STS_b; /*!< [13] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t PWR_RST_CNTRL; /*!< (@ 0x40080114) Power Reset Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PWR_INV : 1; /*!< [0..0] Used by FW to control internal RESET_VCC signal function\r
+ and external PWROK pin. This bit is read-only when VCC_PWRGD\r
+ is de-asserted low. */\r
+ uint32_t : 7;\r
+ __IO uint32_t HOST_RESET_SELECT: 1; /*!< [8..8] Determines what generates the internal platform reset\r
+ signal. 1=LRESET# pin; 0=eSPI PLTRST# VWire */\r
+ } PWR_RST_CNTRL_b; /*!< [9] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SYS_RST; /*!< (@ 0x40080118) System Reset Register */\r
+ \r
+ struct {\r
+ uint32_t : 8;\r
+ __IO uint32_t SOFT_SYS_RESET: 1; /*!< [8..8] A write of a 1 forces an assertion of the RESET_SYS reset\r
+ signal, resetting the device. A write of 0 has no effect. */\r
+ } SYS_RST_b; /*!< [9] BitSize */\r
+ };\r
+ __I uint32_t RESERVED[5];\r
+ \r
+ union {\r
+ __IO uint32_t SLP_EN_0; /*!< (@ 0x40080130) Sleep Enable 0 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTAG_STAP_SLP_EN: 1; /*!< [0..0] JTAG STAP Enable */\r
+ __IO uint32_t EFUSE_SLP_EN: 1; /*!< [1..1] eFuse Enable */\r
+ __IO uint32_t ISPI_SLP_EN: 1; /*!< [2..2] ISPI Enable */\r
+ } SLP_EN_0_b; /*!< [3] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLP_EN_1; /*!< (@ 0x40080134) Sleep Enable 1 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t INT_SLP_EN : 1; /*!< [0..0] Interrupt Sleep Enable */\r
+ __IO uint32_t PECI_SLP_EN: 1; /*!< [1..1] PECI Sleep Enable */\r
+ __IO uint32_t TACH0_SLP_EN: 1; /*!< [2..2] TACH0 Sleep Enable (TACH0_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PWM0_SLP_EN: 1; /*!< [4..4] PWM0 Sleep Enable (PWM0_SLP_EN) */\r
+ __IO uint32_t PMC_SLP_EN : 1; /*!< [5..5] PMC Sleep Enable (PMC_SLP_EN) */\r
+ __IO uint32_t DMA_SLP_EN : 1; /*!< [6..6] DMA Sleep Enable (DMA_SLP_EN) */\r
+ __IO uint32_t TFDP_SLP_EN: 1; /*!< [7..7] TFDP Sleep Enable (TFDP_SLP_EN) */\r
+ __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< [8..8] PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */\r
+ __IO uint32_t WDT_SLP_EN : 1; /*!< [9..9] WDT Sleep Enable (WDT_SLP_EN) */\r
+ __IO uint32_t SMB0_SLP_EN: 1; /*!< [10..10] SMB0 Sleep Enable (SMB0_SLP_EN) */\r
+ __IO uint32_t TACH1_SLP_EN: 1; /*!< [11..11] TACH1 Sleep Enable (TACH1_SLP_EN) */\r
+ __IO uint32_t TACH2_SLP_EN: 1; /*!< [12..12] TACH2 Sleep Enable (TACH2_SLP_EN) */\r
+ uint32_t : 7;\r
+ __IO uint32_t PWM1_SLP_EN: 1; /*!< [20..20] PWM1 Sleep Enable (PWM1_SLP_EN) */\r
+ __IO uint32_t PWM2_SLP_EN: 1; /*!< [21..21] PWM2 Sleep Enable (PWM2_SLP_EN) */\r
+ __IO uint32_t PWM3_SLP_EN: 1; /*!< [22..22] PWM3 Sleep Enable (PWM3_SLP_EN) */\r
+ __IO uint32_t PWM4_SLP_EN: 1; /*!< [23..23] PWM4 Sleep Enable (PWM4_SLP_EN) */\r
+ __IO uint32_t PWM5_SLP_EN: 1; /*!< [24..24] PWM3 Sleep Enable (PWM5_SLP_EN) */\r
+ __IO uint32_t PWM6_SLP_EN: 1; /*!< [25..25] PWM3 Sleep Enable (PWM6_SLP_EN) */\r
+ __IO uint32_t PWM7_SLP_EN: 1; /*!< [26..26] PWM3 Sleep Enable (PWM7_SLP_EN) */\r
+ __IO uint32_t PWM8_SLP_EN: 1; /*!< [27..27] PWM3 Sleep Enable (PWM8_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< [29..29] EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */\r
+ __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< [30..30] TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */\r
+ __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< [31..31] TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */\r
+ } SLP_EN_1_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLP_EN_2; /*!< (@ 0x40080138) Sleep Enable 2 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_SLP_EN : 1; /*!< [0..0] LPC Sleep Enable (LPC_SLP_EN) */\r
+ __IO uint32_t UART_0_SLP_EN: 1; /*!< [1..1] UART 0 Sleep Enable */\r
+ __IO uint32_t UART_1_SLP_EN: 1; /*!< [2..2] UART 1 Sleep Enable */\r
+ uint32_t : 9;\r
+ __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< [13..13] ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< [14..14] ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */\r
+ __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< [15..15] ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */\r
+ __IO uint32_t KBCEM_SLP_EN: 1; /*!< [16..16] 8042EM Sleep Enable (8042EM_SLP_EN) */\r
+ __IO uint32_t MBX_SLP_EN : 1; /*!< [17..17] Mailbox Sleep Enable (8042EM_SLP_EN) */\r
+ __IO uint32_t RTC_SLP_EN : 1; /*!< [18..18] RTC Sleep Enable (RTC_SLP_EN) */\r
+ __IO uint32_t ESPI_SLP_EN: 1; /*!< [19..19] eSPI Sleep Enable */\r
+ uint32_t : 1;\r
+ __IO uint32_t ACPI_EC_2_SLP_EN: 1; /*!< [21..21] ACPI EC 2 Sleep Enable (ACPI_EC_2_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_3_SLP_EN: 1; /*!< [22..22] ACPI EC 3 Sleep Enable (ACPI_EC_3_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_4_SLP_EN: 1; /*!< [23..23] ACPI EC 4 Sleep Enable (ACPI_EC_4_SLP_EN) */\r
+ __IO uint32_t ASIF_SLP_EN: 1; /*!< [24..24] ASIF Sleep Enable */\r
+ __IO uint32_t PORT80_0_SLP_EN: 1; /*!< [25..25] Port 80 0 Sleep Enable */\r
+ __IO uint32_t PORT80_1_SLP_EN: 1; /*!< [26..26] Port 80 1 Sleep Enable */\r
+ } SLP_EN_2_b; /*!< [27] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLP_EN_3; /*!< (@ 0x4008013C) Sleep Enable 3 Register */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __IO uint32_t ADC_SLP_EN : 1; /*!< [3..3] ADC Sleep Enable (ADC_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PS2_0_SLP_EN: 1; /*!< [5..5] PS2_0 Sleep Enable (PS2_0_SLP_EN) */\r
+ __IO uint32_t PS2_1_SLP_EN: 1; /*!< [6..6] PS2_1 Sleep Enable (PS2_1_SLP_EN) */\r
+ __IO uint32_t PS2_2_SLP_EN: 1; /*!< [7..7] PS2_2 Sleep Enable (PS2_2_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t GP_SPI0_SLP_EN: 1; /*!< [9..9] GP SPI0 Sleep Enable (GP_SPI0_SLP_EN) */\r
+ __IO uint32_t HTIMER_0_SLP_EN: 1; /*!< [10..10] HTIMER 0 Sleep Enable (HTIMER_0_SLP_EN) */\r
+ __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< [11..11] KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */\r
+ __IO uint32_t RPMPWM_SLP_EN: 1; /*!< [12..12] RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */\r
+ __IO uint32_t SMB1_SLP_EN: 1; /*!< [13..13] SMB1 Sleep Enable (SMB1_SLP_EN) */\r
+ __IO uint32_t SMB2_SLP_EN: 1; /*!< [14..14] SMB2 Sleep Enable (SMB2_SLP_EN) */\r
+ __IO uint32_t SMB3_SLP_EN: 1; /*!< [15..15] SMB3 Sleep Enable (SMB3_SLP_EN) */\r
+ __IO uint32_t LED0_SLP_EN: 1; /*!< [16..16] LED0 Sleep Enable (LED0_SLP_EN) */\r
+ __IO uint32_t LED1_SLP_EN: 1; /*!< [17..17] LED1 Sleep Enable (LED1_SLP_EN) */\r
+ __IO uint32_t LED2_SLP_EN: 1; /*!< [18..18] LED2 Sleep Enable (LED2_SLP_EN) */\r
+ __IO uint32_t BCM0_SLP_EN: 1; /*!< [19..19] BCM 0 Sleep Enable (BCM0_SLP_EN) */\r
+ __IO uint32_t GP_SPI1_SLP_EN: 1; /*!< [20..20] GP SPI1 Sleep Enable (GP_SPI1_SLP_EN) */\r
+ __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< [21..21] TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */\r
+ __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< [22..22] TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */\r
+ __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< [23..23] TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */\r
+ __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< [24..24] TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */\r
+ __IO uint32_t LED3_SLP_EN: 1; /*!< [25..25] LED3 Sleep Enable (LED3_SLP_EN) */\r
+ __IO uint32_t PKE_SLP_EN : 1; /*!< [26..26] PKE Sleep Enable */\r
+ __IO uint32_t RNG_SLP_EN : 1; /*!< [27..27] RNG Sleep Enable */\r
+ __IO uint32_t AES_HASH_SLP_EN: 1; /*!< [28..28] AES_HASH Sleep Enable */\r
+ __IO uint32_t HTIMER_1_SLP_EN: 1; /*!< [29..29] HTIMER 1 Sleep Enable (HTIMER_1_SLP_EN) */\r
+ __IO uint32_t CCTIMER_SLP_EN: 1; /*!< [30..30] Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)\r
+ */\r
+ __IO uint32_t PWM9_SLP_EN: 1; /*!< [31..31] PWM9 Sleep Enable (PWM9_SLP_EN) */\r
+ } SLP_EN_3_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLP_EN_4; /*!< (@ 0x40080140) Sleep Enable 4 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PWM10_SLP_EN: 1; /*!< [0..0] PWM10 Sleep Enable (PWM10_SLP_EN) */\r
+ __IO uint32_t PWM11_SLP_EN: 1; /*!< [1..1] PWM11 Sleep Enable (PWM11_SLP_EN) */\r
+ __IO uint32_t CNT_TMER0_SLP_EN: 1; /*!< [2..2] CNT_TMER0 Sleep Enable (CNT_TMER0_SLP_EN) */\r
+ __IO uint32_t CNT_TMER1_SLP_EN: 1; /*!< [3..3] CNT_TMER1 Sleep Enable (CNT_TMER1_SLP_EN) */\r
+ __IO uint32_t CNT_TMER2_SLP_EN: 1; /*!< [4..4] CNT_TMER2 Sleep Enable (CNT_TMER2_SLP_EN) */\r
+ __IO uint32_t CNT_TMER3_SLP_EN: 1; /*!< [5..5] CNT_TMER3 Sleep Enable (CNT_TMER3_SLP_EN) */\r
+ __IO uint32_t RTOS_SLP_EN: 1; /*!< [6..6] PWM6 Sleep Enable (RTOS_SLP_EN) */\r
+ __IO uint32_t RPMPWM1_SLP_EN: 1; /*!< [7..7] RPMPWM 1 Sleep Enable (RPMPWM1_SLP_EN) */\r
+ __IO uint32_t QSPI_SLP_EN: 1; /*!< [8..8] Quad SPI Sleep Enable */\r
+ __IO uint32_t BCM1_SLP_EN: 1; /*!< [9..9] BCM 1 Sleep Enable (BCM1_SLP_EN) */\r
+ __IO uint32_t RC_ID0_SLP_EN: 1; /*!< [10..10] RC_ID0 Sleep Enable (RC_ID0_SLP_EN) */\r
+ __IO uint32_t RC_ID1_SLP_EN: 1; /*!< [11..11] RC_ID1 Sleep Enable (RC_ID1_SLP_EN) */\r
+ __IO uint32_t RC_ID2_SLP_EN: 1; /*!< [12..12] RC_ID2 Sleep Enable (RC_ID2_SLP_EN) */\r
+ uint32_t : 2;\r
+ __IO uint32_t FCL_SLP_EN : 1; /*!< [15..15] FCL Sleep Enable (FCL_SLP_EN) */\r
+ } SLP_EN_4_b; /*!< [16] BitSize */\r
+ };\r
+ __I uint32_t RESERVED1[3];\r
+ \r
+ union {\r
+ __IO uint32_t CLK_REQ_0; /*!< (@ 0x40080150) Clock Required 0 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTAG_STAP_CLK_REQ: 1; /*!< [0..0] JTAG STAP Enable */\r
+ __IO uint32_t EFUSE_CLK_REQ: 1; /*!< [1..1] eFuse Enable */\r
+ __IO uint32_t ISPI_CLK_REQ: 1; /*!< [2..2] ISPI Clock Required */\r
+ } CLK_REQ_0_b; /*!< [3] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CLK_REQ_1; /*!< (@ 0x40080154) Clock Required 1 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t INT_CLK_REQ: 1; /*!< [0..0] Interrupt Clock Required */\r
+ __IO uint32_t PECI_CLK_REQ: 1; /*!< [1..1] PECI Clock Required */\r
+ __IO uint32_t TACH0_CLK_REQ: 1; /*!< [2..2] TACH0 Clock Required (TACH0_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PWM0_CLK_REQ: 1; /*!< [4..4] PWM0 Clock Required (PWM0_CLK_REQ) */\r
+ __IO uint32_t PMC_CLK_REQ: 1; /*!< [5..5] PMC Clock Required (PMC_CLK_REQ) */\r
+ __IO uint32_t DMA_CLK_REQ: 1; /*!< [6..6] DMA Clock Required (DMA_CLK_REQ) */\r
+ __IO uint32_t TFDP_CLK_REQ: 1; /*!< [7..7] TFDP Clock Required (TFDP_CLK_REQ) */\r
+ __IO uint32_t PROCESSOR_CLK_REQ: 1; /*!< [8..8] PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */\r
+ __IO uint32_t WDT_CLK_REQ: 1; /*!< [9..9] WDT Clock Required (WDT_CLK_REQ) */\r
+ __IO uint32_t SMB0_CLK_REQ: 1; /*!< [10..10] SMB0 Clock Required (SMB0_CLK_REQ) */\r
+ __IO uint32_t TACH1_CLK_REQ: 1; /*!< [11..11] TACH1 Clock Required (TACH1_CLK_REQ) */\r
+ __IO uint32_t TACH2_CLK_REQ: 1; /*!< [12..12] TACH2 Clock Required (TACH2_CLK_REQ) */\r
+ uint32_t : 7;\r
+ __IO uint32_t PWM1_CLK_REQ: 1; /*!< [20..20] PWM1 Clock Required (PWM1_CLK_REQ) */\r
+ __IO uint32_t PWM2_CLK_REQ: 1; /*!< [21..21] PWM2 Clock Required (PWM2_CLK_REQ) */\r
+ __IO uint32_t PWM3_CLK_REQ: 1; /*!< [22..22] PWM3 Clock Required (PWM3_CLK_REQ) */\r
+ __IO uint32_t PWM4_CLK_REQ: 1; /*!< [23..23] PWM4 Clock Required (PWM4_CLK_REQ) */\r
+ __IO uint32_t PWM5_CLK_REQ: 1; /*!< [24..24] PWM3 Clock Required (PWM5_CLK_REQ) */\r
+ __IO uint32_t PWM6_CLK_REQ: 1; /*!< [25..25] PWM3 Clock Required (PWM6_CLK_REQ) */\r
+ __IO uint32_t PWM7_CLK_REQ: 1; /*!< [26..26] PWM3 Clock Required (PWM7_CLK_REQ) */\r
+ __IO uint32_t PWM8_CLK_REQ: 1; /*!< [27..27] PWM3 Clock Required (PWM8_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __IO uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< [29..29] EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */\r
+ __IO uint32_t TIMER16_0_CLK_REQ: 1; /*!< [30..30] TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */\r
+ __IO uint32_t TIMER16_1_CLK_REQ: 1; /*!< [31..31] TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */\r
+ } CLK_REQ_1_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CLK_REQ_2; /*!< (@ 0x40080158) Clock Required 2 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_CLK_REQ: 1; /*!< [0..0] LPC Clock Required (LPC_CLK_REQ) */\r
+ __IO uint32_t UART_0_CLK_REQ: 1; /*!< [1..1] UART 0 Clock Required */\r
+ __IO uint32_t UART_1_CLK_REQ: 1; /*!< [2..2] UART 1 Clock Required */\r
+ uint32_t : 9;\r
+ __IO uint32_t GLBL_CFG_CLK_REQ: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_CLK_REQ) */\r
+ __IO uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< [13..13] ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */\r
+ __IO uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< [14..14] ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */\r
+ __IO uint32_t ACPI_PM1_CLK_REQ: 1; /*!< [15..15] ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */\r
+ __IO uint32_t KBCEM_CLK_REQ: 1; /*!< [16..16] 8042EM Clock Required (8042EM_CLK_REQ) */\r
+ __IO uint32_t MBX_CLK_REQ: 1; /*!< [17..17] Mailbox Clock Required (8042EM_CLK_REQ) */\r
+ __IO uint32_t RTC_CLK_REQ: 1; /*!< [18..18] RTC Clock Required (RTC_CLK_REQ) */\r
+ __IO uint32_t ESPI_CLK_REQ: 1; /*!< [19..19] eSPI Clock Required */\r
+ uint32_t : 1;\r
+ __IO uint32_t ACPI_EC_2_CLK_REQ: 1; /*!< [21..21] ACPI EC 2 Clock Required (ACPI_EC_2_CLK_REQ) */\r
+ __IO uint32_t ACPI_EC_3_CLK_REQ: 1; /*!< [22..22] ACPI EC 3 Clock Required (ACPI_EC_3_CLK_REQ) */\r
+ __IO uint32_t ACPI_EC_4_CLK_REQ: 1; /*!< [23..23] ACPI EC 4 Clock Required (ACPI_EC_4_CLK_REQ) */\r
+ __IO uint32_t ASIF_CLK_REQ: 1; /*!< [24..24] ASIF Clock Required */\r
+ __IO uint32_t PORT80_0_CLK_REQ: 1; /*!< [25..25] Port 80 0 Clock Required */\r
+ __IO uint32_t PORT80_1_CLK_REQ: 1; /*!< [26..26] Port 80 1 Clock Required */\r
+ } CLK_REQ_2_b; /*!< [27] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CLK_REQ_3; /*!< (@ 0x4008015C) Clock Required 3 Register */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __IO uint32_t ADC_CLK_REQ: 1; /*!< [3..3] ADC Clock Required (ADC_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PS2_0_CLK_REQ: 1; /*!< [5..5] PS2_0 Clock Required (PS2_0_CLK_REQ) */\r
+ __IO uint32_t PS2_1_CLK_REQ: 1; /*!< [6..6] PS2_1 Clock Required (PS2_1_CLK_REQ) */\r
+ __IO uint32_t PS2_2_CLK_REQ: 1; /*!< [7..7] PS2_2 Clock Required (PS2_2_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __IO uint32_t GP_SPI0_CLK_REQ: 1; /*!< [9..9] GP SPI0 Clock Required (GP_SPI0_CLK_REQ) */\r
+ __IO uint32_t HTIMER_0_CLK_REQ: 1; /*!< [10..10] HTIMER 0 Clock Required (HTIMER_0_CLK_REQ) */\r
+ __IO uint32_t KEYSCAN_CLK_REQ: 1; /*!< [11..11] KEYSCAN Clock Required (KEYSCAN_CLK_REQ) */\r
+ __IO uint32_t RPMPWM0_CLK_REQ: 1; /*!< [12..12] RPM-PWM 0 Clock Required (RPMPWM0_CLK_REQ) */\r
+ __IO uint32_t SMB1_CLK_REQ: 1; /*!< [13..13] SMB1 Clock Required (SMB1_CLK_REQ) */\r
+ __IO uint32_t SMB2_CLK_REQ: 1; /*!< [14..14] SMB2 Clock Required (SMB2_CLK_REQ) */\r
+ __IO uint32_t SMB3_CLK_REQ: 1; /*!< [15..15] SMB3 Clock Required (SMB3_CLK_REQ) */\r
+ __IO uint32_t LED0_CLK_REQ: 1; /*!< [16..16] LED0 Clock Required (LED0_CLK_REQ) */\r
+ __IO uint32_t LED1_CLK_REQ: 1; /*!< [17..17] LED1 Clock Required (LED1_CLK_REQ) */\r
+ __IO uint32_t LED2_CLK_REQ: 1; /*!< [18..18] LED2 Clock Required (LED2_CLK_REQ) */\r
+ __IO uint32_t BCM0_CLK_REQ: 1; /*!< [19..19] BCM 0 Clock Required (BCM0_CLK_REQ) */\r
+ __IO uint32_t GP_SPI1_CLK_REQ: 1; /*!< [20..20] GP SPI1 Clock Required (GP_SPI1_CLK_REQ) */\r
+ __IO uint32_t TIMER16_2_CLK_REQ: 1; /*!< [21..21] TIMER16_2_Clock Required (TIMER16_2_CLK_REQ) */\r
+ __IO uint32_t TIMER16_3_CLK_REQ: 1; /*!< [22..22] TIMER16_3 Clock Required (TIMER16_3_CLK_REQ) */\r
+ __IO uint32_t TIMER32_0_CLK_REQ: 1; /*!< [23..23] TIMER32_0 Clock Required (TIMER32_0_CLK_REQ) */\r
+ __IO uint32_t TIMER32_1_CLK_REQ: 1; /*!< [24..24] TIMER32_1 Clock Required (TIMER32_1_CLK_REQ) */\r
+ __IO uint32_t LED3_CLK_REQ: 1; /*!< [25..25] LED3 Clock Required (LED3_CLK_REQ) */\r
+ __IO uint32_t PKE_CLK_REQ: 1; /*!< [26..26] PKE Clock Required */\r
+ __IO uint32_t RNG_CLK_REQ: 1; /*!< [27..27] RNG Clock Required */\r
+ __IO uint32_t AES_HASH_CLK_REQ: 1; /*!< [28..28] AES_HASH Clock Required */\r
+ __IO uint32_t HTIMER_1_CLK_REQ: 1; /*!< [29..29] HTIMER 1 Clock Required (HTIMER_1_CLK_REQ) */\r
+ __IO uint32_t CCTIMER_CLK_REQ: 1; /*!< [30..30] Capture Compare Timer Clock Required (CCTIMER_CLK_REQ)\r
+ */\r
+ __IO uint32_t PWM9_CLK_REQ: 1; /*!< [31..31] PWM9 Clock Required (PWM9_CLK_REQ) */\r
+ } CLK_REQ_3_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CLK_REQ_4; /*!< (@ 0x40080160) Clock Required 4 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PWM10_CLK_REQ: 1; /*!< [0..0] PWM10 Clock Required (PWM10_CLK_REQ) */\r
+ __IO uint32_t PWM11_CLK_REQ: 1; /*!< [1..1] PWM11 Clock Required (PWM11_CLK_REQ) */\r
+ __IO uint32_t CNT_TMER0_CLK_REQ: 1; /*!< [2..2] CNT_TMER0 Clock Required (CNT_TMER0_CLK_REQ) */\r
+ __IO uint32_t CNT_TMER1_CLK_REQ: 1; /*!< [3..3] CNT_TMER1 Clock Required (CNT_TMER1_CLK_REQ) */\r
+ __IO uint32_t CNT_TMER2_CLK_REQ: 1; /*!< [4..4] CNT_TMER2 Clock Required (CNT_TMER2_CLK_REQ) */\r
+ __IO uint32_t CNT_TMER3_CLK_REQ: 1; /*!< [5..5] CNT_TMER3 Clock Required (CNT_TMER3_CLK_REQ) */\r
+ __IO uint32_t RTOS_CLK_REQ: 1; /*!< [6..6] RTOS Clock Required (RTOS_CLK_REQ) */\r
+ __IO uint32_t RPMPWM1_CLK_REQ: 1; /*!< [7..7] RPM-PWM1 Clock Required (RPMPWM1_CLK_REQ) */\r
+ __IO uint32_t QSPI_CLK_REQ: 1; /*!< [8..8] Quad SPI Clock Required */\r
+ __IO uint32_t BCM1_CLK_REQ: 1; /*!< [9..9] BCM 1 Clock Required (BCM1_CLK_REQ) */\r
+ __IO uint32_t RC_ID0_CLK_REQ: 1; /*!< [10..10] RC_ID0 Clock Required (RC_ID0_CLK_REQ) */\r
+ __IO uint32_t RC_ID1_CLK_REQ: 1; /*!< [11..11] RC_ID1 Clock Required (RC_ID1_CLK_REQ) */\r
+ __IO uint32_t RC_ID2_CLK_REQ: 1; /*!< [12..12] RC_ID2 Clock Required (RC_ID2_CLK_REQ) */\r
+ uint32_t : 2;\r
+ __IO uint32_t FCL_CLK_REQ: 1; /*!< [15..15] FCL Clock Required (FCL_CLK_REQ) */\r
+ } CLK_REQ_4_b; /*!< [16] BitSize */\r
+ };\r
+ __I uint32_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint32_t RST_EN_0; /*!< (@ 0x40080170) Reset Enable 0 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTAG_STAP_RST_EN: 1; /*!< [0..0] JTAG STAP Reset Enable */\r
+ __IO uint32_t EFUSE_RST_EN: 1; /*!< [1..1] eFuse Reset Enable */\r
+ __IO uint32_t ISPI_RST_EN: 1; /*!< [2..2] ISPI Reset Enable */\r
+ } RST_EN_0_b; /*!< [3] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t RST_EN_1; /*!< (@ 0x40080174) Reset Enable 1 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t INT_RST_EN : 1; /*!< [0..0] Interrupt Reset Enable */\r
+ __IO uint32_t PECI_RST_EN: 1; /*!< [1..1] PECI Reset Enable */\r
+ __IO uint32_t TACH0_RST_EN: 1; /*!< [2..2] TACH0 Reset Enable (TACH0_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PWM0_RST_EN: 1; /*!< [4..4] PWM0 Reset Enable (PWM0_RST_EN) */\r
+ __IO uint32_t PMC_RST_EN : 1; /*!< [5..5] PMC Reset Enable (PMC_RST_EN) */\r
+ __IO uint32_t DMA_RST_EN : 1; /*!< [6..6] DMA Reset Enable (DMA_RST_EN) */\r
+ __IO uint32_t TFDP_RST_EN: 1; /*!< [7..7] TFDP Reset Enable (TFDP_RST_EN) */\r
+ __IO uint32_t PROCESSOR_RST_EN: 1; /*!< [8..8] PROCESSOR Reset Enable (PROCESSOR_RST_EN) */\r
+ __IO uint32_t WDT_RST_EN : 1; /*!< [9..9] WDT Reset Enable (WDT_RST_EN) */\r
+ __IO uint32_t SMB0_RST_EN: 1; /*!< [10..10] SMB0 Reset Enable (SMB0_RST_EN) */\r
+ __IO uint32_t TACH1_RST_EN: 1; /*!< [11..11] TACH1 Reset Enable (TACH1_RST_EN) */\r
+ __IO uint32_t TACH2_RST_EN: 1; /*!< [12..12] TACH2 Reset Enable (TACH2_RST_EN) */\r
+ uint32_t : 7;\r
+ __IO uint32_t PWM1_RST_EN: 1; /*!< [20..20] PWM1 Reset Enable (PWM1_RST_EN) */\r
+ __IO uint32_t PWM2_RST_EN: 1; /*!< [21..21] PWM2 Reset Enable (PWM2_RST_EN) */\r
+ __IO uint32_t PWM3_RST_EN: 1; /*!< [22..22] PWM3 Reset Enable (PWM3_RST_EN) */\r
+ __IO uint32_t PWM4_RST_EN: 1; /*!< [23..23] PWM4 Reset Enable (PWM4_RST_EN) */\r
+ __IO uint32_t PWM5_RST_EN: 1; /*!< [24..24] PWM3 Reset Enable (PWM5_RST_EN) */\r
+ __IO uint32_t PWM6_RST_EN: 1; /*!< [25..25] PWM3 Reset Enable (PWM6_RST_EN) */\r
+ __IO uint32_t PWM7_RST_EN: 1; /*!< [26..26] PWM3 Reset Enable (PWM7_RST_EN) */\r
+ __IO uint32_t PWM8_RST_EN: 1; /*!< [27..27] PWM3 Reset Enable (PWM8_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< [29..29] EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */\r
+ __IO uint32_t TIMER16_0_RST_EN: 1; /*!< [30..30] TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */\r
+ __IO uint32_t TIMER16_1_RST_EN: 1; /*!< [31..31] TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */\r
+ } RST_EN_1_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t RST_EN_2; /*!< (@ 0x40080178) Reset Enable 2 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_RST_EN : 1; /*!< [0..0] LPC Reset Enable (LPC_RST_EN) */\r
+ __IO uint32_t UART_0_RST_EN: 1; /*!< [1..1] UART 0 Reset Enable */\r
+ __IO uint32_t UART_1_RST_EN: 1; /*!< [2..2] UART 1 Reset Enable */\r
+ uint32_t : 9;\r
+ __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_RST_EN) */\r
+ __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< [13..13] ACPI EC 0 Reset Enable (ACPI_EC_0_RST_EN) */\r
+ __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< [14..14] ACPI EC 1 Reset Enable (ACPI_EC_1_RST_EN) */\r
+ __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< [15..15] ACPI PM1 Reset Enable (ACPI_PM1_RST_EN) */\r
+ __IO uint32_t KBCEM_RST_EN: 1; /*!< [16..16] 8042EM Reset Enable (8042EM_RST_EN) */\r
+ __IO uint32_t MBX_RST_EN : 1; /*!< [17..17] Mailbox Reset Enable (8042EM_RST_EN) */\r
+ __IO uint32_t RTC_RST_EN : 1; /*!< [18..18] RTC Reset Enable (RTC_RST_EN) */\r
+ __IO uint32_t ESPI_RST_EN: 1; /*!< [19..19] eSPI Reset Enable */\r
+ uint32_t : 1;\r
+ __IO uint32_t ACPI_EC_2_RST_EN: 1; /*!< [21..21] ACPI EC 2 Reset Enable (ACPI_EC_2_RST_EN) */\r
+ __IO uint32_t ACPI_EC_3_RST_EN: 1; /*!< [22..22] ACPI EC 3 Reset Enable (ACPI_EC_3_RST_EN) */\r
+ __IO uint32_t ACPI_EC_4_RST_EN: 1; /*!< [23..23] ACPI EC 4 Reset Enable (ACPI_EC_4_RST_EN) */\r
+ __IO uint32_t ASIF_RST_EN: 1; /*!< [24..24] ASIF Reset Enable */\r
+ __IO uint32_t PORT80_0_RST_EN: 1; /*!< [25..25] Port 80 0 Reset Enable */\r
+ __IO uint32_t PORT80_1_RST_EN: 1; /*!< [26..26] Port 80 1 Reset Enable */\r
+ } RST_EN_2_b; /*!< [27] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t RST_EN_3; /*!< (@ 0x4008017C) Reset Enable 3 Register */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __IO uint32_t ADC_RST_EN : 1; /*!< [3..3] ADC Reset Enable (ADC_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PS2_0_RST_EN: 1; /*!< [5..5] PS2_0 Reset Enable (PS2_0_RST_EN) */\r
+ __IO uint32_t PS2_1_RST_EN: 1; /*!< [6..6] PS2_1 Reset Enable (PS2_1_RST_EN) */\r
+ __IO uint32_t PS2_2_RST_EN: 1; /*!< [7..7] PS2_2 Reset Enable (PS2_2_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t GP_SPI0_RST_EN: 1; /*!< [9..9] GP SPI0 Reset Enable (GP_SPI0_RST_EN) */\r
+ __IO uint32_t HTIMER_0_RST_EN: 1; /*!< [10..10] HTIMER 0 Reset Enable (HTIMER_0_RST_EN) */\r
+ __IO uint32_t KEYSCAN_RST_EN: 1; /*!< [11..11] KEYSCAN Reset Enable (KEYSCAN_RST_EN) */\r
+ __IO uint32_t RPMPWM0_RST_EN: 1; /*!< [12..12] RPM-PWM 0 Reset Enable (RPMPWM0_RST_EN) */\r
+ __IO uint32_t SMB1_RST_EN: 1; /*!< [13..13] SMB1 Reset Enable (SMB1_RST_EN) */\r
+ __IO uint32_t SMB2_RST_EN: 1; /*!< [14..14] SMB2 Reset Enable (SMB2_RST_EN) */\r
+ __IO uint32_t SMB3_RST_EN: 1; /*!< [15..15] SMB3 Reset Enable (SMB3_RST_EN) */\r
+ __IO uint32_t LED0_RST_EN: 1; /*!< [16..16] LED0 Reset Enable (LED0_RST_EN) */\r
+ __IO uint32_t LED1_RST_EN: 1; /*!< [17..17] LED1 Reset Enable (LED1_RST_EN) */\r
+ __IO uint32_t LED2_RST_EN: 1; /*!< [18..18] LED2 Reset Enable (LED2_RST_EN) */\r
+ __IO uint32_t BCM0_RST_EN: 1; /*!< [19..19] BCM 0 Reset Enable (BCM0_RST_EN) */\r
+ __IO uint32_t GP_SPI1_RST_EN: 1; /*!< [20..20] GP SPI1 Reset Enable (GP_SPI1_RST_EN) */\r
+ __IO uint32_t TIMER16_2_RST_EN: 1; /*!< [21..21] TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */\r
+ __IO uint32_t TIMER16_3_RST_EN: 1; /*!< [22..22] TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */\r
+ __IO uint32_t TIMER32_0_RST_EN: 1; /*!< [23..23] TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */\r
+ __IO uint32_t TIMER32_1_RST_EN: 1; /*!< [24..24] TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */\r
+ __IO uint32_t LED3_RST_EN: 1; /*!< [25..25] LED3 Reset Enable (LED3_RST_EN) */\r
+ __IO uint32_t PKE_RST_EN : 1; /*!< [26..26] PKE Reset Enable */\r
+ __IO uint32_t RNG_RST_EN : 1; /*!< [27..27] RNG Reset Enable */\r
+ __IO uint32_t AES_HASH_RST_EN: 1; /*!< [28..28] AES_HASH Reset Enable */\r
+ __IO uint32_t HTIMER_1_RST_EN: 1; /*!< [29..29] HTIMER 1 Reset Enable (HTIMER_1_RST_EN) */\r
+ __IO uint32_t CCTIMER_RST_EN: 1; /*!< [30..30] Capture Compare Timer Reset Enable (CCTIMER_RST_EN)\r
+ */\r
+ __IO uint32_t PWM9_RST_EN: 1; /*!< [31..31] PWM9 Reset Enable (PWM9_RST_EN) */\r
+ } RST_EN_3_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t RST_EN_4; /*!< (@ 0x40080180) Reset Enable 4 Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PWM10_RST_EN: 1; /*!< [0..0] PWM10 Reset Enable (PWM10_RST_EN) */\r
+ __IO uint32_t PWM11_RST_EN: 1; /*!< [1..1] PWM11 Reset Enable (PWM11_RST_EN) */\r
+ __IO uint32_t CNT_TMER0_RST_EN: 1; /*!< [2..2] CNT_TMER0 Reset Enable (CNT_TMER0_RST_EN) */\r
+ __IO uint32_t CNT_TMER1_RST_EN: 1; /*!< [3..3] CNT_TMER1 Reset Enable (CNT_TMER1_RST_EN) */\r
+ __IO uint32_t CNT_TMER2_RST_EN: 1; /*!< [4..4] CNT_TMER2 Reset Enable (CNT_TMER2_RST_EN) */\r
+ __IO uint32_t CNT_TMER3_RST_EN: 1; /*!< [5..5] CNT_TMER3 Reset Enable (CNT_TMER3_RST_EN) */\r
+ __IO uint32_t RTOS_RST_EN: 1; /*!< [6..6] RTOS Reset Enable (RTOS_RST_EN) */\r
+ __IO uint32_t RPMPWM1_RST_EN: 1; /*!< [7..7] RPM-PWM1 Reset Enable (RPMPWM1_RST_EN) */\r
+ __IO uint32_t QSPI_RST_EN: 1; /*!< [8..8] Quad SPI Reset Enable */\r
+ __IO uint32_t BCM1_RST_EN: 1; /*!< [9..9] BCM 1 Reset Enable (BCM1_RST_EN) */\r
+ __IO uint32_t RC_ID0_RST_EN: 1; /*!< [10..10] RC_ID0 Reset Enable (RC_ID0_RST_EN) */\r
+ __IO uint32_t RC_ID1_RST_EN: 1; /*!< [11..11] RC_ID1 Reset Enable (RC_ID1_RST_EN) */\r
+ __IO uint32_t RC_ID2_RST_EN: 1; /*!< [12..12] RC_ID2 Reset Enable (RC_ID2_RST_EN) */\r
+ uint32_t : 2;\r
+ __IO uint32_t FCL_RST_EN : 1; /*!< [15..15] FCL Reset Enable (FCL_RST_EN) */\r
+ } RST_EN_4_b; /*!< [16] BitSize */\r
+ };\r
+} PCR_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ INTS ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The interrupt generation logic is made of 16 groups of signals, each of which\r
+ consist of a Status register, a Enable register and a Result register. The Status and Enable are\r
+ latched registers. The Result register is a bit by bit AND function of the Source and Enable registers.\r
+ All the bits of the Result register are OR'ed together and AND'ed with the corresponding bit in the Block\r
+ Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTS)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4000E000) INTS Structure */\r
+ __IO uint32_t GIRQ08_SRC; /*!< (@ 0x4000E000) Status R/W1C */\r
+ __IO uint32_t GIRQ08_EN_SET; /*!< (@ 0x4000E004) Write to set source enables */\r
+ __I uint32_t GIRQ08_RESULT; /*!< (@ 0x4000E008) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ08_EN_CLR; /*!< (@ 0x4000E00C) Write to clear source enables */\r
+ __I uint32_t RESERVED;\r
+ __IO uint32_t GIRQ09_SRC; /*!< (@ 0x4000E014) Status R/W1C */\r
+ __IO uint32_t GIRQ09_EN_SET; /*!< (@ 0x4000E018) Write to set source enables */\r
+ __I uint32_t GIRQ09_RESULT; /*!< (@ 0x4000E01C) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ09_EN_CLR; /*!< (@ 0x4000E020) Write to clear source enables */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t GIRQ10_SRC; /*!< (@ 0x4000E028) Status R/W1C */\r
+ __IO uint32_t GIRQ10_EN_SET; /*!< (@ 0x4000E02C) Write to set source enables */\r
+ __I uint32_t GIRQ10_RESULT; /*!< (@ 0x4000E030) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ10_EN_CLR; /*!< (@ 0x4000E034) Write to clear source enables */\r
+ __I uint32_t RESERVED2;\r
+ __IO uint32_t GIRQ11_SRC; /*!< (@ 0x4000E03C) Status R/W1C */\r
+ __IO uint32_t GIRQ11_EN_SET; /*!< (@ 0x4000E040) Write to set source enables */\r
+ __I uint32_t GIRQ11_RESULT; /*!< (@ 0x4000E044) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ11_EN_CLR; /*!< (@ 0x4000E048) Write to clear source enables */\r
+ __I uint32_t RESERVED3;\r
+ __IO uint32_t GIRQ12_SRC; /*!< (@ 0x4000E050) Status R/W1C */\r
+ __IO uint32_t GIRQ12_EN_SET; /*!< (@ 0x4000E054) Write to set source enables */\r
+ __I uint32_t GIRQ12_RESULT; /*!< (@ 0x4000E058) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ12_EN_CLR; /*!< (@ 0x4000E05C) Write to clear source enables */\r
+ __I uint32_t RESERVED4;\r
+ __IO uint32_t GIRQ13_SRC; /*!< (@ 0x4000E064) Status R/W1C */\r
+ __IO uint32_t GIRQ13_EN_SET; /*!< (@ 0x4000E068) Write to set source enables */\r
+ __I uint32_t GIRQ13_RESULT; /*!< (@ 0x4000E06C) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ13_EN_CLR; /*!< (@ 0x4000E070) Write to clear source enables */\r
+ __I uint32_t RESERVED5;\r
+ __IO uint32_t GIRQ14_SRC; /*!< (@ 0x4000E078) Status R/W1C */\r
+ __IO uint32_t GIRQ14_EN_SET; /*!< (@ 0x4000E07C) Write to set source enables */\r
+ __I uint32_t GIRQ14_RESULT; /*!< (@ 0x4000E080) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ14_EN_CLR; /*!< (@ 0x4000E084) Write to clear source enables */\r
+ __I uint32_t RESERVED6;\r
+ __IO uint32_t GIRQ15_SRC; /*!< (@ 0x4000E08C) Status R/W1C */\r
+ __IO uint32_t GIRQ15_EN_SET; /*!< (@ 0x4000E090) Write to set source enables */\r
+ __I uint32_t GIRQ15_RESULT; /*!< (@ 0x4000E094) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ15_EN_CLR; /*!< (@ 0x4000E098) Write to clear source enables */\r
+ __I uint32_t RESERVED7;\r
+ __IO uint32_t GIRQ16_SRC; /*!< (@ 0x4000E0A0) Status R/W1C */\r
+ __IO uint32_t GIRQ16_EN_SET; /*!< (@ 0x4000E0A4) Write to set source enables */\r
+ __I uint32_t GIRQ16_RESULT; /*!< (@ 0x4000E0A8) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ16_EN_CLR; /*!< (@ 0x4000E0AC) Write to clear source enables */\r
+ __I uint32_t RESERVED8;\r
+ __IO uint32_t GIRQ17_SRC; /*!< (@ 0x4000E0B4) Status R/W1C */\r
+ __IO uint32_t GIRQ17_EN_SET; /*!< (@ 0x4000E0B8) Write to set source enables */\r
+ __I uint32_t GIRQ17_RESULT; /*!< (@ 0x4000E0BC) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ17_EN_CLR; /*!< (@ 0x4000E0C0) Write to clear source enables */\r
+ __I uint32_t RESERVED9;\r
+ __IO uint32_t GIRQ18_SRC; /*!< (@ 0x4000E0C8) Status R/W1C */\r
+ __IO uint32_t GIRQ18_EN_SET; /*!< (@ 0x4000E0CC) Write to set source enables */\r
+ __I uint32_t GIRQ18_RESULT; /*!< (@ 0x4000E0D0) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ18_EN_CLR; /*!< (@ 0x4000E0D4) Write to clear source enables */\r
+ __I uint32_t RESERVED10;\r
+ __IO uint32_t GIRQ19_SRC; /*!< (@ 0x4000E0DC) Status R/W1C */\r
+ __IO uint32_t GIRQ19_EN_SET; /*!< (@ 0x4000E0E0) Write to set source enables */\r
+ __I uint32_t GIRQ19_RESULT; /*!< (@ 0x4000E0E4) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ19_EN_CLR; /*!< (@ 0x4000E0E8) Write to clear source enables */\r
+ __I uint32_t RESERVED11;\r
+ __IO uint32_t GIRQ20_SRC; /*!< (@ 0x4000E0F0) Status R/W1C */\r
+ __IO uint32_t GIRQ20_EN_SET; /*!< (@ 0x4000E0F4) Write to set source enables */\r
+ __I uint32_t GIRQ20_RESULT; /*!< (@ 0x4000E0F8) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ20_EN_CLR; /*!< (@ 0x4000E0FC) Write to clear source enables */\r
+ __I uint32_t RESERVED12;\r
+ __IO uint32_t GIRQ21_SRC; /*!< (@ 0x4000E104) Status R/W1C */\r
+ __IO uint32_t GIRQ21_EN_SET; /*!< (@ 0x4000E108) Write to set source enables */\r
+ __I uint32_t GIRQ21_RESULT; /*!< (@ 0x4000E10C) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ21_EN_CLR; /*!< (@ 0x4000E110) Write to clear source enables */\r
+ __I uint32_t RESERVED13;\r
+ __IO uint32_t GIRQ22_SRC; /*!< (@ 0x4000E118) Status R/W1C */\r
+ __IO uint32_t GIRQ22_EN_SET; /*!< (@ 0x4000E11C) Write to set source enables */\r
+ __I uint32_t GIRQ22_RESULT; /*!< (@ 0x4000E120) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ22_EN_CLR; /*!< (@ 0x4000E124) Write to clear source enables */\r
+ __I uint32_t RESERVED14;\r
+ __IO uint32_t GIRQ23_SRC; /*!< (@ 0x4000E12C) Status R/W1C */\r
+ __IO uint32_t GIRQ23_EN_SET; /*!< (@ 0x4000E130) Write to set source enables */\r
+ __I uint32_t GIRQ23_RESULT; /*!< (@ 0x4000E134) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ23_EN_CLR; /*!< (@ 0x4000E138) Write to clear source enables */\r
+ __I uint32_t RESERVED15;\r
+ __IO uint32_t GIRQ24_SRC; /*!< (@ 0x4000E140) Status R/W1C */\r
+ __IO uint32_t GIRQ24_EN_SET; /*!< (@ 0x4000E144) Write to set source enables */\r
+ __I uint32_t GIRQ24_RESULT; /*!< (@ 0x4000E148) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ24_EN_CLR; /*!< (@ 0x4000E14C) Write to clear source enables */\r
+ __I uint32_t RESERVED16;\r
+ __IO uint32_t GIRQ25_SRC; /*!< (@ 0x4000E154) Status R/W1C */\r
+ __IO uint32_t GIRQ25_EN_SET; /*!< (@ 0x4000E158) Write to set source enables */\r
+ __I uint32_t GIRQ25_RESULT; /*!< (@ 0x4000E15C) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ25_EN_CLR; /*!< (@ 0x4000E160) Write to clear source enables */\r
+ __I uint32_t RESERVED17;\r
+ __IO uint32_t GIRQ26_SRC; /*!< (@ 0x4000E168) Status R/W1C */\r
+ __IO uint32_t GIRQ26_EN_SET; /*!< (@ 0x4000E16C) Write to set source enables */\r
+ __I uint32_t GIRQ26_RESULT; /*!< (@ 0x4000E170) Read-only bitwise OR of Source and Enable */\r
+ __IO uint32_t GIRQ26_EN_CLR; /*!< (@ 0x4000E174) Write to clear source enables */\r
+ __I uint32_t RESERVED18[34];\r
+ \r
+ union {\r
+ __IO uint32_t BLOCK_ENABLE_SET; /*!< (@ 0x4000E200) Block Enable Set Register */\r
+ \r
+ struct {\r
+ __IO uint32_t IRQ_VECTOR_ENABLE_SET: 31; /*!< [0..30] Each GIRQx bit can be individually enabled to assert\r
+ an interrupt event.\r
+ Reads always return the current value of the internal GIRQX_ENABLE\r
+ bit. The state of the GIRQX_ENABLE bit is determined by\r
+ the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_\r
+ CLEAR bit. (0=disabled, 1=enabled) (R/WS)\r
+ 1=Interrupts in the GIRQx Source Register may be enabled\r
+ 0=No effect. */\r
+ } BLOCK_ENABLE_SET_b; /*!< [31] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< (@ 0x4000E204) Block Enable Clear Register. */\r
+ \r
+ struct {\r
+ __IO uint32_t IRQ_VECTOR_ENABLE_CLEAR: 31; /*!< [0..30] Each GIRQx bit can be individually disabled to inhibit\r
+ an interrupt event.\r
+ Reads always return the current value of the internal GIRQX_ENABLE\r
+ bit. The state of the GIRQX_ENABLE bit is determined by\r
+ the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_\r
+ CLEAR bit. (0=disabled, 1=enabled) (R/WC)\r
+ 1=All interrupts in the GIRQx Source Register are disabled\r
+ 0=No effect. */\r
+ } BLOCK_ENABLE_CLEAR_b; /*!< [31] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t BLOCK_IRQ_VECTOR; /*!< (@ 0x4000E208) Block IRQ Vector Register */\r
+ \r
+ struct {\r
+ __I uint32_t IRQ_VECTOR : 25; /*!< [0..24] Each bit in this field reports the status of the group\r
+ GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt\r
+ is disabled as a group, by the Block Enable Clear Register,\r
+ then the corresponding bit will be '0'b and no interrupt will\r
+ be asserted. */\r
+ } BLOCK_IRQ_VECTOR_b; /*!< [25] BitSize */\r
+ };\r
+} INTS_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ TIMER0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This timer block offers a simple mechanism for firmware to maintain a time base. This timer may be instantiated as 16 bits or\r
+ 32 bits. The name of the timer instance indicates the size of the timer. (TIMER0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40000C00) TIMER0 Structure */\r
+ __IO uint32_t COUNT; /*!< (@ 0x40000C00) This is the value of the Timer counter. This\r
+ is updated by Hardware but may be set by Firmware. */\r
+ __IO uint32_t PRE_LOAD; /*!< (@ 0x40000C04) This is the value of the Timer pre-load for the\r
+ counter. This is used by H/W when the counter is to be restarted\r
+ automatically; this will become the new value of the counter\r
+ upon restart. */\r
+ \r
+ union {\r
+ __IO uint32_t STATUS; /*!< (@ 0x40000C08) This is the interrupt status that fires when\r
+ the timer reaches its limit */\r
+ \r
+ struct {\r
+ __IO uint32_t EVENT_INTERRUPT: 1; /*!< [0..0] This is the interrupt status that fires when the timer\r
+ reaches its limit. This is the interrupt status that fires when\r
+ the timer reaches its limit. This may be level or a self clearing\r
+ signal cycle pulse, based on the AUTO_RESTART bit in the Timer\r
+ Control Register. If the timer is set to automatically restart,\r
+ it will provide a pulse, otherwise a level is provided.(R/WC)\r
+ */\r
+ } STATUS_b; /*!< [1] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t INT_EN; /*!< (@ 0x40000C0C) This is the interrupt enable for the status EVENT_INTERRUPT\r
+ bit in the Timer Status Register */\r
+ \r
+ struct {\r
+ __IO uint32_t ENABLE : 1; /*!< [0..0] This is the interrupt enable for the status EVENT_INTERRUPT\r
+ bit in the Timer Status Register. */\r
+ } INT_EN_b; /*!< [1] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO REG32_U CONTROL; /*!< (@ 0x40000C10) Timer Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t ENABLE : 1; /*!< [0..0] This enables the block for operation. 1=This block will\r
+ function normally;\r
+ 0=This block will gate its clock and go into its lowest power\r
+ state */\r
+ uint32_t : 1;\r
+ __IO uint32_t COUNT_UP : 1; /*!< [2..2] This selects the counter direction. When the counter\r
+ in incrementing the counter will saturate and trigger the event\r
+ when it reaches all F's. When the counter is decrementing the\r
+ counter will saturate when it reaches 0h. 1=The counter will\r
+ increment;\r
+ 0=The counter will decrement */\r
+ __IO uint32_t AUTO_RESTART: 1; /*!< [3..3] This will select the action taken upon completing a count.\r
+ 1=The counter will automatically restart the count, using the\r
+ contents of the Timer Preload Register to load the Timer Count\r
+ Register.\r
+ The interrupt will be set in edge mode\r
+ 0=The counter will simply enter a done state and wait for further\r
+ control inputs. The interrupt will be set in level mode. */\r
+ __IO uint32_t SOFT_RESET : 1; /*!< [4..4] This is a soft reset. This is self clearing 1 cycle after\r
+ it is written. */\r
+ __IO uint32_t START : 1; /*!< [5..5] This bit triggers the timer counter. The counter will\r
+ operate until it hits its terminating condition. This will\r
+ clear this bit. It should be noted that when operating in restart\r
+ mode, there is no terminating condition for the counter, so\r
+ this bit will never clear. Clearing this bit will halt the timer\r
+ counter. */\r
+ __IO uint32_t RELOAD : 1; /*!< [6..6] This bit reloads the counter without interrupting it\r
+ operation. This will not function if the timer has already\r
+ completed (when the START bit in this register is '0'). This\r
+ is used to periodically prevent the timer from firing when an\r
+ event occurs. Usage while the timer is off may result in erroneous\r
+ behaviour. */\r
+ __IO uint32_t HALT : 1; /*!< [7..7] This is a halt bit. This will halt the timer as long\r
+ as it is active. Once the halt is inactive, the timer will\r
+ start from where it left off. 1=Timer is halted. It stops counting.\r
+ The clock divider will also be reset. 0=Timer runs normally.\r
+ */\r
+ uint32_t : 8;\r
+ __IO uint32_t PRE_SCALE : 16; /*!< [16..31] This is used to divide down the system clock through\r
+ clock enables to lower the power consumption of the block and\r
+ allow\r
+ slow timers. Updating this value during operation may result\r
+ in erroneous clock enable pulses until the clock divider restarts.\r
+ The number of clocks per clock enable pulse is (Value + 1);\r
+ a setting of 0 runs at the full clock speed, while a setting\r
+ of 1\r
+ runs at half speed. */\r
+ } CONTROL_b; /*!< [32] BitSize */\r
+ };\r
+} TIMER0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ EC_REG_BANK ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x4000FC00) EC_REG_BANK Structure */\r
+ __I uint32_t RESERVED;\r
+ __IO uint32_t AHB_ERROR_ADDRESS; /*!< (@ 0x4000FC04) AHB Error Address [0:0] AHB_ERR_ADDR, In priority\r
+ order:\r
+ 1. AHB address is registered when an AHB error occurs on the\r
+ processor's AHB master port and the register value was\r
+ already 0. This way only the first address to generate an exception\r
+ is captured.\r
+ 2. The processor can clear this register by writing any 32-bit\r
+ value to this register. */\r
+ __I uint32_t RESERVED1[3];\r
+ __IO uint8_t AHB_ERROR_CONTROL; /*!< (@ 0x4000FC14) AHB Error Control [0:0] AHB_ERROR_DISABLE, 0:\r
+ EC memory exceptions are enabled. 1: EC memory exceptions are\r
+ disabled. */\r
+ __I uint8_t RESERVED2[3];\r
+ __IO uint32_t INTERRUPT_CONTROL; /*!< (@ 0x4000FC18) Interrupt Control [0:0] NVIC_EN (NVIC_EN) This\r
+ bit enables Alternate NVIC IRQ's Vectors. The Alternate NVIC\r
+ Vectors provides each interrupt event with a dedicated (direct)\r
+ NVIC vector.\r
+ 0 = Alternate NVIC vectors disabled, 1= Alternate NVIC vectors\r
+ enabled */\r
+ __IO uint32_t ETM_TRACE_ENABLE; /*!< (@ 0x4000FC1C) ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) This\r
+ bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug\r
+ Interface pins are forced to the TRACE functions. 0 = ARM TRACE\r
+ port disabled, 1= ARM TRACE port enabled */\r
+ \r
+ union {\r
+ __IO uint32_t DEBUG_Enable; /*!< (@ 0x4000FC20) Debug Enable Register */\r
+ \r
+ struct {\r
+ __IO uint32_t DEBUG_EN : 1; /*!< [0..0] DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug\r
+ port.\r
+ 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e.,\r
+ the TRST# pin is ignored and the JTAG signals remain in their\r
+ non-JTAG state)\r
+ 1= JTAG/SWD port enabled. A high on TRST# enables JTAG or SWD,\r
+ as determined by SWD_EN. */\r
+ __IO uint32_t DEBUG_PIN_CFG: 2; /*!< [1..2] This field determines which pins are affected by the\r
+ TRST# debug enable pin.\r
+ 3=Reserved\r
+ 2=The pins associated with the JTAG TCK and TMS switch to the\r
+ debug interface when TRST# is de-asserted high. The pins\r
+ associated with TDI and TDO remain controlled by the associated\r
+ GPIO. This setting should be used when the ARM Serial\r
+ Wire Debug (SWD) is required for debugging and the Serial Wire\r
+ Viewer is not required\r
+ 1=The pins associated with the JTAG TCK, TMS and TDO switch\r
+ to the debug interface when TRST# i */\r
+ __IO uint32_t DEBUG_PU_EN: 1; /*!< [3..3] If this bit is set to '1b' internal pull-up resistors\r
+ are automatically enabled on the appropriate debugging port\r
+ wires whenever the debug port is enabled (the DEBUG_EN bit\r
+ in this register is '1b' and the JTAG_RST# pin is high). The\r
+ setting\r
+ of DEBUG_PIN_CFG determines which pins have pull-ups enabled\r
+ when the debug port is enabled. */\r
+ } DEBUG_Enable_b; /*!< [4] BitSize */\r
+ };\r
+ __I uint32_t RESERVED3;\r
+ __IO uint32_t WDT_EVENT_COUNT; /*!< (@ 0x4000FC28) WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These\r
+ EC R/W bits are cleared to 0 on VCC1 POR, but not on a WDT.\r
+ Note: This field is written by Boot ROM firmware to indicate\r
+ the number of times a WDT fired before loading a good EC code\r
+ image. */\r
+ \r
+ union {\r
+ __IO uint32_t AES_HASH_BYTE_SWAP_CONTROL; /*!< (@ 0x4000FC2C) AES HASH Byte Swap Control Register. */\r
+ \r
+ struct {\r
+ __I uint32_t INPUT_BYTE_SWAP_ENABLE: 1; /*!< [0..0] Used to enable byte swap on a DWORD during AHB read from\r
+ AES / HASH block: 1=Enable; 0=Disable. */\r
+ __IO uint32_t OUTPUT_BYTE_SWAP_ENABLE: 1; /*!< [1..1] Used to enable byte swap on a DWORD during AHB write\r
+ from AES / HASH block: 1=Enable; 0=Disable. */\r
+ __IO uint32_t INPUT_BLOCK_SWAP_ENABLE: 3; /*!< [2..4] Used to enable word swap on a DWORD during AHB read from\r
+ AES / HASH block\r
+ 4=Swap 32-bit doublewords in 128-byte blocks\r
+ 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus\r
+ references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C,\r
+ 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,...\r
+ 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references\r
+ issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,...\r
+ 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which\r
+ works on 64- */\r
+ __IO uint32_t OUTPUT_BLOCK_SWAP_ENABLE: 3; /*!< [5..7] Used to enable word swap on a DWORD during AHB write\r
+ from AES / HASH block\r
+ 4=Swap 32-bit doublewords in 128-byte blocks\r
+ 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus\r
+ references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C,\r
+ 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,...\r
+ 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references\r
+ issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,...\r
+ 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which\r
+ works on 64 */\r
+ } AES_HASH_BYTE_SWAP_CONTROL_b; /*!< [8] BitSize */\r
+ };\r
+ __I uint32_t RESERVED4[2];\r
+ \r
+ union {\r
+ __IO uint32_t SYSTEM_SHUTDOWN_RESET; /*!< (@ 0x4000FC38) System Shutdown Reset */\r
+ \r
+ struct {\r
+ __O uint32_t SYS_SHDN_RST: 1; /*!< [0..0] When this bit is asserted ('1'), the SYS_SHDN# output\r
+ is deasserted. */\r
+ } SYSTEM_SHUTDOWN_RESET_b; /*!< [1] BitSize */\r
+ };\r
+ __I uint32_t RESERVED5;\r
+ \r
+ union {\r
+ __IO uint32_t MISC_TRIM; /*!< (@ 0x4000FC40) Misc Trim */\r
+ \r
+ struct {\r
+ __O uint32_t PECI_DISABLE: 1; /*!< [0..0] When this bit is asserted ('1'), it disables the PECI\r
+ pads to reduce leakage. */\r
+ } MISC_TRIM_b; /*!< [1] BitSize */\r
+ };\r
+ __I uint32_t RESERVED6[6];\r
+ \r
+ union {\r
+ __IO uint32_t CRYPTO_SOFT_RESET; /*!< (@ 0x4000FC5C) System Shutdown Reset */\r
+ \r
+ struct {\r
+ __O uint32_t RNG_SOFT_RESET: 1; /*!< [0..0] When this bit is asserted ('1'), the Random Number Generator\r
+ block is reset. */\r
+ __O uint32_t PUBLIC_KEY_SOFT_RESET: 1; /*!< [1..1] When this bit is asserted ('1'), the Public Key block\r
+ is reset. */\r
+ __O uint32_t AES_HASH_SOFT_RESET: 1; /*!< [2..2] When this bit is asserted ('1'), the AES and Hash blocks\r
+ are reset. */\r
+ } CRYPTO_SOFT_RESET_b; /*!< [3] BitSize */\r
+ };\r
+ __I uint32_t RESERVED7;\r
+ \r
+ union {\r
+ __IO uint32_t GPIO_BANK_POWER; /*!< (@ 0x4000FC64) GPIO Bank Power Register */\r
+ \r
+ struct {\r
+ __O uint32_t VTR_LEVEL1 : 1; /*!< [0..0] Voltage value on VTR1. This bit is set by hardware after\r
+ a VTR Power On Reset, but may be overridden by software.\r
+ It must be set by software if the VTR power rail is not active\r
+ when RESET_SYS is de-asserted.\r
+ 1=VTR1 is powered by 3.3V\r
+ 0=VTR1 is powered by 1.8V. */\r
+ __O uint32_t VTR_LEVEL2 : 1; /*!< [1..1] Voltage value on VTR2. This bit is set by hardware after\r
+ a VTR Power On Reset, but may be overridden by software.\r
+ It must be set by software if the VTR power rail is not active\r
+ when RESET_SYS is de-asserted.\r
+ 1=VTR2 is powered by 3.3V\r
+ 0=VTR2 is powered by 1.8V. */\r
+ __O uint32_t VTR_LEVEL3 : 1; /*!< [2..2] Voltage value on VTR3. This bit is set by hardware after\r
+ a VTR Power On Reset, but may be overridden by software.\r
+ It must be set by software if the VTR power rail is not active\r
+ when RESET_SYS is de-asserted.\r
+ 1=VTR3 is powered by 3.3V\r
+ 0=VTR3 is powered by 1.8V. */\r
+ } GPIO_BANK_POWER_b; /*!< [3] BitSize */\r
+ };\r
+ __I uint32_t RESERVED8[2];\r
+ \r
+ union {\r
+ __IO uint32_t JTAG_MASTER_CFG; /*!< (@ 0x4000FC70) JTAG Master Configuration Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTM_CLK : 3; /*!< [0..2] This field determines the JTAG Master clock rate, derived\r
+ from the 48MHz master clock.\r
+ 7=375KHz; 6=750KHz; 5=1.5Mhz; 4=3Mhz; 3=6Mhz; 2=12Mhz; 1=24MHz;\r
+ 0=Reserved. */\r
+ __IO uint32_t MASTER_SLAVE: 1; /*!< [3..3] This bit controls the direction of the JTAG port. 1=The\r
+ JTAG Port is configured as a Master\r
+ 0=The JTAG Port is configures as a Slave. */\r
+ } JTAG_MASTER_CFG_b; /*!< [4] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t JTAG_MASTER_STS; /*!< (@ 0x4000FC74) JTAG Master Status Register */\r
+ \r
+ struct {\r
+ __I uint32_t JTM_DONE : 1; /*!< [0..0] This bit is set to '1b' when the JTAG Master Command\r
+ Register is written. It becomes '0b' when shifting has completed.\r
+ Software can poll this bit to determine when a command has\r
+ completed and it is therefore safe to remove the data in the\r
+ JTAG Master TDO\r
+ Register and load new data into the JTAG Master TMS Register\r
+ and the JTAG Master TDI Register. */\r
+ } JTAG_MASTER_STS_b; /*!< [1] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t JTAG_MASTER_TDO; /*!< (@ 0x4000FC78) JTAG Master TDO Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTM_TDO : 32; /*!< [0..31] When the JTAG Master Command Register is written, from\r
+ 1 to 32 bits are shifted into this register, starting with bit\r
+ 0,\r
+ from the JTAG_TDO pin. Shifting is at the rate determined by\r
+ the JTM_CLK field in the JTAG Master Configuration Register.\r
+ */\r
+ } JTAG_MASTER_TDO_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t JTAG_MASTER_TDI; /*!< (@ 0x4000FC7C) JTAG Master TDI Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTM_TDI : 32; /*!< [0..31] When the JTAG Master Command Register is written, from\r
+ 1 to 32 bits are shifted out of this register, starting with\r
+ bit 0,\r
+ onto the JTAG_TDI pin. Shifting is at the rate determined by\r
+ the JTM_CLK field in the JTAG Master Configuration Register.\r
+ */\r
+ } JTAG_MASTER_TDI_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t JTAG_MASTER_TMS; /*!< (@ 0x4000FC80) JTAG Master TMS Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTM_TMS : 32; /*!< [0..31] When the JTAG Master Command Register is written, from\r
+ 1 to 32 bits are shifted out of this register, starting with\r
+ bit 0,\r
+ onto the JTAG_TMS pin. Shifting is at the rate determined by\r
+ the JTM_CLK field in the JTAG Master Configuration Register.\r
+ */\r
+ } JTAG_MASTER_TMS_b; /*!< [32] BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t JTAG_MASTER_CMD; /*!< (@ 0x4000FC84) JTAG Master Command Register */\r
+ \r
+ struct {\r
+ __IO uint32_t JTM_COUNT : 5; /*!< [0..4] If the JTAG Port is configured as a Master, writing this\r
+ register starts clocking and shifting on the JTAG port. The\r
+ JTAG\r
+ Master port will shift JTM_COUNT+1 times, so writing a '0h'\r
+ will shift 1 bit, and writing '31h' will shift 32 bits. The\r
+ signal JTAG_CLK\r
+ will cycle JTM_COUNT+1 times. The contents of the JTAG Master\r
+ TMS Register and the JTAG Master TDI Register will be shifted\r
+ out on\r
+ the falling edge of JTAG_CLK and the.JTAG Master TDO Register\r
+ will get shifted in on the rising edge of JTAG_CLK.\r
+ If t */\r
+ } JTAG_MASTER_CMD_b; /*!< [5] BitSize */\r
+ };\r
+} EC_REG_BANK_Type;\r
+\r
+\r
+/* -------------------- End of section using anonymous unions ------------------- */\r
+#if defined(__CC_ARM)\r
+ #pragma pop\r
+#elif defined(__ICCARM__)\r
+ /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning restore\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PCR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */\r
+#define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bit 0) */\r
+#define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bitfield-Mask: 0x01) */\r
+#define PCR_SYS_SLP_CNTRL_TEST_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bit 2) */\r
+#define PCR_SYS_SLP_CNTRL_TEST_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bitfield-Mask: 0x01) */\r
+#define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Pos (3UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bit 3) */\r
+#define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Msk (0x8UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- PCR_PROC_CLK_CNTRL ----------------------------- */\r
+#define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Pos (0UL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bit 0) */\r
+#define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Msk (0xffUL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bitfield-Mask: 0xff) */\r
+\r
+/* ----------------------------- PCR_SLOW_CLK_CNTRL ----------------------------- */\r
+#define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Pos (0UL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bit 0) */\r
+#define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Msk (0x3ffUL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bitfield-Mask: 0x3ff) */\r
+\r
+/* --------------------------------- PCR_OSC_ID --------------------------------- */\r
+#define PCR_OSC_ID_TEST_Pos (0UL) /*!< PCR OSC_ID: TEST (Bit 0) */\r
+#define PCR_OSC_ID_TEST_Msk (0xffUL) /*!< PCR OSC_ID: TEST (Bitfield-Mask: 0xff) */\r
+#define PCR_OSC_ID_PLL_LOCK_Pos (8UL) /*!< PCR OSC_ID: PLL_LOCK (Bit 8) */\r
+#define PCR_OSC_ID_PLL_LOCK_Msk (0x100UL) /*!< PCR OSC_ID: PLL_LOCK (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- PCR_PCR_PWR_RST_STS ---------------------------- */\r
+#define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Pos (2UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bit 2) */\r
+#define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Msk (0x4UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Pos (3UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bit 3) */\r
+#define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Msk (0x8UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Pos (5UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bit 5) */\r
+#define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Msk (0x20UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Pos (6UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bit 6) */\r
+#define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Msk (0x40UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Pos (7UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bit 7) */\r
+#define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Msk (0x80UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bit 10) */\r
+#define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */\r
+#define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */\r
+#define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Pos (12UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bit 12) */\r
+#define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Msk (0x1000UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ PCR_PWR_RST_CNTRL ----------------------------- */\r
+#define PCR_PWR_RST_CNTRL_PWR_INV_Pos (0UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bit 0) */\r
+#define PCR_PWR_RST_CNTRL_PWR_INV_Msk (0x1UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bitfield-Mask: 0x01) */\r
+#define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Pos (8UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bit 8) */\r
+#define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Msk (0x100UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- PCR_SYS_RST -------------------------------- */\r
+#define PCR_SYS_RST_SOFT_SYS_RESET_Pos (8UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bit 8) */\r
+#define PCR_SYS_RST_SOFT_SYS_RESET_Msk (0x100UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_SLP_EN_0 -------------------------------- */\r
+#define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bit 0) */\r
+#define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_0_EFUSE_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bit 1) */\r
+#define PCR_SLP_EN_0_EFUSE_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_0_ISPI_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bit 2) */\r
+#define PCR_SLP_EN_0_ISPI_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_SLP_EN_1 -------------------------------- */\r
+#define PCR_SLP_EN_1_INT_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bit 0) */\r
+#define PCR_SLP_EN_1_INT_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PECI_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bit 1) */\r
+#define PCR_SLP_EN_1_PECI_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TACH0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bit 2) */\r
+#define PCR_SLP_EN_1_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM0_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bit 4) */\r
+#define PCR_SLP_EN_1_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PMC_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bit 5) */\r
+#define PCR_SLP_EN_1_PMC_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_DMA_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bit 6) */\r
+#define PCR_SLP_EN_1_DMA_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TFDP_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bit 7) */\r
+#define PCR_SLP_EN_1_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bit 8) */\r
+#define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_WDT_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bit 9) */\r
+#define PCR_SLP_EN_1_WDT_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_SMB0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bit 10) */\r
+#define PCR_SLP_EN_1_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TACH1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bit 11) */\r
+#define PCR_SLP_EN_1_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TACH2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bit 12) */\r
+#define PCR_SLP_EN_1_TACH2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bit 20) */\r
+#define PCR_SLP_EN_1_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bit 21) */\r
+#define PCR_SLP_EN_1_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bit 22) */\r
+#define PCR_SLP_EN_1_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bit 23) */\r
+#define PCR_SLP_EN_1_PWM4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM5_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bit 24) */\r
+#define PCR_SLP_EN_1_PWM5_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM6_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bit 25) */\r
+#define PCR_SLP_EN_1_PWM6_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM7_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bit 26) */\r
+#define PCR_SLP_EN_1_PWM7_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_PWM8_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bit 27) */\r
+#define PCR_SLP_EN_1_PWM8_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bit 29) */\r
+#define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bit 30) */\r
+#define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bit 31) */\r
+#define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_SLP_EN_2 -------------------------------- */\r
+#define PCR_SLP_EN_2_LPC_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bit 0) */\r
+#define PCR_SLP_EN_2_LPC_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_UART_0_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bit 1) */\r
+#define PCR_SLP_EN_2_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_UART_1_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bit 2) */\r
+#define PCR_SLP_EN_2_UART_1_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bit 12) */\r
+#define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bit 13) */\r
+#define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bit 14) */\r
+#define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bit 15) */\r
+#define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_KBCEM_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bit 16) */\r
+#define PCR_SLP_EN_2_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_MBX_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bit 17) */\r
+#define PCR_SLP_EN_2_MBX_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_RTC_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bit 18) */\r
+#define PCR_SLP_EN_2_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ESPI_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bit 19) */\r
+#define PCR_SLP_EN_2_ESPI_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bit 21) */\r
+#define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bit 22) */\r
+#define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bit 23) */\r
+#define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_ASIF_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bit 24) */\r
+#define PCR_SLP_EN_2_ASIF_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_PORT80_0_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bit 25) */\r
+#define PCR_SLP_EN_2_PORT80_0_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_2_PORT80_1_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bit 26) */\r
+#define PCR_SLP_EN_2_PORT80_1_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_SLP_EN_3 -------------------------------- */\r
+#define PCR_SLP_EN_3_ADC_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bit 3) */\r
+#define PCR_SLP_EN_3_ADC_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_PS2_0_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bit 5) */\r
+#define PCR_SLP_EN_3_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_PS2_1_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bit 6) */\r
+#define PCR_SLP_EN_3_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_PS2_2_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bit 7) */\r
+#define PCR_SLP_EN_3_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bit 9) */\r
+#define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bit 10) */\r
+#define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bit 11) */\r
+#define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bit 12) */\r
+#define PCR_SLP_EN_3_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_SMB1_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bit 13) */\r
+#define PCR_SLP_EN_3_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_SMB2_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bit 14) */\r
+#define PCR_SLP_EN_3_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_SMB3_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bit 15) */\r
+#define PCR_SLP_EN_3_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_LED0_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bit 16) */\r
+#define PCR_SLP_EN_3_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_LED1_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bit 17) */\r
+#define PCR_SLP_EN_3_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_LED2_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bit 18) */\r
+#define PCR_SLP_EN_3_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_BCM0_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bit 19) */\r
+#define PCR_SLP_EN_3_BCM0_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bit 20) */\r
+#define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bit 21) */\r
+#define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bit 22) */\r
+#define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bit 23) */\r
+#define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bit 24) */\r
+#define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_LED3_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bit 25) */\r
+#define PCR_SLP_EN_3_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_PKE_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bit 26) */\r
+#define PCR_SLP_EN_3_PKE_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_RNG_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bit 27) */\r
+#define PCR_SLP_EN_3_RNG_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_AES_HASH_SLP_EN_Pos (28UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bit 28) */\r
+#define PCR_SLP_EN_3_AES_HASH_SLP_EN_Msk (0x10000000UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bit 29) */\r
+#define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_CCTIMER_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bit 30) */\r
+#define PCR_SLP_EN_3_CCTIMER_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_3_PWM9_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bit 31) */\r
+#define PCR_SLP_EN_3_PWM9_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_SLP_EN_4 -------------------------------- */\r
+#define PCR_SLP_EN_4_PWM10_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bit 0) */\r
+#define PCR_SLP_EN_4_PWM10_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_PWM11_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bit 1) */\r
+#define PCR_SLP_EN_4_PWM11_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bit 2) */\r
+#define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bit 3) */\r
+#define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bit 4) */\r
+#define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bit 5) */\r
+#define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_RTOS_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bit 6) */\r
+#define PCR_SLP_EN_4_RTOS_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bit 7) */\r
+#define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_QSPI_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bit 8) */\r
+#define PCR_SLP_EN_4_QSPI_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_BCM1_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bit 9) */\r
+#define PCR_SLP_EN_4_BCM1_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_RC_ID0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bit 10) */\r
+#define PCR_SLP_EN_4_RC_ID0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_RC_ID1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bit 11) */\r
+#define PCR_SLP_EN_4_RC_ID1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_RC_ID2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bit 12) */\r
+#define PCR_SLP_EN_4_RC_ID2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_SLP_EN_4_FCL_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bit 15) */\r
+#define PCR_SLP_EN_4_FCL_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_CLK_REQ_0 ------------------------------- */\r
+#define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bit 0) */\r
+#define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bit 1) */\r
+#define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_0_ISPI_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bit 2) */\r
+#define PCR_CLK_REQ_0_ISPI_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_CLK_REQ_1 ------------------------------- */\r
+#define PCR_CLK_REQ_1_INT_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bit 0) */\r
+#define PCR_CLK_REQ_1_INT_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PECI_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bit 1) */\r
+#define PCR_CLK_REQ_1_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TACH0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bit 2) */\r
+#define PCR_CLK_REQ_1_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM0_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bit 4) */\r
+#define PCR_CLK_REQ_1_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PMC_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bit 5) */\r
+#define PCR_CLK_REQ_1_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_DMA_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bit 6) */\r
+#define PCR_CLK_REQ_1_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TFDP_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bit 7) */\r
+#define PCR_CLK_REQ_1_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bit 8) */\r
+#define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_WDT_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bit 9) */\r
+#define PCR_CLK_REQ_1_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_SMB0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bit 10) */\r
+#define PCR_CLK_REQ_1_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TACH1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bit 11) */\r
+#define PCR_CLK_REQ_1_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TACH2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bit 12) */\r
+#define PCR_CLK_REQ_1_TACH2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bit 20) */\r
+#define PCR_CLK_REQ_1_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bit 21) */\r
+#define PCR_CLK_REQ_1_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bit 22) */\r
+#define PCR_CLK_REQ_1_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bit 23) */\r
+#define PCR_CLK_REQ_1_PWM4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM5_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bit 24) */\r
+#define PCR_CLK_REQ_1_PWM5_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM6_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bit 25) */\r
+#define PCR_CLK_REQ_1_PWM6_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM7_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bit 26) */\r
+#define PCR_CLK_REQ_1_PWM7_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_PWM8_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bit 27) */\r
+#define PCR_CLK_REQ_1_PWM8_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bit 29) */\r
+#define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bit 30) */\r
+#define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bit 31) */\r
+#define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_CLK_REQ_2 ------------------------------- */\r
+#define PCR_CLK_REQ_2_LPC_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bit 0) */\r
+#define PCR_CLK_REQ_2_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_UART_0_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bit 1) */\r
+#define PCR_CLK_REQ_2_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_UART_1_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bit 2) */\r
+#define PCR_CLK_REQ_2_UART_1_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bit 12) */\r
+#define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bit 13) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bit 14) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bit 15) */\r
+#define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bit 16) */\r
+#define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_MBX_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bit 17) */\r
+#define PCR_CLK_REQ_2_MBX_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_RTC_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bit 18) */\r
+#define PCR_CLK_REQ_2_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ESPI_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bit 19) */\r
+#define PCR_CLK_REQ_2_ESPI_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bit 21) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bit 22) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bit 23) */\r
+#define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_ASIF_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bit 24) */\r
+#define PCR_CLK_REQ_2_ASIF_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bit 25) */\r
+#define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bit 26) */\r
+#define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_CLK_REQ_3 ------------------------------- */\r
+#define PCR_CLK_REQ_3_ADC_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bit 3) */\r
+#define PCR_CLK_REQ_3_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bit 5) */\r
+#define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bit 6) */\r
+#define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bit 7) */\r
+#define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bit 9) */\r
+#define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bit 10) */\r
+#define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bit 11) */\r
+#define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bit 12) */\r
+#define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_SMB1_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bit 13) */\r
+#define PCR_CLK_REQ_3_SMB1_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_SMB2_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bit 14) */\r
+#define PCR_CLK_REQ_3_SMB2_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_SMB3_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bit 15) */\r
+#define PCR_CLK_REQ_3_SMB3_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_LED0_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bit 16) */\r
+#define PCR_CLK_REQ_3_LED0_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_LED1_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bit 17) */\r
+#define PCR_CLK_REQ_3_LED1_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_LED2_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bit 18) */\r
+#define PCR_CLK_REQ_3_LED2_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_BCM0_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bit 19) */\r
+#define PCR_CLK_REQ_3_BCM0_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bit 20) */\r
+#define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bit 21) */\r
+#define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bit 22) */\r
+#define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bit 23) */\r
+#define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bit 24) */\r
+#define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_LED3_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bit 25) */\r
+#define PCR_CLK_REQ_3_LED3_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_PKE_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bit 26) */\r
+#define PCR_CLK_REQ_3_PKE_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_RNG_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bit 27) */\r
+#define PCR_CLK_REQ_3_RNG_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Pos (28UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bit 28) */\r
+#define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Msk (0x10000000UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bit 29) */\r
+#define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bit 30) */\r
+#define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_3_PWM9_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bit 31) */\r
+#define PCR_CLK_REQ_3_PWM9_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_CLK_REQ_4 ------------------------------- */\r
+#define PCR_CLK_REQ_4_PWM10_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bit 0) */\r
+#define PCR_CLK_REQ_4_PWM10_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_PWM11_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bit 1) */\r
+#define PCR_CLK_REQ_4_PWM11_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bit 2) */\r
+#define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bit 3) */\r
+#define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bit 4) */\r
+#define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bit 5) */\r
+#define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_RTOS_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bit 6) */\r
+#define PCR_CLK_REQ_4_RTOS_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bit 7) */\r
+#define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_QSPI_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bit 8) */\r
+#define PCR_CLK_REQ_4_QSPI_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_BCM1_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bit 9) */\r
+#define PCR_CLK_REQ_4_BCM1_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bit 10) */\r
+#define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bit 11) */\r
+#define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bit 12) */\r
+#define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_CLK_REQ_4_FCL_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bit 15) */\r
+#define PCR_CLK_REQ_4_FCL_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_RST_EN_0 -------------------------------- */\r
+#define PCR_RST_EN_0_JTAG_STAP_RST_EN_Pos (0UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bit 0) */\r
+#define PCR_RST_EN_0_JTAG_STAP_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_0_EFUSE_RST_EN_Pos (1UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bit 1) */\r
+#define PCR_RST_EN_0_EFUSE_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_0_ISPI_RST_EN_Pos (2UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bit 2) */\r
+#define PCR_RST_EN_0_ISPI_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_RST_EN_1 -------------------------------- */\r
+#define PCR_RST_EN_1_INT_RST_EN_Pos (0UL) /*!< PCR RST_EN_1: INT_RST_EN (Bit 0) */\r
+#define PCR_RST_EN_1_INT_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_1: INT_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PECI_RST_EN_Pos (1UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bit 1) */\r
+#define PCR_RST_EN_1_PECI_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TACH0_RST_EN_Pos (2UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bit 2) */\r
+#define PCR_RST_EN_1_TACH0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM0_RST_EN_Pos (4UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bit 4) */\r
+#define PCR_RST_EN_1_PWM0_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PMC_RST_EN_Pos (5UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bit 5) */\r
+#define PCR_RST_EN_1_PMC_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_DMA_RST_EN_Pos (6UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bit 6) */\r
+#define PCR_RST_EN_1_DMA_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TFDP_RST_EN_Pos (7UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bit 7) */\r
+#define PCR_RST_EN_1_TFDP_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bit 8) */\r
+#define PCR_RST_EN_1_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_WDT_RST_EN_Pos (9UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bit 9) */\r
+#define PCR_RST_EN_1_WDT_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_SMB0_RST_EN_Pos (10UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bit 10) */\r
+#define PCR_RST_EN_1_SMB0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TACH1_RST_EN_Pos (11UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bit 11) */\r
+#define PCR_RST_EN_1_TACH1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TACH2_RST_EN_Pos (12UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bit 12) */\r
+#define PCR_RST_EN_1_TACH2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM1_RST_EN_Pos (20UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bit 20) */\r
+#define PCR_RST_EN_1_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM2_RST_EN_Pos (21UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bit 21) */\r
+#define PCR_RST_EN_1_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM3_RST_EN_Pos (22UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bit 22) */\r
+#define PCR_RST_EN_1_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM4_RST_EN_Pos (23UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bit 23) */\r
+#define PCR_RST_EN_1_PWM4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM5_RST_EN_Pos (24UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bit 24) */\r
+#define PCR_RST_EN_1_PWM5_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM6_RST_EN_Pos (25UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bit 25) */\r
+#define PCR_RST_EN_1_PWM6_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM7_RST_EN_Pos (26UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bit 26) */\r
+#define PCR_RST_EN_1_PWM7_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_PWM8_RST_EN_Pos (27UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bit 27) */\r
+#define PCR_RST_EN_1_PWM8_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bit 29) */\r
+#define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bit 30) */\r
+#define PCR_RST_EN_1_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_1_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bit 31) */\r
+#define PCR_RST_EN_1_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_RST_EN_2 -------------------------------- */\r
+#define PCR_RST_EN_2_LPC_RST_EN_Pos (0UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bit 0) */\r
+#define PCR_RST_EN_2_LPC_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_UART_0_RST_EN_Pos (1UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bit 1) */\r
+#define PCR_RST_EN_2_UART_0_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_UART_1_RST_EN_Pos (2UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bit 2) */\r
+#define PCR_RST_EN_2_UART_1_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bit 12) */\r
+#define PCR_RST_EN_2_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bit 13) */\r
+#define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bit 14) */\r
+#define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bit 15) */\r
+#define PCR_RST_EN_2_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_KBCEM_RST_EN_Pos (16UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bit 16) */\r
+#define PCR_RST_EN_2_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_MBX_RST_EN_Pos (17UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bit 17) */\r
+#define PCR_RST_EN_2_MBX_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_RTC_RST_EN_Pos (18UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bit 18) */\r
+#define PCR_RST_EN_2_RTC_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ESPI_RST_EN_Pos (19UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bit 19) */\r
+#define PCR_RST_EN_2_ESPI_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bit 21) */\r
+#define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bit 22) */\r
+#define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Pos (23UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bit 23) */\r
+#define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_ASIF_RST_EN_Pos (24UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bit 24) */\r
+#define PCR_RST_EN_2_ASIF_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_PORT80_0_RST_EN_Pos (25UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bit 25) */\r
+#define PCR_RST_EN_2_PORT80_0_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_2_PORT80_1_RST_EN_Pos (26UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bit 26) */\r
+#define PCR_RST_EN_2_PORT80_1_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_RST_EN_3 -------------------------------- */\r
+#define PCR_RST_EN_3_ADC_RST_EN_Pos (3UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bit 3) */\r
+#define PCR_RST_EN_3_ADC_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_PS2_0_RST_EN_Pos (5UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bit 5) */\r
+#define PCR_RST_EN_3_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_PS2_1_RST_EN_Pos (6UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bit 6) */\r
+#define PCR_RST_EN_3_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_PS2_2_RST_EN_Pos (7UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bit 7) */\r
+#define PCR_RST_EN_3_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_GP_SPI0_RST_EN_Pos (9UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bit 9) */\r
+#define PCR_RST_EN_3_GP_SPI0_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_HTIMER_0_RST_EN_Pos (10UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bit 10) */\r
+#define PCR_RST_EN_3_HTIMER_0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bit 11) */\r
+#define PCR_RST_EN_3_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_RPMPWM0_RST_EN_Pos (12UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bit 12) */\r
+#define PCR_RST_EN_3_RPMPWM0_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_SMB1_RST_EN_Pos (13UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bit 13) */\r
+#define PCR_RST_EN_3_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_SMB2_RST_EN_Pos (14UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bit 14) */\r
+#define PCR_RST_EN_3_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_SMB3_RST_EN_Pos (15UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bit 15) */\r
+#define PCR_RST_EN_3_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_LED0_RST_EN_Pos (16UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bit 16) */\r
+#define PCR_RST_EN_3_LED0_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_LED1_RST_EN_Pos (17UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bit 17) */\r
+#define PCR_RST_EN_3_LED1_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_LED2_RST_EN_Pos (18UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bit 18) */\r
+#define PCR_RST_EN_3_LED2_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_BCM0_RST_EN_Pos (19UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bit 19) */\r
+#define PCR_RST_EN_3_BCM0_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_GP_SPI1_RST_EN_Pos (20UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bit 20) */\r
+#define PCR_RST_EN_3_GP_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bit 21) */\r
+#define PCR_RST_EN_3_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bit 22) */\r
+#define PCR_RST_EN_3_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bit 23) */\r
+#define PCR_RST_EN_3_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bit 24) */\r
+#define PCR_RST_EN_3_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_LED3_RST_EN_Pos (25UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bit 25) */\r
+#define PCR_RST_EN_3_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_PKE_RST_EN_Pos (26UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bit 26) */\r
+#define PCR_RST_EN_3_PKE_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_RNG_RST_EN_Pos (27UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bit 27) */\r
+#define PCR_RST_EN_3_RNG_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_AES_HASH_RST_EN_Pos (28UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bit 28) */\r
+#define PCR_RST_EN_3_AES_HASH_RST_EN_Msk (0x10000000UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_HTIMER_1_RST_EN_Pos (29UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bit 29) */\r
+#define PCR_RST_EN_3_HTIMER_1_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_CCTIMER_RST_EN_Pos (30UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bit 30) */\r
+#define PCR_RST_EN_3_CCTIMER_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_3_PWM9_RST_EN_Pos (31UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bit 31) */\r
+#define PCR_RST_EN_3_PWM9_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_RST_EN_4 -------------------------------- */\r
+#define PCR_RST_EN_4_PWM10_RST_EN_Pos (0UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bit 0) */\r
+#define PCR_RST_EN_4_PWM10_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_PWM11_RST_EN_Pos (1UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bit 1) */\r
+#define PCR_RST_EN_4_PWM11_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_CNT_TMER0_RST_EN_Pos (2UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bit 2) */\r
+#define PCR_RST_EN_4_CNT_TMER0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_CNT_TMER1_RST_EN_Pos (3UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bit 3) */\r
+#define PCR_RST_EN_4_CNT_TMER1_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_CNT_TMER2_RST_EN_Pos (4UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bit 4) */\r
+#define PCR_RST_EN_4_CNT_TMER2_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_CNT_TMER3_RST_EN_Pos (5UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bit 5) */\r
+#define PCR_RST_EN_4_CNT_TMER3_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_RTOS_RST_EN_Pos (6UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bit 6) */\r
+#define PCR_RST_EN_4_RTOS_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_RPMPWM1_RST_EN_Pos (7UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bit 7) */\r
+#define PCR_RST_EN_4_RPMPWM1_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_QSPI_RST_EN_Pos (8UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bit 8) */\r
+#define PCR_RST_EN_4_QSPI_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_BCM1_RST_EN_Pos (9UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bit 9) */\r
+#define PCR_RST_EN_4_BCM1_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_RC_ID0_RST_EN_Pos (10UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bit 10) */\r
+#define PCR_RST_EN_4_RC_ID0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_RC_ID1_RST_EN_Pos (11UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bit 11) */\r
+#define PCR_RST_EN_4_RC_ID1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_RC_ID2_RST_EN_Pos (12UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bit 12) */\r
+#define PCR_RST_EN_4_RC_ID2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_RST_EN_4_FCL_RST_EN_Pos (15UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bit 15) */\r
+#define PCR_RST_EN_4_FCL_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'INTS' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------- INTS_BLOCK_ENABLE_SET --------------------------- */\r
+#define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Pos (0UL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bit 0) */\r
+#define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bitfield-Mask: 0x7fffffff) */\r
+\r
+/* --------------------------- INTS_BLOCK_ENABLE_CLEAR -------------------------- */\r
+#define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Pos (0UL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bit 0) */\r
+#define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bitfield-Mask: 0x7fffffff) */\r
+\r
+/* ---------------------------- INTS_BLOCK_IRQ_VECTOR --------------------------- */\r
+#define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Pos (0UL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bit 0) */\r
+#define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Msk (0x1ffffffUL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bitfield-Mask: 0x1ffffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'WDT' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- WDT_WDT_CONTROL ------------------------------ */\r
+#define WDT_WDT_CONTROL_WDT_ENABLE_Pos (0UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bit 0) */\r
+#define WDT_WDT_CONTROL_WDT_ENABLE_Msk (0x1UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bitfield-Mask: 0x01) */\r
+#define WDT_WDT_CONTROL_WDT_STATUS_Pos (1UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bit 1) */\r
+#define WDT_WDT_CONTROL_WDT_STATUS_Msk (0x2UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bitfield-Mask: 0x01) */\r
+#define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Pos (2UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bit 2) */\r
+#define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Msk (0x4UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bitfield-Mask: 0x01) */\r
+#define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Pos (3UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bit 3) */\r
+#define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Msk (0x8UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bitfield-Mask: 0x01) */\r
+#define WDT_WDT_CONTROL_JTAG_STALL_Pos (4UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bit 4) */\r
+#define WDT_WDT_CONTROL_JTAG_STALL_Msk (0x10UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER0_STATUS ------------------------------- */\r
+#define TIMER0_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER0_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER0_INT_EN ------------------------------- */\r
+#define TIMER0_INT_EN_ENABLE_Pos (0UL) /*!< TIMER0 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER0_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER0 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER0_CONTROL ------------------------------- */\r
+#define TIMER0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER0 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER0 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_START_Pos (5UL) /*!< TIMER0 CONTROL: START (Bit 5) */\r
+#define TIMER0_CONTROL_START_Msk (0x20UL) /*!< TIMER0 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER0 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_HALT_Pos (7UL) /*!< TIMER0 CONTROL: HALT (Bit 7) */\r
+#define TIMER0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER0 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER1_STATUS ------------------------------- */\r
+#define TIMER1_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER1_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER1_INT_EN ------------------------------- */\r
+#define TIMER1_INT_EN_ENABLE_Pos (0UL) /*!< TIMER1 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER1_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER1 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER1_CONTROL ------------------------------- */\r
+#define TIMER1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER1 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER1 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_START_Pos (5UL) /*!< TIMER1 CONTROL: START (Bit 5) */\r
+#define TIMER1_CONTROL_START_Msk (0x20UL) /*!< TIMER1 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER1 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_HALT_Pos (7UL) /*!< TIMER1 CONTROL: HALT (Bit 7) */\r
+#define TIMER1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER1 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER2_STATUS ------------------------------- */\r
+#define TIMER2_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER2_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER2_INT_EN ------------------------------- */\r
+#define TIMER2_INT_EN_ENABLE_Pos (0UL) /*!< TIMER2 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER2_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER2 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER2_CONTROL ------------------------------- */\r
+#define TIMER2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER2 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER2 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_START_Pos (5UL) /*!< TIMER2 CONTROL: START (Bit 5) */\r
+#define TIMER2_CONTROL_START_Msk (0x20UL) /*!< TIMER2 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER2 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_HALT_Pos (7UL) /*!< TIMER2 CONTROL: HALT (Bit 7) */\r
+#define TIMER2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER2 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER3_STATUS ------------------------------- */\r
+#define TIMER3_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER3_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER3_INT_EN ------------------------------- */\r
+#define TIMER3_INT_EN_ENABLE_Pos (0UL) /*!< TIMER3 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER3_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER3 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER3_CONTROL ------------------------------- */\r
+#define TIMER3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER3 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER3 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_START_Pos (5UL) /*!< TIMER3 CONTROL: START (Bit 5) */\r
+#define TIMER3_CONTROL_START_Msk (0x20UL) /*!< TIMER3 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER3 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_HALT_Pos (7UL) /*!< TIMER3 CONTROL: HALT (Bit 7) */\r
+#define TIMER3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER3 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER4' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER4_STATUS ------------------------------- */\r
+#define TIMER4_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER4_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER4_INT_EN ------------------------------- */\r
+#define TIMER4_INT_EN_ENABLE_Pos (0UL) /*!< TIMER4 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER4_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER4 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER4_CONTROL ------------------------------- */\r
+#define TIMER4_CONTROL_ENABLE_Pos (0UL) /*!< TIMER4 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER4_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER4 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER4 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER4_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER4 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER4_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER4_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_START_Pos (5UL) /*!< TIMER4 CONTROL: START (Bit 5) */\r
+#define TIMER4_CONTROL_START_Msk (0x20UL) /*!< TIMER4 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_RELOAD_Pos (6UL) /*!< TIMER4 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER4_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER4 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_HALT_Pos (7UL) /*!< TIMER4 CONTROL: HALT (Bit 7) */\r
+#define TIMER4_CONTROL_HALT_Msk (0x80UL) /*!< TIMER4 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER4_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER4_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER5' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TIMER5_STATUS ------------------------------- */\r
+#define TIMER5_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bit 0) */\r
+#define TIMER5_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- TIMER5_INT_EN ------------------------------- */\r
+#define TIMER5_INT_EN_ENABLE_Pos (0UL) /*!< TIMER5 INT_EN: ENABLE (Bit 0) */\r
+#define TIMER5_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER5 INT_EN: ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- TIMER5_CONTROL ------------------------------- */\r
+#define TIMER5_CONTROL_ENABLE_Pos (0UL) /*!< TIMER5 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER5_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER5 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER5 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER5_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER5 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER5_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER5_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_START_Pos (5UL) /*!< TIMER5 CONTROL: START (Bit 5) */\r
+#define TIMER5_CONTROL_START_Msk (0x20UL) /*!< TIMER5 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_RELOAD_Pos (6UL) /*!< TIMER5 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER5_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER5 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_HALT_Pos (7UL) /*!< TIMER5 CONTROL: HALT (Bit 7) */\r
+#define TIMER5_CONTROL_HALT_Msk (0x80UL) /*!< TIMER5 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER5_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER5_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'EC_REG_BANK' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------- EC_REG_BANK_DEBUG_Enable -------------------------- */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Pos (0UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bit 0) */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Msk (0x1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Pos (1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bit 1) */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Msk (0x6UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bitfield-Mask: 0x03) */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Pos (3UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bit 3) */\r
+#define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Msk (0x8UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------- EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL ------------------- */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Pos (0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bit 0) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Msk (0x1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Pos (1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bit 1) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Msk (0x2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Pos (2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bit 2) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Msk (0x1cUL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Pos (5UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bit 5) */\r
+#define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Msk (0xe0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */\r
+\r
+/* ---------------------- EC_REG_BANK_SYSTEM_SHUTDOWN_RESET --------------------- */\r
+#define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Pos (0UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bit 0) */\r
+#define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Msk (0x1UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------- EC_REG_BANK_MISC_TRIM --------------------------- */\r
+#define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Pos (0UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bit 0) */\r
+#define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Msk (0x1UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------ EC_REG_BANK_CRYPTO_SOFT_RESET ----------------------- */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Pos (0UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bit 0) */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Msk (0x1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Pos (1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bit 1) */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Msk (0x2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Pos (2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bit 2) */\r
+#define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Msk (0x4UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------- EC_REG_BANK_GPIO_BANK_POWER ------------------------ */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Pos (0UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bit 0) */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Msk (0x1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Pos (1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bit 1) */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Msk (0x2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bitfield-Mask: 0x01) */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Pos (2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bit 2) */\r
+#define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Msk (0x4UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_CFG ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Msk (0x7UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bitfield-Mask: 0x07) */\r
+#define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Pos (3UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bit 3) */\r
+#define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Msk (0x8UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_STS ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Msk (0x1UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_TDO ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bitfield-Mask: 0xffffffff) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_TDI ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bitfield-Mask: 0xffffffff) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_TMS ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bitfield-Mask: 0xffffffff) */\r
+\r
+/* ------------------------- EC_REG_BANK_JTAG_MASTER_CMD ------------------------ */\r
+#define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bit 0) */\r
+#define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Msk (0x1fUL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bitfield-Mask: 0x1f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral memory map ================ */\r
+/* ================================================================================ */\r
+\r
+#define PCR_BASE 0x40080100UL\r
+#define INTS_BASE 0x4000E000UL\r
+#define TIMER0_BASE 0x40000C00UL\r
+#define TIMER1_BASE 0x40000C20UL\r
+#define TIMER2_BASE 0x40000C40UL\r
+#define TIMER3_BASE 0x40000C60UL\r
+#define TIMER4_BASE 0x40000C80UL\r
+#define TIMER5_BASE 0x40000CA0UL\r
+#define EC_REG_BANK_BASE 0x4000FC00UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral declaration ================ */\r
+/* ================================================================================ */\r
+\r
+#define MEC2016_PCR ((PCR_Type *) PCR_BASE)\r
+#define MEC2016_INTS ((INTS_Type *) INTS_BASE)\r
+#define MEC2016_TIMER0 ((TIMER0_Type *) TIMER0_BASE)\r
+#define MEC2016_TIMER1 ((TIMER0_Type *) TIMER1_BASE)\r
+#define MEC2016_TIMER2 ((TIMER0_Type *) TIMER2_BASE)\r
+#define MEC2016_TIMER3 ((TIMER0_Type *) TIMER3_BASE)\r
+#define MEC2016_TIMER4 ((TIMER0_Type *) TIMER4_BASE)\r
+#define MEC2016_TIMER5 ((TIMER0_Type *) TIMER5_BASE)\r
+#define MEC2016_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group MCHP_device_internal */\r
+/** @} */ /* End of group Microchip Technology Inc. */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* MCHP_device_internal_H */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated with unit testing feedbacks\r
+******************************************************************************/\r
+/** @file btimer.h\r
+* \brief Basic Timer Peripheral Header file\r
+* \author jvasanth\r
+* \r
+* This file is the header file for Basic Timer Peripheral \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#ifndef _BTIMER_H\r
+#define _BTIMER_H\r
+\r
+/******************************************************************************/\r
+/** Logical Timer ID for APIs.\r
+ * This is the timer IDs passed to Basic Timer API function calls \r
+ *******************************************************************************/\r
+enum _PID_BTIMER_\r
+{\r
+ PID_BTIMER_0,\r
+ PID_BTIMER_1,\r
+ PID_BTIMER_2,\r
+ PID_BTIMER_3,\r
+ PID_BTIMER_4,\r
+ PID_BTIMER_5,\r
+ PID_BTIMER_MAX \r
+};\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Logical flags for Timer Control */\r
+/* ---------------------------------------------------------------------- */\r
+//This is for tmr_cntl parameter in btimer_init function\r
+#define BTIMER_AUTO_RESTART (0x08u)\r
+#define BTIMER_ONE_SHOT (0u)\r
+#define BTIMER_COUNT_UP (0x04u)\r
+#define BTIMER_COUNT_DOWN (0u)\r
+#define BTIMER_INT_EN (0x01u)\r
+#define BTIMER_NO_INT (0u)\r
+/* ---------------------------------------------------------------------- */\r
+\r
+\r
+//Timer Block Hardware Bits and Masks\r
+#define BTIMER_CNTL_HALT (0x80UL)\r
+#define BTIMER_CNTL_RELOAD (0x40UL)\r
+#define BTIMER_CNTL_START (0x20UL)\r
+#define BTIMER_CNTL_SOFT_RESET (0x10UL)\r
+#define BTIMER_CNTL_AUTO_RESTART (0x08UL)\r
+#define BTIMER_CNTL_COUNT_UP (0x04UL)\r
+#define BTIMER_CNTL_ENABLE (0x01UL)\r
+\r
+#define BTIMER_CNTL_HALT_BIT (7U)\r
+#define BTIMER_CNTL_RELOAD_BIT (6U)\r
+#define BTIMER_CNTL_START_BIT (5U)\r
+#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)\r
+#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)\r
+#define BTIMER_CNTL_COUNT_DIR_BIT (2U)\r
+#define BTIMER_CNTL_ENABLE_BIT (0U)\r
+\r
+#define BTIMER_GIRQ MEC_GIRQ23_ID\r
+#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Basic Timer Intitialization function */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Initialize specified timer\r
+ * @param btimer_id Basic Timer ID\r
+ * @param tmr_cntl Logical flags for Timer Control\r
+ * @param initial_count Initial Count\r
+ * @param preload_count Preload Count\r
+ * @note Performs a soft reset of the timer before configuration \r
+ */\r
+void btimer_init(uint8_t btimer_id, \r
+ uint16_t tmr_cntl,\r
+ uint16_t prescaler,\r
+ uint32_t initial_count,\r
+ uint32_t preload_count);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to program and read the Basic Timer Counter */\r
+/* ---------------------------------------------------------------------- */\r
+/** Program timer's counter register.\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count new counter value \r
+ * @note Timer hardware may implement a 16-bit or 32-bit \r
+ * hardware counter. If the timer is 16-bit only the lower\r
+ * 16-bits of the count paramter are used.\r
+ */\r
+void btimer_count_set(uint8_t btimer_id, uint32_t count);\r
+\r
+/** Return current value of timer's count register.\r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint32_t timer count may be 32 or 16 bits depending \r
+ * upon the hardware. Timers 0-3 are 16-bit\r
+ * and Timers 4-5 are 32-bit.\r
+ */\r
+uint32_t btimer_count_get(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Function to reload counter from Preload Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Force timer to reload counter from preload \r
+ * register. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note Hardware will only reload counter if timer is running. \r
+ */\r
+void btimer_reload(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for stopping and starting the basic Timer */\r
+/* ---------------------------------------------------------------------- */\r
+/** Start timer counting.\r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_start(uint8_t btimer_id);\r
+\r
+/** Stop timer. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note When a stopped timer is started again it will reload \r
+ * the count register from preload value.\r
+ */\r
+void btimer_stop(uint8_t btimer_id);\r
+\r
+/** Return state of timer's START bit. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 0(timer not started), 1 (timer started)\r
+ */\r
+uint8_t btimer_is_started(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Function to perform basic timer soft reset */\r
+/* ---------------------------------------------------------------------- */\r
+/** Peform soft reset of specified timer. \r
+ * @param btimer_id Basic Timer ID \r
+ * @note Soft reset set all registers to POR values.\r
+ * Spins 256 times waiting on hardware to clear reset bit. \r
+ */\r
+void btimer_reset(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to halt/unhalt the timer counting */\r
+/* ---------------------------------------------------------------------- */\r
+/** Halt timer counting with no reload on unhalt. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note A halted timer will not reload the count register when \r
+ * unhalted, it will continue counting from the current\r
+ * count value.\r
+ */\r
+void btimer_halt(uint8_t btimer_id);\r
+\r
+/** Unhalt timer counting. \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_unhalt(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer interrupt */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enable specified timer's interrupt from the block. \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param ien Non-zero enable interrupt in timer block, 0 \r
+ * disable.\r
+ */\r
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);\r
+\r
+/** Read Timer interrupt status and clear if set \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 1 (Timer interrupt status set) else 0. \r
+ * @note If timer interrupt status is set then clear it before \r
+ * returning.\r
+ */\r
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer GIRQ */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enables GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_clr(uint8_t btimer_id);\r
+\r
+/** Returns GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
+ */\r
+uint8_t btimer_girq_src_get(uint8_t btimer_id);\r
+\r
+/** Clears GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_src_clr(uint8_t btimer_id);\r
+\r
+/** Returns GIRQ result bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
+ */\r
+uint8_t btimer_girq_result_get(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer Sleep */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enable/Disable clock gating on idle of a timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
+ */\r
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);\r
+\r
+/** Returns clk required status for the timer block\r
+ * @param btimer_id Basic Timer ID.\r
+ * @return Non-zero if clk required, else 0\r
+ */\r
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);\r
+\r
+/** Enable/Disable reset on sleep for the timer block \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param reset_en 1 to enable, 0 to disable\r
+ */\r
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to set and read Timer Counter Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Sets timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count - 32-bit counter \r
+ */\r
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count);\r
+\r
+/** Read the timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @return count - 32-bit counter \r
+ */\r
+uint32_t p_btimer_count_get(uint8_t btimer_id);\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program the Preload */\r
+/* ---------------------------------------------------------------------- */\r
+/** Sets preload for the counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param preload_count - 32-bit pre-load value \r
+ */\r
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Functions - Functions for basic timer interrupts */\r
+/* ---------------------------------------------------------------------- */\r
+/** Reads the interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ * @return status - 1 if interrupt status set, else 0\r
+ */\r
+uint8_t p_btimer_int_status_get(uint8_t btimer_id);\r
+\r
+/** Clears interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_status_clr(uint8_t btimer_id);\r
+\r
+/** Sets interrupt enable bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears interrupt enable bit for the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_clr(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Functions - Functions for Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Writes the control register 32-bits\r
+ * @param btimer_id Basic Timer ID\r
+ * @param value - 32-bit value to program\r
+ */\r
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);\r
+\r
+/** Reads the control register \r
+ * @param btimer_id Basic Timer ID\r
+ * @return uint32_t - 32-bit value\r
+ */\r
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id);\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id);\r
+\r
+/** Sets counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);\r
+\r
+/** Clears counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);\r
+\r
+/** Sets auto restart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);\r
+\r
+/** Clears auto resetart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);\r
+\r
+/** Sets soft reset bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);\r
+\r
+/** Read Soft Reset bit \r
+ * @param btimer_id Basic Timer ID\r
+ * @return 0 if soft reset status bit cleared; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);\r
+\r
+/** Sets start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_set(uint8_t btimer_id);\r
+\r
+/** Read start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ * @return 0 if start bit not set; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);\r
+\r
+/** Clears start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_clr(uint8_t btimer_id);\r
+\r
+/** Sets reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_set(uint8_t btimer_id);\r
+\r
+/** Clears reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id);\r
+\r
+/** Sets halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_set(uint8_t btimer_id);\r
+\r
+/** Clears halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+\r
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id);\r
+\r
+/** Sets prescale value\r
+ * @param btimer_id Basic Timer ID\r
+ * @param prescaler - 16-bit pre-scale value \r
+ */\r
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);\r
+\r
+\r
+#endif // #ifndef _BTIMER_H\r
+\r
+/* end btimer_perphl.c */\r
+\r
+/** @} //Peripherals Basic_Timer\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file btimer_api.c\r
+* \brief Basic Timer APIs Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the Basic Timer API functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "btimer.h"\r
+#include "..\pcr\pcr.h"\r
+//#include "..\interrupt\ecia.h"\r
+\r
+/** Basic Timer Sleep Registers & Bit Positions */\r
+static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {\r
+ PCR_BTIMER0,\r
+ PCR_BTIMER1,\r
+ PCR_BTIMER2,\r
+ PCR_BTIMER3,\r
+ PCR_BTIMER4,\r
+ PCR_BTIMER5\r
+};\r
+\r
+#ifdef PLIB_BTIMER_CHECK_ID\r
+\r
+/** Local helper that checks if logical Timer ID is valid. \r
+ * @param btimer_id Basic Timer ID \r
+ * @return uint8_t Non-zero(VALID), 0(Invalid)\r
+ */\r
+static uint8_t btmr_valid(uint8_t btimer_id)\r
+{\r
+ if ( btimer_id < (PID_BTIMER_MAX ) ) {\r
+ return true;\r
+ }\r
+ return false;\r
+}\r
+\r
+#else\r
+\r
+\r
+/** This version of tmr_valid skips checking always returning 1. \r
+ * Compiler may optimize it out.\r
+ * @param btimer_id Basic Timer ID \r
+ * @return uint8_t 1(VALID) \r
+ */\r
+static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }\r
+\r
+#endif\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Basic Timer Intitialization function */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Initialize specified timer\r
+ * @param btimer_id Basic Timer ID\r
+ * @param tmr_cntl Logical flags for Timer Control\r
+ * @param initial_count Initial Count\r
+ * @param preload_count Preload Count\r
+ * @note Performs a soft reset of the timer before configuration \r
+ */\r
+void btimer_init(uint8_t btimer_id, \r
+ uint16_t tmr_cntl,\r
+ uint16_t prescaler,\r
+ uint32_t initial_count,\r
+ uint32_t preload_count)\r
+{ \r
+ uint32_t value; \r
+\r
+ if (btmr_valid(btimer_id)) {\r
+ \r
+ btimer_reset(btimer_id); \r
+ \r
+ // Ungate timer clocks and program prescale\r
+ value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); \r
+ p_btimer_ctrl_write(btimer_id, value);\r
+ \r
+ // Program Preload & initial counter value\r
+ p_btimer_preload_set(btimer_id, preload_count);\r
+ p_btimer_count_set(btimer_id, initial_count); \r
+ \r
+ // Program control register, interrupt enable, and clear status\r
+ if (tmr_cntl & BTIMER_COUNT_UP) { \r
+ p_btimer_ctrl_counter_dir_set(btimer_id); \r
+ }\r
+ if (tmr_cntl & BTIMER_AUTO_RESTART) {\r
+ p_btimer_ctrl_auto_restart_set(btimer_id); \r
+ } \r
+ if (tmr_cntl & BTIMER_INT_EN) { \r
+ p_btimer_int_enable_set(btimer_id); // enable first\r
+ p_btimer_int_status_clr(btimer_id); // clear status \r
+ }\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to program and read the Basic Timer Counter */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Program timer's counter register.\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count new counter value \r
+ * @note Timer hardware may implement a 16-bit or 32-bit \r
+ * hardware counter. If the timer is 16-bit only the lower\r
+ * 16-bits of the count paramter are used.\r
+ */\r
+void btimer_count_set(uint8_t btimer_id, uint32_t count)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_count_set(btimer_id, count); \r
+ }\r
+}\r
+\r
+/** Return current value of timer's count register.\r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint32_t timer count may be 32 or 16 bits depending \r
+ * upon the hardware. Timers 0-3 are 16-bit\r
+ * and Timers 4-5 are 32-bit.\r
+ */\r
+uint32_t btimer_count_get(uint8_t btimer_id)\r
+{ \r
+ uint32_t cnt;\r
+ \r
+ cnt = 0ul;\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ cnt = p_btimer_count_get(btimer_id); \r
+ }\r
+ \r
+ return cnt;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to reload counter from Preload Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Force timer to reload counter from preload \r
+ * register. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note Hardware will only reload counter if timer is running. \r
+ */\r
+void btimer_reload(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running\r
+ {\r
+ p_btimer_ctrl_reload_set(btimer_id);\r
+ }\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for stopping and starting the basic Timer */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Start timer counting.\r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_start(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) {\r
+ \r
+ p_btimer_ctrl_start_set(btimer_id);\r
+ }\r
+}\r
+\r
+/** Stop timer. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note When a stopped timer is started again it will reload \r
+ * the count register from preload value.\r
+ */\r
+void btimer_stop(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_ctrl_start_clr(btimer_id); \r
+ \r
+ }\r
+}\r
+\r
+/** Return state of timer's START bit. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 0(timer not started), 1 (timer started)\r
+ */\r
+uint8_t btimer_is_started(uint8_t btimer_id)\r
+{ \r
+ uint8_t sts;\r
+ \r
+ sts = 0;\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ if (p_btimer_ctrl_start_get(btimer_id)) \r
+ {\r
+ sts = 1;\r
+ } \r
+ }\r
+ return sts;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to perform basic timer soft reset */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Peform soft reset of specified timer. \r
+ * @param btimer_id Basic Timer ID \r
+ * @note Soft reset set all registers to POR values.\r
+ * Spins 256 times waiting on hardware to clear reset bit. \r
+ */\r
+void btimer_reset(uint8_t btimer_id)\r
+{ \r
+ uint32_t wait_cnt;\r
+ uint8_t soft_reset_sts;\r
+\r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ p_btimer_ctrl_soft_reset_set(btimer_id); \r
+\r
+ wait_cnt = 256ul;\r
+ do {\r
+ soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);\r
+ \r
+ if (0 == soft_reset_sts){ \r
+ break;\r
+ }\r
+ } \r
+ while ( wait_cnt-- ); \r
+ } \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to halt/unhalt the timer counting */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Halt timer counting with no reload on unhalt. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note A halted timer will not reload the count register when \r
+ * unhalted, it will continue counting from the current\r
+ * count value.\r
+ */\r
+void btimer_halt(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) {\r
+ \r
+ p_btimer_ctrl_halt_set(btimer_id); \r
+ }\r
+}\r
+\r
+/** Unhalt timer counting. \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_unhalt(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_ctrl_halt_clr(btimer_id);\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer interrupt */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enable specified timer's interrupt from the block. \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param ien Non-zero enable interrupt in timer block, 0 \r
+ * disable.\r
+ */\r
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)\r
+{ \r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ p_btimer_int_enable_set(btimer_id);\r
+\r
+ if (ien) {\r
+ p_btimer_int_enable_set(btimer_id);\r
+ } else {\r
+ p_btimer_int_enable_clr(btimer_id);\r
+ }\r
+ }\r
+}\r
+\r
+/** Read Timer interrupt status and clear if set \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 1 (Timer interrupt status set) else 0. \r
+ * @note If timer interrupt status is set then clear it before \r
+ * returning.\r
+ */\r
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)\r
+{ \r
+ uint8_t sts;\r
+\r
+ sts = 0;\r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ sts = p_btimer_int_status_get(btimer_id);\r
+ if (sts) {\r
+ p_btimer_int_status_clr(btimer_id); \r
+ }\r
+ }\r
+ return sts;\r
+}\r
+\r
+#if 0 //Temporary disable until interrupt module\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer GIRQ */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enables GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_set(uint8_t btimer_id)\r
+{\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);\r
+ } \r
+}\r
+\r
+/** Clears GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_clr(uint8_t btimer_id)\r
+{ \r
+ if (btmr_valid(btimer_id))\r
+ { \r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);\r
+ } \r
+ \r
+}\r
+\r
+/** Returns GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
+ */\r
+uint8_t btimer_girq_src_get(uint8_t btimer_id)\r
+{\r
+ uint8_t retVal;\r
+\r
+ retVal = 0;\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); \r
+ }\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Clears GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_src_clr(uint8_t btimer_id)\r
+{\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); \r
+ } \r
+}\r
+\r
+/** Returns GIRQ result bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
+ */\r
+uint8_t btimer_girq_result_get(uint8_t btimer_id)\r
+{\r
+ uint8_t retVal;\r
+\r
+ retVal = 0;\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); \r
+ }\r
+\r
+ return retVal; \r
+}\r
+#endif\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer Sleep */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable clock gating on idle of a timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
+ */\r
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)\r
+{\r
+ uint32_t pcr_blk_id;\r
+ \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id]; \r
+ \r
+ pcr_sleep_enable(pcr_blk_id, sleep_en); \r
+ }\r
+}\r
+\r
+/** Returns clk required status for the timer block\r
+ * @param btimer_id Basic Timer ID.\r
+ * @return Non-zero if clk required, else 0\r
+ */\r
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)\r
+{\r
+ uint32_t retVal;\r
+ uint32_t pcr_blk_id;\r
+ \r
+ retVal = 0ul; \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id];\r
+ \r
+ retVal = pcr_clock_reqd_status_get(pcr_blk_id); \r
+ }\r
+ \r
+ return retVal;\r
+}\r
+\r
+/** Enable/Disable reset on sleep for the timer block \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param reset_en 1 to enable, 0 to disable\r
+ */\r
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)\r
+{\r
+ uint32_t pcr_blk_id; \r
+ \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id];\r
+ \r
+ pcr_reset_enable(pcr_blk_id, reset_en); \r
+ }\r
+}\r
+\r
+/* end btimer_api.c */\r
+\r
+/** @} //Peripheral Basic_Timer\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file btimer_perphl.c\r
+* \brief Basic Timer Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the Basic Timer Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "btimer.h"\r
+\r
+/** Basic Timer Instance base addresses */\r
+static TIMER0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {\r
+ MEC2016_TIMER0,\r
+ MEC2016_TIMER1,\r
+ MEC2016_TIMER2,\r
+ MEC2016_TIMER3,\r
+ MEC2016_TIMER4,\r
+ MEC2016_TIMER5\r
+};\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to set and read Timer Counter Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count - 32-bit counter \r
+ */\r
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count)\r
+{\r
+ btmr_inst[btimer_id]->COUNT = count; \r
+}\r
+\r
+/** Read the timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @return count - 32-bit counter \r
+ */\r
+uint32_t p_btimer_count_get(uint8_t btimer_id)\r
+{ \r
+ return btmr_inst[btimer_id]->COUNT; \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program the Preload */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets preload for the counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param preload_count - 32-bit pre-load value \r
+ */\r
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)\r
+{\r
+ btmr_inst[btimer_id]->PRE_LOAD = preload_count; \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for basic timer interrupts */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ * @return status - 1 if interrupt status set, else 0\r
+ */\r
+uint8_t p_btimer_int_status_get(uint8_t btimer_id)\r
+{\r
+ return (uint8_t)(btmr_inst[btimer_id]->STATUS);\r
+}\r
+\r
+/** Clears interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_status_clr(uint8_t btimer_id)\r
+{\r
+ // Write 1 to clear\r
+ btmr_inst[btimer_id]->STATUS = 1;\r
+}\r
+\r
+/** Sets interrupt enable bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->INT_EN = 1;\r
+}\r
+\r
+/** Clears interrupt enable bit for the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->INT_EN = 0;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Writes the control register 32-bits\r
+ * @param btimer_id Basic Timer ID\r
+ * @param value - 32-bit value to program\r
+ */\r
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.w = value;\r
+}\r
+\r
+/** Reads the control register \r
+ * @param btimer_id Basic Timer ID\r
+ * @return uint32_t - 32-bit value\r
+ */\r
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id)\r
+{ \r
+ uint32_t retVal;\r
+\r
+ retVal = btmr_inst[btimer_id]->CONTROL.w;\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Sets enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;\r
+}\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;\r
+}\r
+\r
+/** Sets counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;\r
+}\r
+\r
+/** Clears counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;\r
+}\r
+\r
+/** Sets auto restart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;\r
+}\r
+\r
+/** Clears auto resetart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;\r
+}\r
+\r
+/** Sets soft reset bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;\r
+}\r
+\r
+/** Read Soft Reset bit \r
+ * @param btimer_id Basic Timer ID\r
+ * @return 0 if soft reset status bit cleared; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)\r
+{ \r
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);\r
+}\r
+\r
+/** Sets start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;\r
+}\r
+\r
+/** Read start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ * @return 0 if start bit not set; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)\r
+{ \r
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);\r
+}\r
+\r
+/** Clears start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;\r
+}\r
+\r
+/** Sets reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;\r
+}\r
+\r
+/** Clears reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;\r
+}\r
+\r
+/** Sets halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;\r
+}\r
+\r
+/** Clears halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;\r
+}\r
+\r
+/** Sets prescale value\r
+ * @param btimer_id Basic Timer ID\r
+ * @param prescaler - 16-bit pre-scale value \r
+ */\r
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;\r
+}\r
+\r
+\r
+/* end btimer_perphl.c */\r
+\r
+/** @} //Peripheral Basic_Timer\r
+ */\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * common.h\r
+ * This is the header file including common headers from various modules\r
+ **********************************************************************************\r
+ * $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $\r
+ * Description: added ict module\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common.h $\r
+ */\r
+\r
+/*********************************************************************************/\r
+/** @defgroup common common\r
+ * @{\r
+ */\r
+\r
+/** @file common.h\r
+* \brief header file including common headers from various modules\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _COMMON_H_\r
+#define _COMMON_H_\r
+\r
+// Include common headers from various modules\r
+// !!! The include order is important !!!\r
+#include "platform.h"\r
+#include "MCHP_device_header.h"\r
+/* Cortex-M4 processor and core peripherals */\r
+#include "core_cm4.h"\r
+\r
+#include "defs.h"\r
+#include "string.h"\r
+#include "interrupt.h"\r
+#include "system_internal.h"\r
+\r
+\r
+#endif /*_COMMON_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * common.h\r
+ * This is the header file including common headers from various modules\r
+ **********************************************************************************\r
+ * $Revision: #1 $ $DateTime: 2016/09/22 08:03:49 $ $ $\r
+ * Description: added ict module\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/common_lib.h $\r
+ */\r
+\r
+/*********************************************************************************/\r
+/** @defgroup common common\r
+ * @{\r
+ */\r
+\r
+/** @file common.h\r
+* \brief header file including common headers from various modules\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _COMMON_LIB_H_\r
+#define _COMMON_LIB_H_\r
+\r
+// Include common headers from various modules\r
+// !!! The include order is important !!!\r
+#include "platform.h"\r
+#include "ARM_REG.h"\r
+#include "MCHP_device_header.h"\r
+/* Cortex-M4 processor and core peripherals */\r
+#include "core_cm4.h" \r
+#include "defs.h"\r
+#include "string.h"\r
+#include "system_internal.h"\r
+#include <stdbool.h>\r
+#endif /*_COMMON_LIB_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * defs.h\r
+ * This is the definition header file for generic usages\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/defs.h $\r
+ */\r
+\r
+\r
+/*********************************************************************************/\r
+/** @defgroup defs defs\r
+ * @{\r
+ */\r
+\r
+/** @file defs.h\r
+* \brief definition header file for generic usages\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _DEFS_H_\r
+#define _DEFS_H_\r
+\r
+/* bit operation MACRO, xvar could be byte, word or dword */\r
+#define mSET_BIT(x, xvar) ( xvar |= x )\r
+#define mCLR_BIT(x, xvar) ( xvar &= ~x )\r
+#define mGET_BIT(x, xvar) ( xvar & x )\r
+#define mCLR_SRC_BIT(x, xvar) ( xvar = x )\r
+#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}\r
+\r
+#endif /*_DEFS_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Renamed ecia_init to interrupt_init\r
+******************************************************************************/\r
+/** @file interrupt.h\r
+* \brief Interrupt Header File\r
+* \author jvasanth\r
+* \r
+* This file implements the Interrupt Module Header file \r
+******************************************************************************/\r
+\r
+/** @defgroup Interrupt\r
+ * @{\r
+ */\r
+\r
+#ifndef _INTERRUPT_H\r
+#define _INTERRUPT_H\r
+\r
+// GIRQ IDs for EC Interrupt Aggregator\r
+enum MEC_GIRQ_IDS\r
+{\r
+ MEC_GIRQ08_ID = 0,\r
+ MEC_GIRQ09_ID, \r
+ MEC_GIRQ10_ID, \r
+ MEC_GIRQ11_ID, \r
+ MEC_GIRQ12_ID, \r
+ MEC_GIRQ13_ID, \r
+ MEC_GIRQ14_ID, \r
+ MEC_GIRQ15_ID, \r
+ MEC_GIRQ16_ID, \r
+ MEC_GIRQ17_ID, \r
+ MEC_GIRQ18_ID, \r
+ MEC_GIRQ19_ID, \r
+ MEC_GIRQ20_ID, \r
+ MEC_GIRQ21_ID, \r
+ MEC_GIRQ22_ID, \r
+ MEC_GIRQ23_ID, \r
+ MEC_GIRQ_ID_MAX\r
+};\r
+\r
+//Bitmask of GIRQ in ECIA Block Registers\r
+#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))\r
+#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) \r
+#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) \r
+#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) \r
+#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) \r
+#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) \r
+#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) \r
+#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) \r
+#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) \r
+#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) \r
+#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) \r
+#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) \r
+#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) \r
+#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) \r
+#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) \r
+#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) \r
+\r
+#define INTERRUPT_MODE_ALL_AGGREGATED (0u)\r
+#define INTERRUPT_MODE_DIRECT (1u)\r
+\r
+// Bit map of GIRQs whose sources can be directly connected to the NVIC\r
+// GIRQs 13 - 19, 21, 23, 24-26\r
+#define ECIA_GIRQ_DIRECT_BITMAP (0x07AFE000ul)\r
+\r
+/*\r
+ * n = b[7:0] = zero-based direct mapped NVIC ID\r
+ * m = b[15:8] = zero-based aggregated NVIC ID\r
+ * a = b[23:16] = block Aggregator register block ID\r
+ * b = b[31:24] = block bit position in Aggregator registers\r
+*/\r
+#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \\r
+ (((uint32_t)(m)&0xFFul)<<8u) + \\r
+ ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \\r
+ (((uint32_t)(b)&0x1Ful)<<24))\r
+\r
+#define ECIA_NVIC_ID_BITPOS (0u)\r
+#define ECIA_IA_NVIC_ID_BITPOS (8u)\r
+#define ECIA_GIRQ_ID_BITPOS (16u)\r
+#define ECIA_GIRQ_BIT_BITPOS (24u)\r
+\r
+//\r
+// GIRQ08\r
+//\r
+#define GPIO_0140_IROUTE IROUTE(0,8,0,0)\r
+#define GPIO_0141_IROUTE IROUTE(1,8,0,0)\r
+#define GPIO_0142_IROUTE IROUTE(2,8,0,0)\r
+#define GPIO_0143_IROUTE IROUTE(3,8,0,0)\r
+#define GPIO_0144_IROUTE IROUTE(4,8,0,0)\r
+#define GPIO_0145_IROUTE IROUTE(5,8,0,0)\r
+#define GPIO_0147_IROUTE IROUTE(7,8,0,0)\r
+//\r
+#define GPIO_0150_IROUTE IROUTE(8,8,0,0)\r
+#define GPIO_0151_IROUTE IROUTE(9,8,0,0)\r
+#define GPIO_0152_IROUTE IROUTE(10,8,0,0)\r
+#define GPIO_0153_IROUTE IROUTE(11,8,0,0)\r
+#define GPIO_0154_IROUTE IROUTE(12,8,0,0)\r
+#define GPIO_0155_IROUTE IROUTE(13,8,0,0)\r
+#define GPIO_0156_IROUTE IROUTE(14,8,0,0)\r
+#define GPIO_0157_IROUTE IROUTE(15,8,0,0)\r
+//\r
+#define GPIO_0160_IROUTE IROUTE(16,8,0,0)\r
+#define GPIO_0161_IROUTE IROUTE(17,8,0,0)\r
+#define GPIO_0162_IROUTE IROUTE(18,8,0,0)\r
+#define GPIO_0163_IROUTE IROUTE(19,8,0,0)\r
+#define GPIO_0164_IROUTE IROUTE(20,8,0,0)\r
+#define GPIO_0165_IROUTE IROUTE(21,8,0,0)\r
+#define GPIO_0166_IROUTE IROUTE(22,8,0,0)\r
+#define GPIO_0167_IROUTE IROUTE(23,8,0,0)\r
+\r
+#define GPIO_0170_IROUTE IROUTE(24,8,0,0)\r
+#define GPIO_0171_IROUTE IROUTE(25,8,0,0)\r
+#define GPIO_0172_IROUTE IROUTE(26,8,0,0)\r
+#define GPIO_0173_IROUTE IROUTE(27,8,0,0)\r
+#define GPIO_0174_IROUTE IROUTE(28,8,0,0)\r
+#define GPIO_0175_IROUTE IROUTE(29,8,0,0)\r
+#define GPIO_0176_IROUTE IROUTE(30,8,0,0)\r
+\r
+//\r
+// GIRQ09\r
+//\r
+#define GPIO_0100_IROUTE IROUTE(0,9,1,1)\r
+#define GPIO_0101_IROUTE IROUTE(1,9,1,1)\r
+#define GPIO_0102_IROUTE IROUTE(2,9,1,1)\r
+#define GPIO_0103_IROUTE IROUTE(3,9,1,1)\r
+#define GPIO_0104_IROUTE IROUTE(4,9,1,1)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,1,1)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,1,1)\r
+#define GPIO_0107_IROUTE IROUTE(7,9,1,1)\r
+//\r
+#define GPIO_0110_IROUTE IROUTE(8,9,1,1)\r
+#define GPIO_0111_IROUTE IROUTE(9,9,1,1)\r
+#define GPIO_0112_IROUTE IROUTE(10,9,1,1)\r
+#define GPIO_0113_IROUTE IROUTE(11,9,1,1)\r
+#define GPIO_0114_IROUTE IROUTE(12,9,1,1)\r
+#define GPIO_0115_IROUTE IROUTE(13,9,1,1)\r
+#define GPIO_0116_IROUTE IROUTE(14,9,1,1)\r
+#define GPIO_0117_IROUTE IROUTE(15,9,1,1)\r
+//\r
+#define GPIO_0120_IROUTE IROUTE(16,9,1,1)\r
+#define GPIO_0121_IROUTE IROUTE(17,9,1,1)\r
+#define GPIO_0122_IROUTE IROUTE(18,9,1,1)\r
+#define GPIO_0124_IROUTE IROUTE(20,9,1,1)\r
+#define GPIO_0125_IROUTE IROUTE(21,9,1,1)\r
+#define GPIO_0126_IROUTE IROUTE(22,9,1,1)\r
+#define GPIO_0127_IROUTE IROUTE(23,9,1,1)\r
+//\r
+#define GPIO_0130_IROUTE IROUTE(24,9,1,1)\r
+#define GPIO_0131_IROUTE IROUTE(25,9,1,1)\r
+#define GPIO_0132_IROUTE IROUTE(26,9,1,1)\r
+#define GPIO_0133_IROUTE IROUTE(27,9,1,1)\r
+#define GPIO_0134_IROUTE IROUTE(28,9,1,1)\r
+#define GPIO_0135_IROUTE IROUTE(29,9,1,1)\r
+#define GPIO_0136_IROUTE IROUTE(30,9,1,1)\r
+\r
+//\r
+// GIRQ10\r
+//\r
+#define GPIO_0040_IROUTE IROUTE(0,10,2,2)\r
+#define GPIO_0041_IROUTE IROUTE(1,10,2,2)\r
+#define GPIO_0042_IROUTE IROUTE(2,10,2,2)\r
+#define GPIO_0043_IROUTE IROUTE(3,10,2,2)\r
+#define GPIO_0044_IROUTE IROUTE(4,10,2,2)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,2,2)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,2,2)\r
+#define GPIO_0047_IROUTE IROUTE(7,10,2,2)\r
+//\r
+#define GPIO_0050_IROUTE IROUTE(8,10,2,2)\r
+#define GPIO_0051_IROUTE IROUTE(9,10,2,2)\r
+#define GPIO_0052_IROUTE IROUTE(10,10,2,2)\r
+#define GPIO_0053_IROUTE IROUTE(11,10,2,2)\r
+#define GPIO_0054_IROUTE IROUTE(12,10,2,2)\r
+#define GPIO_0055_IROUTE IROUTE(13,10,2,2)\r
+#define GPIO_0056_IROUTE IROUTE(14,10,2,2)\r
+#define GPIO_0057_IROUTE IROUTE(15,10,2,2)\r
+//\r
+#define GPIO_0060_IROUTE IROUTE(16,10,2,2)\r
+#define GPIO_0061_IROUTE IROUTE(17,10,2,2)\r
+#define GPIO_0062_IROUTE IROUTE(18,10,2,2)\r
+#define GPIO_0063_IROUTE IROUTE(19,10,2,2)\r
+#define GPIO_0064_IROUTE IROUTE(20,10,2,2)\r
+#define GPIO_0065_IROUTE IROUTE(21,10,2,2)\r
+#define GPIO_0066_IROUTE IROUTE(22,10,2,2)\r
+#define GPIO_0067_IROUTE IROUTE(23,10,2,2)\r
+//\r
+#define GPIO_0070_IROUTE IROUTE(24,10,2,2)\r
+#define GPIO_0071_IROUTE IROUTE(25,10,2,2)\r
+#define GPIO_0072_IROUTE IROUTE(26,10,2,2)\r
+#define GPIO_0073_IROUTE IROUTE(27,10,2,2)\r
+#define GPIO_0074_IROUTE IROUTE(28,10,2,2)\r
+#define GPIO_0075_IROUTE IROUTE(29,10,2,2)\r
+#define GPIO_0076_IROUTE IROUTE(30,10,2,2)\r
+\r
+//\r
+// GIRQ11\r
+//\r
+#define GPIO_0000_IROUTE IROUTE(0,11,3,3)\r
+#define GPIO_0001_IROUTE IROUTE(1,11,3,3)\r
+#define GPIO_0002_IROUTE IROUTE(2,11,3,3)\r
+#define GPIO_0003_IROUTE IROUTE(3,11,3,3)\r
+#define GPIO_0004_IROUTE IROUTE(4,11,3,3)\r
+#define GPIO_0005_IROUTE IROUTE(5,11,3,3)\r
+#define GPIO_0006_IROUTE IROUTE(6,11,3,3)\r
+#define GPIO_0007_IROUTE IROUTE(7,11,3,3)\r
+//\r
+#define GPIO_0010_IROUTE IROUTE(8,11,3,3)\r
+#define GPIO_0011_IROUTE IROUTE(9,11,3,3)\r
+#define GPIO_0012_IROUTE IROUTE(10,11,3,3)\r
+#define GPIO_0013_IROUTE IROUTE(11,11,3,3)\r
+#define GPIO_0014_IROUTE IROUTE(12,11,3,3)\r
+#define GPIO_0015_IROUTE IROUTE(13,11,3,3)\r
+#define GPIO_0016_IROUTE IROUTE(14,11,3,3)\r
+#define GPIO_0017_IROUTE IROUTE(15,11,3,3)\r
+//\r
+#define GPIO_0020_IROUTE IROUTE(16,11,3,3)\r
+#define GPIO_0021_IROUTE IROUTE(17,11,3,3)\r
+#define GPIO_0022_IROUTE IROUTE(18,11,3,3)\r
+#define GPIO_0023_IROUTE IROUTE(19,11,3,3)\r
+#define GPIO_0024_IROUTE IROUTE(20,11,3,3)\r
+#define GPIO_0025_IROUTE IROUTE(21,11,3,3)\r
+#define GPIO_0026_IROUTE IROUTE(22,11,3,3)\r
+#define GPIO_0027_IROUTE IROUTE(23,11,3,3)\r
+//\r
+#define GPIO_0030_IROUTE IROUTE(24,11,3,3)\r
+#define GPIO_0031_IROUTE IROUTE(25,11,3,3)\r
+#define GPIO_0032_IROUTE IROUTE(26,11,3,3)\r
+#define GPIO_0033_IROUTE IROUTE(27,11,3,3)\r
+#define GPIO_0034_IROUTE IROUTE(28,11,3,3)\r
+#define GPIO_0035_IROUTE IROUTE(29,11,3,3)\r
+#define GPIO_0036_IROUTE IROUTE(30,11,3,3)\r
+\r
+\r
+// GIRQ12\r
+//\r
+#define GPIO_0200_IROUTE IROUTE(0,12,4,4)\r
+#define GPIO_0201_IROUTE IROUTE(1,12,4,4)\r
+#define GPIO_0202_IROUTE IROUTE(2,12,4,4)\r
+#define GPIO_0203_IROUTE IROUTE(3,12,4,4)\r
+#define GPIO_0204_IROUTE IROUTE(4,12,4,4)\r
+#define GPIO_0205_IROUTE IROUTE(5,12,4,4)\r
+#define GPIO_0206_IROUTE IROUTE(6,12,4,4)\r
+#define GPIO_0207_IROUTE IROUTE(7,12,4,4)\r
+//\r
+#define GPIO_0210_IROUTE IROUTE(8,12,4,4)\r
+#define GPIO_0211_IROUTE IROUTE(9,12,4,4)\r
+#define GPIO_0212_IROUTE IROUTE(10,12,4,4)\r
+#define GPIO_0213_IROUTE IROUTE(11,12,4,4)\r
+#define GPIO_0214_IROUTE IROUTE(12,12,4,4)\r
+#define GPIO_0215_IROUTE IROUTE(13,12,4,4)\r
+#define GPIO_0216_IROUTE IROUTE(14,12,4,4)\r
+#define GPIO_0217_IROUTE IROUTE(15,12,4,4)\r
+//\r
+#define GPIO_0220_IROUTE IROUTE(16,12,4,4)\r
+#define GPIO_0221_IROUTE IROUTE(17,12,4,4)\r
+#define GPIO_0222_IROUTE IROUTE(18,12,4,4)\r
+#define GPIO_0223_IROUTE IROUTE(19,12,4,4)\r
+#define GPIO_0224_IROUTE IROUTE(20,12,4,4)\r
+#define GPIO_0225_IROUTE IROUTE(21,12,4,4)\r
+#define GPIO_0226_IROUTE IROUTE(22,12,4,4)\r
+#define GPIO_0227_IROUTE IROUTE(23,12,4,4)\r
+//\r
+#define GPIO_0230_IROUTE IROUTE(24,12,4,4)\r
+#define GPIO_0231_IROUTE IROUTE(25,12,4,4)\r
+#define GPIO_0232_IROUTE IROUTE(26,12,4,4)\r
+#define GPIO_0233_IROUTE IROUTE(27,12,4,4)\r
+#define GPIO_0234_IROUTE IROUTE(28,12,4,4)\r
+#define GPIO_0235_IROUTE IROUTE(29,12,4,4)\r
+#define GPIO_0236_IROUTE IROUTE(30,12,4,4)\r
+\r
+\r
+\r
+//\r
+// GIRQ13\r
+//\r
+#define SMB0_IROUTE IROUTE(0,13,5,20)\r
+#define SMB1_IROUTE IROUTE(1,13,5,21)\r
+#define SMB2_IROUTE IROUTE(2,13,5,22)\r
+#define SMB3_IROUTE IROUTE(3,13,5,23)\r
+\r
+//\r
+// GIRQ14\r
+//\r
+#define DMA0_IROUTE IROUTE(0,14,6,24)\r
+#define DMA1_IROUTE IROUTE(1,14,6,25)\r
+#define DMA2_IROUTE IROUTE(2,14,6,26)\r
+#define DMA3_IROUTE IROUTE(3,14,6,27)\r
+#define DMA4_IROUTE IROUTE(4,14,6,28)\r
+#define DMA5_IROUTE IROUTE(5,14,6,29)\r
+#define DMA6_IROUTE IROUTE(6,14,6,30)\r
+#define DMA7_IROUTE IROUTE(7,14,6,31)\r
+#define DMA8_IROUTE IROUTE(8,14,6,33)\r
+#define DMA9_IROUTE IROUTE(9,14,6,33)\r
+#define DMA10_IROUTE IROUTE(10,14,6,34)\r
+#define DMA11_IROUTE IROUTE(11,14,6,35)\r
+#define DMA12_IROUTE IROUTE(12,14,6,36)\r
+#define DMA13_IROUTE IROUTE(13,14,6,37)\r
+\r
+\r
+//\r
+// GIRQ15\r
+//\r
+#define UART0_IROUTE IROUTE(0,15,7,40)\r
+#define UART1_IROUTE IROUTE(1,15,7,41)\r
+#define EMI0_IROUTE IROUTE(2,15,7,42)\r
+#define EMI1_IROUTE IROUTE(3,15,7,43)\r
+#define EMI2_IROUTE IROUTE(4,15,7,44)\r
+#define ACPI_EC0_IBF_IROUTE IROUTE(5,15,7,45)\r
+#define ACPI_EC0_OBF_IROUTE IROUTE(6,15,7,46)\r
+#define ACPI_EC1_IBF_IROUTE IROUTE(7,15,7,47)\r
+#define ACPI_EC1_OBF_IROUTE IROUTE(8,15,7,48)\r
+#define ACPI_EC2_IBF_IROUTE IROUTE(9,15,7,49)\r
+#define ACPI_EC2_OBF_IROUTE IROUTE(10,15,7,50)\r
+#define ACPI_EC3_IBF_IROUTE IROUTE(11,15,7,51)\r
+#define ACPI_EC3_OBF_IROUTE IROUTE(12,15,7,52)\r
+#define ACPI_EC4_IBF_IROUTE IROUTE(13,15,7,53)\r
+#define ACPI_EC4_OBF_IROUTE IROUTE(14,15,7,54)\r
+#define ACPI_PM1_CTL_IROUTE IROUTE(15,15,7,55)\r
+#define ACPI_PM1_EN_IROUTE IROUTE(16,15,7,56)\r
+#define ACPI_PM1_STS_IROUTE IROUTE(17,15,7,57)\r
+#define EM8042_OBF_IROUTE IROUTE(18,15,7,58)\r
+#define EM8042_IBF_IROUTE IROUTE(19,15,7,59)\r
+#define MBOX_IROUTE IROUTE(20,15,7,60)\r
+#define PORT80_DBG0_BDPINT_IROUTE IROUTE(22,15,7,62)\r
+#define PORT80_DBG1_BDPINT_IROUTE IROUTE(23,15,7,63)\r
+#define TEST_IROUTE IROUTE(24,15,7,64)\r
+\r
+//\r
+// GIRQ16\r
+//\r
+#define PKE_ERROR_IROUTE IROUTE(0,16,8,65)\r
+#define PKE_END_IROUTE IROUTE(1,16,8,66)\r
+#define RNG_IROUTE IROUTE(2,16,8,67)\r
+#define AES_IROUTE IROUTE(3,16,8,68)\r
+#define HASH_IROUTE IROUTE(4,16,8,69)\r
+\r
+//\r
+// GIRQ17\r
+//\r
+#define PECI_IROUTE IROUTE(0,17,9,70)\r
+#define TACH0_IROUTE IROUTE(1,17,9,71)\r
+#define TACH1_IROUTE IROUTE(2,17,9,72)\r
+#define TACH2_IROUTE IROUTE(3,17,9,73)\r
+#define RPM2PWM0_FAIL_IROUTE IROUTE(4,17,9,74)\r
+#define RPM2PWM0_STALL_IROUTE IROUTE(5,17,9,75)\r
+#define RPM2PWM1_FAIL_IROUTE IROUTE(6,17,9,76)\r
+#define RPM2PWM1_STALL_IROUTE IROUTE(7,17,9,77)\r
+#define ADC_SNGL_IROUTE IROUTE(8,17,9,78)\r
+#define ADC_RPT_IROUTE IROUTE(9,17,9,79)\r
+#define RC_ID0_IROUTE IROUTE(10,17,9,80)\r
+#define RC_ID1_IROUTE IROUTE(11,17,9,81)\r
+#define RC_ID2_IROUTE IROUTE(12,17,9,82)\r
+#define LED0_IROUTE IROUTE(13,17,9,83)\r
+#define LED1_IROUTE IROUTE(14,17,9,84)\r
+#define LED2_IROUTE IROUTE(15,17,9,85)\r
+#define LED3_IROUTE IROUTE(16,17,9,86)\r
+#define PHOT_IROUTE IROUTE(17,17,9,87)\r
+#define POWER_GUARD0_IROUTE IROUTE(18,17,9,88)\r
+#define POWER_GUARD1_IROUTE IROUTE(19,17,9,89)\r
+#define RTOS_SWI0_IROUTE IROUTE(25,17,9,9)\r
+#define RTOS_SWI1_IROUTE IROUTE(26,17,9,9)\r
+#define RTOS_SWI2_IROUTE IROUTE(27,17,9,9)\r
+#define RTOS_SWI3_IROUTE IROUTE(28,17,9,9)\r
+\r
+//\r
+// GIRQ18 \r
+//\r
+#define LPC_INT_ERR_IROUTE IROUTE(0,18,10,90)\r
+#define QMSPI_INT_IROUTE IROUTE(1,18,10,91)\r
+#define GP_SPI0_TXBE_STS_IROUTE IROUTE(2,18,10,92)\r
+#define GP_SPI0_RXBF_STS_IROUTE IROUTE(3,18,10,93)\r
+#define GP_SPI1_TXBE_STS_IROUTE IROUTE(4,18,10,94)\r
+#define GP_SPI1_RXBF_STS_IROUTE IROUTE(5,18,10,95)\r
+#define BCLINK0_BCM_ERR_IROUTE IROUTE(6,18,10,96)\r
+#define BCLINK0_BUSY_CLR_IROUTE IROUTE(7,18,10,97)\r
+#define BCLINK1_BCM_ERR_IROUTE IROUTE(8,18,10,98)\r
+#define BCLINK1_BUSY_CLR_IROUTE IROUTE(9,18,10,99)\r
+#define PS2_IFACE0_ACT_IROUTE IROUTE(10,18,10,100)\r
+#define PS2_IFACE1_ACT_IROUTE IROUTE(11,18,10,101)\r
+#define PS2_IFACE2_ACT_IROUTE IROUTE(12,18,10,102)\r
+#define EEPROM_IROUTE IROUTE(13,18,10,155)\r
+\r
+\r
+//\r
+// GIRQ19\r
+//\r
+#define ESPI_SLAVE_INTR_PC_IROUTE IROUTE(0,19,11,103)\r
+#define ESPI_SLAVE_INTR_BM1_IROUTE IROUTE(1,19,11,104)\r
+#define ESPI_SLAVE_INTR_BM2_IROUTE IROUTE(2,19,11,105)\r
+#define ESPI_SLAVE_INTR_LTR_IROUTE IROUTE(3,19,11,106)\r
+#define ESPI_SLAVE_INTR_OOB_UP_IROUTE IROUTE(4,19,11,107)\r
+#define ESPI_SLAVE_INTR_OOB_DN_IROUTE IROUTE(5,19,11,108)\r
+#define ESPI_SLAVE_INTR_FLASH_IROUTE IROUTE(6,19,11,109)\r
+#define ESPI_SLAVE_ESPI_RESET_IROUTE IROUTE(7,19,11,110)\r
+#define ESPI_SLAVE_VW_ENABLE_IROUTE IROUTE(8,19,11,156)\r
+\r
+//\r
+// GIRQ20\r
+//\r
+\r
+\r
+//\r
+// GIRQ21\r
+//\r
+#define RTOS_TIMER_IROUTE IROUTE(0,21,13,111)\r
+#define HTIMER0_IROUTE IROUTE(1,21,13,112)\r
+#define HTIMER1_IROUTE IROUTE(2,21,13,113)\r
+#define WEEK_ALARM_INT_IROUTE IROUTE(3,21,13,114)\r
+#define SUB_WEEK_ALARM_IN_IROUTE IROUTE(4,21,13,115)\r
+#define WEEK_ALARM_ONE_SECOND_IROUTE IROUTE(5,21,13,116)\r
+#define WEEK_ALARM_SUB_SECOND_IROUTE IROUTE(6,21,13,117)\r
+#define WEEK_ALARM_SYSPWR_PRES_IROUTE IROUTE(7,21,13,118)\r
+#define RTC_IROUTE IROUTE(8,21,13,119)\r
+#define RTC_ALARM_IROUTE IROUTE(9,21,13,120)\r
+#define VBAT_VCI_OVRD_IN_IROUTE IROUTE(10,21,13,121)\r
+#define VBAT_VCI_IN0_IROUTE IROUTE(11,21,13,122)\r
+#define VBAT_VCI_IN1_IROUTE IROUTE(12,21,13,123)\r
+#define VBAT_VCI_IN2_IROUTE IROUTE(13,21,13,124)\r
+#define VBAT_VCI_IN3_IROUTE IROUTE(14,21,13,125)\r
+#define VBAT_VCI_IN4_IROUTE IROUTE(15,21,13,126)\r
+#define VBAT_VCI_IN5_IROUTE IROUTE(16,21,13,127)\r
+#define VBAT_VCI_IN6_IROUTE IROUTE(17,21,13,128)\r
+#define PS2_0A_WK_IROUTE IROUTE(18,21,13,129)\r
+#define PS2_0B_WK_IROUTE IROUTE(19,21,13,130)\r
+#define PS2_1A_WK_IROUTE IROUTE(20,21,13,131)\r
+#define PS2_1B_WK_IROUTE IROUTE(21,21,13,132)\r
+#define PS2_2_WK_IROUTE IROUTE(22,21,13,133)\r
+#define ENVMON_IROUTE IROUTE(24,21,13,134)\r
+#define KSC_INT_IROUTE IROUTE(25,21,13,135)\r
+\r
+\r
+//\r
+// GIRQ22 (No Aggregated & No direct source, WAKE ONLY EVENTS)\r
+//\r
+#define LPC_WAKE_ONLY_IROUTE IROUTE(0,22,22,22)\r
+#define SMB0_WAKE_ONLY_IROUTE IROUTE(1,22,22,22)\r
+#define SMB1_WAKE_ONLY_IROUTE IROUTE(2,22,22,22)\r
+#define SMB2_WAKE_ONLY_IROUTE IROUTE(3,22,22,22)\r
+#define SMB3_WAKE_ONLY_IROUTE IROUTE(4,22,22,22)\r
+#define ESPI_WAKE_ONLY_IROUTE IROUTE(9,22,22,22)\r
+\r
+//\r
+// GIRQ23\r
+//\r
+#define BTMR0_IROUTE IROUTE(0,23,14,136)\r
+#define BTMR1_IROUTE IROUTE(1,23,14,137)\r
+#define BTMR2_IROUTE IROUTE(2,23,14,138)\r
+#define BTMR3_IROUTE IROUTE(3,23,14,139)\r
+#define BTMR4_IROUTE IROUTE(4,23,14,140)\r
+#define BTMR5_IROUTE IROUTE(5,23,14,141)\r
+#define CTIMER0_IROUTE IROUTE(6,23,14,142)\r
+#define CTIMER1_IROUTE IROUTE(7,23,14,143)\r
+#define CTIMER2_IROUTE IROUTE(8,23,14,144)\r
+#define CTIMER3_IROUTE IROUTE(9,23,14,145)\r
+#define CAP_TIMER_IROUTE IROUTE(10,23,14,146)\r
+#define CC_TIMER0_IROUTE IROUTE(11,23,14,147)\r
+#define CC_TIMER1_IROUTE IROUTE(12,23,14,148)\r
+#define CC_TIMER2_IROUTE IROUTE(13,23,14,149)\r
+#define CC_TIMER3_IROUTE IROUTE(14,23,14,150)\r
+#define CC_TIMER4_IROUTE IROUTE(15,23,14,151)\r
+#define CC_TIMER5_IROUTE IROUTE(16,23,14,152)\r
+#define CC_TIMER_CMP0_IROUTE IROUTE(17,23,14,153)\r
+#define CC_TIMER_CMP1_IROUTE IROUTE(18,23,14,154)\r
+\r
+//\r
+// GIRQ23\r
+//\r
+#define ESPI_SLAVE_VW00_SRC0_IROUTE IROUTE(0,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC1_IROUTE IROUTE(1,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC2_IROUTE IROUTE(2,24,15,15)\r
+#define ESPI_SLAVE_VW00_SRC3_IROUTE IROUTE(3,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC0_IROUTE IROUTE(4,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC1_IROUTE IROUTE(5,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC2_IROUTE IROUTE(6,24,15,15)\r
+#define ESPI_SLAVE_VW01_SRC3_IROUTE IROUTE(7,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC0_IROUTE IROUTE(8,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC1_IROUTE IROUTE(9,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC2_IROUTE IROUTE(10,24,15,15)\r
+#define ESPI_SLAVE_VW02_SRC3_IROUTE IROUTE(11,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC0_IROUTE IROUTE(12,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC1_IROUTE IROUTE(13,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC2_IROUTE IROUTE(14,24,15,15)\r
+#define ESPI_SLAVE_VW03_SRC3_IROUTE IROUTE(15,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC0_IROUTE IROUTE(16,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC1_IROUTE IROUTE(17,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC2_IROUTE IROUTE(18,24,15,15)\r
+#define ESPI_SLAVE_VW04_SRC3_IROUTE IROUTE(19,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC0_IROUTE IROUTE(20,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC1_IROUTE IROUTE(21,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC2_IROUTE IROUTE(22,24,15,15)\r
+#define ESPI_SLAVE_VW05_SRC3_IROUTE IROUTE(23,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC0_IROUTE IROUTE(24,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC1_IROUTE IROUTE(25,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC2_IROUTE IROUTE(26,24,15,15)\r
+#define ESPI_SLAVE_VW06_SRC3_IROUTE IROUTE(27,24,15,15)\r
+\r
+\r
+//\r
+// GIRQ25\r
+//\r
+#define ESPI_SLAVE_VW07_SRC0_IROUTE IROUTE(0,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC1_IROUTE IROUTE(1,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC2_IROUTE IROUTE(2,25,15,15)\r
+#define ESPI_SLAVE_VW07_SRC3_IROUTE IROUTE(3,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC0_IROUTE IROUTE(4,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC1_IROUTE IROUTE(5,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC2_IROUTE IROUTE(6,25,15,15)\r
+#define ESPI_SLAVE_VW08_SRC3_IROUTE IROUTE(7,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC0_IROUTE IROUTE(8,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC1_IROUTE IROUTE(9,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC2_IROUTE IROUTE(10,25,15,15)\r
+#define ESPI_SLAVE_VW09_SRC3_IROUTE IROUTE(11,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC0_IROUTE IROUTE(12,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC1_IROUTE IROUTE(13,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC2_IROUTE IROUTE(14,25,15,15)\r
+#define ESPI_SLAVE_VW10_SRC3_IROUTE IROUTE(15,25,15,15)\r
+\r
+//\r
+// GIRQ26\r
+//\r
+#define GPIO_0240_IROUTE IROUTE(0,26,17,17)\r
+#define GPIO_0241_IROUTE IROUTE(1,26,17,17)\r
+#define GPIO_0242_IROUTE IROUTE(2,26,17,17)\r
+#define GPIO_0243_IROUTE IROUTE(3,26,17,17)\r
+#define GPIO_0244_IROUTE IROUTE(4,26,17,17)\r
+#define GPIO_0245_IROUTE IROUTE(5,26,17,17)\r
+#define GPIO_0246_IROUTE IROUTE(6,26,17,17)\r
+#define GPIO_0247_IROUTE IROUTE(7,26,17,17)\r
+//\r
+#define GPIO_0250_IROUTE IROUTE(8,26,17,17)\r
+#define GPIO_0251_IROUTE IROUTE(9,26,17,17)\r
+#define GPIO_0252_IROUTE IROUTE(10,26,17,17)\r
+#define GPIO_0253_IROUTE IROUTE(11,26,17,17)\r
+#define GPIO_0254_IROUTE IROUTE(12,26,17,17)\r
+#define GPIO_0255_IROUTE IROUTE(13,26,17,17)\r
+#define GPIO_0256_IROUTE IROUTE(14,26,17,17)\r
+#define GPIO_0257_IROUTE IROUTE(15,26,17,17)\r
+//\r
+#define GPIO_0260_IROUTE IROUTE(16,26,17,17)\r
+#define GPIO_0261_IROUTE IROUTE(17,26,17,17)\r
+#define GPIO_0262_IROUTE IROUTE(18,26,17,17)\r
+#define GPIO_0263_IROUTE IROUTE(19,26,17,17)\r
+#define GPIO_0264_IROUTE IROUTE(20,26,17,17)\r
+#define GPIO_0265_IROUTE IROUTE(21,26,17,17)\r
+#define GPIO_0266_IROUTE IROUTE(22,26,17,17)\r
+#define GPIO_0267_IROUTE IROUTE(23,26,17,17)\r
+//\r
+#define GPIO_0270_IROUTE IROUTE(24,26,17,17)\r
+#define GPIO_0271_IROUTE IROUTE(25,26,17,17)\r
+#define GPIO_0272_IROUTE IROUTE(26,26,17,17)\r
+#define GPIO_0273_IROUTE IROUTE(27,26,17,17)\r
+#define GPIO_0274_IROUTE IROUTE(28,26,17,17)\r
+#define GPIO_0275_IROUTE IROUTE(29,26,17,17)\r
+#define GPIO_0276_IROUTE IROUTE(30,26,17,17)\r
+\r
+\r
+// GIRQ08 Bit Positions \r
+#define GIRQ08_GPIO_0140_BITPOS (0)\r
+#define GIRQ08_GPIO_0141_BITPOS (1)\r
+#define GIRQ08_GPIO_0142_BITPOS (2)\r
+#define GIRQ08_GPIO_0143_BITPOS (3)\r
+#define GIRQ08_GPIO_0144_BITPOS (4)\r
+#define GIRQ08_GPIO_0145_BITPOS (5)\r
+#define GIRQ08_GPIO_0146_BITPOS (6)\r
+#define GIRQ08_GPIO_0147_BITPOS (7)\r
+//\r
+#define GIRQ08_GPIO_0150_BITPOS (8)\r
+#define GIRQ08_GPIO_0151_BITPOS (9)\r
+#define GIRQ08_GPIO_0152_BITPOS (10)\r
+#define GIRQ08_GPIO_0153_BITPOS (11)\r
+#define GIRQ08_GPIO_0154_BITPOS (12)\r
+#define GIRQ08_GPIO_0155_BITPOS (13)\r
+#define GIRQ08_GPIO_0156_BITPOS (14) \r
+#define GIRQ08_GPIO_0157_BITPOS (15)\r
+//\r
+#define GIRQ08_GPIO_0160_BITPOS (16)\r
+#define GIRQ08_GPIO_0161_BITPOS (17)\r
+#define GIRQ08_GPIO_0162_BITPOS (18)\r
+#define GIRQ08_GPIO_0163_BITPOS (19)\r
+#define GIRQ08_GPIO_0164_BITPOS (20)\r
+#define GIRQ08_GPIO_0165_BITPOS (21)\r
+#define GIRQ08_GPIO_0166_BITPOS (22) \r
+#define GIRQ08_GPIO_0167_BITPOS (23)\r
+\r
+#define GIRQ08_GPIO_0170_BITPOS (24)\r
+#define GIRQ08_GPIO_0171_BITPOS (25)\r
+#define GIRQ08_GPIO_0172_BITPOS (26)\r
+#define GIRQ08_GPIO_0173_BITPOS (27)\r
+#define GIRQ08_GPIO_0174_BITPOS (28)\r
+#define GIRQ08_GPIO_0175_BITPOS (29)\r
+#define GIRQ08_GPIO_0176_BITPOS (30) \r
+\r
+//\r
+#define GIRQ08_MASK (0x7FFFFFFFul)\r
+#define GIRQ08_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ09 Bit Positions \r
+#define GIRQ09_GPIO_0100_BITPOS (0)\r
+#define GIRQ09_GPIO_0101_BITPOS (1)\r
+#define GIRQ09_GPIO_0102_BITPOS (2)\r
+#define GIRQ09_GPIO_0103_BITPOS (3)\r
+#define GIRQ09_GPIO_0104_BITPOS (4)\r
+#define GIRQ09_GPIO_0105_BITPOS (5)\r
+#define GIRQ09_GPIO_0106_BITPOS (6) \r
+#define GIRQ09_GPIO_0107_BITPOS (7)\r
+//\r
+#define GIRQ09_GPIO_0110_BITPOS (8)\r
+#define GIRQ09_GPIO_0111_BITPOS (9)\r
+#define GIRQ09_GPIO_0112_BITPOS (10)\r
+#define GIRQ09_GPIO_0113_BITPOS (11)\r
+#define GIRQ09_GPIO_0114_BITPOS (12)\r
+#define GIRQ09_GPIO_0115_BITPOS (13)\r
+#define GIRQ09_GPIO_0116_BITPOS (14) \r
+#define GIRQ09_GPIO_0117_BITPOS (15)\r
+//\r
+#define GIRQ09_GPIO_0120_BITPOS (16)\r
+#define GIRQ09_GPIO_0121_BITPOS (17)\r
+#define GIRQ09_GPIO_0122_BITPOS (18)\r
+#define GIRQ09_GPIO_0123_BITPOS (19)\r
+#define GIRQ09_GPIO_0124_BITPOS (20)\r
+#define GIRQ09_GPIO_0125_BITPOS (21)\r
+#define GIRQ09_GPIO_0126_BITPOS (22) \r
+#define GIRQ09_GPIO_0127_BITPOS (23)\r
+//\r
+#define GIRQ09_GPIO_0130_BITPOS (24)\r
+#define GIRQ09_GPIO_0131_BITPOS (25)\r
+#define GIRQ09_GPIO_0132_BITPOS (26)\r
+#define GIRQ09_GPIO_0133_BITPOS (27)\r
+#define GIRQ09_GPIO_0134_BITPOS (28)\r
+#define GIRQ09_GPIO_0135_BITPOS (29)\r
+#define GIRQ09_GPIO_0136_BITPOS (30) \r
+\r
+//\r
+#define GIRQ09_MASK (0x7FFFFFFFul)\r
+#define GIRQ09_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ10 Bit Positions \r
+#define GIRQ10_GPIO_0040_BITPOS (0)\r
+#define GIRQ10_GPIO_0041_BITPOS (1)\r
+#define GIRQ10_GPIO_0042_BITPOS (2)\r
+#define GIRQ10_GPIO_0043_BITPOS (3)\r
+#define GIRQ10_GPIO_0044_BITPOS (4)\r
+#define GIRQ10_GPIO_0045_BITPOS (5)\r
+#define GIRQ10_GPIO_0046_BITPOS (6) \r
+#define GIRQ10_GPIO_0047_BITPOS (7)\r
+//\r
+#define GIRQ10_GPIO_0050_BITPOS (8)\r
+#define GIRQ10_GPIO_0051_BITPOS (9)\r
+#define GIRQ10_GPIO_0052_BITPOS (10)\r
+#define GIRQ10_GPIO_0053_BITPOS (11)\r
+#define GIRQ10_GPIO_0054_BITPOS (12)\r
+#define GIRQ10_GPIO_0055_BITPOS (13)\r
+#define GIRQ10_GPIO_0056_BITPOS (14) \r
+#define GIRQ10_GPIO_0057_BITPOS (15)\r
+//\r
+#define GIRQ10_GPIO_0060_BITPOS (16)\r
+#define GIRQ10_GPIO_0061_BITPOS (17)\r
+#define GIRQ10_GPIO_0062_BITPOS (18)\r
+#define GIRQ10_GPIO_0063_BITPOS (19)\r
+#define GIRQ10_GPIO_0064_BITPOS (20)\r
+#define GIRQ10_GPIO_0065_BITPOS (21)\r
+#define GIRQ10_GPIO_0066_BITPOS (22) \r
+#define GIRQ10_GPIO_0067_BITPOS (23)\r
+//\r
+#define GIRQ10_GPIO_0070_BITPOS (24)\r
+#define GIRQ10_GPIO_0071_BITPOS (25)\r
+#define GIRQ10_GPIO_0072_BITPOS (26)\r
+#define GIRQ10_GPIO_0073_BITPOS (27)\r
+#define GIRQ10_GPIO_0074_BITPOS (28)\r
+#define GIRQ10_GPIO_0075_BITPOS (29)\r
+#define GIRQ10_GPIO_0076_BITPOS (30) \r
+\r
+//\r
+#define GIRQ10_MASK (0x7FFFFFFFul)\r
+#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ11 Bit Positions \r
+#define GIRQ11_GPIO_0000_BITPOS (0)\r
+#define GIRQ11_GPIO_0001_BITPOS (1)\r
+#define GIRQ11_GPIO_0002_BITPOS (2)\r
+#define GIRQ11_GPIO_0003_BITPOS (3)\r
+#define GIRQ11_GPIO_0004_BITPOS (4)\r
+#define GIRQ11_GPIO_0005_BITPOS (5)\r
+#define GIRQ11_GPIO_0006_BITPOS (6) \r
+#define GIRQ11_GPIO_0007_BITPOS (7)\r
+//\r
+#define GIRQ11_GPIO_0010_BITPOS (8)\r
+#define GIRQ11_GPIO_0011_BITPOS (9)\r
+#define GIRQ11_GPIO_0012_BITPOS (10)\r
+#define GIRQ11_GPIO_0013_BITPOS (11)\r
+#define GIRQ11_GPIO_0014_BITPOS (12)\r
+#define GIRQ11_GPIO_0015_BITPOS (13)\r
+#define GIRQ11_GPIO_0016_BITPOS (14) \r
+#define GIRQ11_GPIO_0017_BITPOS (15)\r
+//\r
+#define GIRQ11_GPIO_0020_BITPOS (16)\r
+#define GIRQ11_GPIO_0021_BITPOS (17)\r
+#define GIRQ11_GPIO_0022_BITPOS (18)\r
+#define GIRQ11_GPIO_0023_BITPOS (19)\r
+#define GIRQ11_GPIO_0024_BITPOS (20)\r
+#define GIRQ11_GPIO_0025_BITPOS (21)\r
+#define GIRQ11_GPIO_0026_BITPOS (22) \r
+#define GIRQ11_GPIO_0027_BITPOS (23)\r
+//\r
+#define GIRQ11_GPIO_0030_BITPOS (24)\r
+#define GIRQ11_GPIO_0031_BITPOS (25)\r
+#define GIRQ11_GPIO_0032_BITPOS (26)\r
+#define GIRQ11_GPIO_0033_BITPOS (27)\r
+#define GIRQ11_GPIO_0034_BITPOS (28)\r
+#define GIRQ11_GPIO_0035_BITPOS (29)\r
+#define GIRQ11_GPIO_0036_BITPOS (30) \r
+\r
+//\r
+#define GIRQ11_MASK (0x7FFFFFFFul)\r
+#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ12 Bit Positions \r
+#define GIRQ12_GPIO_0200_BITPOS (0)\r
+#define GIRQ12_GPIO_0201_BITPOS (1)\r
+#define GIRQ12_GPIO_0202_BITPOS (2)\r
+#define GIRQ12_GPIO_0203_BITPOS (3)\r
+#define GIRQ12_GPIO_0204_BITPOS (4)\r
+#define GIRQ12_GPIO_0205_BITPOS (5)\r
+#define GIRQ12_GPIO_0206_BITPOS (6) \r
+#define GIRQ12_GPIO_0207_BITPOS (7)\r
+//\r
+#define GIRQ12_GPIO_0210_BITPOS (8)\r
+#define GIRQ12_GPIO_0211_BITPOS (9)\r
+#define GIRQ12_GPIO_0212_BITPOS (10)\r
+#define GIRQ12_GPIO_0213_BITPOS (11)\r
+#define GIRQ12_GPIO_0214_BITPOS (12)\r
+#define GIRQ12_GPIO_0215_BITPOS (13)\r
+#define GIRQ12_GPIO_0216_BITPOS (14) \r
+#define GIRQ12_GPIO_0217_BITPOS (15)\r
+//\r
+#define GIRQ12_GPIO_0220_BITPOS (16)\r
+#define GIRQ12_GPIO_0221_BITPOS (17)\r
+#define GIRQ12_GPIO_0222_BITPOS (18)\r
+#define GIRQ12_GPIO_0223_BITPOS (19)\r
+#define GIRQ12_GPIO_0224_BITPOS (20)\r
+#define GIRQ12_GPIO_0225_BITPOS (21)\r
+#define GIRQ12_GPIO_0226_BITPOS (22) \r
+#define GIRQ12_GPIO_0227_BITPOS (23)\r
+//\r
+#define GIRQ12_GPIO_0230_BITPOS (24)\r
+#define GIRQ12_GPIO_0231_BITPOS (25)\r
+#define GIRQ12_GPIO_0232_BITPOS (26)\r
+#define GIRQ12_GPIO_0233_BITPOS (27)\r
+#define GIRQ12_GPIO_0234_BITPOS (28)\r
+#define GIRQ12_GPIO_0235_BITPOS (29)\r
+#define GIRQ12_GPIO_0236_BITPOS (30) \r
+\r
+//\r
+#define GIRQ12_MASK (0x7FFFFFFFul)\r
+#define GIRQ12_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+\r
+// GIRQ13 Bit Positions \r
+#define GIRQ13_SMBUS0_BITPOS (0)\r
+#define GIRQ13_SMBUS1_BITPOS (1)\r
+#define GIRQ13_SMBUS2_BITPOS (2)\r
+#define GIRQ13_SMBUS3_BITPOS (3)\r
+\r
+#define GIRQ13_MASK (0xFul)\r
+#define GIRQ13_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ14 Bit Positions \r
+#define GIRQ14_DMA0_BITPOS (0)\r
+#define GIRQ14_DMA1_BITPOS (1)\r
+#define GIRQ14_DMA2_BITPOS (2)\r
+#define GIRQ14_DMA3_BITPOS (3)\r
+#define GIRQ14_DMA4_BITPOS (4)\r
+#define GIRQ14_DMA5_BITPOS (5)\r
+#define GIRQ14_DMA6_BITPOS (6)\r
+#define GIRQ14_DMA7_BITPOS (7)\r
+#define GIRQ14_DMA8_BITPOS (8)\r
+#define GIRQ14_DMA9_BITPOS (9)\r
+#define GIRQ14_DMA10_BITPOS (10)\r
+#define GIRQ14_DMA11_BITPOS (11)\r
+#define GIRQ14_DMA12_BITPOS (12)\r
+#define GIRQ14_DMA13_BITPOS (13)\r
+//\r
+#define GIRQ14_MASK (0x3FFFul)\r
+#define GIRQ14_WAKE_CAPABLE_MASK (0x00000000ul)\r
+//\r
+\r
+\r
+// GIRQ15 Bit Positions \r
+#define GIRQ15_UART0_BITPOS (0)\r
+#define GIRQ15_UART1_BITPOS (1)\r
+#define GIRQ15_EMI0_BITPOS (2)\r
+#define GIRQ15_EMI1_BITPOS (3)\r
+#define GIRQ15_EMI2_BITPOS (4)\r
+#define GIRQ15_ACPI0_IBF_BITPOS (5)\r
+#define GIRQ15_ACPI0_OBF_BITPOS (6)\r
+#define GIRQ15_ACPI1_IBF_BITPOS (7)\r
+#define GIRQ15_ACPI1_OBF_BITPOS (8)\r
+#define GIRQ15_ACPI2_IBF_BITPOS (9)\r
+#define GIRQ15_ACPI2_OBF_BITPOS (10)\r
+#define GIRQ15_ACPI3_IBF_BITPOS (11)\r
+#define GIRQ15_ACPI3_OBF_BITPOS (12)\r
+#define GIRQ15_ACPI4_IBF_BITPOS (13)\r
+#define GIRQ15_ACPI4_OBF_BITPOS (14)\r
+#define GIRQ15_ACPI_PM1CTL_BITPOS (15)\r
+#define GIRQ15_ACPI_PM1EN_BITPOS (16)\r
+#define GIRQ15_ACPI_PM1STS_BITPOS (17)\r
+#define GIRQ15_MF8042_OBF_BITPOS (18)\r
+#define GIRQ15_MF8042_IBF_BITPOS (19)\r
+#define GIRQ15_MAILBOX_BITPOS (20)\r
+#define GIRQ15_PORT80_DBG0_BITPOS (22)\r
+#define GIRQ15_PORT80_DBG1_BITPOS (23)\r
+#define GIRQ15_TEST_BITPOS (24)\r
+\r
+//\r
+#define GIRQ15_MASK (0x1FFFFFFul)\r
+#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)\r
+//\r
+\r
+// GIRQ16 Bit Positions \r
+#define PKE_ERROR_BITPOS (0)\r
+#define PKE_END_BITPOS (1)\r
+#define RNG_BITPOS (2)\r
+#define AES_BITPOS (3)\r
+#define HASH_BITPOS (4)\r
+\r
+//\r
+#define GIRQ16_MASK (0x1Ful)\r
+#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)\r
+//\r
+\r
+// GIRQ17 Bit Positions \r
+#define GIRQ17_PECI_BITPOS (0)\r
+#define GIRQ17_TACH0_BITPOS (1)\r
+#define GIRQ17_TACH1_BITPOS (2)\r
+#define GIRQ17_TACH2_BITPOS (3)\r
+#define GIRQ17_RPM2PWM0_FAIL_BITPOS (4)\r
+#define GIRQ17_RPM2PWM0_STALL_BITPOS (5)\r
+#define GIRQ17_RPM2PWM1_FAIL_BITPOS (6)\r
+#define GIRQ17_RPM2PWM1_STALL_BITPOS (7)\r
+#define GIRQ17_ADC_INT0_BITPOS (8)\r
+#define GIRQ17_ADC_INT1_BITPOS (9)\r
+#define GIRQ17_RC_ID0_BITPOS (10)\r
+#define GIRQ17_RC_ID1_BITPOS (11)\r
+#define GIRQ17_RC_ID2_BITPOS (12)\r
+#define GIRQ17_LED0_BITPOS (13)\r
+#define GIRQ17_LED1_BITPOS (14)\r
+#define GIRQ17_LED2_BITPOS (15)\r
+#define GIRQ17_LED3_BITPOS (16)\r
+#define GIRQ17_PHOT_BITPOS (17)\r
+#define GIRQ17_PWRGUARD0_BITPOS (18)\r
+#define GIRQ17_PWRGUARD1_BITPOS (19)\r
+#define GIRQ17_RTOS_SWI0_BITPOS (25)\r
+#define GIRQ17_RTOS_SWI1_BITPOS (26)\r
+#define GIRQ17_RTOS_SWI2_BITPOS (27)\r
+#define GIRQ17_RTOS_SWI3_BITPOS (28)\r
+\r
+//\r
+#define GIRQ17_MASK (0x1E0FFFFFul)\r
+#define GIRQ17_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ18 Bit Positions\r
+#define GIRQ18_LPC_ERROR_BITPOS (0)\r
+#define GIRQ18_QMSPI_INT_BITPOS (1)\r
+#define GIRQ18_SPI0_TX_BITPOS (2)\r
+#define GIRQ18_SPI0_RX_BITPOS (3)\r
+#define GIRQ18_SPI1_TX_BITPOS (4)\r
+#define GIRQ18_SPI1_RX_BITPOS (5)\r
+#define GIRQ18_BCM0_BUSY_CLR_BITPOS (6)\r
+#define GIRQ18_BCM0_ERROR_BITPOS (7)\r
+#define GIRQ18_BCM1_BUSY_CLR_BITPOS (8)\r
+#define GIRQ18_BCM1_ERROR_BITPOS (9)\r
+#define GIRQ18_PS2_ACT0_BITPOS (10)\r
+#define GIRQ18_PS2_ACT1_BITPOS (11)\r
+#define GIRQ18_PS2_ACT2_BITPOS (12)\r
+#define GIRQ18_EEPROM_BITPOS (13)\r
+\r
+//\r
+#define GIRQ18_MASK (0x3FFFul)\r
+#define GIRQ18_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ19 Bit Positions \r
+#define GIRQ19_ESPI_INTR_PC_BITPOS (0)\r
+#define GIRQ19_ESPI_INTR_BM1_BITPOS (1)\r
+#define GIRQ19_ESPI_INTR_BM2_BITPOS (2)\r
+#define GIRQ19_ESPI_INTR_LTR_BITPOS (3)\r
+#define GIRQ19_ESPI_INTR_OOB_UP_BITPOS (4)\r
+#define GIRQ19_ESPI_INTR_OOB_DN_BITPOS (5)\r
+#define GIRQ19_ESPI_INTR_FLASH_BITPOS (6)\r
+#define GIRQ19_ESPI_RESET_BITPOS (7)\r
+#define GIRQ19_ESPI_VW_ENABLE_BITPOS (8)\r
+\r
+//\r
+#define GIRQ19_MASK (0x01FFul)\r
+#define GIRQ19_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ20 Bit Positions \r
+\r
+// \r
+#define GIRQ20_MASK (0x0ul)\r
+#define GIRQ20_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ21 Bit Positions \r
+#define GIRQ21_RTOS_TIMER_BITPOS (0)\r
+#define GIRQ21_HTIMER0_BITPOS (1)\r
+#define GIRQ21_HTIMER1_BITPOS (2)\r
+#define GIRQ21_WEEK_ALRM_INT_BITPOS (3)\r
+#define GIRQ21_SUB_WEEK_ALRM_INT_BITPOS (4)\r
+#define GIRQ21_ONE_SECOND_BITPOS (5)\r
+#define GIRQ21_SUB_SECOND_BITPOS (6)\r
+#define GIRQ21_SYSPWR_PRES_BITPOS (7)\r
+#define GIRQ21_RTC_BITPOS (8)\r
+#define GIRQ21_RTC_ALARM_BITPOS (9)\r
+#define GIRQ21_VBAT_VCI_OVRD_IN_BITPOS (10)\r
+#define GIRQ21_VBAT_VCI_IN0_BITPOS (11)\r
+#define GIRQ21_VBAT_VCI_IN1_BITPOS (12)\r
+#define GIRQ21_VBAT_VCI_IN2_BITPOS (13)\r
+#define GIRQ21_VBAT_VCI_IN3_BITPOS (14)\r
+#define GIRQ21_VBAT_VCI_IN4_BITPOS (15)\r
+#define GIRQ21_VBAT_VCI_IN5_BITPOS (16)\r
+#define GIRQ21_VBAT_VCI_IN6_BITPOS (17)\r
+#define GIRQ21_PS2_0A_WK_BITPOS (18)\r
+#define GIRQ21_PS2_0B_WK_BITPOS (19)\r
+#define GIRQ21_PS2_1A_WK_BITPOS (20)\r
+#define GIRQ21_PS2_1B_WK_BITPOS (21)\r
+#define GIRQ21_PS2_2_WK_BITPOS (22)\r
+#define GIRQ21_ENVMON_BITPOS (24)\r
+#define GIRQ21_KSC_INT_BITPOS (25)\r
+\r
+//\r
+#define GIRQ21_MASK (0x37FFFFFul)\r
+#define GIRQ21_WAKE_CAPABLE_MASK (0x37FFFFFul)\r
+//\r
+\r
+// GIRQ22 Bit Positions \r
+#define GIRQ22_LPC_WAKE_ONLY_BITPOS (0)\r
+#define GIRQ22_SMB0_WAKE_ONLY_BITPOS (1)\r
+#define GIRQ22_SMB1_WAKE_ONLY_BITPOS (2)\r
+#define GIRQ22_SMB2_WAKE_ONLY_BITPOS (3)\r
+#define GIRQ22_SMB3_WAKE_ONLY_BITPOS (4)\r
+#define GIRQ22_ESPI_WAKE_ONLY_BITPOS (9)\r
+\r
+#define GIRQ22_MASK (0x021Ful)\r
+#define GIRQ22_WAKE_CAPABLE_MASK (0x021Ful)\r
+\r
+// GIRQ23 Bit Positions \r
+#define GIRQ23_TMR0_BITPOS (0)\r
+#define GIRQ23_TMR1_BITPOS (1)\r
+#define GIRQ23_TMR2_BITPOS (2)\r
+#define GIRQ23_TMR3_BITPOS (3)\r
+#define GIRQ23_TMR4_BITPOS (4)\r
+#define GIRQ23_TMR5_BITPOS (5)\r
+#define GIRQ23_CTIMER0_BITPOS (6)\r
+#define GIRQ23_CTIMER1_BITPOS (7)\r
+#define GIRQ23_CTIMER2_BITPOS (8)\r
+#define GIRQ23_CTIMER3_BITPOS (9)\r
+#define GIRQ23_CAP_TIMER_BITPOS (10)\r
+#define GIRQ23_CCTIMER0_BITPOS (11)\r
+#define GIRQ23_CCTIMER1_BITPOS (12)\r
+#define GIRQ23_CCTIMER2_BITPOS (13)\r
+#define GIRQ23_CCTIMER3_BITPOS (14)\r
+#define GIRQ23_CCTIMER4_BITPOS (15)\r
+#define GIRQ23_CCTIMER5_BITPOS (16)\r
+#define GIRQ23_CCTIMER6_BITPOS (17)\r
+#define GIRQ23_CCTIMER7_BITPOS (18)\r
+\r
+//\r
+#define GIRQ23_MASK (0x07FFFFul)\r
+#define GIRQ23_WAKE_CAPABLE_MASK (0x0ul)\r
+//\r
+\r
+// GIRQ24 Bit Positions\r
+#define GIRQ24_ESPI_VW00_SRC0_BITPOS (0)\r
+#define GIRQ24_ESPI_VW00_SRC1_BITPOS (1)\r
+#define GIRQ24_ESPI_VW00_SRC2_BITPOS (2)\r
+#define GIRQ24_ESPI_VW00_SRC3_BITPOS (3)\r
+#define GIRQ24_ESPI_VW01_SRC0_BITPOS (4)\r
+#define GIRQ24_ESPI_VW01_SRC1_BITPOS (5)\r
+#define GIRQ24_ESPI_VW01_SRC2_BITPOS (6)\r
+#define GIRQ24_ESPI_VW01_SRC3_BITPOS (7)\r
+#define GIRQ24_ESPI_VW02_SRC0_BITPOS (8)\r
+#define GIRQ24_ESPI_VW02_SRC1_BITPOS (9)\r
+#define GIRQ24_ESPI_VW02_SRC2_BITPOS (10)\r
+#define GIRQ24_ESPI_VW02_SRC3_BITPOS (11)\r
+#define GIRQ24_ESPI_VW03_SRC0_BITPOS (12)\r
+#define GIRQ24_ESPI_VW03_SRC1_BITPOS (13)\r
+#define GIRQ24_ESPI_VW03_SRC2_BITPOS (14)\r
+#define GIRQ24_ESPI_VW03_SRC3_BITPOS (15)\r
+#define GIRQ24_ESPI_VW04_SRC0_BITPOS (16)\r
+#define GIRQ24_ESPI_VW04_SRC1_BITPOS (17)\r
+#define GIRQ24_ESPI_VW04_SRC2_BITPOS (18)\r
+#define GIRQ24_ESPI_VW04_SRC3_BITPOS (19)\r
+#define GIRQ24_ESPI_VW05_SRC0_BITPOS (20)\r
+#define GIRQ24_ESPI_VW05_SRC1_BITPOS (21)\r
+#define GIRQ24_ESPI_VW05_SRC2_BITPOS (22)\r
+#define GIRQ24_ESPI_VW05_SRC3_BITPOS (23)\r
+#define GIRQ24_ESPI_VW06_SRC0_BITPOS (24)\r
+#define GIRQ24_ESPI_VW06_SRC1_BITPOS (25)\r
+#define GIRQ24_ESPI_VW06_SRC2_BITPOS (26)\r
+#define GIRQ24_ESPI_VW06_SRC3_BITPOS (27)\r
+\r
+//\r
+#define GIRQ24_MASK (0x0FFFFFFFul)\r
+#define GIRQ24_WAKE_CAPABLE_MASK (0x0FFFFFFFul)\r
+//\r
+\r
+// GIRQ25 Bit Positions\r
+#define GIRQ25_ESPI_VW07_SRC0_BITPOS (0)\r
+#define GIRQ25_ESPI_VW07_SRC1_BITPOS (1)\r
+#define GIRQ25_ESPI_VW07_SRC2_BITPOS (2)\r
+#define GIRQ25_ESPI_VW07_SRC3_BITPOS (3)\r
+#define GIRQ25_ESPI_VW08_SRC0_BITPOS (4)\r
+#define GIRQ25_ESPI_VW08_SRC1_BITPOS (5)\r
+#define GIRQ25_ESPI_VW08_SRC2_BITPOS (6)\r
+#define GIRQ25_ESPI_VW08_SRC3_BITPOS (7)\r
+#define GIRQ25_ESPI_VW09_SRC0_BITPOS (8)\r
+#define GIRQ25_ESPI_VW09_SRC1_BITPOS (9)\r
+#define GIRQ25_ESPI_VW09_SRC2_BITPOS (10)\r
+#define GIRQ25_ESPI_VW09_SRC3_BITPOS (11)\r
+#define GIRQ25_ESPI_VW10_SRC0_BITPOS (12)\r
+#define GIRQ25_ESPI_VW10_SRC1_BITPOS (13)\r
+#define GIRQ25_ESPI_VW10_SRC2_BITPOS (14)\r
+#define GIRQ25_ESPI_VW10_SRC3_BITPOS (15)\r
+\r
+//\r
+#define GIRQ25_MASK (0x0FFFFul)\r
+#define GIRQ25_WAKE_CAPABLE_MASK (0x0FFFFul)\r
+//\r
+\r
+// GIRQ26 bit positions\r
+#define GIRQ26_GPIO240_BITPOS (0)\r
+#define GIRQ26_GPIO241_BITPOS (1)\r
+#define GIRQ26_GPIO242_BITPOS (2)\r
+#define GIRQ26_GPIO243_BITPOS (3)\r
+#define GIRQ26_GPIO244_BITPOS (4)\r
+#define GIRQ26_GPIO245_BITPOS (5)\r
+#define GIRQ26_GPIO246_BITPOS (6)\r
+#define GIRQ26_GPIO247_BITPOS (7)\r
+\r
+#define GIRQ26_GPIO250_BITPOS (8)\r
+#define GIRQ26_GPIO251_BITPOS (9)\r
+#define GIRQ26_GPIO252_BITPOS (10)\r
+#define GIRQ26_GPIO253_BITPOS (11)\r
+#define GIRQ26_GPIO254_BITPOS (12)\r
+#define GIRQ26_GPIO255_BITPOS (13)\r
+#define GIRQ26_GPIO256_BITPOS (14)\r
+#define GIRQ26_GPIO257_BITPOS (15)\r
+\r
+#define GIRQ26_GPIO260_BITPOS (16)\r
+#define GIRQ26_GPIO261_BITPOS (17)\r
+#define GIRQ26_GPIO262_BITPOS (18)\r
+#define GIRQ26_GPIO263_BITPOS (19)\r
+#define GIRQ26_GPIO264_BITPOS (20)\r
+#define GIRQ26_GPIO265_BITPOS (21)\r
+#define GIRQ26_GPIO266_BITPOS (22)\r
+#define GIRQ26_GPIO267_BITPOS (23)\r
+\r
+#define GIRQ26_GPIO270_BITPOS (24)\r
+#define GIRQ26_GPIO271_BITPOS (25)\r
+#define GIRQ26_GPIO272_BITPOS (26)\r
+#define GIRQ26_GPIO273_BITPOS (27)\r
+#define GIRQ26_GPIO274_BITPOS (28)\r
+#define GIRQ26_GPIO275_BITPOS (29)\r
+#define GIRQ26_GPIO276_BITPOS (30)\r
+\r
+#define GIRQ26_MASK (0x7FFFFFFFul)\r
+#define GIRQ26_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC,ECIA Routing Policy for Direct Mode */\r
+/* ------------------------------------------------------------------------------- */\r
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
+ * Configuration:\r
+ * 1. Always set ECS Interrupt Direct enable bit. \r
+ * 2. If GIRQn aggregated set Block Enable bit.\r
+ * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
+ * Switching issues:\r
+ * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
+ * Also requires set/clear of individual NVIC Enables.\r
+ * \r
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
+ * if any interrupt is configured as direct or aggregated\r
+*/\r
+\r
+/** Initialize EC Interrupt Aggregator\r
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
+ * This parameter is only applicable in direct mode.\r
+ * @note All GPIO's and wake capable sources are always \r
+ * aggregated! GPIO's interrupts will still work in direct mode.\r
+ * Block wakes are not be routed to the processor in direct \r
+ * mode. \r
+ * Note2: This function disables and enables global interrupt \r
+ */\r
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask);\r
+\r
+/** Set interrupt routing mode to aggregated or direct. \r
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
+ * @note In direct mode, one could enable certain GIRQs as aggregated using \r
+ * p_interrupt_ecia_block_enable_set function\r
+ */\r
+void interrupt_mode_set(uint8_t mode);\r
+\r
+/** Clears all individual interrupts Enables and Source in ECIA,\r
+ * and Clears all NVIC external enables and pending bits \r
+ */\r
+void interrupt_reset(void);\r
+\r
+/** Enables interrupt for a device \r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_enable(uint32_t dev_iroute);\r
+\r
+/** Disables interrupt for a device\r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_disable(uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* ECIA APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear Source in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ */\r
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);\r
+\r
+/** Get the Source bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);\r
+\r
+/** Get the Result bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if result bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
+ * NVIC corresponding to the aggregated GIRQ \r
+ */\r
+\r
+/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
+ * @note Recommended to use interrupt_device_enable, interrupt_device_disable\r
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
+ */\r
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);\r
+\r
+/** Set NVIC priority for specified peripheral interrupt source\r
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
+ * @param nvic_pri - NVIC Priority\r
+ * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt \r
+ * sources in the GIRQ. \r
+ * 2. This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);\r
+\r
+/** Return NVIC priority for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint32_t NVIC priority \r
+ */\r
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);\r
+\r
+/** Return NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
+ * \r
+ */\r
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);\r
+\r
+/** Set NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ */\r
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);\r
+\r
+/** Clears NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *\r
+ * and Status Register */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable specified GIRQ in ECIA block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+ void p_interrupt_ecia_block_enable_set(uint8_t girq_id);\r
+ \r
+ /** Enable GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);\r
+\r
+/** Check if specified GIRQ block enabled or not\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
+ */\r
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);\r
+\r
+/** Set all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_set(void);\r
+\r
+/** Clear specified GIRQ in ECIA Block \r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);\r
+\r
+/** Clear GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);\r
+\r
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_clr(void);\r
+ \r
+ /** Get status of GIRQ in ECIA Block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return 0 if status bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);\r
+\r
+/** Reads the Block IRQ Vector Register\r
+ * @return 32-bit value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void);\r
+\r
+/* ---------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *\r
+ * and Enable Registers */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/** Clear specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Enable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Disable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the status of the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the result bit of the interrupt in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Operations on all GIRQs */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear all aggregator GIRQn status registers */\r
+void p_interrupt_ecia_girqs_source_reset(void);\r
+\r
+/** Clear all aggregator GIRQn enables */\r
+ void p_interrupt_ecia_girqs_enable_reset(void);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to set interrupt control */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Set interrupt control \r
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+ void p_interrupt_control_set(uint8_t nvic_en_flag);\r
+ \r
+ /** Read interrupt control \r
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+uint8_t p_interrupt_control_get(void);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - NVIC */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
+ * @param nvic_num : NVIC number (see enum IRQn_Type)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ\r
+ * @note Application should perform this operation\r
+ */\r
+ void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);\r
+ \r
+ /** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
+void p_interrupt_nvic_extEnables_clr(void);\r
+\r
+/** Clear all NVIC external enables and pending bits */\r
+void p_interrupt_nvic_enpend_clr(void);\r
+\r
+/** Set NVIC external priorities to POR value */\r
+void p_interrupt_nvic_priorities_default_set(void);\r
+\r
+/** Set NVIC external priorities to specified priority (0 - 7)\r
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
+ * @note NVIC highest priority is the value 0, lowest is all 1's.\r
+ * Each external interrupt has an 8-bit register and the priority \r
+ * is left justified in the registers. MECxxx implements 8 priority \r
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
+ */\r
+void p_interrupt_nvic_priorities_set(uint8_t new_pri);\r
+\r
+#endif // #ifndef _INTERRUPT_H\r
+/* end interrupt.h */\r
+/** @}\r
+ */\r
+\r
+\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Renamed ecia_init to interrupt_init\r
+******************************************************************************/\r
+/** @file interrupt_api.c\r
+* \brief Interrupt APIs Source File\r
+* \author jvasanth\r
+* \r
+* This file implements the Interrupt Source file \r
+******************************************************************************/\r
+\r
+/** @defgroup Interrupt\r
+ * @{\r
+ */\r
+ \r
+#include "common_lib.h"\r
+#include "interrupt.h"\r
+#include "..\pcr\pcr.h"\r
+\r
+static uint8_t interrupt_is_girq_direct(uint8_t girq_num);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC,ECIA Routing Policy for Direct Mode */\r
+/* ------------------------------------------------------------------------------- */\r
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
+ * Configuration:\r
+ * 1. Always set ECS Interrupt Direct enable bit. \r
+ * 2. If GIRQn aggregated set Block Enable bit.\r
+ * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
+ * Switching issues:\r
+ * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
+ * Also requires set/clear of individual NVIC Enables.\r
+ * \r
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
+ * if any interrupt is configured as direct or aggregated\r
+*/\r
+\r
+/** Initialize EC Interrupt Aggregator\r
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
+ * This parameter is only applicable in direct mode.\r
+ * @note All GPIO's and wake capable sources are always \r
+ * aggregated! GPIO's interrupts will still work in direct mode.\r
+ * Block wakes are not be routed to the processor in direct \r
+ * mode. \r
+ * Note2: This function disables and enables global interrupt \r
+ */\r
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask)\r
+{\r
+ uint32_t isave;\r
+ \r
+ isave = __get_PRIMASK();\r
+ __disable_irq();\r
+ \r
+ //Clear Sleep for Interrupt block\r
+ pcr_sleep_enable(PCR_INT, 0);\r
+\r
+ interrupt_mode_set(mode);\r
+\r
+ p_interrupt_ecia_girqs_enable_reset(); \r
+ \r
+ p_interrupt_nvic_enpend_clr();\r
+ \r
+ p_interrupt_nvic_priorities_default_set();\r
+ \r
+ if (mode)\r
+ {//If direct mode, enable specific GIRQs to be aggregated\r
+ p_interrupt_ecia_block_enable_bitmask_set(girq_bitmask);\r
+ }\r
+ \r
+ if (!isave) {\r
+ __enable_irq();\r
+ }\r
+}\r
+\r
+/** Set interrupt routing mode to aggregated or direct. \r
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
+ * @note In direct mode, one could enable certain GIRQs as aggregated using \r
+ * p_interrupt_ecia_block_enable_set function\r
+ */\r
+void interrupt_mode_set(uint8_t mode)\r
+{\r
+ if (mode) \r
+ {\r
+ p_interrupt_ecia_block_enable_all_clr(); \r
+ } \r
+ else \r
+ {\r
+ p_interrupt_ecia_block_enable_all_set(); \r
+ }\r
+ \r
+ p_interrupt_control_set(mode);\r
+}\r
+\r
+/** Clears all individual interrupts Enables and Source in ECIA,\r
+ * and Clears all NVIC external enables and pending bits \r
+ */\r
+void interrupt_reset(void)\r
+{ \r
+ p_interrupt_ecia_girqs_enable_reset();\r
+ p_interrupt_ecia_girqs_source_reset(); \r
+\r
+ p_interrupt_nvic_enpend_clr();\r
+}\r
+\r
+/** Enables interrupt for a device \r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_enable(uint32_t dev_iroute)\r
+{\r
+ uint32_t isave;\r
+ IRQn_Type nvic_num;\r
+ uint8_t girq_num;\r
+ uint8_t ia_bitpos;\r
+ \r
+ girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;\r
+ ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; \r
+ \r
+ if (interrupt_is_girq_direct(girq_num)) \r
+ { // GIRQ is hooked direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ } \r
+ else \r
+ { // GIRQ is aggregated \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ isave = __get_PRIMASK();\r
+ __disable_irq();\r
+\r
+ NVIC_EnableIRQ(nvic_num);\r
+ p_interrupt_ecia_girq_enable_set(girq_num, ia_bitpos); \r
+ __DSB(); \r
+\r
+ if (!isave) {\r
+ __enable_irq();\r
+ }\r
+}\r
+\r
+\r
+/** Disables interrupt for a device\r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_disable(uint32_t dev_iroute)\r
+{\r
+ uint32_t isave;\r
+ IRQn_Type nvic_num;\r
+ uint8_t girq_num;\r
+ uint8_t ia_bitpos;\r
+\r
+ girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;\r
+ ia_bitpos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; \r
+ \r
+ isave = __get_PRIMASK();\r
+ __disable_irq();\r
+ \r
+ if (interrupt_is_girq_direct(girq_num)) \r
+ { // GIRQ is hooked direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ NVIC_DisableIRQ(nvic_num);\r
+ } \r
+ \r
+ p_interrupt_ecia_girq_enable_clr(girq_num, ia_bitpos); \r
+ __DSB(); \r
+\r
+ if (!isave) {\r
+ __enable_irq();\r
+ }\r
+}\r
+\r
+/** ecia_is_girq_direct - Return true if GIRQn sources can be directly \r
+ * connected to the NVIC - based on ECS->INTERRUPT_CONTROL and GIRQ block enable\r
+ * @param girq_num - enum MEC_GIRQ_IDS\r
+ * @return 1 if GIRQn sources can be directly routed to the NVIC, else 0\r
+ */\r
+static uint8_t interrupt_is_girq_direct(uint8_t girq_num)\r
+{ \r
+ uint32_t bpos;\r
+ uint8_t retVal;\r
+ uint8_t girq_block_enabled;\r
+ \r
+ retVal = 0;\r
+ \r
+ bpos = (girq_num & 0x1Fu) + 8u;\r
+ \r
+ if ((ECIA_GIRQ_DIRECT_BITMAP) & (1ul << bpos)) \r
+ { \r
+ if (p_interrupt_control_get()) \r
+ {// direct NVIC enabled\r
+ \r
+ girq_block_enabled = p_interrupt_ecia_block_enable_get(girq_num);\r
+ \r
+ if (!girq_block_enabled)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ }\r
+ }\r
+ return retVal;\r
+}\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* ECIA APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear Source in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ */\r
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute)\r
+{ \r
+ uint8_t girq_num;\r
+ uint8_t ia_bit_pos;\r
+ \r
+ girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;\r
+ ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; \r
+ \r
+ p_interrupt_ecia_girq_source_clr(girq_num, ia_bit_pos); \r
+ __DSB();\r
+}\r
+\r
+/** Get the Source bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute)\r
+{ \r
+ uint8_t girq_num;\r
+ uint8_t ia_bit_pos;\r
+ uint8_t retVal;\r
+ \r
+ girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;\r
+ ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; \r
+ \r
+ retVal = p_interrupt_ecia_girq_source_get(girq_num, ia_bit_pos); \r
+ return retVal;\r
+}\r
+\r
+/** Get the Result bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if result bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute)\r
+{ \r
+ uint8_t girq_num;\r
+ uint8_t ia_bit_pos;\r
+ uint8_t retVal;\r
+ \r
+ girq_num = (uint8_t)(dev_iroute >> (ECIA_GIRQ_ID_BITPOS)) & 0x1Fu;\r
+ ia_bit_pos = (uint8_t)(dev_iroute >> (ECIA_GIRQ_BIT_BITPOS)) & 0x1Fu; \r
+ \r
+ retVal = p_interrupt_ecia_girq_result_get(girq_num, ia_bit_pos); \r
+ return retVal;\r
+}\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
+ * NVIC corresponding to the aggregated GIRQ \r
+ */\r
+\r
+/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
+ * @note 1. Recommended to use interrupt_device_enable, interrupt_device_disable\r
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
+ * 2. This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag)\r
+{\r
+ uint32_t isave;\r
+ IRQn_Type nvic_num;\r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ isave = __get_PRIMASK();\r
+ __disable_irq();\r
+ \r
+ p_interrupt_nvic_enable(nvic_num, en_flag); \r
+ \r
+ if (!isave) {\r
+ __enable_irq();\r
+ }\r
+}\r
+\r
+\r
+/** Set NVIC priority for specified peripheral interrupt \r
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
+ * @param nvic_pri - NVIC Priority\r
+ * @note If ECIA is in aggregated mode, the priority affects all interrupt \r
+ * sources in the GIRQ. \r
+ */\r
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri)\r
+{\r
+ IRQn_Type nvic_num;\r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ NVIC_SetPriority(nvic_num, (uint32_t)nvic_pri);\r
+}\r
+\r
+/** Return NVIC priority for the device's interrupt\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint32_t NVIC priority \r
+ */\r
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute)\r
+{\r
+ IRQn_Type nvic_num;\r
+ uint32_t nvic_priority;\r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ nvic_priority = NVIC_GetPriority(nvic_num);\r
+ \r
+ return nvic_priority;\r
+}\r
+\r
+\r
+/** Return NVIC pending for the device\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
+ * \r
+ */\r
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute)\r
+{\r
+ IRQn_Type nvic_num;\r
+ uint8_t nvic_pending;\r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ nvic_pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num));\r
+ \r
+ return nvic_pending;\r
+}\r
+\r
+\r
+/** Set NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ */\r
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute)\r
+{\r
+ IRQn_Type nvic_num; \r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ NVIC_SetPendingIRQ(nvic_num); \r
+}\r
+\r
+/** Clears NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute)\r
+{\r
+ uint32_t was_masked;\r
+ IRQn_Type nvic_num;\r
+ uint8_t pending;\r
+ \r
+ if (p_interrupt_control_get()) \r
+ { // direct \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_NVIC_ID_BITPOS)) & 0xFFul); \r
+ } \r
+ else // fully aggregated\r
+ { \r
+ nvic_num = (IRQn_Type)((dev_iroute >> (ECIA_IA_NVIC_ID_BITPOS)) & 0xFFul);\r
+ }\r
+ \r
+ was_masked = __get_PRIMASK();\r
+ __disable_irq();\r
+ \r
+ pending = (uint8_t)(NVIC_GetPendingIRQ(nvic_num));\r
+\r
+ NVIC_ClearPendingIRQ(nvic_num);\r
+ __DSB();\r
+ \r
+ if (!was_masked) {\r
+ __enable_irq();\r
+ }\r
+ \r
+ return pending;\r
+}\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/* end interrupt_api.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Initial Draft\r
+******************************************************************************/\r
+/** @file interrupt_ecia_perphl.c\r
+* \brief Interrupt ECIA Peripheral Source File\r
+* \author jvasanth\r
+* \r
+* This file implements the ECIA peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Interrupt\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "interrupt.h"\r
+\r
+#define ECIA ((INTS_Type *) INTS_BASE)\r
+#define ECS ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Operations on GIRQ Block Enable Set, Enable Clear and Status Register */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable specified GIRQ in ECIA block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+void p_interrupt_ecia_block_enable_set(uint8_t girq_id)\r
+{\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ ECIA->BLOCK_ENABLE_SET = (1ul << ((girq_id + 8) & 0x1Fu));\r
+ }\r
+}\r
+\r
+/** Enable GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask)\r
+{ \r
+ ECIA->BLOCK_ENABLE_SET = girq_bitmask; \r
+}\r
+\r
+/** Check if specified GIRQ block enabled or not\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
+ */\r
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id)\r
+{\r
+ uint8_t retVal;\r
+ \r
+ retVal = 0;\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) \r
+ { \r
+ if ((ECIA->BLOCK_ENABLE_SET) & (1ul << ((girq_id + 8) & 0x1Fu)))\r
+ {\r
+ retVal = 1; \r
+ }\r
+ }\r
+ return retVal;\r
+}\r
+\r
+/** Set all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_set(void)\r
+{ \r
+ ECIA->BLOCK_ENABLE_SET = 0xfffffffful; \r
+}\r
+\r
+/** Clear specified GIRQ in ECIA Block \r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id)\r
+{\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ ECIA->BLOCK_ENABLE_CLEAR = (1ul << ((girq_id + 8) & 0x1Fu));\r
+ }\r
+}\r
+\r
+/** Clear GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask)\r
+{ \r
+ ECIA->BLOCK_ENABLE_CLEAR = girq_bitmask; \r
+}\r
+\r
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
+ void p_interrupt_ecia_block_enable_all_clr(void)\r
+{ \r
+ ECIA->BLOCK_ENABLE_CLEAR = 0xfffffffful; \r
+}\r
+\r
+/** Get status of GIRQ in ECIA Block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return 0 if status bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id)\r
+{ \r
+ uint32_t retVal;\r
+\r
+ retVal = ECIA->BLOCK_IRQ_VECTOR & (1ul << ((girq_id + 8) & 0x1Fu));\r
+\r
+ return retVal; \r
+}\r
+\r
+/** Reads the Block IRQ Vector Register\r
+ * @return 32-bit value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void)\r
+{ \r
+ uint32_t retVal;\r
+\r
+ retVal = ECIA->BLOCK_IRQ_VECTOR;\r
+\r
+ return retVal; \r
+}\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Operations on GIRQx Source, Enable, Result and Enable Registers */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum)\r
+{\r
+ __IO uint32_t *girq_source = (uint32_t*)ECIA;\r
+ \r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_source += (5 * girq_id);\r
+ *girq_source |= (1ul << (bitnum & 0x1Fu));\r
+ }\r
+}\r
+\r
+/** Read the specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum)\r
+{\r
+ uint32_t retVal;\r
+ __IO uint32_t *girq_source = (uint32_t*)ECIA;\r
+ \r
+ retVal = 0;\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_source += (5 * girq_id); \r
+ retVal = (*girq_source & (1ul << (bitnum & 0x1Fu)));\r
+ } \r
+ return retVal;\r
+}\r
+\r
+/** Enable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum)\r
+{\r
+ __IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET));\r
+ \r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_enable_set += (5 * girq_id); \r
+ *girq_enable_set |= (1ul << (bitnum & 0x1Fu));\r
+ }\r
+}\r
+\r
+/** Disable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum)\r
+{\r
+ __IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR));\r
+ \r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_enable_clr += (5 * girq_id); \r
+ *girq_enable_clr |= (1ul << (bitnum & 0x1Fu));\r
+ }\r
+}\r
+\r
+/** Read the status of the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum)\r
+{\r
+ uint32_t retVal;\r
+ __IO uint32_t *girq_enable_set = (uint32_t*)(&(ECIA->GIRQ08_EN_SET));\r
+\r
+ retVal = 0;\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_enable_set += (5 * girq_id); \r
+ retVal = (*girq_enable_set & (1ul << (bitnum & 0x1Fu)));\r
+ }\r
+ return retVal;\r
+}\r
+\r
+/** Read the result bit of the interrupt in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum)\r
+{\r
+ uint32_t retVal;\r
+ __IO uint32_t *girq_result = (uint32_t*)(&(ECIA->GIRQ08_RESULT));\r
+ \r
+ retVal = 0;\r
+ if ( girq_id < (MEC_GIRQ_ID_MAX) ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_result += (5 * girq_id); \r
+ retVal = (*girq_result & (1ul << (bitnum & 0x1Fu)));\r
+ }\r
+ \r
+ return retVal;\r
+}\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Operations on all GIRQs */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear all aggregator GIRQn status registers */\r
+void p_interrupt_ecia_girqs_source_reset(void)\r
+{\r
+ uint16_t i;\r
+ __IO uint32_t *girq_source = (uint32_t*)ECIA;\r
+\r
+ for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_source += 5; \r
+ *girq_source = 0xfffffffful;\r
+ } \r
+}\r
+\r
+/** Clear all aggregator GIRQn enables */\r
+ void p_interrupt_ecia_girqs_enable_reset(void)\r
+{\r
+ uint16_t i;\r
+ __IO uint32_t *girq_enable_clr = (uint32_t*)(&(ECIA->GIRQ08_EN_CLR));\r
+\r
+ for ( i = 0u; i < (MEC_GIRQ_ID_MAX); i++ ) {\r
+ /* Each GIRQ has 5 32bit fields: SRC, ENABLE_SET, ENABLE_CLR, RESULT & RESERVED\r
+ * please refer INTS_Type in MCHP_device_internal.h\r
+ * Based on the girq id calculate the offset in the structure INTS_Type\r
+ * \r
+ * BASED ON THE STRUCTURE DEFINITION OF INTS_Type ALL FIELDS ARE ALIGNED ON\r
+ * 32 BIT BOUNDARY, FOLLOWING WILL NOT WORK IF THIS SCHEME CHANGES\r
+ */\r
+ girq_enable_clr += 5; \r
+ *girq_enable_clr = 0xfffffffful;\r
+ } \r
+}\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Function to set interrupt control */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Set interrupt control \r
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+void p_interrupt_control_set(uint8_t nvic_en_flag)\r
+{ \r
+ ECS->INTERRUPT_CONTROL = nvic_en_flag;\r
+}\r
+\r
+/** Read interrupt control \r
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+uint8_t p_interrupt_control_get(void)\r
+{ \r
+ return (ECS->INTERRUPT_CONTROL & 0x1);\r
+}\r
+\r
+/* end interrupt_ecia_perphl.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Initial Draft\r
+******************************************************************************/\r
+/** @file interrupt_nvic_perphl.c\r
+* \brief Interrupt NVIC Peripheral Source File\r
+* \author jvasanth\r
+* \r
+* This file implements the NVIC peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Interrupt\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "interrupt.h"\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC Functions */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
+ * @param nvic_num : NVIC number (see enum IRQn_Type)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
+ */\r
+void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag)\r
+{ \r
+ if (en_flag) {\r
+ NVIC_EnableIRQ(nvic_num);\r
+ } else {\r
+ NVIC_DisableIRQ(nvic_num);\r
+ }\r
+ __DSB(); \r
+}\r
+\r
+/** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
+void p_interrupt_nvic_extEnables_clr(void)\r
+{\r
+ uint32_t i, m;\r
+ \r
+ m = (uint32_t)(MAX_IRQn) >> 5;\r
+ if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; }\r
+ \r
+ for ( i = 0ul; i < m ; i++ ) \r
+ {\r
+ NVIC->ICER[i] = 0xfffffffful; \r
+ }\r
+}\r
+\r
+/** Clear all NVIC external enables and pending bits */\r
+void p_interrupt_nvic_enpend_clr(void)\r
+{\r
+ uint32_t i, m;\r
+\r
+ // Clear NVIC enables & pending status\r
+ m = (uint32_t)(MAX_IRQn) >> 5;\r
+ if ( (uint32_t)(MAX_IRQn) & 0x1Ful ) { m++; }\r
+ \r
+ for ( i = 0ul; i < m ; i++ ) \r
+ {\r
+ NVIC->ICER[i] = 0xfffffffful;\r
+ NVIC->ICPR[i] = 0xfffffffful;\r
+ } \r
+}\r
+\r
+/** Set NVIC external priorities to POR value */\r
+void p_interrupt_nvic_priorities_default_set(void)\r
+{\r
+ uint32_t i;\r
+ // Set POR default NVIC priority (highest)\r
+ for ( i = 0ul; i < (uint32_t)MAX_IRQn; i++ ) {\r
+ NVIC->IP[i] = 0u;\r
+ }\r
+}\r
+\r
+/** Set NVIC external priorities to specified priority (0 - 7)\r
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
+ * @note NVIC highest priority is the value 0, lowest is all 1's.\r
+ * Each external interrupt has an 8-bit register and the priority \r
+ * is left justified in the registers. MECxxx implements 8 priority \r
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
+ */\r
+void p_interrupt_nvic_priorities_set(uint8_t new_pri)\r
+{\r
+ uint16_t i;\r
+ \r
+ for ( i = 0ul; i < MAX_IRQn; i++ ) {\r
+ NVIC_SetPriority((IRQn_Type)i, new_pri);\r
+ }\r
+}\r
+\r
+\r
+/* end interrupt_nvic_perphl.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr.h\r
+* \brief Power, Clocks, and Resets Header file\r
+* \author jvasanth\r
+* \r
+* This file is the PCR header file \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#ifndef _PCR_H\r
+#define _PCR_H\r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Register IDS \r
+ *******************************************************************************/\r
+enum _PCR_REGSET_ID_\r
+{\r
+ PCR_REG_SYSTEM_SLEEP_CTRL = 0, \r
+ PCR_REG_PROCESSOR_CLK_CTRL, \r
+ PCR_REG_SLOW_CLK_CTRL,\r
+ PCR_REG_OSCILLATOR_ID,\r
+ PCR_REG_PWR_RESET_STS,\r
+ PCR_REG_PWR_RESET_CTRL,\r
+ PCR_REG_SYSTEM_RESET,\r
+ PCR_TEST0,\r
+ PCR_TEST1,\r
+ PCR_REG_EC_SLEEP_ENABLE_0 = 12,\r
+ PCR_REG_EC_SLEEP_ENABLE_1,\r
+ PCR_REG_EC_SLEEP_ENABLE_2,\r
+ PCR_REG_EC_SLEEP_ENABLE_3, \r
+ PCR_REG_EC_SLEEP_ENABLE_4, \r
+ PCR_REG_EC_CLK_REQD_STS_0 = 20,\r
+ PCR_REG_EC_CLK_REQD_STS_1,\r
+ PCR_REG_EC_CLK_REQD_STS_2,\r
+ PCR_REG_EC_CLK_REQD_STS_3,\r
+ PCR_REG_EC_CLK_REQD_STS_4,\r
+ PCR_REG_EC_RESET_ENABLE_0 = 28,\r
+ PCR_REG_EC_RESET_ENABLE_1,\r
+ PCR_REG_EC_RESET_ENABLE_2,\r
+ PCR_REG_EC_RESET_ENABLE_3,\r
+ PCR_REG_EC_RESET_ENABLE_4,\r
+ \r
+};\r
+/* ---------------------------------------------------------------------- */\r
+\r
+// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable\r
+//PCR register group 0 - EC 0\r
+#define PCR0_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_0) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_0) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_0) & 0xFF)<<16u))\r
+\r
+//PCR register group 1 - EC 1\r
+#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_1) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_1) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_1) & 0xFF)<<16u))\r
+\r
+//PCR register group 2 - EC 2\r
+#define PCR2_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))\r
+\r
+//PCR register group 3 - EC 3\r
+#define PCR3_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_3) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_3) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_3) & 0xFF)<<16u))\r
+ \r
+//PCR register group 4 - EC 4\r
+#define PCR4_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_4) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_4) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_4) & 0xFF)<<16u))\r
+ \r
+//PCR0_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR0_EC_JTAG_STAP_BITPOS (0u)\r
+#define PCR0_EC_EFUSE_BITPOS (1u)\r
+#define PCR0_EC_ISPI_BITPOS (2u)\r
+\r
+//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR1_EC_INT_BITPOS (0u)\r
+#define PCR1_EC_PECI_BITPOS (1u)\r
+#define PCR1_EC_TACH0_BITPOS (2u)\r
+#define PCR1_EC_PWM0_BITPOS (4u)\r
+#define PCR1_EC_PMC_BITPOS (5u)\r
+#define PCR1_EC_DMA_BITPOS (6u)\r
+#define PCR1_EC_TFDP_BITPOS (7u)\r
+#define PCR1_EC_CPU_BITPOS (8u)\r
+#define PCR1_EC_WDT_BITPOS (9u)\r
+#define PCR1_EC_SMB0_BITPOS (10u)\r
+#define PCR1_EC_TACH1_BITPOS (11u)\r
+#define PCR1_EC_TACH2_BITPOS (12u)\r
+#define PCR1_EC_PWM1_BITPOS (20u)\r
+#define PCR1_EC_PWM2_BITPOS (21u)\r
+#define PCR1_EC_PWM3_BITPOS (22u)\r
+#define PCR1_EC_PWM4_BITPOS (23u)\r
+#define PCR1_EC_PWM5_BITPOS (24u)\r
+#define PCR1_EC_PWM6_BITPOS (25u)\r
+#define PCR1_EC_PWM7_BITPOS (26u)\r
+#define PCR1_EC_PWM8_BITPOS (27u)\r
+#define PCR1_EC_REG_BITPOS (29u)\r
+#define PCR1_EC_BTIMER0_BITPOS (30u)\r
+#define PCR1_EC_BTIMER1_BITPOS (31u)\r
+\r
+//PCR2_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR2_EC_LPC_BITPOS (0u)\r
+#define PCR2_EC_UART0_BITPOS (1u)\r
+#define PCR2_EC_UART1_BITPOS (2u)\r
+#define PCR2_EC_GLBL_CFG_BITPOS (12u)\r
+#define PCR2_EC_ACPI_EC0_BITPOS (13u)\r
+#define PCR2_EC_ACPI_EC1_BITPOS (14u)\r
+#define PCR2_EC_ACPI_PM1_BITPOS (15u)\r
+#define PCR2_EC_8042EM_BITPOS (16u)\r
+#define PCR2_EC_MBOX_BITPOS (17u)\r
+#define PCR2_EC_RTC_BITPOS (18u)\r
+#define PCR2_EC_ESPI_BITPOS (19u)\r
+#define PCR2_EC_ACPI_EC_2_BITPOS (21u)\r
+#define PCR2_EC_ACPI_EC_3_BITPOS (22u)\r
+#define PCR2_EC_ACPI_EC_BITPOS (23u)\r
+#define PCR2_EC_PORT80_0_BITPOS (25u)\r
+#define PCR2_EC_PORT80_1_BITPOS (26u)\r
+\r
+//PCR3_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR3_EC_ADC_BITPOS (3u)\r
+#define PCR3_EC_PS2_0_BITPOS (5u)\r
+#define PCR3_EC_PS2_1_BITPOS (6u)\r
+#define PCR3_EC_PS2_2_BITPOS (7u)\r
+#define PCR3_EC_SPI0_BITPOS (9u)\r
+#define PCR3_EC_HTIMER_BITPOS (10u)\r
+#define PCR3_EC_KEYSCAN_BITPOS (11u)\r
+#define PCR3_EC_RPM_PWM_BITPOS (12u)\r
+#define PCR3_EC_SMB1_BITPOS (13u)\r
+#define PCR3_EC_SMB2_BITPOS (14u)\r
+#define PCR3_EC_SMB3_BITPOS (15u)\r
+#define PCR3_EC_LED0_BITPOS (16u)\r
+#define PCR3_EC_LED1_BITPOS (17u)\r
+#define PCR3_EC_LED2_BITPOS (18u)\r
+#define PCR3_EC_BCM_BITPOS (19u)\r
+#define PCR3_EC_SPI1_BITPOS (20u)\r
+#define PCR3_EC_BTIMER2_BITPOS (21u)\r
+#define PCR3_EC_BTIMER3_BITPOS (22u)\r
+#define PCR3_EC_BTIMER4_BITPOS (23u)\r
+#define PCR3_EC_BTIMER5_BITPOS (24u)\r
+#define PCR3_EC_LED3_BITPOS (25u)\r
+#define PCR3_EC_PKE_BITPOS (26u)\r
+#define PCR3_EC_RNG_BITPOS (27u)\r
+#define PCR3_EC_AES_BITPOS (28u)\r
+#define PCR3_EC_HTIMER_1_BITPOS (29u)\r
+#define PCR3_EC_C_C_TIMER_BITPOS (30u)\r
+#define PCR3_EC_PWM9_BITPOS (31u)\r
+\r
+\r
+//PCR4_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR4_EC_PWM10_BITPOS (0u)\r
+#define PCR4_EC_PWM11_BITPOS (1u)\r
+#define PCR4_EC_CTIMER0_BITPOS (2u)\r
+#define PCR4_EC_CTIMER1_BITPOS (3u)\r
+#define PCR4_EC_CTIMER2_BITPOS (4u)\r
+#define PCR4_EC_CTIMER3_BITPOS (5u)\r
+#define PCR4_EC_RTOS_TIMER_BITPOS (6u)\r
+#define PCR4_EC_RPM2_PWM_BITPOS (7u)\r
+#define PCR4_EC_QMSPI_BITPOS (8u)\r
+#define PCR4_EC_BCM_1_BITPOS (9u)\r
+#define PCR4_EC_RC_ID0_BITPOS (10u)\r
+#define PCR4_EC_RC_ID1_BITPOS (11u)\r
+#define PCR4_EC_RC_ID2_BITPOS (12u)\r
+#define PCR4_EC_PROCHOT_BITPOS (13u)\r
+#define PCR4_EC_EEPROM_BITPOS (14u)\r
+#define PCR4_EC_CUST_LOG_BITPOS (15u)\r
+\r
+\r
+/*\r
+ * n = b[7:0] = PCR Reg Bit Position\r
+ * m = b[31:8] = PCRx Regs IDs\r
+ */\r
+//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) \r
+\r
+//PCRx_REGS_BIT positions \r
+#define PCRx_REGS_POS_SLEEP_ENABLE (8u)\r
+#define PCRx_REGS_POS_CLK_REQD_STS (16u)\r
+#define PCRx_REGS_POS_RESET_ENABLE (24u) \r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Block IDS. \r
+ * These IDs are used to directly refer to a block \r
+ *******************************************************************************/\r
+typedef enum {\r
+ PCR_JTAG = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_JTAG_STAP_BITPOS & 0xFFu)),\r
+ PCR_EFUSE = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_EFUSE_BITPOS & 0xFFu)),\r
+ PCR_ISPI = (((uint32_t)(PCR0_REGS_EC) << 8) + (uint32_t)(PCR0_EC_ISPI_BITPOS & 0xFFu)),\r
+ \r
+ PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), \r
+ PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), \r
+ PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), \r
+ PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), \r
+ PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), \r
+ PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), \r
+ PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), \r
+ PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), \r
+ PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), \r
+ PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), \r
+ PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),\r
+ PCR_TACH2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH2_BITPOS & 0xFFu)), \r
+ PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), \r
+ PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), \r
+ PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), \r
+ PCR_PWM4 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM4_BITPOS & 0xFFu)), \r
+ PCR_PWM5 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM5_BITPOS & 0xFFu)), \r
+ PCR_PWM6 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM6_BITPOS & 0xFFu)), \r
+ PCR_PWM7 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM7_BITPOS & 0xFFu)), \r
+ PCR_PWM8 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM8_BITPOS & 0xFFu)), \r
+ PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), \r
+ PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), \r
+ PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), \r
+ \r
+ PCR_LPC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_LPC_BITPOS & 0xFFu)),\r
+ PCR_UART0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART0_BITPOS & 0xFFu)),\r
+ PCR_UART1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_UART1_BITPOS & 0xFFu)),\r
+ PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_GLBL_CFG_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC0_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC1_BITPOS & 0xFFu)),\r
+ PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_PM1_BITPOS & 0xFFu)),\r
+ PCR_8042EM = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_8042EM_BITPOS & 0xFFu)),\r
+ PCR_MBOX = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_MBOX_BITPOS & 0xFFu)),\r
+ PCR_RTC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_RTC_BITPOS & 0xFFu)),\r
+ PCR_ESPI = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ESPI_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC2 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_2_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC3 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_3_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_ACPI_EC_BITPOS & 0xFFu)),\r
+ PCR_PORT80_0 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_0_BITPOS & 0xFFu)),\r
+ PCR_PORT80_1 = (((uint32_t)(PCR2_REGS_EC) << 8) + (uint32_t)(PCR2_EC_PORT80_1_BITPOS & 0xFFu)),\r
+ \r
+ PCR_ADC = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_ADC_BITPOS & 0xFFu)),\r
+ PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_0_BITPOS & 0xFFu)), \r
+ PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_1_BITPOS & 0xFFu)), \r
+ PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PS2_2_BITPOS & 0xFFu)), \r
+ PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI0_BITPOS & 0xFFu)), \r
+ PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_BITPOS & 0xFFu)), \r
+ PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_KEYSCAN_BITPOS & 0xFFu)), \r
+ PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RPM_PWM_BITPOS & 0xFFu)), \r
+ PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB1_BITPOS & 0xFFu)), \r
+ PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB2_BITPOS & 0xFFu)), \r
+ PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SMB3_BITPOS & 0xFFu)), \r
+ PCR_LED0 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED0_BITPOS & 0xFFu)), \r
+ PCR_LED1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED1_BITPOS & 0xFFu)), \r
+ PCR_LED2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED2_BITPOS & 0xFFu)), \r
+ PCR_BCM = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BCM_BITPOS & 0xFFu)), \r
+ PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_SPI1_BITPOS & 0xFFu)), \r
+ PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER2_BITPOS & 0xFFu)), \r
+ PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER3_BITPOS & 0xFFu)), \r
+ PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER4_BITPOS & 0xFFu)), \r
+ PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_BTIMER5_BITPOS & 0xFFu)), \r
+ PCR_LED3 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_LED3_BITPOS & 0xFFu)), \r
+ PCR_PKE = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PKE_BITPOS & 0xFFu)), \r
+ PCR_RNG = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_RNG_BITPOS & 0xFFu)), \r
+ PCR_AES = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_AES_BITPOS & 0xFFu)), \r
+ PCR_HTIMER_1 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_HTIMER_1_BITPOS & 0xFFu)), \r
+ PCR_C_C_TIMER = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_C_C_TIMER_BITPOS & 0xFFu)), \r
+ PCR_PWM9 = (((uint32_t)(PCR3_REGS_EC) << 8) + (uint32_t)(PCR3_EC_PWM9_BITPOS & 0xFFu)),\r
+ \r
+ PCR_PWM10 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM10_BITPOS & 0xFFu)), \r
+ PCR_PWM11 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PWM11_BITPOS & 0xFFu)), \r
+ PCR_CTIMER0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER0_BITPOS & 0xFFu)), \r
+ PCR_CTIMER1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER1_BITPOS & 0xFFu)), \r
+ PCR_CTIMER2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER2_BITPOS & 0xFFu)), \r
+ PCR_CTIMER3 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CTIMER3_BITPOS & 0xFFu)), \r
+ PCR_RTOS_TIMER = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RTOS_TIMER_BITPOS & 0xFFu)), \r
+ PCR_RPM2_PWM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RPM2_PWM_BITPOS & 0xFFu)), \r
+ PCR_QMSPI = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_QMSPI_BITPOS & 0xFFu)), \r
+ PCR_BCM1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_BCM_1_BITPOS & 0xFFu)), \r
+ PCR_RCID0 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID0_BITPOS & 0xFFu)), \r
+ PCR_RCID1 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID1_BITPOS & 0xFFu)), \r
+ PCR_RCID2 = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_RC_ID2_BITPOS & 0xFFu)), \r
+ PCR_PROCHOT = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_PROCHOT_BITPOS & 0xFFu)), \r
+ PCR_EEPROM = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_EEPROM_BITPOS & 0xFFu)), \r
+ PCR_CUST_LOG = (((uint32_t)(PCR4_REGS_EC) << 8) + (uint32_t)(PCR4_EC_CUST_LOG_BITPOS & 0xFFu)), \r
+} PCR_BLK_ID;\r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Processor ClK Divide Values \r
+ *******************************************************************************/\r
+enum PROCESSOR_CLK_DIVIDE_VALUE\r
+{\r
+ PCR_CPU_CLK_DIVIDE_1 = 1,\r
+ PCR_CPU_CLK_DIVIDE_2 = 2,\r
+ PCR_CPU_CLK_DIVIDE_3 = 3,\r
+ PCR_CPU_CLK_DIVIDE_4 = 4,\r
+ PCR_CPU_CLK_DIVIDE_16 = 16,\r
+ PCR_CPU_CLK_DIVIDE_48 = 48 \r
+};\r
+\r
+/******************************************************************************/\r
+/** System Sleep Modes \r
+ *******************************************************************************/\r
+enum SYSTEM_SLEEP_MODES\r
+{\r
+ SYSTEM_LIGHT_SLEEP = 0, \r
+ SYSTEM_HEAVY_SLEEP = 1,\r
+ SYSTEM_SLEEP_ALL = 4\r
+};\r
+\r
+/* Bitmask for Power Reset Status Register */\r
+#define PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK (1UL<<2)\r
+#define PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK (1UL<<3)\r
+#define PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK (1UL<<5)\r
+#define PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK (1UL<<6)\r
+#define PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK (1UL<<7)\r
+#define PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK (1UL<<10)\r
+#define PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)\r
+#define PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK (1UL<<12)\r
+\r
+/* Bitmask for Processor Clock Control Register */\r
+#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)\r
+\r
+/* Bitmask for Power Reset Control Register */\r
+#define PCR_PWR_RESET_CTRL_PWR_INV_BITMASK (1UL<<0)\r
+#define PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK (1UL<<8)\r
+\r
+/* Bitmask for OScillator ID register */\r
+#define PCR_OSCILLATOR_ID_FOUNDARY_BITMASK (3UL<<5)\r
+#define PCR_OSCILLATOR_ID_REVISION_BITMASK (0xFUL)\r
+\r
+#define PCR_OSCILLATOR_ID_FOUNDARY_CHART_TSMC (0UL)\r
+#define PCR_OSCILLATOR_ID_FOUNDARY_TSMC (0x10u)\r
+#define PCR_OSCILLATOR_ID_FOUNDARY_CHART (0x20u)\r
+#define PCR_OSCILLATOR_ID_FOUNDARY_GRACE (0x30u)\r
+\r
+/* Bitmask for PKE Clock register */\r
+#define PCR_PKE_CLOCK_REG_PKE_CLK_BITMASK (1UL<<1)\r
+#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_BITMASK (1UL<<0)\r
+\r
+#define PCR_PKE_CLOCK_REG_PKE_CLK_48MHZ (1UL<<1)\r
+#define PCR_PKE_CLOCK_REG_PKE_CLK_96MHZ (0UL<<0)\r
+#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_EN (1UL<<0)\r
+#define PCR_PKE_CLOCK_REG_AUTO_SWITCH_DIS (0UL<<0)\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to program Sleep Enable, CLK Reqd Status, *\r
+ * Reset Enable for a block *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Sets or Clears block specific bit in PCR Sleep Enable Register\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
+ */\r
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
+\r
+/** Get Clock Required Status for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @return uint8_t - 1 if Clock Required Status set, else 0\r
+ */\r
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);\r
+\r
+/** Sets or Clears Reset Enable register bit for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
+ */\r
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for entering low power modes */\r
+/* ---------------------------------------------------------------------- */\r
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
+void pcr_all_blocks_sleep(void);\r
+\r
+/** Clears the Sleep Enable bits for all blocks */\r
+void pcr_all_blocks_wake(void);\r
+\r
+/** Programs required sleep mode in System Sleep Control Register\r
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
+ */\r
+void pcr_system_sleep(uint8_t sleep_mode);\r
+\r
+/** Reads the value of Power Reset status register\r
+ * @param none\r
+ * @return Power Status Reg value\r
+ */\r
+uint16_t pcr_power_reset_status_read(void);\r
+\r
+/** Reads the value of Power Reset control register\r
+ * @param none\r
+ * @return Power reset control Reg value\r
+ */\r
+uint16_t pcr_power_reset_ctrl_read(void);\r
+\r
+/** Sets the value of PWR_INV bit to 1 or 0\r
+* @param set_clr: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);\r
+\r
+/** Sets the value of HOST_RESET bit to 1 or 0\r
+* @param set_clr: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);\r
+\r
+/** Sets the SOFT SYS RESET bit to 1\r
+* @param none\r
+ * @return none\r
+ */\r
+void pcr_system_reset_set(void);\r
+\r
+/** Writes to the PKE Clock register\r
+* @param clock value\r
+ * @return none\r
+ */\r
+void pcr_pke_clock_write(uint8_t pke_clk_val);\r
+\r
+/** Reads the PKE clock register\r
+* @param none\r
+ * @return clock value\r
+ */\r
+uint8_t pcr_pke_clock_read(void);\r
+\r
+/** Writes to the OSC cal register\r
+* @param calibration value: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_osc_cal_write(uint8_t pke_clk_val);\r
+\r
+/** Reads the osc cal register\r
+* @param none\r
+ * @return cal value\r
+ */\r
+uint8_t pcr_osc_cal_read(void);\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to program and read 32-bit values *\r
+ * from PCR Registers *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Write 32-bit value in the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param value - 32-bit value\r
+ */\r
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);\r
+\r
+/** Reads 32-bit value from the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to set, clr and get bits in *\r
+ * PCR Registers * \r
+ * ---------------------------------------------------------------------- */\r
+ /** Sets bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set \r
+ */\r
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Clears bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to clear \r
+ */\r
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Read bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to read \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Sets or Clears bits in a PCR Register - Helper Function\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set or clear\r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
+ */\r
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);\r
+ \r
+//Functions to operate on System Sleep Control Register \r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to operate on System Sleep Control *\r
+ * Register * \r
+ * ---------------------------------------------------------------------- */\r
+/** Writes required sleep mode in System Sleep Control Register\r
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
+ */\r
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);\r
+\r
+/** Reads the System Sleep Control PCR Register\r
+ * @return value - byte 0 of the system sleep control PCR register\r
+ */\r
+uint8_t p_pcr_system_sleep_ctrl_read(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program to CLK Divide Value * \r
+ * ---------------------------------------------------------------------- */\r
+ /** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program the Slow Clock Control *\r
+ * Register *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Write the slow clock divide value in the Slow Clock Control Register\r
+ * @param slow_clk_divide_value - slow clk divide value\r
+ */\r
+void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to read the Oscillator Lock Status */ \r
+/* ---------------------------------------------------------------------- */\r
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
+ * @return 1 if Oscillator Lock Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_oscillator_lock_sts_get(void);\r
+\r
+/** Reads the Oscillator ID Register\r
+ * @return oscillator ID value\r
+ */\r
+uint16_t p_pcr_oscillator_id_reg_read(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to read various power status in *\r
+ * Power Reset register *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Reads the VCC Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VCC Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vcc_reset_sts_get(void);\r
+\r
+/** Reads the Host Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if Host Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_host_reset_sts_get(void);\r
+\r
+/** Reads the VBAT Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VBAT Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void);\r
+\r
+/** Clears the VBAT Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_vbat_reset_sts_clr(void);\r
+\r
+/** Reads the VTR Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VCC1 Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void);\r
+\r
+/** Clears the VTR Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_chip_subsystem_vtr_reset_sts_clr(void);\r
+\r
+/** Reads the 32K_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if 32_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_32K_active_sts_get(void);\r
+\r
+/** Reads the PCICLK_ACTIVE status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if CICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void);\r
+\r
+/** Reads the ESPICLK_ACTIVE status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if ESPICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void);\r
+\r
+/** Reads the Power status reg\r
+ * @return Power Status Reg value\r
+ */\r
+uint16_t p_pcr_pwr_reset_sts_get(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions for Power Reset Control Register */ \r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Power Reset Control Register\r
+ * @return Power Reset Control Register value\r
+ */\r
+uint16_t p_pcr_pwr_reset_ctrl_read(void);\r
+\r
+/** Set the PWR_INV bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr);\r
+\r
+/** Set the HOST RESET SELECT bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions for System Reset Register */ \r
+/* ---------------------------------------------------------------------- */\r
+/** Set the SOFT_SYS_RESET bit in the System Reset Register\r
+ * @param none\r
+ * @return none\r
+ */\r
+void p_pcr_system_reset_set(void);\r
+\r
+\r
+/** Set the value in PKE CLOCK Register\r
+ * @param PKE Clock value \r
+ * @return none\r
+ */\r
+void p_pcr_pke_clock_write(uint8_t pke_clk_val);\r
+\r
+/** Read the value in PKE CLOCK Register\r
+ * @none \r
+ * @return PKE Clock value \r
+ */\r
+uint8_t p_pcr_pke_clock_read(void);\r
+\r
+/** Set the value in Oscillator calibration Register\r
+ * @param Oscillator calibration value \r
+ * @return none\r
+ */\r
+void p_pcr_osc_cal_write(uint8_t osc_cal_val);\r
+\r
+/** Read the value in Osc cal Register\r
+ * @none \r
+ * @return Osc cal value \r
+ */\r
+uint8_t p_pcr_osc_cal_read(void);\r
+\r
+#endif // #ifndef _PCR_H\r
+/* end pcr.h */\r
+/** @}\r
+ */\r
+\r
+\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr_api.c\r
+* \brief Power, Clocks, and Resets API Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the PCR APIs \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "pcr.h"\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Sets or Clears block specific bit in PCR Sleep Enable Register\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
+ */\r
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);\r
+\r
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
+}\r
+\r
+\r
+/** Get Clock Required Status for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @return uint8_t - 1 if Clock Required Status set, else 0\r
+ */\r
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id, retVal; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);\r
+\r
+ retVal = 0;\r
+ if (p_pcr_reg_get(pcr_reg_id, bit_mask))\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+}\r
+\r
+/** Sets or Clears Reset Enable register bit for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
+ */\r
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);\r
+\r
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
+}\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Functions for entering low power modes */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
+void pcr_all_blocks_sleep(void)\r
+{\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0xFFFFFFFF); \r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0xFFFFFFFF); \r
+}\r
+\r
+/** Clears the Sleep Enable bits for all blocks */\r
+ void pcr_all_blocks_wake(void)\r
+{\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_0, 0);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_1, 0);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_3, 0); \r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_4, 0); \r
+}\r
+\r
+/** Programs required sleep mode in System Sleep Control Register\r
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
+ */\r
+void pcr_system_sleep(uint8_t sleep_mode)\r
+{\r
+ p_pcr_system_sleep_ctrl_write(sleep_mode);\r
+}\r
+\r
+/** Reads the value of Power Reset status register\r
+ * @param none\r
+ * @return Power Reset Status Reg value\r
+ */\r
+uint16_t pcr_power_reset_status_read(void)\r
+{\r
+ return (p_pcr_pwr_reset_sts_get());\r
+}\r
+\r
+/** Reads the value of Power Reset control register\r
+ * @param none\r
+ * @return Power reset control Reg value\r
+ */\r
+uint16_t pcr_power_reset_ctrl_read(void)\r
+{\r
+ return (p_pcr_pwr_reset_ctrl_read());\r
+}\r
+\r
+/** Sets the value of PWR_INV bit to 1 or 0\r
+* @param set_clr: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)\r
+{\r
+ p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(set_clr);\r
+}\r
+\r
+/** Sets the value of HOST_RESET bit to 1 or 0\r
+* @param set_clr: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)\r
+{\r
+ p_pcr_pwr_reset_ctrl_host_rst_set_clr(set_clr);\r
+}\r
+\r
+/** Sets the SOFT SYS RESET bit to 1\r
+* @param none\r
+ * @return none\r
+ */\r
+void pcr_system_reset_set()\r
+{\r
+ p_pcr_system_reset_set();\r
+}\r
+\r
+/** Writes to the PKE Clock register\r
+* @param clock value\r
+ * @return none\r
+ */\r
+void pcr_pke_clock_write(uint8_t pke_clk_val)\r
+{\r
+ p_pcr_pke_clock_write(pke_clk_val);\r
+}\r
+\r
+/** Reads the PKE clock register\r
+* @param none\r
+ * @return clock value\r
+ */\r
+uint8_t pcr_pke_clock_read()\r
+{\r
+ return (p_pcr_pke_clock_read());\r
+}\r
+\r
+/** Writes to the OSC cal register\r
+* @param calibration value: 1 or 0\r
+ * @return none\r
+ */\r
+void pcr_osc_cal_write(uint8_t pke_clk_val)\r
+{\r
+ p_pcr_osc_cal_write(pke_clk_val);\r
+}\r
+\r
+/** Reads the osc cal register\r
+* @param none\r
+ * @return cal value\r
+ */\r
+uint8_t pcr_osc_cal_read()\r
+{\r
+ return (p_pcr_osc_cal_read());\r
+}\r
+\r
+\r
+/* end pcr_api.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2016/09/22 08:03:49 $ \r
+$Author: pramans $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr_perphl.c\r
+* \brief Power, Clocks, and Resets Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the PCR Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "pcr.h"\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Generic functions to program and read 32-bit values from PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+/** Writes 32-bit value in the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param value - 32-bit value\r
+ */\r
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg = value; \r
+}\r
+\r
+/** Reads 32-bit value from the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = *pPCR_Reg;\r
+\r
+ return retVal;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to set, clr and get bits in PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set \r
+ */\r
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg |= bit_mask; \r
+}\r
+\r
+/** Clears bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to clear \r
+ */\r
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg &= ~bit_mask; \r
+}\r
+\r
+/** Read bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to read \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = (*pPCR_Reg) & bit_mask;\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Sets or Clears bits in a PCR Register - Helper Function\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set or clear\r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
+ */\r
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)\r
+{\r
+ if (set_clr_flag)\r
+ {\r
+ p_pcr_reg_set(pcr_reg_id, bit_mask);\r
+ }\r
+ else\r
+ {\r
+ p_pcr_reg_clr(pcr_reg_id, bit_mask);\r
+ } \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to operate on System Sleep Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+\r
+/** Writes required sleep mode in System Sleep Control Register\r
+ * @param sleep_value - System Sleep control value (Heavy/Light/Sleep All)\r
+ */\r
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ \r
+ /* Check for valid value */\r
+ if ((sleep_value == SYSTEM_LIGHT_SLEEP) || \r
+ (sleep_value == SYSTEM_LIGHT_SLEEP) ||\r
+ (sleep_value == SYSTEM_LIGHT_SLEEP))\r
+ { \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ *pPCR_Reg = (sleep_value & 0x7); \r
+ }\r
+}\r
+\r
+/** Reads the System Sleep Control PCR Register\r
+ * @return value - byte 0 of the system sleep control PCR register\r
+ */\r
+uint8_t p_pcr_system_sleep_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ retVal = (uint8_t)((*pPCR_Reg) & 0xFF);\r
+\r
+ return retVal;\r
+}\r
+\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program to CLK Divide Value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ /* Check for valid value */\r
+ if (((clk_divide_value >= PCR_CPU_CLK_DIVIDE_1) && \r
+ (clk_divide_value <= PCR_CPU_CLK_DIVIDE_4)) ||\r
+ (clk_divide_value == PCR_CPU_CLK_DIVIDE_16) ||\r
+ (clk_divide_value == PCR_CPU_CLK_DIVIDE_48))\r
+ { \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (clk_divide_value & 0xFF);\r
+ }\r
+ \r
+}\r
+\r
+/** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param none\r
+ * @ return value - clk divide value, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+uint8_t p_pcr_processor_clk_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
+\r
+ retVal = ((uint8_t)((*pPCR_Reg) & 0xFF));\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program the slow clock divide value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Write the slow clock divide value in the Slow Clock Control Register\r
+ * @param slow_clk_divide_value - slow clk divide value\r
+ */\r
+void p_pcr_slow_clk_ctrl_write(uint16_t slow_clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (slow_clk_divide_value & 0x3FF); \r
+\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to read the Oscillator Lock Status */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
+ * @return 1 if Oscillator Lock Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_oscillator_lock_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+\r
+/** Reads the Oscillator ID Register\r
+ * @return oscillator ID value\r
+ */\r
+uint16_t p_pcr_oscillator_id_reg_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
+\r
+ retVal = ((uint16_t)((*pPCR_Reg) & 0x1FFu));\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to read various power status in Power Reset register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the VCC PWRGD Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VCC PWRGD Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vcc_pwrdg_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VCC_PWRGD_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the Host Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if Host Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_host_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_HOST_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the VBAT Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VBAT Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vbat_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VBAT Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_vbat_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_VBAT_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the VTR Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if VTR Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_vtr_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VTR Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_vtr_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_VTR_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the JTAG Reset Status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if JTAG Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_jtag_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the JTAG Reset Status bit \r
+ * in the Power Reset Status Register \r
+ */\r
+void p_pcr_pwr_reset_jtag_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg |= PCR_PWR_RESET_STS_JTAG_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the 32K_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if 32_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_32K_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_32K_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the PCICLK_ACTIVE status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if PCICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_pciclk_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_PCICLK_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ } \r
+ return retVal; \r
+}\r
+\r
+/** Reads the ESPI status bit \r
+ * in the Power Reset Status Register\r
+ * @return 1 if ESPICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_pwr_reset_espiclk_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_PWR_RESET_STS_ESPICLK_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ } \r
+ return retVal; \r
+}\r
+\r
+/** Reads the Power status reg\r
+ * @return Power Status Reg value\r
+ */\r
+uint16_t p_pcr_pwr_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_STS; \r
+\r
+ retVal = (uint16_t)((*pPCR_Reg) & 0xFFF);\r
+ \r
+ return (retVal); \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Power Reset Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Power Reset Control Register\r
+ * @return Power Reset Control Register value\r
+ */\r
+uint16_t p_pcr_pwr_reset_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint16_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ retVal = (uint16_t)((*pPCR_Reg) & 0x1FFUL); \r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Set the PWR_INV bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_pwr_inv_set_clr(uint8_t set_clr)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ if (set_clr)\r
+ {\r
+ *pPCR_Reg |= (PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);\r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_PWR_INV_BITMASK);\r
+ }\r
+}\r
+\r
+/** Set the HOST RESET SELECT bit in the Power Reset Control Register\r
+ * @param set_clr value 1 or 0\r
+ * @return none\r
+ */\r
+void p_pcr_pwr_reset_ctrl_host_rst_set_clr(uint8_t set_clr)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ if (set_clr)\r
+ {\r
+ *pPCR_Reg |= (PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); \r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~(PCR_PWR_RESET_CTRL_HOST_RST_SELECT_BITMASK); \r
+ }\r
+}\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for System Reset Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the SOFT_SYS_RESET bit in the System Reset Register\r
+ * @param none\r
+ * @return none\r
+ */\r
+void p_pcr_system_reset_set()\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_RESET; \r
+\r
+ *pPCR_Reg |= (1<<8); \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for PKE Clock Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the value in PKE CLOCK Register\r
+ * @param PKE Clock value \r
+ * @return none\r
+ */\r
+void p_pcr_pke_clock_write(uint8_t pke_clk_val)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; \r
+\r
+ *pPCR_Reg = pke_clk_val;\r
+}\r
+\r
+/** Read the value in PKE CLOCK Register\r
+ * @none \r
+ * @return PKE Clock value \r
+ */\r
+uint8_t p_pcr_pke_clock_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST0; \r
+\r
+ return ((uint8_t)(*pPCR_Reg & 0xFF));\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Oscillator calibration Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Set the value in Oscillator calibration Register\r
+ * @param Oscillator calibration value \r
+ * @return none\r
+ */\r
+void p_pcr_osc_cal_write(uint8_t osc_cal_val)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; \r
+\r
+ *pPCR_Reg = osc_cal_val;\r
+}\r
+\r
+/** Read the value in Osc cal Register\r
+ * @none \r
+ * @return Osc cal value \r
+ */\r
+uint8_t p_pcr_osc_cal_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_TEST1; \r
+\r
+ return ((uint8_t)(*pPCR_Reg & 0xFF));\r
+}\r
+\r
+/* end pcr_perphl.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup pwm pwm_c_wrapper\r
+ * @{\r
+ */\r
+/** @file pwm_c_wrapper.cpp\r
+ \brief the pwm component C wrapper \r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/platform.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2016/09/22 08:03:49 $\r
+ * AUTHOR: $Author: pramans $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+#ifndef _PLATFORM_H_\r
+#define _PLATFORM_H_\r
+#include <stdint.h>\r
+\r
+/* Enable any one of the below flag which enables either Aggregated or Disaggregated Interrupts */\r
+#define DISAGGREGATED_INPT_DEFINED 1\r
+//#define AGGREGATED_INPT_DEFINED 1\r
+\r
+/* Platform Configuration PreProcessor Conditions */\r
+#define TOOLKEIL 1\r
+#define TOOLPC 2\r
+#define TOOLMW 3\r
+#define TOOLMDK 4\r
+\r
+#define PCLINT 9 //added to satisfy PC Lint's need for a value here\r
+\r
+#ifdef __CC_ARM // Keil ARM MDK\r
+#define TOOLSET TOOLMDK\r
+#endif\r
+\r
+#if 0\r
+#ifdef _WIN32 //always defined by visual c++\r
+#define TOOLSET TOOLPC\r
+#endif\r
+\r
+#ifdef __WIN32__ //always defined by borland\r
+#define TOOLSET TOOLPC\r
+#endif\r
+#endif\r
+\r
+\r
+#ifdef _ARC\r
+#define TOOLSET TOOLMW // ARC Metaware\r
+#endif\r
+\r
+#ifndef TOOLSET\r
+//#error "ERROR: cfg.h TOOLSET not defined!"\r
+#endif\r
+\r
+#if TOOLSET == TOOLMDK\r
+#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */\r
+#define _KEIL_ 0 /* Make 1 for Keil Compiler */\r
+#define _PC_ 0 \r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLKEIL\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 1 /* Make 1 for Keil Compiler */\r
+#define _PC_ 0 \r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLPC\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 0 \r
+#define _PC_ 1 /* Make 1 for PC Environment */\r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLMW\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 0\r
+#define _PC_ 0\r
+#define _ARC_CORE_ 1\r
+#endif\r
+\r
+/* Short form for Standard Data Types */\r
+typedef unsigned char UINT8;\r
+typedef unsigned short UINT16;\r
+typedef unsigned long UINT32;\r
+\r
+typedef volatile unsigned char REG8;\r
+\r
+typedef unsigned char BYTE;\r
+typedef unsigned short WORD;\r
+typedef unsigned long DWORD;\r
+\r
+typedef unsigned char UCHAR;\r
+typedef unsigned short USHORT;\r
+typedef unsigned long ULONG;\r
+\r
+typedef unsigned char BOOL;\r
+typedef unsigned int UINT;\r
+\r
+/* signed types */\r
+typedef signed char INT8;\r
+typedef signed short INT16;\r
+typedef signed long INT32;\r
+\r
+typedef void VOID;\r
+\r
+typedef volatile unsigned char VUINT8;\r
+typedef volatile unsigned short int VUINT16;\r
+typedef volatile unsigned long int VUINT32;\r
+/* union types */\r
+typedef union _BITS_8\r
+{\r
+ UINT8 byte;\r
+ struct\r
+ {\r
+ UINT8 bit0: 1;\r
+ UINT8 bit1: 1;\r
+ UINT8 bit2: 1;\r
+ UINT8 bit3: 1;\r
+ UINT8 bit4: 1;\r
+ UINT8 bit5: 1;\r
+ UINT8 bit6: 1;\r
+ UINT8 bit7: 1;\r
+ }bit;\r
+}BITS_8;\r
+\r
+\r
+/* MACROS FOR Platform Portability */\r
+\r
+/* macro for defining MMCR register */\r
+/* add MMCRARRAY() & EXTERNMMCRARRAY() */\r
+#if _KEIL_\r
+#define MMCR(name,address) volatile unsigned char xdata name _at_ address\r
+#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address\r
+#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address\r
+#define EXTERNMMCR(name) extern volatile unsigned char xdata name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name\r
+#define SFR(name,address) sfr name = address\r
+#define SFRBIT(name,address) sbit name = address\r
+#define EXTERNSFR(name) \r
+#define BITADDRESSTYPE(name) bit name\r
+#define XDATA xdata\r
+#define CODE code\r
+#define DATA data\r
+#define IDATA idata\r
+#define INTERRUPT(x) interrupt x\r
+#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
+#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
+#define NULLPTR (char *)(0)\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() \r
+#define DISABLE_INTERRUPTS() sfrIE_EAbit=0\r
+#define ENABLE_INTERRUPTS() sfrIE_EAbit=1\r
+#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; }\r
+#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; }\r
+#define ATOMIC_CPU_SLEEP()\r
+#define NUM_IRQ_VECTORS 12 // DW-8051\r
+#define IRQ_VECTOR_SIZE 8 \r
+#define USE_INLINE_PATCHER 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start\r
+#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start\r
+#define FUNC_NEVER_RETURNS\r
+#define BEGIN_SMALL_DATA_BLOCK(x)\r
+#define END_SMALL_DATA_BLOCK()\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _PC_\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name\r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name\r
+#define SFRBIT(name,address) volatile unsigned char name\r
+#define EXTERNSFR(name) extern volatile unsigned char name\r
+#define BITADDRESSTYPE(name) volatile unsigned char name\r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
+#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
+#define NULLPTR (char *)(0)\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() \r
+#define DISABLE_INTERRUPTS() \r
+#define ENABLE_INTERRUPTS()\r
+#define SAVE_DIS_INTERRUPTS(x) \r
+#define RESTORE_INTERRUPTS(x) \r
+#define ATOMIC_CPU_SLEEP()\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define FUNC_NEVER_RETURNS\r
+#define BEGIN_SMALL_DATA_BLOCK(x)\r
+#define END_SMALL_DATA_BLOCK()\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _ARC_CORE_\r
+// ARC C has no equivalent operator to specify address of a variable\r
+// ARC MMCR's are 32-bit registers\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name \r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name \r
+#define SFRBIT(name,address) volatile unsigned char name \r
+#define EXTERNSFR(name) extern volatile unsigned char name \r
+#define BITADDRESSTYPE(name) \r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (_enable())\r
+#define CLR_GLOBAL_INTR_ENABLE() (_disable())\r
+#define NULLPTR (char *)(0)\r
+#define NULLVOIDPTR (void *)(0)\r
+#define NULLFPTR (void (*)(void))0\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() _nop()\r
+#define DISABLE_INTERRUPTS() _disable()\r
+#define ENABLE_INTERRUPTS() _enable()\r
+#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
+#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
+#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop();\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 0\r
+#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
+#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
+/// y #define IRQ_VECTABLE_IN_RAM 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
+#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
+#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
+#define NORM(x) _norm(x)\r
+\r
+#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
+\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _KEIL_ARM_\r
+// For ARM MDK compiler\r
+// ARM MMCR's are 32-bit registers\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name \r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name \r
+#define SFRBIT(name,address) volatile unsigned char name \r
+#define EXTERNSFR(name) extern volatile unsigned char name \r
+#define BITADDRESSTYPE(name) \r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (__enable_irq())\r
+#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq())\r
+#define NULLPTR (char *)(0)\r
+#define NULLVOIDPTR (void *)(0)\r
+#define NULLFPTR (void (*)(void))0\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() __NOP()\r
+#define DISABLE_INTERRUPTS() __disable_irq()\r
+#define ENABLE_INTERRUPTS() __enable_irq()\r
+#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop();\r
+\r
+#if 0 /* need further efforts if needed */\r
+#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
+#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 0\r
+#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
+#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
+/// y #define IRQ_VECTABLE_IN_RAM 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
+#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
+#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if 0\r
+#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
+#define NORM(x) _norm(x)\r
+#else\r
+/* for ARM MDK */\r
+#define FUNC_NEVER_RETURNS\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+#endif\r
+#endif\r
+\r
+/* General Constants */\r
+#define FALSE 0x00\r
+#define TRUE !FALSE\r
+\r
+#define BIT_n_MASK(n) (1U << (n))\r
+#define BIT_0_MASK (1<<0)\r
+#define BIT_1_MASK (1<<1)\r
+#define BIT_2_MASK (1<<2)\r
+#define BIT_3_MASK (1<<3)\r
+#define BIT_4_MASK (1<<4)\r
+#define BIT_5_MASK (1<<5)\r
+#define BIT_6_MASK (1<<6)\r
+#define BIT_7_MASK (1<<7)\r
+#define BIT_8_MASK ((UINT16)1<<8)\r
+#define BIT_9_MASK ((UINT16)1<<9)\r
+#define BIT_10_MASK ((UINT16)1<<10)\r
+#define BIT_11_MASK ((UINT16)1<<11)\r
+#define BIT_12_MASK ((UINT16)1<<12)\r
+#define BIT_13_MASK ((UINT16)1<<13)\r
+#define BIT_14_MASK ((UINT16)1<<14)\r
+#define BIT_15_MASK ((UINT16)1<<15)\r
+#define BIT_16_MASK ((UINT32)1<<16)\r
+#define BIT_17_MASK ((UINT32)1<<17)\r
+#define BIT_18_MASK ((UINT32)1<<18)\r
+#define BIT_19_MASK ((UINT32)1<<19)\r
+#define BIT_20_MASK ((UINT32)1<<20)\r
+#define BIT_21_MASK ((UINT32)1<<21)\r
+#define BIT_22_MASK ((UINT32)1<<22)\r
+#define BIT_23_MASK ((UINT32)1<<23)\r
+#define BIT_24_MASK ((UINT32)1<<24)\r
+#define BIT_25_MASK ((UINT32)1<<25)\r
+#define BIT_26_MASK ((UINT32)1<<26)\r
+#define BIT_27_MASK ((UINT32)1<<27)\r
+#define BIT_28_MASK ((UINT32)1<<28)\r
+#define BIT_29_MASK ((UINT32)1<<29)\r
+#define BIT_30_MASK ((UINT32)1<<30)\r
+#define BIT_31_MASK ((UINT32)1<<31)\r
+\r
+\r
+/* For CEC application */\r
+#define ON 1\r
+#define OFF 0\r
+\r
+#endif /*_PLATFORM_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
--- /dev/null
+[Position]\r
+Line=79\r
+Column=1\r
+[FoldedLines]\r
+Count=0\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_internal.c\r
+ * @brief CMSIS Device System Source File for\r
+ * Microchip ARMCM4F Device Series\r
+ * @version V1.09\r
+ * @date 27. August 2014\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2011 - 2014 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Device CMSIS header file \r
+ */\r
+#include "common_lib.h"\r
+#include "MCHP_device_header.h"\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks\r
+ *----------------------------------------------------------------------------*/\r
+#define __HSI ( 48000000UL)\r
+#define __XTAL ( 48000000UL) /* Oscillator frequency */\r
+\r
+/*\r
+ * Core system clock is 48MHz derived from an internal oscillator\r
+ * It may be divided down using the PCR Processor Clock Control register. \r
+ * Supported dividers are: 1, 2, 3, 4, 16, and 48.\r
+ * Power on default is 4.\r
+ */\r
+#define __SYSTEM_CLOCK (__XTAL)\r
+\r
+/* !!!! Define EC_INIT_CLK_DIV for the clock divider you \r
+ * want the ARM CM4F core to run at !!!!\r
+ */\r
+#ifndef EC_INIT_CLK_DIV\r
+#define EC_INIT_CLK_DIV (1u)\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ System Core Clock Variable\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/* System Core Clock Frequency */\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ * @note Read the EC core clock divider from the PCR block's processor \r
+ * clock control register. Actual EC core frequency is 48MHz / proc_clock_control[7:0].\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t cpu_clk_div;\r
+ \r
+ SystemCoreClock = __SYSTEM_CLOCK;\r
+ cpu_clk_div = PCR->PROC_CLK_CNTRL;\r
+ if (cpu_clk_div) {\r
+ SystemCoreClock = __SYSTEM_CLOCK / cpu_clk_div;\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System.\r
+ * @note SystemInit is usually called from early startup code before \r
+ * C/C++ library initialization. It is used for early hardware initialization \r
+ * such as clocks, FPU, debug hardware, etc.\r
+ */\r
+void SystemInit (void)\r
+{\r
+ #if (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+ #endif\r
+\r
+#ifdef UNALIGNED_SUPPORT_DISABLE\r
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\r
+#endif\r
+\r
+ /* Program device PCR Processor Clock Control divider to set the EC core clock */\r
+ PCR->PROC_CLK_CNTRL = (EC_INIT_CLK_DIV);\r
+ SystemCoreClock = ( __SYSTEM_CLOCK / (EC_INIT_CLK_DIV) );\r
+ \r
+}\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_internal.h\r
+ * @brief CMSIS Device System Header File for\r
+ * Microchip ARMCM4F Device Series\r
+ * @version V1.08\r
+ * @date 23. November 2012\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2011 - 2012 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef SYSTEM_INTERNAL_H\r
+#define SYSTEM_INTERNAL_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * @brief Updates the SystemCoreClock with current core Clock\r
+ * retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+#define PCR MEC2016_PCR\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SYSTEM_INTERNAL_H */\r
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