2 /****************************************************************************************************//**
\r
3 * @file MCHP_device_header.h
\r
5 * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
\r
6 * MCHP_device_header from Microchip Technology Inc..
\r
9 * @date 5. November 2015
\r
11 * @note Generated with SVDConv V2.87e
\r
12 * from CMSIS SVD File 'MCHP_device_header.svd' Version 1.0,
\r
14 * @par ARM Limited (ARM) is supplying this software for use with Cortex-M
\r
15 * processor based microcontroller, but can be equally used for other
\r
16 * suitable processor architectures. This file can be freely distributed.
\r
17 * Modifications to this file shall be clearly marked.
\r
19 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
20 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
22 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
23 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
25 *******************************************************************************************************/
\r
29 /** @addtogroup Microchip Technology Inc.
\r
33 /** @addtogroup MCHP_device_header
\r
37 #ifndef MCHP_DEVICE_HEADER_H
\r
38 #define MCHP_DEVICE_HEADER_H
\r
45 /* ------------------------- Interrupt Number Definition ------------------------ */
\r
48 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
\r
49 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
\r
50 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
\r
51 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
\r
52 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
\r
54 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
\r
56 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
\r
57 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
\r
58 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
\r
59 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
\r
60 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
\r
61 /* ----------------Device Specific Interrupt Numbers---------------- */
\r
62 GPIO_140_176_IRQn = 0, /*!< 0 GPIO[140:176], GIRQ08 */
\r
63 GPIO_100_137_IRQn = 1, /*!< 1 GPIO[100:137], GIRQ09 */
\r
64 GPIO_040_076_IRQn = 2, /*!< 2 GPIO[040:076], GIRQ10 */
\r
65 GPIO_000_036_IRQn = 3, /*!< 3 GPIO[000:036], GIRQ11 */
\r
66 GPIO_200_236_IRQn = 4, /*!< 4 GPIO[200:236], GIRQ12 */
\r
67 MSVW00_06_IRQn = 15, /*!< 15 MSVW[00:06]_SRC[0:3], GIRQ 24 */
\r
68 MSVW07_10_IRQn = 16, /*!< 16 MSVW[07:10]_SRC[0:3], GIRQ 25 */
\r
69 GPIO_240_257_IRQn = 17, /*!< 17 GPIO[240:257], GIRQ26 */
\r
70 SMB0_IRQn = 20, /*!< 20 SMB0, GIRQ 13.0 */
\r
71 SMB1_IRQn = 21, /*!< 21 SMB1 */
\r
72 SMB2_IRQn = 22, /*!< 22 SMB2 */
\r
73 SMB3_IRQn = 23, /*!< 23 SMB3 */
\r
74 DMA0_IRQn = 24, /*!< 24 DMA0, GIRQ14.0 */
\r
75 DMA1_IRQn = 25, /*!< 25 DMA1 */
\r
76 DMA2_IRQn = 26, /*!< 26 DMA2 */
\r
77 DMA3_IRQn = 27, /*!< 27 DMA3 */
\r
78 DMA4_IRQn = 28, /*!< 28 DMA4 */
\r
79 DMA5_IRQn = 29, /*!< 29 DMA5 */
\r
80 DMA6_IRQn = 30, /*!< 30 DMA6 */
\r
81 DMA7_IRQn = 31, /*!< 31 DMA7 */
\r
82 DMA8_IRQn = 32, /*!< 32 DMA8 */
\r
83 DMA9_IRQn = 33, /*!< 33 DMA9 */
\r
84 DMA10_IRQn = 34, /*!< 34 DMA10 */
\r
85 DMA11_IRQn = 35, /*!< 35 DMA11 */
\r
86 DMA12_IRQn = 36, /*!< 36 DMA12 */
\r
87 DMA13_IRQn = 37, /*!< 37 DMA13 */
\r
88 UART_0_IRQn = 40, /*!< 40 UART 0, GIRQ 15.0 */
\r
89 UART_1_IRQn = 41, /*!< 41 UART 1, GIRQ 15.1 */
\r
90 EMI_0_IRQn = 42, /*!< 42 EMI_0, GIRQ 15.2 */
\r
91 EMI_1_IRQn = 43, /*!< 43 EMI_1, GIRQ 15.3 */
\r
92 EMI_2_IRQn = 44, /*!< 44 EMI_2, GIRQ 15.4 */
\r
93 ACPIEC0_IBF_IRQn = 45, /*!< 45 ACPIEC[0] IBF, GIRQ 15.5 */
\r
94 ACPIEC0_OBF_IRQn = 46, /*!< 46 ACPIEC[0] OBF, GIRQ 15.6 */
\r
95 ACPIEC1_IBF_IRQn = 47, /*!< 47 ACPIEC[1] IBF, GIRQ 15.7 */
\r
96 ACPIEC1_OBF_IRQn = 48, /*!< 48 ACPIEC[1] OBF, GIRQ 15.8 */
\r
97 ACPIEC2_IBF_IRQn = 49, /*!< 49 ACPIEC[2] IBF, GIRQ 15.9 */
\r
98 ACPIEC2_OBF_IRQn = 50, /*!< 50 ACPIEC[2] OBF, GIRQ 15.10 */
\r
99 ACPIEC3_IBF_IRQn = 51, /*!< 51 ACPIEC[3] IBF, GIRQ 15.11 */
\r
100 ACPIEC3_OBF_IRQn = 52, /*!< 52 ACPIEC[3] OBF, GIRQ 15.12 */
\r
101 ACPIEC4_IBF_IRQn = 53, /*!< 53 ACPIEC[4] IBF, GIRQ 15.13 */
\r
102 ACPIEC4_OBF_IRQn = 54, /*!< 54 ACPIEC[4] OBF, GIRQ 15.14 */
\r
103 ACPIPM1_CTL_IRQn = 55, /*!< 55 ACPIPM1_CTL, GIRQ 15.10 */
\r
104 ACPIPM1_EN_IRQn = 56, /*!< 56 ACPIPM1_EN, GIRQ 15.11 */
\r
105 ACPIPM1_STS_IRQn = 57, /*!< 57 ACPIPM1_STS, GIRQ 15.12 */
\r
106 KBC8042_OBF_IRQn = 58, /*!< 58 8042EM OBF, GIRQ 15.18 */
\r
107 KBC8042_IBF_IRQn = 59, /*!< 59 8042EM IBF, GIRQ 15.19 */
\r
108 MAILBOX_IRQn = 60, /*!< 60 MAILBOX, GIRQ 15.20 */
\r
109 MAILBOX_DATA_IRQn = 61, /*!< 61 MAILBOX DATA, GIRQ 15.21 */
\r
110 PORT80_DEBUG_0_IRQn = 62, /*!< 62 PORT80_DEBUG_0, GIRQ 15.22 */
\r
111 PORT80_DEBUG_1_IRQn = 63, /*!< 63 PORT80_DEBUG_1, GIRQ 15.23 */
\r
112 ASIF_INT_IRQn = 64, /*!< 64 ASIF_INT, GIRQ 15.24 */
\r
113 PECIHOST_IRQn = 70, /*!< 70 PECIHOST, GIRQ 17.0 */
\r
114 TACH_0_IRQn = 71, /*!< 71 TACH_0, GIRQ 17.1 */
\r
115 TACH_1_IRQn = 72, /*!< 72 TACH_1, GIRQ 17.2 */
\r
116 TACH_2_IRQn = 73, /*!< 73 TACH_2, GIRQ 17.3 */
\r
117 RPM2PWM_0_FAIL_IRQn = 74, /*!< 74 RPM2PWM_0 Fail, GIRQ 17.4 */
\r
118 RPM2PWM_0_STALL_IRQn = 75, /*!< 75 RPM2PWM_0 Stall, GIRQ 17.5 */
\r
119 RPM2PWM_1_FAIL_IRQn = 76, /*!< 76 RPM2PWM_1 Fail, GIRQ 17.6 */
\r
120 RPM2PWM_1_STALL_IRQn = 77, /*!< 77 RPM2PWM_1 Stall, GIRQ 17.7 */
\r
121 ADC_SNGL_IRQn = 78, /*!< 78 ADC_SNGL, GIRQ 17.8 */
\r
122 ADC_RPT_IRQn = 79, /*!< 79 ADC_RPT, GIRQ 17.9 */
\r
123 RC_ID_0_IRQn = 80, /*!< 80 RC_ID_0, GIRQ 17.10 */
\r
124 RC_ID_1_IRQn = 81, /*!< 81 RC_ID_1, GIRQ 17.11 */
\r
125 RC_ID_2_IRQn = 82, /*!< 82 RC_ID_2, GIRQ 17.12 */
\r
126 LED_0_IRQn = 83, /*!< 83 Breathing LED 0, GIRQ 17.13 */
\r
127 LED_1_IRQn = 84, /*!< 84 Breathing LED 1, GIRQ 17.14 */
\r
128 LED_2_IRQn = 85, /*!< 85 Breathing LED 2, GIRQ 17.15 */
\r
129 LED_3_IRQn = 86, /*!< 86 Breathing LED 3, GIRQ 17.16 */
\r
130 PROCHOT_MON_IRQn = 87, /*!< 87 PROCHOT_MON, GIRQ 17.17 */
\r
131 POWERGUARD_0_IRQn = 88, /*!< 88 POWERGUARD_0, GIRQ 17.18 */
\r
132 POWERGUARD_1_IRQn = 89, /*!< 89 POWERGUARD_1, GIRQ 17.19 */
\r
133 LPC_IRQn = 90, /*!< 90 LPC (GIRQ 18.0) */
\r
134 QMSPI_IRQn = 91, /*!< 91 QMSPI, GIRQ 18.1 */
\r
135 SPI0_TX_IRQn = 92, /*!< 92 SPI0 TX, GIRQ 18.2 */
\r
136 SPI0_RX_IRQn = 93, /*!< 93 SPI0 RX, GIRQ 18.3 */
\r
137 SPI1_TX_IRQn = 94, /*!< 94 SPI1 TX, GIRQ 18.4 */
\r
138 SPI1_RX_IRQn = 95, /*!< 95 SPI1 RX, GIRQ 18.5 */
\r
139 BCM_BUSY_CLR_0_IRQn = 96, /*!< 96 BCM_BUSY_CLR_0, GIRQ 18.6 */
\r
140 BCM_ERR_0_IRQn = 97, /*!< 97 BCM_ERR_0, GIRQ 18.7 */
\r
141 BCM_BUSY_CLR_1_IRQn = 98, /*!< 98 BCM_BUSY_CLR_1, GIRQ 18.8 */
\r
142 BCM_ERR_1_IRQn = 99, /*!< 99 BCM_ERR_1, GIRQ 18.9 */
\r
143 PS2_0_ACT_IRQn = 100, /*!< 100 PS2 Controller 0 Activity, GIRQ 17.14 */
\r
144 PS2_1_ACT_IRQn = 101, /*!< 101 PS2 Controller 1 Activity, GIRQ 17.15 */
\r
145 PS2_2_ACT_IRQn = 102, /*!< 102 PS2 Controller 2 Activity, GIRQ 17.16 */
\r
146 INTR_PC_IRQn = 103, /*!< 103 PC, GIRQ 19.0 */
\r
147 INTR_BM1_IRQn = 104, /*!< 104 BM1, GIRQ 19.1 */
\r
148 INTR_BM2_IRQn = 105, /*!< 105 BM2, GIRQ 19.2 */
\r
149 INTR_LTR_IRQn = 106, /*!< 106 LTR, GIRQ 19.3 */
\r
150 INTR_OOB_UP_IRQn = 107, /*!< 107 OOB_UP, GIRQ 19.4 */
\r
151 INTR_OOB_DOWN_IRQn = 108, /*!< 108 OOB_DOWN, GIRQ 19.5 */
\r
152 INTR_FLASH_IRQn = 109, /*!< 109 FLASH, GIRQ 19.6 */
\r
153 ESPI_RESET_IRQn = 110, /*!< 110 ESPI_RESET, GIRQ 19.7 */
\r
154 RTOS_TIMER_IRQn = 111, /*!< 111 RTOS_TIMER, GIRQ 21.0 */
\r
155 HTIMER0_IRQn = 112, /*!< 112 HTIMER0, GIRQ 21.1 */
\r
156 HTIMER1_IRQn = 113, /*!< 113 HTIMER1, GIRQ 21.2 */
\r
157 WEEK_ALARM_IRQn = 114, /*!< 114 WEEK_ALARM_INT, GIRQ 21.3 */
\r
158 SUB_WEEK_ALARM_IRQn = 115, /*!< 115 SUB_WEEK_ALARM_INT, GIRQ 21.4 */
\r
159 ONE_SECOND_IRQn = 116, /*!< 116 ONE_SECOND, GIRQ 21.5 */
\r
160 SUB_SECOND_IRQn = 117, /*!< 117 SUB_SECOND, GIRQ 21.6 */
\r
161 SYSPWR_PRES_IRQn = 118, /*!< 118 SYSPWR_PRES, GIRQ 21.7 */
\r
162 RTC_IRQn = 119, /*!< 119 RTC, GIRQ 21.8 */
\r
163 RTC_ALARM_IRQn = 120, /*!< 120 RTC ALARM, GIRQ 21.9 */
\r
164 VCI_OVRD_IN_IRQn = 121, /*!< 121 VCI_OVRD_IN, GIRQ 21.10 */
\r
165 VCI_IN0_IRQn = 122, /*!< 122 VCI_IN0, GIRQ 21.11 */
\r
166 VCI_IN1_IRQn = 123, /*!< 123 VCI_IN1, GIRQ 21.12 */
\r
167 VCI_IN2_IRQn = 124, /*!< 124 VCI_IN2, GIRQ 21.13 */
\r
168 VCI_IN3_IRQn = 125, /*!< 125 VCI_IN3, GIRQ 21.14 */
\r
169 VCI_IN4_IRQn = 126, /*!< 126 VCI_IN4, GIRQ 21.15 */
\r
170 VCI_IN5_IRQn = 127, /*!< 127 VCI_IN5, GIRQ 21.16 */
\r
171 VCI_IN6_IRQn = 128, /*!< 128 VCI_IN6, GIRQ 21.17 */
\r
172 PS2_0A_WK_IRQn = 129, /*!< 129 PS2 Controller 0 Port A Wake, GIRQ 21.18 */
\r
173 PS2_0B_WK_IRQn = 130, /*!< 130 PS2 Controller 0 Port B Wake, GIRQ 21.19 */
\r
174 PS2_1A_WK_IRQn = 131, /*!< 131 PS2 Controller 1 Port A Wake, GIRQ 21.20 */
\r
175 PS2_1B_WK_IRQn = 132, /*!< 132 PS2 Controller 1 Port B Wake, GIRQ 21.21 */
\r
176 PS2_2_WK_IRQn = 133, /*!< 133 PS2 Controller 2 Wake, GIRQ 21.22 */
\r
177 KSC_INT_IRQn = 135, /*!< 135 KSC, GIRQ 21.25 */
\r
178 TIMER0_IRQn = 136, /*!< 136 TIMER_16_0, GIRQ 23.0 */
\r
179 TIMER1_IRQn = 137, /*!< 137 TIMER_16_1, GIRQ 23.1 */
\r
180 TIMER2_IRQn = 138, /*!< 138 TIMER_16_2, GIRQ 23.2 */
\r
181 TIMER3_IRQn = 139, /*!< 139 TIMER_16_3, GIRQ 23.3 */
\r
182 TIMER4_IRQn = 140, /*!< 140 TIMER_32_0, GIRQ 23.4 */
\r
183 TIMER5_IRQn = 141, /*!< 141 TIMER_32_1, GIRQ 23.5 */
\r
184 COUNTER_TIMER_0_IRQn = 142, /*!< 142 COUNTER_TIMER_0, GIRQ 23.6 */
\r
185 COUNTER_TIMER_1_IRQn = 143, /*!< 143 COUNTER_TIMER_1, GIRQ 23.7 */
\r
186 COUNTER_TIMER_2_IRQn = 144, /*!< 144 COUNTER_TIMER_2, GIRQ 23.8 */
\r
187 COUNTER_TIMER_3_IRQn = 145, /*!< 145 COUNTER_TIMER_3, GIRQ 23.9 */
\r
188 CAPTURE_TIMER_IRQn = 146, /*!< 146 CAPTURE_TIMER, GIRQ 23.10 */
\r
189 CAPTURE_0_IRQn = 147, /*!< 147 CAPTURE_0, GIRQ 23.11 */
\r
190 CAPTURE_1_IRQn = 148, /*!< 148 CAPTURE_1, GIRQ 23.12 */
\r
191 CAPTURE_2_IRQn = 149, /*!< 149 CAPTURE_2, GIRQ 23.13 */
\r
192 CAPTURE_3_IRQn = 150, /*!< 150 CAPTURE_3, GIRQ 23.14 */
\r
193 CAPTURE_4_IRQn = 151, /*!< 151 CAPTURE_4, GIRQ 23.15 */
\r
194 CAPTURE_5_IRQn = 152, /*!< 152 CAPTURE_5, GIRQ 23.16 */
\r
195 COMPARE_0_IRQn = 153, /*!< 153 COMPARE_0, GIRQ 23.17 */
\r
196 COMPARE_1_IRQn = 154, /*!< 154 COMPARE_1, GIRQ 23.18 */
\r
197 EEPROM_IRQn = 155, /*!< 155 EEPROM, GIRQ 18.13 */
\r
198 VWIRE_ENABLE_IRQn = 156, /*!< 156 VWIRE_ENABLE, GIRQ 19.8 */
\r
203 /** @addtogroup Configuration_of_CMSIS
\r
208 /* ================================================================================ */
\r
209 /* ================ Processor and Core Peripheral Section ================ */
\r
210 /* ================================================================================ */
\r
212 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
\r
213 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
\r
214 #define __MPU_PRESENT 1 /*!< MPU present or not */
\r
215 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
\r
216 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
217 #define __FPU_PRESENT 1 /*!< FPU present or not */
\r
218 /** @} */ /* End of group Configuration_of_CMSIS */
\r
220 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
\r
222 /* ================================================================================ */
\r
223 /* ================ Custom Defines (added manually) ================ */
\r
224 /* ================================================================================ */
\r
226 /* Register Union */
\r
234 /* ================================================================================ */
\r
235 /* ================ Device Specific Peripheral Section ================ */
\r
236 /* ================================================================================ */
\r
239 /** @addtogroup Device_Peripheral_Registers
\r
244 /* ------------------- Start of section using anonymous unions ------------------ */
\r
245 #if defined(__CC_ARM)
\r
247 #pragma anon_unions
\r
248 #elif defined(__ICCARM__)
\r
249 #pragma language=extended
\r
250 #elif defined(__GNUC__)
\r
251 /* anonymous unions are enabled by default */
\r
252 #elif defined(__TMS470__)
\r
253 /* anonymous unions are enabled by default */
\r
254 #elif defined(__TASKING__)
\r
255 #pragma warning 586
\r
257 #warning Not supported compiler type
\r
262 /* ================================================================================ */
\r
263 /* ================ PCR ================ */
\r
264 /* ================================================================================ */
\r
268 * @brief The Power, Clocks, and Resets (PCR) Section identifies all the power supplies,
\r
269 clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR)
\r
272 typedef struct { /*!< (@ 0x40080100) PCR Structure */
\r
275 __IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control */
\r
278 __IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode */
\r
280 __IO uint32_t TEST : 1; /*!< [2..2] Test bit */
\r
281 __IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode */
\r
282 } SYS_SLP_CNTRL_b; /*!< [4] BitSize */
\r
286 __IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Register [7:0] Processor
\r
287 Clock Divide Value (PROC_DIV)
\r
288 1: divide 48 MHz Ring Oscillator by 1.
\r
289 2: divide 48 MHz Ring Oscillator by 2.
\r
290 3: divide 48 MHz Ring Oscillator by 3.
\r
291 4: divide 48 MHz Ring Oscillator by 4.
\r
292 16: divide 48 MHz Ring Oscillator by 16.
\r
293 48: divide 48 MHz Ring Oscillator by 48.
\r
294 No other values are supported. */
\r
297 __IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate */
\r
298 } PROC_CLK_CNTRL_b; /*!< [8] BitSize */
\r
302 __IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock domain */
\r
305 __IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Clock off */
\r
306 } SLOW_CLK_CNTRL_b; /*!< [10] BitSize */
\r
310 __IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register */
\r
313 __IO uint32_t TEST : 8; /*!< [0..7] Test bits */
\r
314 __IO uint32_t PLL_LOCK : 1; /*!< [8..8] PLL Lock Status */
\r
315 } OSC_ID_b; /*!< [9] BitSize */
\r
319 __IO uint32_t PCR_PWR_RST_STS; /*!< (@ 0x40080110) PCR Power Reset Status Register */
\r
323 __I uint32_t VCC_PWRGD_STATUS: 1; /*!< [2..2] Indicates the status of VCC_PWRGD. 0 = PWRGD not asserted.
\r
324 1 = PWRGD asserte. */
\r
325 __I uint32_t RESET_HOST_STATUS: 1; /*!< [3..3] Indicates the status of RESET_VCC. 0 = reset active.
\r
326 1 = reset not active. */
\r
328 __IO uint32_t VBAT_RESET_STATUS: 1; /*!< [5..5] VBAT reset status 0 = No reset occurred while VTR was
\r
329 off or since the last time this bit was cleared. 1 = A reset
\r
331 __IO uint32_t VTR_RESET_STATUS: 1; /*!< [6..6] Indicates the status of VTR_RESET.(R/WC)
\r
332 0 = No reset occurred since the last time this bit was cleared.
\r
333 1 = A reset occurred. */
\r
334 __IO uint32_t JTAG_RESET_STATUS: 1; /*!< [7..7] Indicates s RESET_SYS was triggered by a JTAG action.(R/WC)
\r
335 0 = No JTAG reset occurred since the last time this bit was
\r
337 1 = A reset occurred because of a JATAG command. */
\r
339 __I uint32_t _32K_ACTIVE: 1; /*!< [10..10] 32K_ACTIVE (32K_ACTIVE) */
\r
340 __I uint32_t PCICLK_ACTIVE: 1; /*!< [11..11] PCICLK_ACTIVE (PCICLK_ACTIVE) */
\r
341 __I uint32_t ESPI_CLK_ACTIVE: 1; /*!< [12..12] ESPI_CLK_ACTIVE */
\r
342 } PCR_PWR_RST_STS_b; /*!< [13] BitSize */
\r
346 __IO uint32_t PWR_RST_CNTRL; /*!< (@ 0x40080114) Power Reset Control Register */
\r
349 __IO uint32_t PWR_INV : 1; /*!< [0..0] Used by FW to control internal RESET_VCC signal function
\r
350 and external PWROK pin. This bit is read-only when VCC_PWRGD
\r
351 is de-asserted low. */
\r
353 __IO uint32_t HOST_RESET_SELECT: 1; /*!< [8..8] Determines what generates the internal platform reset
\r
354 signal. 1=LRESET# pin; 0=eSPI PLTRST# VWire */
\r
355 } PWR_RST_CNTRL_b; /*!< [9] BitSize */
\r
359 __IO uint32_t SYS_RST; /*!< (@ 0x40080118) System Reset Register */
\r
363 __IO uint32_t SOFT_SYS_RESET: 1; /*!< [8..8] A write of a 1 forces an assertion of the RESET_SYS reset
\r
364 signal, resetting the device. A write of 0 has no effect. */
\r
365 } SYS_RST_b; /*!< [9] BitSize */
\r
367 __I uint32_t RESERVED[5];
\r
370 __IO uint32_t SLP_EN_0; /*!< (@ 0x40080130) Sleep Enable 0 Register */
\r
373 __IO uint32_t JTAG_STAP_SLP_EN: 1; /*!< [0..0] JTAG STAP Enable */
\r
374 __IO uint32_t EFUSE_SLP_EN: 1; /*!< [1..1] eFuse Enable */
\r
375 __IO uint32_t ISPI_SLP_EN: 1; /*!< [2..2] ISPI Enable */
\r
376 } SLP_EN_0_b; /*!< [3] BitSize */
\r
380 __IO uint32_t SLP_EN_1; /*!< (@ 0x40080134) Sleep Enable 1 Register */
\r
383 __IO uint32_t INT_SLP_EN : 1; /*!< [0..0] Interrupt Sleep Enable */
\r
384 __IO uint32_t PECI_SLP_EN: 1; /*!< [1..1] PECI Sleep Enable */
\r
385 __IO uint32_t TACH0_SLP_EN: 1; /*!< [2..2] TACH0 Sleep Enable (TACH0_SLP_EN) */
\r
387 __IO uint32_t PWM0_SLP_EN: 1; /*!< [4..4] PWM0 Sleep Enable (PWM0_SLP_EN) */
\r
388 __IO uint32_t PMC_SLP_EN : 1; /*!< [5..5] PMC Sleep Enable (PMC_SLP_EN) */
\r
389 __IO uint32_t DMA_SLP_EN : 1; /*!< [6..6] DMA Sleep Enable (DMA_SLP_EN) */
\r
390 __IO uint32_t TFDP_SLP_EN: 1; /*!< [7..7] TFDP Sleep Enable (TFDP_SLP_EN) */
\r
391 __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< [8..8] PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */
\r
392 __IO uint32_t WDT_SLP_EN : 1; /*!< [9..9] WDT Sleep Enable (WDT_SLP_EN) */
\r
393 __IO uint32_t SMB0_SLP_EN: 1; /*!< [10..10] SMB0 Sleep Enable (SMB0_SLP_EN) */
\r
394 __IO uint32_t TACH1_SLP_EN: 1; /*!< [11..11] TACH1 Sleep Enable (TACH1_SLP_EN) */
\r
395 __IO uint32_t TACH2_SLP_EN: 1; /*!< [12..12] TACH2 Sleep Enable (TACH2_SLP_EN) */
\r
397 __IO uint32_t PWM1_SLP_EN: 1; /*!< [20..20] PWM1 Sleep Enable (PWM1_SLP_EN) */
\r
398 __IO uint32_t PWM2_SLP_EN: 1; /*!< [21..21] PWM2 Sleep Enable (PWM2_SLP_EN) */
\r
399 __IO uint32_t PWM3_SLP_EN: 1; /*!< [22..22] PWM3 Sleep Enable (PWM3_SLP_EN) */
\r
400 __IO uint32_t PWM4_SLP_EN: 1; /*!< [23..23] PWM4 Sleep Enable (PWM4_SLP_EN) */
\r
401 __IO uint32_t PWM5_SLP_EN: 1; /*!< [24..24] PWM3 Sleep Enable (PWM5_SLP_EN) */
\r
402 __IO uint32_t PWM6_SLP_EN: 1; /*!< [25..25] PWM3 Sleep Enable (PWM6_SLP_EN) */
\r
403 __IO uint32_t PWM7_SLP_EN: 1; /*!< [26..26] PWM3 Sleep Enable (PWM7_SLP_EN) */
\r
404 __IO uint32_t PWM8_SLP_EN: 1; /*!< [27..27] PWM3 Sleep Enable (PWM8_SLP_EN) */
\r
406 __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< [29..29] EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */
\r
407 __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< [30..30] TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */
\r
408 __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< [31..31] TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */
\r
409 } SLP_EN_1_b; /*!< [32] BitSize */
\r
413 __IO uint32_t SLP_EN_2; /*!< (@ 0x40080138) Sleep Enable 2 Register */
\r
416 __IO uint32_t LPC_SLP_EN : 1; /*!< [0..0] LPC Sleep Enable (LPC_SLP_EN) */
\r
417 __IO uint32_t UART_0_SLP_EN: 1; /*!< [1..1] UART 0 Sleep Enable */
\r
418 __IO uint32_t UART_1_SLP_EN: 1; /*!< [2..2] UART 1 Sleep Enable */
\r
420 __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_SLP_EN) */
\r
421 __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< [13..13] ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */
\r
422 __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< [14..14] ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */
\r
423 __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< [15..15] ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */
\r
424 __IO uint32_t KBCEM_SLP_EN: 1; /*!< [16..16] 8042EM Sleep Enable (8042EM_SLP_EN) */
\r
425 __IO uint32_t MBX_SLP_EN : 1; /*!< [17..17] Mailbox Sleep Enable (8042EM_SLP_EN) */
\r
426 __IO uint32_t RTC_SLP_EN : 1; /*!< [18..18] RTC Sleep Enable (RTC_SLP_EN) */
\r
427 __IO uint32_t ESPI_SLP_EN: 1; /*!< [19..19] eSPI Sleep Enable */
\r
429 __IO uint32_t ACPI_EC_2_SLP_EN: 1; /*!< [21..21] ACPI EC 2 Sleep Enable (ACPI_EC_2_SLP_EN) */
\r
430 __IO uint32_t ACPI_EC_3_SLP_EN: 1; /*!< [22..22] ACPI EC 3 Sleep Enable (ACPI_EC_3_SLP_EN) */
\r
431 __IO uint32_t ACPI_EC_4_SLP_EN: 1; /*!< [23..23] ACPI EC 4 Sleep Enable (ACPI_EC_4_SLP_EN) */
\r
432 __IO uint32_t ASIF_SLP_EN: 1; /*!< [24..24] ASIF Sleep Enable */
\r
433 __IO uint32_t PORT80_0_SLP_EN: 1; /*!< [25..25] Port 80 0 Sleep Enable */
\r
434 __IO uint32_t PORT80_1_SLP_EN: 1; /*!< [26..26] Port 80 1 Sleep Enable */
\r
435 } SLP_EN_2_b; /*!< [27] BitSize */
\r
439 __IO uint32_t SLP_EN_3; /*!< (@ 0x4008013C) Sleep Enable 3 Register */
\r
443 __IO uint32_t ADC_SLP_EN : 1; /*!< [3..3] ADC Sleep Enable (ADC_SLP_EN) */
\r
445 __IO uint32_t PS2_0_SLP_EN: 1; /*!< [5..5] PS2_0 Sleep Enable (PS2_0_SLP_EN) */
\r
446 __IO uint32_t PS2_1_SLP_EN: 1; /*!< [6..6] PS2_1 Sleep Enable (PS2_1_SLP_EN) */
\r
447 __IO uint32_t PS2_2_SLP_EN: 1; /*!< [7..7] PS2_2 Sleep Enable (PS2_2_SLP_EN) */
\r
449 __IO uint32_t GP_SPI0_SLP_EN: 1; /*!< [9..9] GP SPI0 Sleep Enable (GP_SPI0_SLP_EN) */
\r
450 __IO uint32_t HTIMER_0_SLP_EN: 1; /*!< [10..10] HTIMER 0 Sleep Enable (HTIMER_0_SLP_EN) */
\r
451 __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< [11..11] KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */
\r
452 __IO uint32_t RPMPWM_SLP_EN: 1; /*!< [12..12] RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */
\r
453 __IO uint32_t SMB1_SLP_EN: 1; /*!< [13..13] SMB1 Sleep Enable (SMB1_SLP_EN) */
\r
454 __IO uint32_t SMB2_SLP_EN: 1; /*!< [14..14] SMB2 Sleep Enable (SMB2_SLP_EN) */
\r
455 __IO uint32_t SMB3_SLP_EN: 1; /*!< [15..15] SMB3 Sleep Enable (SMB3_SLP_EN) */
\r
456 __IO uint32_t LED0_SLP_EN: 1; /*!< [16..16] LED0 Sleep Enable (LED0_SLP_EN) */
\r
457 __IO uint32_t LED1_SLP_EN: 1; /*!< [17..17] LED1 Sleep Enable (LED1_SLP_EN) */
\r
458 __IO uint32_t LED2_SLP_EN: 1; /*!< [18..18] LED2 Sleep Enable (LED2_SLP_EN) */
\r
459 __IO uint32_t BCM0_SLP_EN: 1; /*!< [19..19] BCM 0 Sleep Enable (BCM0_SLP_EN) */
\r
460 __IO uint32_t GP_SPI1_SLP_EN: 1; /*!< [20..20] GP SPI1 Sleep Enable (GP_SPI1_SLP_EN) */
\r
461 __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< [21..21] TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */
\r
462 __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< [22..22] TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */
\r
463 __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< [23..23] TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */
\r
464 __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< [24..24] TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */
\r
465 __IO uint32_t LED3_SLP_EN: 1; /*!< [25..25] LED3 Sleep Enable (LED3_SLP_EN) */
\r
466 __IO uint32_t PKE_SLP_EN : 1; /*!< [26..26] PKE Sleep Enable */
\r
467 __IO uint32_t RNG_SLP_EN : 1; /*!< [27..27] RNG Sleep Enable */
\r
468 __IO uint32_t AES_HASH_SLP_EN: 1; /*!< [28..28] AES_HASH Sleep Enable */
\r
469 __IO uint32_t HTIMER_1_SLP_EN: 1; /*!< [29..29] HTIMER 1 Sleep Enable (HTIMER_1_SLP_EN) */
\r
470 __IO uint32_t CCTIMER_SLP_EN: 1; /*!< [30..30] Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)
\r
472 __IO uint32_t PWM9_SLP_EN: 1; /*!< [31..31] PWM9 Sleep Enable (PWM9_SLP_EN) */
\r
473 } SLP_EN_3_b; /*!< [32] BitSize */
\r
477 __IO uint32_t SLP_EN_4; /*!< (@ 0x40080140) Sleep Enable 4 Register */
\r
480 __IO uint32_t PWM10_SLP_EN: 1; /*!< [0..0] PWM10 Sleep Enable (PWM10_SLP_EN) */
\r
481 __IO uint32_t PWM11_SLP_EN: 1; /*!< [1..1] PWM11 Sleep Enable (PWM11_SLP_EN) */
\r
482 __IO uint32_t CNT_TMER0_SLP_EN: 1; /*!< [2..2] CNT_TMER0 Sleep Enable (CNT_TMER0_SLP_EN) */
\r
483 __IO uint32_t CNT_TMER1_SLP_EN: 1; /*!< [3..3] CNT_TMER1 Sleep Enable (CNT_TMER1_SLP_EN) */
\r
484 __IO uint32_t CNT_TMER2_SLP_EN: 1; /*!< [4..4] CNT_TMER2 Sleep Enable (CNT_TMER2_SLP_EN) */
\r
485 __IO uint32_t CNT_TMER3_SLP_EN: 1; /*!< [5..5] CNT_TMER3 Sleep Enable (CNT_TMER3_SLP_EN) */
\r
486 __IO uint32_t RTOS_SLP_EN: 1; /*!< [6..6] PWM6 Sleep Enable (RTOS_SLP_EN) */
\r
487 __IO uint32_t RPMPWM1_SLP_EN: 1; /*!< [7..7] RPMPWM 1 Sleep Enable (RPMPWM1_SLP_EN) */
\r
488 __IO uint32_t QSPI_SLP_EN: 1; /*!< [8..8] Quad SPI Sleep Enable */
\r
489 __IO uint32_t BCM1_SLP_EN: 1; /*!< [9..9] BCM 1 Sleep Enable (BCM1_SLP_EN) */
\r
490 __IO uint32_t RC_ID0_SLP_EN: 1; /*!< [10..10] RC_ID0 Sleep Enable (RC_ID0_SLP_EN) */
\r
491 __IO uint32_t RC_ID1_SLP_EN: 1; /*!< [11..11] RC_ID1 Sleep Enable (RC_ID1_SLP_EN) */
\r
492 __IO uint32_t RC_ID2_SLP_EN: 1; /*!< [12..12] RC_ID2 Sleep Enable (RC_ID2_SLP_EN) */
\r
494 __IO uint32_t FCL_SLP_EN : 1; /*!< [15..15] FCL Sleep Enable (FCL_SLP_EN) */
\r
495 } SLP_EN_4_b; /*!< [16] BitSize */
\r
497 __I uint32_t RESERVED1[3];
\r
500 __IO uint32_t CLK_REQ_0; /*!< (@ 0x40080150) Clock Required 0 Register */
\r
503 __IO uint32_t JTAG_STAP_CLK_REQ: 1; /*!< [0..0] JTAG STAP Enable */
\r
504 __IO uint32_t EFUSE_CLK_REQ: 1; /*!< [1..1] eFuse Enable */
\r
505 __IO uint32_t ISPI_CLK_REQ: 1; /*!< [2..2] ISPI Clock Required */
\r
506 } CLK_REQ_0_b; /*!< [3] BitSize */
\r
510 __IO uint32_t CLK_REQ_1; /*!< (@ 0x40080154) Clock Required 1 Register */
\r
513 __IO uint32_t INT_CLK_REQ: 1; /*!< [0..0] Interrupt Clock Required */
\r
514 __IO uint32_t PECI_CLK_REQ: 1; /*!< [1..1] PECI Clock Required */
\r
515 __IO uint32_t TACH0_CLK_REQ: 1; /*!< [2..2] TACH0 Clock Required (TACH0_CLK_REQ) */
\r
517 __IO uint32_t PWM0_CLK_REQ: 1; /*!< [4..4] PWM0 Clock Required (PWM0_CLK_REQ) */
\r
518 __IO uint32_t PMC_CLK_REQ: 1; /*!< [5..5] PMC Clock Required (PMC_CLK_REQ) */
\r
519 __IO uint32_t DMA_CLK_REQ: 1; /*!< [6..6] DMA Clock Required (DMA_CLK_REQ) */
\r
520 __IO uint32_t TFDP_CLK_REQ: 1; /*!< [7..7] TFDP Clock Required (TFDP_CLK_REQ) */
\r
521 __IO uint32_t PROCESSOR_CLK_REQ: 1; /*!< [8..8] PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */
\r
522 __IO uint32_t WDT_CLK_REQ: 1; /*!< [9..9] WDT Clock Required (WDT_CLK_REQ) */
\r
523 __IO uint32_t SMB0_CLK_REQ: 1; /*!< [10..10] SMB0 Clock Required (SMB0_CLK_REQ) */
\r
524 __IO uint32_t TACH1_CLK_REQ: 1; /*!< [11..11] TACH1 Clock Required (TACH1_CLK_REQ) */
\r
525 __IO uint32_t TACH2_CLK_REQ: 1; /*!< [12..12] TACH2 Clock Required (TACH2_CLK_REQ) */
\r
527 __IO uint32_t PWM1_CLK_REQ: 1; /*!< [20..20] PWM1 Clock Required (PWM1_CLK_REQ) */
\r
528 __IO uint32_t PWM2_CLK_REQ: 1; /*!< [21..21] PWM2 Clock Required (PWM2_CLK_REQ) */
\r
529 __IO uint32_t PWM3_CLK_REQ: 1; /*!< [22..22] PWM3 Clock Required (PWM3_CLK_REQ) */
\r
530 __IO uint32_t PWM4_CLK_REQ: 1; /*!< [23..23] PWM4 Clock Required (PWM4_CLK_REQ) */
\r
531 __IO uint32_t PWM5_CLK_REQ: 1; /*!< [24..24] PWM3 Clock Required (PWM5_CLK_REQ) */
\r
532 __IO uint32_t PWM6_CLK_REQ: 1; /*!< [25..25] PWM3 Clock Required (PWM6_CLK_REQ) */
\r
533 __IO uint32_t PWM7_CLK_REQ: 1; /*!< [26..26] PWM3 Clock Required (PWM7_CLK_REQ) */
\r
534 __IO uint32_t PWM8_CLK_REQ: 1; /*!< [27..27] PWM3 Clock Required (PWM8_CLK_REQ) */
\r
536 __IO uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< [29..29] EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */
\r
537 __IO uint32_t TIMER16_0_CLK_REQ: 1; /*!< [30..30] TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */
\r
538 __IO uint32_t TIMER16_1_CLK_REQ: 1; /*!< [31..31] TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */
\r
539 } CLK_REQ_1_b; /*!< [32] BitSize */
\r
543 __IO uint32_t CLK_REQ_2; /*!< (@ 0x40080158) Clock Required 2 Register */
\r
546 __IO uint32_t LPC_CLK_REQ: 1; /*!< [0..0] LPC Clock Required (LPC_CLK_REQ) */
\r
547 __IO uint32_t UART_0_CLK_REQ: 1; /*!< [1..1] UART 0 Clock Required */
\r
548 __IO uint32_t UART_1_CLK_REQ: 1; /*!< [2..2] UART 1 Clock Required */
\r
550 __IO uint32_t GLBL_CFG_CLK_REQ: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_CLK_REQ) */
\r
551 __IO uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< [13..13] ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */
\r
552 __IO uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< [14..14] ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */
\r
553 __IO uint32_t ACPI_PM1_CLK_REQ: 1; /*!< [15..15] ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */
\r
554 __IO uint32_t KBCEM_CLK_REQ: 1; /*!< [16..16] 8042EM Clock Required (8042EM_CLK_REQ) */
\r
555 __IO uint32_t MBX_CLK_REQ: 1; /*!< [17..17] Mailbox Clock Required (8042EM_CLK_REQ) */
\r
556 __IO uint32_t RTC_CLK_REQ: 1; /*!< [18..18] RTC Clock Required (RTC_CLK_REQ) */
\r
557 __IO uint32_t ESPI_CLK_REQ: 1; /*!< [19..19] eSPI Clock Required */
\r
559 __IO uint32_t ACPI_EC_2_CLK_REQ: 1; /*!< [21..21] ACPI EC 2 Clock Required (ACPI_EC_2_CLK_REQ) */
\r
560 __IO uint32_t ACPI_EC_3_CLK_REQ: 1; /*!< [22..22] ACPI EC 3 Clock Required (ACPI_EC_3_CLK_REQ) */
\r
561 __IO uint32_t ACPI_EC_4_CLK_REQ: 1; /*!< [23..23] ACPI EC 4 Clock Required (ACPI_EC_4_CLK_REQ) */
\r
562 __IO uint32_t ASIF_CLK_REQ: 1; /*!< [24..24] ASIF Clock Required */
\r
563 __IO uint32_t PORT80_0_CLK_REQ: 1; /*!< [25..25] Port 80 0 Clock Required */
\r
564 __IO uint32_t PORT80_1_CLK_REQ: 1; /*!< [26..26] Port 80 1 Clock Required */
\r
565 } CLK_REQ_2_b; /*!< [27] BitSize */
\r
569 __IO uint32_t CLK_REQ_3; /*!< (@ 0x4008015C) Clock Required 3 Register */
\r
573 __IO uint32_t ADC_CLK_REQ: 1; /*!< [3..3] ADC Clock Required (ADC_CLK_REQ) */
\r
575 __IO uint32_t PS2_0_CLK_REQ: 1; /*!< [5..5] PS2_0 Clock Required (PS2_0_CLK_REQ) */
\r
576 __IO uint32_t PS2_1_CLK_REQ: 1; /*!< [6..6] PS2_1 Clock Required (PS2_1_CLK_REQ) */
\r
577 __IO uint32_t PS2_2_CLK_REQ: 1; /*!< [7..7] PS2_2 Clock Required (PS2_2_CLK_REQ) */
\r
579 __IO uint32_t GP_SPI0_CLK_REQ: 1; /*!< [9..9] GP SPI0 Clock Required (GP_SPI0_CLK_REQ) */
\r
580 __IO uint32_t HTIMER_0_CLK_REQ: 1; /*!< [10..10] HTIMER 0 Clock Required (HTIMER_0_CLK_REQ) */
\r
581 __IO uint32_t KEYSCAN_CLK_REQ: 1; /*!< [11..11] KEYSCAN Clock Required (KEYSCAN_CLK_REQ) */
\r
582 __IO uint32_t RPMPWM0_CLK_REQ: 1; /*!< [12..12] RPM-PWM 0 Clock Required (RPMPWM0_CLK_REQ) */
\r
583 __IO uint32_t SMB1_CLK_REQ: 1; /*!< [13..13] SMB1 Clock Required (SMB1_CLK_REQ) */
\r
584 __IO uint32_t SMB2_CLK_REQ: 1; /*!< [14..14] SMB2 Clock Required (SMB2_CLK_REQ) */
\r
585 __IO uint32_t SMB3_CLK_REQ: 1; /*!< [15..15] SMB3 Clock Required (SMB3_CLK_REQ) */
\r
586 __IO uint32_t LED0_CLK_REQ: 1; /*!< [16..16] LED0 Clock Required (LED0_CLK_REQ) */
\r
587 __IO uint32_t LED1_CLK_REQ: 1; /*!< [17..17] LED1 Clock Required (LED1_CLK_REQ) */
\r
588 __IO uint32_t LED2_CLK_REQ: 1; /*!< [18..18] LED2 Clock Required (LED2_CLK_REQ) */
\r
589 __IO uint32_t BCM0_CLK_REQ: 1; /*!< [19..19] BCM 0 Clock Required (BCM0_CLK_REQ) */
\r
590 __IO uint32_t GP_SPI1_CLK_REQ: 1; /*!< [20..20] GP SPI1 Clock Required (GP_SPI1_CLK_REQ) */
\r
591 __IO uint32_t TIMER16_2_CLK_REQ: 1; /*!< [21..21] TIMER16_2_Clock Required (TIMER16_2_CLK_REQ) */
\r
592 __IO uint32_t TIMER16_3_CLK_REQ: 1; /*!< [22..22] TIMER16_3 Clock Required (TIMER16_3_CLK_REQ) */
\r
593 __IO uint32_t TIMER32_0_CLK_REQ: 1; /*!< [23..23] TIMER32_0 Clock Required (TIMER32_0_CLK_REQ) */
\r
594 __IO uint32_t TIMER32_1_CLK_REQ: 1; /*!< [24..24] TIMER32_1 Clock Required (TIMER32_1_CLK_REQ) */
\r
595 __IO uint32_t LED3_CLK_REQ: 1; /*!< [25..25] LED3 Clock Required (LED3_CLK_REQ) */
\r
596 __IO uint32_t PKE_CLK_REQ: 1; /*!< [26..26] PKE Clock Required */
\r
597 __IO uint32_t RNG_CLK_REQ: 1; /*!< [27..27] RNG Clock Required */
\r
598 __IO uint32_t AES_HASH_CLK_REQ: 1; /*!< [28..28] AES_HASH Clock Required */
\r
599 __IO uint32_t HTIMER_1_CLK_REQ: 1; /*!< [29..29] HTIMER 1 Clock Required (HTIMER_1_CLK_REQ) */
\r
600 __IO uint32_t CCTIMER_CLK_REQ: 1; /*!< [30..30] Capture Compare Timer Clock Required (CCTIMER_CLK_REQ)
\r
602 __IO uint32_t PWM9_CLK_REQ: 1; /*!< [31..31] PWM9 Clock Required (PWM9_CLK_REQ) */
\r
603 } CLK_REQ_3_b; /*!< [32] BitSize */
\r
607 __IO uint32_t CLK_REQ_4; /*!< (@ 0x40080160) Clock Required 4 Register */
\r
610 __IO uint32_t PWM10_CLK_REQ: 1; /*!< [0..0] PWM10 Clock Required (PWM10_CLK_REQ) */
\r
611 __IO uint32_t PWM11_CLK_REQ: 1; /*!< [1..1] PWM11 Clock Required (PWM11_CLK_REQ) */
\r
612 __IO uint32_t CNT_TMER0_CLK_REQ: 1; /*!< [2..2] CNT_TMER0 Clock Required (CNT_TMER0_CLK_REQ) */
\r
613 __IO uint32_t CNT_TMER1_CLK_REQ: 1; /*!< [3..3] CNT_TMER1 Clock Required (CNT_TMER1_CLK_REQ) */
\r
614 __IO uint32_t CNT_TMER2_CLK_REQ: 1; /*!< [4..4] CNT_TMER2 Clock Required (CNT_TMER2_CLK_REQ) */
\r
615 __IO uint32_t CNT_TMER3_CLK_REQ: 1; /*!< [5..5] CNT_TMER3 Clock Required (CNT_TMER3_CLK_REQ) */
\r
616 __IO uint32_t RTOS_CLK_REQ: 1; /*!< [6..6] RTOS Clock Required (RTOS_CLK_REQ) */
\r
617 __IO uint32_t RPMPWM1_CLK_REQ: 1; /*!< [7..7] RPM-PWM1 Clock Required (RPMPWM1_CLK_REQ) */
\r
618 __IO uint32_t QSPI_CLK_REQ: 1; /*!< [8..8] Quad SPI Clock Required */
\r
619 __IO uint32_t BCM1_CLK_REQ: 1; /*!< [9..9] BCM 1 Clock Required (BCM1_CLK_REQ) */
\r
620 __IO uint32_t RC_ID0_CLK_REQ: 1; /*!< [10..10] RC_ID0 Clock Required (RC_ID0_CLK_REQ) */
\r
621 __IO uint32_t RC_ID1_CLK_REQ: 1; /*!< [11..11] RC_ID1 Clock Required (RC_ID1_CLK_REQ) */
\r
622 __IO uint32_t RC_ID2_CLK_REQ: 1; /*!< [12..12] RC_ID2 Clock Required (RC_ID2_CLK_REQ) */
\r
624 __IO uint32_t FCL_CLK_REQ: 1; /*!< [15..15] FCL Clock Required (FCL_CLK_REQ) */
\r
625 } CLK_REQ_4_b; /*!< [16] BitSize */
\r
627 __I uint32_t RESERVED2[3];
\r
630 __IO uint32_t RST_EN_0; /*!< (@ 0x40080170) Reset Enable 0 Register */
\r
633 __IO uint32_t JTAG_STAP_RST_EN: 1; /*!< [0..0] JTAG STAP Reset Enable */
\r
634 __IO uint32_t EFUSE_RST_EN: 1; /*!< [1..1] eFuse Reset Enable */
\r
635 __IO uint32_t ISPI_RST_EN: 1; /*!< [2..2] ISPI Reset Enable */
\r
636 } RST_EN_0_b; /*!< [3] BitSize */
\r
640 __IO uint32_t RST_EN_1; /*!< (@ 0x40080174) Reset Enable 1 Register */
\r
643 __IO uint32_t INT_RST_EN : 1; /*!< [0..0] Interrupt Reset Enable */
\r
644 __IO uint32_t PECI_RST_EN: 1; /*!< [1..1] PECI Reset Enable */
\r
645 __IO uint32_t TACH0_RST_EN: 1; /*!< [2..2] TACH0 Reset Enable (TACH0_RST_EN) */
\r
647 __IO uint32_t PWM0_RST_EN: 1; /*!< [4..4] PWM0 Reset Enable (PWM0_RST_EN) */
\r
648 __IO uint32_t PMC_RST_EN : 1; /*!< [5..5] PMC Reset Enable (PMC_RST_EN) */
\r
649 __IO uint32_t DMA_RST_EN : 1; /*!< [6..6] DMA Reset Enable (DMA_RST_EN) */
\r
650 __IO uint32_t TFDP_RST_EN: 1; /*!< [7..7] TFDP Reset Enable (TFDP_RST_EN) */
\r
651 __IO uint32_t PROCESSOR_RST_EN: 1; /*!< [8..8] PROCESSOR Reset Enable (PROCESSOR_RST_EN) */
\r
652 __IO uint32_t WDT_RST_EN : 1; /*!< [9..9] WDT Reset Enable (WDT_RST_EN) */
\r
653 __IO uint32_t SMB0_RST_EN: 1; /*!< [10..10] SMB0 Reset Enable (SMB0_RST_EN) */
\r
654 __IO uint32_t TACH1_RST_EN: 1; /*!< [11..11] TACH1 Reset Enable (TACH1_RST_EN) */
\r
655 __IO uint32_t TACH2_RST_EN: 1; /*!< [12..12] TACH2 Reset Enable (TACH2_RST_EN) */
\r
657 __IO uint32_t PWM1_RST_EN: 1; /*!< [20..20] PWM1 Reset Enable (PWM1_RST_EN) */
\r
658 __IO uint32_t PWM2_RST_EN: 1; /*!< [21..21] PWM2 Reset Enable (PWM2_RST_EN) */
\r
659 __IO uint32_t PWM3_RST_EN: 1; /*!< [22..22] PWM3 Reset Enable (PWM3_RST_EN) */
\r
660 __IO uint32_t PWM4_RST_EN: 1; /*!< [23..23] PWM4 Reset Enable (PWM4_RST_EN) */
\r
661 __IO uint32_t PWM5_RST_EN: 1; /*!< [24..24] PWM3 Reset Enable (PWM5_RST_EN) */
\r
662 __IO uint32_t PWM6_RST_EN: 1; /*!< [25..25] PWM3 Reset Enable (PWM6_RST_EN) */
\r
663 __IO uint32_t PWM7_RST_EN: 1; /*!< [26..26] PWM3 Reset Enable (PWM7_RST_EN) */
\r
664 __IO uint32_t PWM8_RST_EN: 1; /*!< [27..27] PWM3 Reset Enable (PWM8_RST_EN) */
\r
666 __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< [29..29] EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */
\r
667 __IO uint32_t TIMER16_0_RST_EN: 1; /*!< [30..30] TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */
\r
668 __IO uint32_t TIMER16_1_RST_EN: 1; /*!< [31..31] TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */
\r
669 } RST_EN_1_b; /*!< [32] BitSize */
\r
673 __IO uint32_t RST_EN_2; /*!< (@ 0x40080178) Reset Enable 2 Register */
\r
676 __IO uint32_t LPC_RST_EN : 1; /*!< [0..0] LPC Reset Enable (LPC_RST_EN) */
\r
677 __IO uint32_t UART_0_RST_EN: 1; /*!< [1..1] UART 0 Reset Enable */
\r
678 __IO uint32_t UART_1_RST_EN: 1; /*!< [2..2] UART 1 Reset Enable */
\r
680 __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_RST_EN) */
\r
681 __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< [13..13] ACPI EC 0 Reset Enable (ACPI_EC_0_RST_EN) */
\r
682 __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< [14..14] ACPI EC 1 Reset Enable (ACPI_EC_1_RST_EN) */
\r
683 __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< [15..15] ACPI PM1 Reset Enable (ACPI_PM1_RST_EN) */
\r
684 __IO uint32_t KBCEM_RST_EN: 1; /*!< [16..16] 8042EM Reset Enable (8042EM_RST_EN) */
\r
685 __IO uint32_t MBX_RST_EN : 1; /*!< [17..17] Mailbox Reset Enable (8042EM_RST_EN) */
\r
686 __IO uint32_t RTC_RST_EN : 1; /*!< [18..18] RTC Reset Enable (RTC_RST_EN) */
\r
687 __IO uint32_t ESPI_RST_EN: 1; /*!< [19..19] eSPI Reset Enable */
\r
689 __IO uint32_t ACPI_EC_2_RST_EN: 1; /*!< [21..21] ACPI EC 2 Reset Enable (ACPI_EC_2_RST_EN) */
\r
690 __IO uint32_t ACPI_EC_3_RST_EN: 1; /*!< [22..22] ACPI EC 3 Reset Enable (ACPI_EC_3_RST_EN) */
\r
691 __IO uint32_t ACPI_EC_4_RST_EN: 1; /*!< [23..23] ACPI EC 4 Reset Enable (ACPI_EC_4_RST_EN) */
\r
692 __IO uint32_t ASIF_RST_EN: 1; /*!< [24..24] ASIF Reset Enable */
\r
693 __IO uint32_t PORT80_0_RST_EN: 1; /*!< [25..25] Port 80 0 Reset Enable */
\r
694 __IO uint32_t PORT80_1_RST_EN: 1; /*!< [26..26] Port 80 1 Reset Enable */
\r
695 } RST_EN_2_b; /*!< [27] BitSize */
\r
699 __IO uint32_t RST_EN_3; /*!< (@ 0x4008017C) Reset Enable 3 Register */
\r
703 __IO uint32_t ADC_RST_EN : 1; /*!< [3..3] ADC Reset Enable (ADC_RST_EN) */
\r
705 __IO uint32_t PS2_0_RST_EN: 1; /*!< [5..5] PS2_0 Reset Enable (PS2_0_RST_EN) */
\r
706 __IO uint32_t PS2_1_RST_EN: 1; /*!< [6..6] PS2_1 Reset Enable (PS2_1_RST_EN) */
\r
707 __IO uint32_t PS2_2_RST_EN: 1; /*!< [7..7] PS2_2 Reset Enable (PS2_2_RST_EN) */
\r
709 __IO uint32_t GP_SPI0_RST_EN: 1; /*!< [9..9] GP SPI0 Reset Enable (GP_SPI0_RST_EN) */
\r
710 __IO uint32_t HTIMER_0_RST_EN: 1; /*!< [10..10] HTIMER 0 Reset Enable (HTIMER_0_RST_EN) */
\r
711 __IO uint32_t KEYSCAN_RST_EN: 1; /*!< [11..11] KEYSCAN Reset Enable (KEYSCAN_RST_EN) */
\r
712 __IO uint32_t RPMPWM0_RST_EN: 1; /*!< [12..12] RPM-PWM 0 Reset Enable (RPMPWM0_RST_EN) */
\r
713 __IO uint32_t SMB1_RST_EN: 1; /*!< [13..13] SMB1 Reset Enable (SMB1_RST_EN) */
\r
714 __IO uint32_t SMB2_RST_EN: 1; /*!< [14..14] SMB2 Reset Enable (SMB2_RST_EN) */
\r
715 __IO uint32_t SMB3_RST_EN: 1; /*!< [15..15] SMB3 Reset Enable (SMB3_RST_EN) */
\r
716 __IO uint32_t LED0_RST_EN: 1; /*!< [16..16] LED0 Reset Enable (LED0_RST_EN) */
\r
717 __IO uint32_t LED1_RST_EN: 1; /*!< [17..17] LED1 Reset Enable (LED1_RST_EN) */
\r
718 __IO uint32_t LED2_RST_EN: 1; /*!< [18..18] LED2 Reset Enable (LED2_RST_EN) */
\r
719 __IO uint32_t BCM0_RST_EN: 1; /*!< [19..19] BCM 0 Reset Enable (BCM0_RST_EN) */
\r
720 __IO uint32_t GP_SPI1_RST_EN: 1; /*!< [20..20] GP SPI1 Reset Enable (GP_SPI1_RST_EN) */
\r
721 __IO uint32_t TIMER16_2_RST_EN: 1; /*!< [21..21] TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */
\r
722 __IO uint32_t TIMER16_3_RST_EN: 1; /*!< [22..22] TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */
\r
723 __IO uint32_t TIMER32_0_RST_EN: 1; /*!< [23..23] TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */
\r
724 __IO uint32_t TIMER32_1_RST_EN: 1; /*!< [24..24] TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */
\r
725 __IO uint32_t LED3_RST_EN: 1; /*!< [25..25] LED3 Reset Enable (LED3_RST_EN) */
\r
726 __IO uint32_t PKE_RST_EN : 1; /*!< [26..26] PKE Reset Enable */
\r
727 __IO uint32_t RNG_RST_EN : 1; /*!< [27..27] RNG Reset Enable */
\r
728 __IO uint32_t AES_HASH_RST_EN: 1; /*!< [28..28] AES_HASH Reset Enable */
\r
729 __IO uint32_t HTIMER_1_RST_EN: 1; /*!< [29..29] HTIMER 1 Reset Enable (HTIMER_1_RST_EN) */
\r
730 __IO uint32_t CCTIMER_RST_EN: 1; /*!< [30..30] Capture Compare Timer Reset Enable (CCTIMER_RST_EN)
\r
732 __IO uint32_t PWM9_RST_EN: 1; /*!< [31..31] PWM9 Reset Enable (PWM9_RST_EN) */
\r
733 } RST_EN_3_b; /*!< [32] BitSize */
\r
737 __IO uint32_t RST_EN_4; /*!< (@ 0x40080180) Reset Enable 4 Register */
\r
740 __IO uint32_t PWM10_RST_EN: 1; /*!< [0..0] PWM10 Reset Enable (PWM10_RST_EN) */
\r
741 __IO uint32_t PWM11_RST_EN: 1; /*!< [1..1] PWM11 Reset Enable (PWM11_RST_EN) */
\r
742 __IO uint32_t CNT_TMER0_RST_EN: 1; /*!< [2..2] CNT_TMER0 Reset Enable (CNT_TMER0_RST_EN) */
\r
743 __IO uint32_t CNT_TMER1_RST_EN: 1; /*!< [3..3] CNT_TMER1 Reset Enable (CNT_TMER1_RST_EN) */
\r
744 __IO uint32_t CNT_TMER2_RST_EN: 1; /*!< [4..4] CNT_TMER2 Reset Enable (CNT_TMER2_RST_EN) */
\r
745 __IO uint32_t CNT_TMER3_RST_EN: 1; /*!< [5..5] CNT_TMER3 Reset Enable (CNT_TMER3_RST_EN) */
\r
746 __IO uint32_t RTOS_RST_EN: 1; /*!< [6..6] RTOS Reset Enable (RTOS_RST_EN) */
\r
747 __IO uint32_t RPMPWM1_RST_EN: 1; /*!< [7..7] RPM-PWM1 Reset Enable (RPMPWM1_RST_EN) */
\r
748 __IO uint32_t QSPI_RST_EN: 1; /*!< [8..8] Quad SPI Reset Enable */
\r
749 __IO uint32_t BCM1_RST_EN: 1; /*!< [9..9] BCM 1 Reset Enable (BCM1_RST_EN) */
\r
750 __IO uint32_t RC_ID0_RST_EN: 1; /*!< [10..10] RC_ID0 Reset Enable (RC_ID0_RST_EN) */
\r
751 __IO uint32_t RC_ID1_RST_EN: 1; /*!< [11..11] RC_ID1 Reset Enable (RC_ID1_RST_EN) */
\r
752 __IO uint32_t RC_ID2_RST_EN: 1; /*!< [12..12] RC_ID2 Reset Enable (RC_ID2_RST_EN) */
\r
754 __IO uint32_t FCL_RST_EN : 1; /*!< [15..15] FCL Reset Enable (FCL_RST_EN) */
\r
755 } RST_EN_4_b; /*!< [16] BitSize */
\r
760 /* ================================================================================ */
\r
761 /* ================ INTS ================ */
\r
762 /* ================================================================================ */
\r
766 * @brief The interrupt generation logic is made of 16 groups of signals, each of which
\r
767 consist of a Status register, a Enable register and a Result register. The Status and Enable are
\r
768 latched registers. The Result register is a bit by bit AND function of the Source and Enable registers.
\r
769 All the bits of the Result register are OR'ed together and AND'ed with the corresponding bit in the Block
\r
770 Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTS)
\r
773 typedef struct { /*!< (@ 0x4000E000) INTS Structure */
\r
774 __IO uint32_t GIRQ08_SRC; /*!< (@ 0x4000E000) Status R/W1C */
\r
775 __IO uint32_t GIRQ08_EN_SET; /*!< (@ 0x4000E004) Write to set source enables */
\r
776 __I uint32_t GIRQ08_RESULT; /*!< (@ 0x4000E008) Read-only bitwise OR of Source and Enable */
\r
777 __IO uint32_t GIRQ08_EN_CLR; /*!< (@ 0x4000E00C) Write to clear source enables */
\r
778 __I uint32_t RESERVED;
\r
779 __IO uint32_t GIRQ09_SRC; /*!< (@ 0x4000E014) Status R/W1C */
\r
780 __IO uint32_t GIRQ09_EN_SET; /*!< (@ 0x4000E018) Write to set source enables */
\r
781 __I uint32_t GIRQ09_RESULT; /*!< (@ 0x4000E01C) Read-only bitwise OR of Source and Enable */
\r
782 __IO uint32_t GIRQ09_EN_CLR; /*!< (@ 0x4000E020) Write to clear source enables */
\r
783 __I uint32_t RESERVED1;
\r
784 __IO uint32_t GIRQ10_SRC; /*!< (@ 0x4000E028) Status R/W1C */
\r
785 __IO uint32_t GIRQ10_EN_SET; /*!< (@ 0x4000E02C) Write to set source enables */
\r
786 __I uint32_t GIRQ10_RESULT; /*!< (@ 0x4000E030) Read-only bitwise OR of Source and Enable */
\r
787 __IO uint32_t GIRQ10_EN_CLR; /*!< (@ 0x4000E034) Write to clear source enables */
\r
788 __I uint32_t RESERVED2;
\r
789 __IO uint32_t GIRQ11_SRC; /*!< (@ 0x4000E03C) Status R/W1C */
\r
790 __IO uint32_t GIRQ11_EN_SET; /*!< (@ 0x4000E040) Write to set source enables */
\r
791 __I uint32_t GIRQ11_RESULT; /*!< (@ 0x4000E044) Read-only bitwise OR of Source and Enable */
\r
792 __IO uint32_t GIRQ11_EN_CLR; /*!< (@ 0x4000E048) Write to clear source enables */
\r
793 __I uint32_t RESERVED3;
\r
794 __IO uint32_t GIRQ12_SRC; /*!< (@ 0x4000E050) Status R/W1C */
\r
795 __IO uint32_t GIRQ12_EN_SET; /*!< (@ 0x4000E054) Write to set source enables */
\r
796 __I uint32_t GIRQ12_RESULT; /*!< (@ 0x4000E058) Read-only bitwise OR of Source and Enable */
\r
797 __IO uint32_t GIRQ12_EN_CLR; /*!< (@ 0x4000E05C) Write to clear source enables */
\r
798 __I uint32_t RESERVED4;
\r
799 __IO uint32_t GIRQ13_SRC; /*!< (@ 0x4000E064) Status R/W1C */
\r
800 __IO uint32_t GIRQ13_EN_SET; /*!< (@ 0x4000E068) Write to set source enables */
\r
801 __I uint32_t GIRQ13_RESULT; /*!< (@ 0x4000E06C) Read-only bitwise OR of Source and Enable */
\r
802 __IO uint32_t GIRQ13_EN_CLR; /*!< (@ 0x4000E070) Write to clear source enables */
\r
803 __I uint32_t RESERVED5;
\r
804 __IO uint32_t GIRQ14_SRC; /*!< (@ 0x4000E078) Status R/W1C */
\r
805 __IO uint32_t GIRQ14_EN_SET; /*!< (@ 0x4000E07C) Write to set source enables */
\r
806 __I uint32_t GIRQ14_RESULT; /*!< (@ 0x4000E080) Read-only bitwise OR of Source and Enable */
\r
807 __IO uint32_t GIRQ14_EN_CLR; /*!< (@ 0x4000E084) Write to clear source enables */
\r
808 __I uint32_t RESERVED6;
\r
809 __IO uint32_t GIRQ15_SRC; /*!< (@ 0x4000E08C) Status R/W1C */
\r
810 __IO uint32_t GIRQ15_EN_SET; /*!< (@ 0x4000E090) Write to set source enables */
\r
811 __I uint32_t GIRQ15_RESULT; /*!< (@ 0x4000E094) Read-only bitwise OR of Source and Enable */
\r
812 __IO uint32_t GIRQ15_EN_CLR; /*!< (@ 0x4000E098) Write to clear source enables */
\r
813 __I uint32_t RESERVED7;
\r
814 __IO uint32_t GIRQ16_SRC; /*!< (@ 0x4000E0A0) Status R/W1C */
\r
815 __IO uint32_t GIRQ16_EN_SET; /*!< (@ 0x4000E0A4) Write to set source enables */
\r
816 __I uint32_t GIRQ16_RESULT; /*!< (@ 0x4000E0A8) Read-only bitwise OR of Source and Enable */
\r
817 __IO uint32_t GIRQ16_EN_CLR; /*!< (@ 0x4000E0AC) Write to clear source enables */
\r
818 __I uint32_t RESERVED8;
\r
819 __IO uint32_t GIRQ17_SRC; /*!< (@ 0x4000E0B4) Status R/W1C */
\r
820 __IO uint32_t GIRQ17_EN_SET; /*!< (@ 0x4000E0B8) Write to set source enables */
\r
821 __I uint32_t GIRQ17_RESULT; /*!< (@ 0x4000E0BC) Read-only bitwise OR of Source and Enable */
\r
822 __IO uint32_t GIRQ17_EN_CLR; /*!< (@ 0x4000E0C0) Write to clear source enables */
\r
823 __I uint32_t RESERVED9;
\r
824 __IO uint32_t GIRQ18_SRC; /*!< (@ 0x4000E0C8) Status R/W1C */
\r
825 __IO uint32_t GIRQ18_EN_SET; /*!< (@ 0x4000E0CC) Write to set source enables */
\r
826 __I uint32_t GIRQ18_RESULT; /*!< (@ 0x4000E0D0) Read-only bitwise OR of Source and Enable */
\r
827 __IO uint32_t GIRQ18_EN_CLR; /*!< (@ 0x4000E0D4) Write to clear source enables */
\r
828 __I uint32_t RESERVED10;
\r
829 __IO uint32_t GIRQ19_SRC; /*!< (@ 0x4000E0DC) Status R/W1C */
\r
830 __IO uint32_t GIRQ19_EN_SET; /*!< (@ 0x4000E0E0) Write to set source enables */
\r
831 __I uint32_t GIRQ19_RESULT; /*!< (@ 0x4000E0E4) Read-only bitwise OR of Source and Enable */
\r
832 __IO uint32_t GIRQ19_EN_CLR; /*!< (@ 0x4000E0E8) Write to clear source enables */
\r
833 __I uint32_t RESERVED11;
\r
834 __IO uint32_t GIRQ20_SRC; /*!< (@ 0x4000E0F0) Status R/W1C */
\r
835 __IO uint32_t GIRQ20_EN_SET; /*!< (@ 0x4000E0F4) Write to set source enables */
\r
836 __I uint32_t GIRQ20_RESULT; /*!< (@ 0x4000E0F8) Read-only bitwise OR of Source and Enable */
\r
837 __IO uint32_t GIRQ20_EN_CLR; /*!< (@ 0x4000E0FC) Write to clear source enables */
\r
838 __I uint32_t RESERVED12;
\r
839 __IO uint32_t GIRQ21_SRC; /*!< (@ 0x4000E104) Status R/W1C */
\r
840 __IO uint32_t GIRQ21_EN_SET; /*!< (@ 0x4000E108) Write to set source enables */
\r
841 __I uint32_t GIRQ21_RESULT; /*!< (@ 0x4000E10C) Read-only bitwise OR of Source and Enable */
\r
842 __IO uint32_t GIRQ21_EN_CLR; /*!< (@ 0x4000E110) Write to clear source enables */
\r
843 __I uint32_t RESERVED13;
\r
844 __IO uint32_t GIRQ22_SRC; /*!< (@ 0x4000E118) Status R/W1C */
\r
845 __IO uint32_t GIRQ22_EN_SET; /*!< (@ 0x4000E11C) Write to set source enables */
\r
846 __I uint32_t GIRQ22_RESULT; /*!< (@ 0x4000E120) Read-only bitwise OR of Source and Enable */
\r
847 __IO uint32_t GIRQ22_EN_CLR; /*!< (@ 0x4000E124) Write to clear source enables */
\r
848 __I uint32_t RESERVED14;
\r
849 __IO uint32_t GIRQ23_SRC; /*!< (@ 0x4000E12C) Status R/W1C */
\r
850 __IO uint32_t GIRQ23_EN_SET; /*!< (@ 0x4000E130) Write to set source enables */
\r
851 __I uint32_t GIRQ23_RESULT; /*!< (@ 0x4000E134) Read-only bitwise OR of Source and Enable */
\r
852 __IO uint32_t GIRQ23_EN_CLR; /*!< (@ 0x4000E138) Write to clear source enables */
\r
853 __I uint32_t RESERVED15;
\r
854 __IO uint32_t GIRQ24_SRC; /*!< (@ 0x4000E140) Status R/W1C */
\r
855 __IO uint32_t GIRQ24_EN_SET; /*!< (@ 0x4000E144) Write to set source enables */
\r
856 __I uint32_t GIRQ24_RESULT; /*!< (@ 0x4000E148) Read-only bitwise OR of Source and Enable */
\r
857 __IO uint32_t GIRQ24_EN_CLR; /*!< (@ 0x4000E14C) Write to clear source enables */
\r
858 __I uint32_t RESERVED16;
\r
859 __IO uint32_t GIRQ25_SRC; /*!< (@ 0x4000E154) Status R/W1C */
\r
860 __IO uint32_t GIRQ25_EN_SET; /*!< (@ 0x4000E158) Write to set source enables */
\r
861 __I uint32_t GIRQ25_RESULT; /*!< (@ 0x4000E15C) Read-only bitwise OR of Source and Enable */
\r
862 __IO uint32_t GIRQ25_EN_CLR; /*!< (@ 0x4000E160) Write to clear source enables */
\r
863 __I uint32_t RESERVED17;
\r
864 __IO uint32_t GIRQ26_SRC; /*!< (@ 0x4000E168) Status R/W1C */
\r
865 __IO uint32_t GIRQ26_EN_SET; /*!< (@ 0x4000E16C) Write to set source enables */
\r
866 __I uint32_t GIRQ26_RESULT; /*!< (@ 0x4000E170) Read-only bitwise OR of Source and Enable */
\r
867 __IO uint32_t GIRQ26_EN_CLR; /*!< (@ 0x4000E174) Write to clear source enables */
\r
868 __I uint32_t RESERVED18[34];
\r
871 __IO uint32_t BLOCK_ENABLE_SET; /*!< (@ 0x4000E200) Block Enable Set Register */
\r
874 __IO uint32_t IRQ_VECTOR_ENABLE_SET: 31; /*!< [0..30] Each GIRQx bit can be individually enabled to assert
\r
875 an interrupt event.
\r
876 Reads always return the current value of the internal GIRQX_ENABLE
\r
877 bit. The state of the GIRQX_ENABLE bit is determined by
\r
878 the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_
\r
879 CLEAR bit. (0=disabled, 1=enabled) (R/WS)
\r
880 1=Interrupts in the GIRQx Source Register may be enabled
\r
882 } BLOCK_ENABLE_SET_b; /*!< [31] BitSize */
\r
886 __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< (@ 0x4000E204) Block Enable Clear Register. */
\r
889 __IO uint32_t IRQ_VECTOR_ENABLE_CLEAR: 31; /*!< [0..30] Each GIRQx bit can be individually disabled to inhibit
\r
890 an interrupt event.
\r
891 Reads always return the current value of the internal GIRQX_ENABLE
\r
892 bit. The state of the GIRQX_ENABLE bit is determined by
\r
893 the corresponding GIRQX_ENABLE_SET bit and the GIRQX_ENABLE_
\r
894 CLEAR bit. (0=disabled, 1=enabled) (R/WC)
\r
895 1=All interrupts in the GIRQx Source Register are disabled
\r
897 } BLOCK_ENABLE_CLEAR_b; /*!< [31] BitSize */
\r
901 __I uint32_t BLOCK_IRQ_VECTOR; /*!< (@ 0x4000E208) Block IRQ Vector Register */
\r
904 __I uint32_t IRQ_VECTOR : 25; /*!< [0..24] Each bit in this field reports the status of the group
\r
905 GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt
\r
906 is disabled as a group, by the Block Enable Clear Register,
\r
907 then the corresponding bit will be '0'b and no interrupt will
\r
909 } BLOCK_IRQ_VECTOR_b; /*!< [25] BitSize */
\r
914 /* ================================================================================ */
\r
915 /* ================ TIMER0 ================ */
\r
916 /* ================================================================================ */
\r
920 * @brief This timer block offers a simple mechanism for firmware to maintain a time base. This timer may be instantiated as 16 bits or
\r
921 32 bits. The name of the timer instance indicates the size of the timer. (TIMER0)
\r
924 typedef struct { /*!< (@ 0x40000C00) TIMER0 Structure */
\r
925 __IO uint32_t COUNT; /*!< (@ 0x40000C00) This is the value of the Timer counter. This
\r
926 is updated by Hardware but may be set by Firmware. */
\r
927 __IO uint32_t PRE_LOAD; /*!< (@ 0x40000C04) This is the value of the Timer pre-load for the
\r
928 counter. This is used by H/W when the counter is to be restarted
\r
929 automatically; this will become the new value of the counter
\r
933 __IO uint32_t STATUS; /*!< (@ 0x40000C08) This is the interrupt status that fires when
\r
934 the timer reaches its limit */
\r
937 __IO uint32_t EVENT_INTERRUPT: 1; /*!< [0..0] This is the interrupt status that fires when the timer
\r
938 reaches its limit. This is the interrupt status that fires when
\r
939 the timer reaches its limit. This may be level or a self clearing
\r
940 signal cycle pulse, based on the AUTO_RESTART bit in the Timer
\r
941 Control Register. If the timer is set to automatically restart,
\r
942 it will provide a pulse, otherwise a level is provided.(R/WC)
\r
944 } STATUS_b; /*!< [1] BitSize */
\r
948 __IO uint32_t INT_EN; /*!< (@ 0x40000C0C) This is the interrupt enable for the status EVENT_INTERRUPT
\r
949 bit in the Timer Status Register */
\r
952 __IO uint32_t ENABLE : 1; /*!< [0..0] This is the interrupt enable for the status EVENT_INTERRUPT
\r
953 bit in the Timer Status Register. */
\r
954 } INT_EN_b; /*!< [1] BitSize */
\r
958 __IO REG32_U CONTROL; /*!< (@ 0x40000C10) Timer Control Register */
\r
961 __IO uint32_t ENABLE : 1; /*!< [0..0] This enables the block for operation. 1=This block will
\r
963 0=This block will gate its clock and go into its lowest power
\r
966 __IO uint32_t COUNT_UP : 1; /*!< [2..2] This selects the counter direction. When the counter
\r
967 in incrementing the counter will saturate and trigger the event
\r
968 when it reaches all F's. When the counter is decrementing the
\r
969 counter will saturate when it reaches 0h. 1=The counter will
\r
971 0=The counter will decrement */
\r
972 __IO uint32_t AUTO_RESTART: 1; /*!< [3..3] This will select the action taken upon completing a count.
\r
973 1=The counter will automatically restart the count, using the
\r
974 contents of the Timer Preload Register to load the Timer Count
\r
976 The interrupt will be set in edge mode
\r
977 0=The counter will simply enter a done state and wait for further
\r
978 control inputs. The interrupt will be set in level mode. */
\r
979 __IO uint32_t SOFT_RESET : 1; /*!< [4..4] This is a soft reset. This is self clearing 1 cycle after
\r
981 __IO uint32_t START : 1; /*!< [5..5] This bit triggers the timer counter. The counter will
\r
982 operate until it hits its terminating condition. This will
\r
983 clear this bit. It should be noted that when operating in restart
\r
984 mode, there is no terminating condition for the counter, so
\r
985 this bit will never clear. Clearing this bit will halt the timer
\r
987 __IO uint32_t RELOAD : 1; /*!< [6..6] This bit reloads the counter without interrupting it
\r
988 operation. This will not function if the timer has already
\r
989 completed (when the START bit in this register is '0'). This
\r
990 is used to periodically prevent the timer from firing when an
\r
991 event occurs. Usage while the timer is off may result in erroneous
\r
993 __IO uint32_t HALT : 1; /*!< [7..7] This is a halt bit. This will halt the timer as long
\r
994 as it is active. Once the halt is inactive, the timer will
\r
995 start from where it left off. 1=Timer is halted. It stops counting.
\r
996 The clock divider will also be reset. 0=Timer runs normally.
\r
999 __IO uint32_t PRE_SCALE : 16; /*!< [16..31] This is used to divide down the system clock through
\r
1000 clock enables to lower the power consumption of the block and
\r
1002 slow timers. Updating this value during operation may result
\r
1003 in erroneous clock enable pulses until the clock divider restarts.
\r
1004 The number of clocks per clock enable pulse is (Value + 1);
\r
1005 a setting of 0 runs at the full clock speed, while a setting
\r
1007 runs at half speed. */
\r
1008 } CONTROL_b; /*!< [32] BitSize */
\r
1013 /* ================================================================================ */
\r
1014 /* ================ EC_REG_BANK ================ */
\r
1015 /* ================================================================================ */
\r
1019 * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK)
\r
1022 typedef struct { /*!< (@ 0x4000FC00) EC_REG_BANK Structure */
\r
1023 __I uint32_t RESERVED;
\r
1024 __IO uint32_t AHB_ERROR_ADDRESS; /*!< (@ 0x4000FC04) AHB Error Address [0:0] AHB_ERR_ADDR, In priority
\r
1026 1. AHB address is registered when an AHB error occurs on the
\r
1027 processor's AHB master port and the register value was
\r
1028 already 0. This way only the first address to generate an exception
\r
1030 2. The processor can clear this register by writing any 32-bit
\r
1031 value to this register. */
\r
1032 __I uint32_t RESERVED1[3];
\r
1033 __IO uint8_t AHB_ERROR_CONTROL; /*!< (@ 0x4000FC14) AHB Error Control [0:0] AHB_ERROR_DISABLE, 0:
\r
1034 EC memory exceptions are enabled. 1: EC memory exceptions are
\r
1036 __I uint8_t RESERVED2[3];
\r
1037 __IO uint32_t INTERRUPT_CONTROL; /*!< (@ 0x4000FC18) Interrupt Control [0:0] NVIC_EN (NVIC_EN) This
\r
1038 bit enables Alternate NVIC IRQ's Vectors. The Alternate NVIC
\r
1039 Vectors provides each interrupt event with a dedicated (direct)
\r
1041 0 = Alternate NVIC vectors disabled, 1= Alternate NVIC vectors
\r
1043 __IO uint32_t ETM_TRACE_ENABLE; /*!< (@ 0x4000FC1C) ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) This
\r
1044 bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug
\r
1045 Interface pins are forced to the TRACE functions. 0 = ARM TRACE
\r
1046 port disabled, 1= ARM TRACE port enabled */
\r
1049 __IO uint32_t DEBUG_Enable; /*!< (@ 0x4000FC20) Debug Enable Register */
\r
1052 __IO uint32_t DEBUG_EN : 1; /*!< [0..0] DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug
\r
1054 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e.,
\r
1055 the TRST# pin is ignored and the JTAG signals remain in their
\r
1057 1= JTAG/SWD port enabled. A high on TRST# enables JTAG or SWD,
\r
1058 as determined by SWD_EN. */
\r
1059 __IO uint32_t DEBUG_PIN_CFG: 2; /*!< [1..2] This field determines which pins are affected by the
\r
1060 TRST# debug enable pin.
\r
1062 2=The pins associated with the JTAG TCK and TMS switch to the
\r
1063 debug interface when TRST# is de-asserted high. The pins
\r
1064 associated with TDI and TDO remain controlled by the associated
\r
1065 GPIO. This setting should be used when the ARM Serial
\r
1066 Wire Debug (SWD) is required for debugging and the Serial Wire
\r
1067 Viewer is not required
\r
1068 1=The pins associated with the JTAG TCK, TMS and TDO switch
\r
1069 to the debug interface when TRST# i */
\r
1070 __IO uint32_t DEBUG_PU_EN: 1; /*!< [3..3] If this bit is set to '1b' internal pull-up resistors
\r
1071 are automatically enabled on the appropriate debugging port
\r
1072 wires whenever the debug port is enabled (the DEBUG_EN bit
\r
1073 in this register is '1b' and the JTAG_RST# pin is high). The
\r
1075 of DEBUG_PIN_CFG determines which pins have pull-ups enabled
\r
1076 when the debug port is enabled. */
\r
1077 } DEBUG_Enable_b; /*!< [4] BitSize */
\r
1079 __I uint32_t RESERVED3;
\r
1080 __IO uint32_t WDT_EVENT_COUNT; /*!< (@ 0x4000FC28) WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These
\r
1081 EC R/W bits are cleared to 0 on VCC1 POR, but not on a WDT.
\r
1082 Note: This field is written by Boot ROM firmware to indicate
\r
1083 the number of times a WDT fired before loading a good EC code
\r
1087 __IO uint32_t AES_HASH_BYTE_SWAP_CONTROL; /*!< (@ 0x4000FC2C) AES HASH Byte Swap Control Register. */
\r
1090 __I uint32_t INPUT_BYTE_SWAP_ENABLE: 1; /*!< [0..0] Used to enable byte swap on a DWORD during AHB read from
\r
1091 AES / HASH block: 1=Enable; 0=Disable. */
\r
1092 __IO uint32_t OUTPUT_BYTE_SWAP_ENABLE: 1; /*!< [1..1] Used to enable byte swap on a DWORD during AHB write
\r
1093 from AES / HASH block: 1=Enable; 0=Disable. */
\r
1094 __IO uint32_t INPUT_BLOCK_SWAP_ENABLE: 3; /*!< [2..4] Used to enable word swap on a DWORD during AHB read from
\r
1096 4=Swap 32-bit doublewords in 128-byte blocks
\r
1097 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus
\r
1098 references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C,
\r
1099 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,...
\r
1100 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references
\r
1101 issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,...
\r
1102 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which
\r
1104 __IO uint32_t OUTPUT_BLOCK_SWAP_ENABLE: 3; /*!< [5..7] Used to enable word swap on a DWORD during AHB write
\r
1105 from AES / HASH block
\r
1106 4=Swap 32-bit doublewords in 128-byte blocks
\r
1107 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus
\r
1108 references issued in the order 0x3C, 0x38, 0x34, 0x30, 0x2C,
\r
1109 0x28, 0x24, 0x20, 0x1C, 0x18, 0x14, 0x10, 0xC, 0x8, 0x4, 0x0,...
\r
1110 2=Swap doublewords in 16-byte blocks. Useful for AES. Bus references
\r
1111 issued in the order 0xC, 0x8, 0x4, 0x0, 0x1C, 0x18,...
\r
1112 1=Swap doublewords in 8-byte blocks. Useful for SHA-512, which
\r
1114 } AES_HASH_BYTE_SWAP_CONTROL_b; /*!< [8] BitSize */
\r
1116 __I uint32_t RESERVED4[2];
\r
1119 __IO uint32_t SYSTEM_SHUTDOWN_RESET; /*!< (@ 0x4000FC38) System Shutdown Reset */
\r
1122 __O uint32_t SYS_SHDN_RST: 1; /*!< [0..0] When this bit is asserted ('1'), the SYS_SHDN# output
\r
1124 } SYSTEM_SHUTDOWN_RESET_b; /*!< [1] BitSize */
\r
1126 __I uint32_t RESERVED5;
\r
1129 __IO uint32_t MISC_TRIM; /*!< (@ 0x4000FC40) Misc Trim */
\r
1132 __O uint32_t PECI_DISABLE: 1; /*!< [0..0] When this bit is asserted ('1'), it disables the PECI
\r
1133 pads to reduce leakage. */
\r
1134 } MISC_TRIM_b; /*!< [1] BitSize */
\r
1136 __I uint32_t RESERVED6[6];
\r
1139 __IO uint32_t CRYPTO_SOFT_RESET; /*!< (@ 0x4000FC5C) System Shutdown Reset */
\r
1142 __O uint32_t RNG_SOFT_RESET: 1; /*!< [0..0] When this bit is asserted ('1'), the Random Number Generator
\r
1143 block is reset. */
\r
1144 __O uint32_t PUBLIC_KEY_SOFT_RESET: 1; /*!< [1..1] When this bit is asserted ('1'), the Public Key block
\r
1146 __O uint32_t AES_HASH_SOFT_RESET: 1; /*!< [2..2] When this bit is asserted ('1'), the AES and Hash blocks
\r
1148 } CRYPTO_SOFT_RESET_b; /*!< [3] BitSize */
\r
1150 __I uint32_t RESERVED7;
\r
1153 __IO uint32_t GPIO_BANK_POWER; /*!< (@ 0x4000FC64) GPIO Bank Power Register */
\r
1156 __O uint32_t VTR_LEVEL1 : 1; /*!< [0..0] Voltage value on VTR1. This bit is set by hardware after
\r
1157 a VTR Power On Reset, but may be overridden by software.
\r
1158 It must be set by software if the VTR power rail is not active
\r
1159 when RESET_SYS is de-asserted.
\r
1160 1=VTR1 is powered by 3.3V
\r
1161 0=VTR1 is powered by 1.8V. */
\r
1162 __O uint32_t VTR_LEVEL2 : 1; /*!< [1..1] Voltage value on VTR2. This bit is set by hardware after
\r
1163 a VTR Power On Reset, but may be overridden by software.
\r
1164 It must be set by software if the VTR power rail is not active
\r
1165 when RESET_SYS is de-asserted.
\r
1166 1=VTR2 is powered by 3.3V
\r
1167 0=VTR2 is powered by 1.8V. */
\r
1168 __O uint32_t VTR_LEVEL3 : 1; /*!< [2..2] Voltage value on VTR3. This bit is set by hardware after
\r
1169 a VTR Power On Reset, but may be overridden by software.
\r
1170 It must be set by software if the VTR power rail is not active
\r
1171 when RESET_SYS is de-asserted.
\r
1172 1=VTR3 is powered by 3.3V
\r
1173 0=VTR3 is powered by 1.8V. */
\r
1174 } GPIO_BANK_POWER_b; /*!< [3] BitSize */
\r
1176 __I uint32_t RESERVED8[2];
\r
1179 __IO uint32_t JTAG_MASTER_CFG; /*!< (@ 0x4000FC70) JTAG Master Configuration Register */
\r
1182 __IO uint32_t JTM_CLK : 3; /*!< [0..2] This field determines the JTAG Master clock rate, derived
\r
1183 from the 48MHz master clock.
\r
1184 7=375KHz; 6=750KHz; 5=1.5Mhz; 4=3Mhz; 3=6Mhz; 2=12Mhz; 1=24MHz;
\r
1186 __IO uint32_t MASTER_SLAVE: 1; /*!< [3..3] This bit controls the direction of the JTAG port. 1=The
\r
1187 JTAG Port is configured as a Master
\r
1188 0=The JTAG Port is configures as a Slave. */
\r
1189 } JTAG_MASTER_CFG_b; /*!< [4] BitSize */
\r
1193 __I uint32_t JTAG_MASTER_STS; /*!< (@ 0x4000FC74) JTAG Master Status Register */
\r
1196 __I uint32_t JTM_DONE : 1; /*!< [0..0] This bit is set to '1b' when the JTAG Master Command
\r
1197 Register is written. It becomes '0b' when shifting has completed.
\r
1198 Software can poll this bit to determine when a command has
\r
1199 completed and it is therefore safe to remove the data in the
\r
1201 Register and load new data into the JTAG Master TMS Register
\r
1202 and the JTAG Master TDI Register. */
\r
1203 } JTAG_MASTER_STS_b; /*!< [1] BitSize */
\r
1207 __IO uint32_t JTAG_MASTER_TDO; /*!< (@ 0x4000FC78) JTAG Master TDO Register */
\r
1210 __IO uint32_t JTM_TDO : 32; /*!< [0..31] When the JTAG Master Command Register is written, from
\r
1211 1 to 32 bits are shifted into this register, starting with bit
\r
1213 from the JTAG_TDO pin. Shifting is at the rate determined by
\r
1214 the JTM_CLK field in the JTAG Master Configuration Register.
\r
1216 } JTAG_MASTER_TDO_b; /*!< [32] BitSize */
\r
1220 __IO uint32_t JTAG_MASTER_TDI; /*!< (@ 0x4000FC7C) JTAG Master TDI Register */
\r
1223 __IO uint32_t JTM_TDI : 32; /*!< [0..31] When the JTAG Master Command Register is written, from
\r
1224 1 to 32 bits are shifted out of this register, starting with
\r
1226 onto the JTAG_TDI pin. Shifting is at the rate determined by
\r
1227 the JTM_CLK field in the JTAG Master Configuration Register.
\r
1229 } JTAG_MASTER_TDI_b; /*!< [32] BitSize */
\r
1233 __IO uint32_t JTAG_MASTER_TMS; /*!< (@ 0x4000FC80) JTAG Master TMS Register */
\r
1236 __IO uint32_t JTM_TMS : 32; /*!< [0..31] When the JTAG Master Command Register is written, from
\r
1237 1 to 32 bits are shifted out of this register, starting with
\r
1239 onto the JTAG_TMS pin. Shifting is at the rate determined by
\r
1240 the JTM_CLK field in the JTAG Master Configuration Register.
\r
1242 } JTAG_MASTER_TMS_b; /*!< [32] BitSize */
\r
1246 __IO uint32_t JTAG_MASTER_CMD; /*!< (@ 0x4000FC84) JTAG Master Command Register */
\r
1249 __IO uint32_t JTM_COUNT : 5; /*!< [0..4] If the JTAG Port is configured as a Master, writing this
\r
1250 register starts clocking and shifting on the JTAG port. The
\r
1252 Master port will shift JTM_COUNT+1 times, so writing a '0h'
\r
1253 will shift 1 bit, and writing '31h' will shift 32 bits. The
\r
1255 will cycle JTM_COUNT+1 times. The contents of the JTAG Master
\r
1256 TMS Register and the JTAG Master TDI Register will be shifted
\r
1258 the falling edge of JTAG_CLK and the.JTAG Master TDO Register
\r
1259 will get shifted in on the rising edge of JTAG_CLK.
\r
1261 } JTAG_MASTER_CMD_b; /*!< [5] BitSize */
\r
1263 } EC_REG_BANK_Type;
\r
1266 /* -------------------- End of section using anonymous unions ------------------- */
\r
1267 #if defined(__CC_ARM)
\r
1269 #elif defined(__ICCARM__)
\r
1270 /* leave anonymous unions enabled */
\r
1271 #elif defined(__GNUC__)
\r
1272 /* anonymous unions are enabled by default */
\r
1273 #elif defined(__TMS470__)
\r
1274 /* anonymous unions are enabled by default */
\r
1275 #elif defined(__TASKING__)
\r
1276 #pragma warning restore
\r
1278 #warning Not supported compiler type
\r
1283 /* ================================================================================ */
\r
1284 /* ================ struct 'PCR' Position & Mask ================ */
\r
1285 /* ================================================================================ */
\r
1288 /* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */
\r
1289 #define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bit 0) */
\r
1290 #define PCR_SYS_SLP_CNTRL_SLEEP_MODE_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_MODE (Bitfield-Mask: 0x01) */
\r
1291 #define PCR_SYS_SLP_CNTRL_TEST_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bit 2) */
\r
1292 #define PCR_SYS_SLP_CNTRL_TEST_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: TEST (Bitfield-Mask: 0x01) */
\r
1293 #define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Pos (3UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bit 3) */
\r
1294 #define PCR_SYS_SLP_CNTRL_SLEEP_ALL_Msk (0x8UL) /*!< PCR SYS_SLP_CNTRL: SLEEP_ALL (Bitfield-Mask: 0x01) */
\r
1296 /* ----------------------------- PCR_PROC_CLK_CNTRL ----------------------------- */
\r
1297 #define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Pos (0UL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bit 0) */
\r
1298 #define PCR_PROC_CLK_CNTRL_PROCESSOR_CLOCK_DIVIDE_Msk (0xffUL) /*!< PCR PROC_CLK_CNTRL: PROCESSOR_CLOCK_DIVIDE (Bitfield-Mask: 0xff) */
\r
1300 /* ----------------------------- PCR_SLOW_CLK_CNTRL ----------------------------- */
\r
1301 #define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Pos (0UL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bit 0) */
\r
1302 #define PCR_SLOW_CLK_CNTRL_SLOW_CLOCK_DIVIDE_Msk (0x3ffUL) /*!< PCR SLOW_CLK_CNTRL: SLOW_CLOCK_DIVIDE (Bitfield-Mask: 0x3ff) */
\r
1304 /* --------------------------------- PCR_OSC_ID --------------------------------- */
\r
1305 #define PCR_OSC_ID_TEST_Pos (0UL) /*!< PCR OSC_ID: TEST (Bit 0) */
\r
1306 #define PCR_OSC_ID_TEST_Msk (0xffUL) /*!< PCR OSC_ID: TEST (Bitfield-Mask: 0xff) */
\r
1307 #define PCR_OSC_ID_PLL_LOCK_Pos (8UL) /*!< PCR OSC_ID: PLL_LOCK (Bit 8) */
\r
1308 #define PCR_OSC_ID_PLL_LOCK_Msk (0x100UL) /*!< PCR OSC_ID: PLL_LOCK (Bitfield-Mask: 0x01) */
\r
1310 /* ----------------------------- PCR_PCR_PWR_RST_STS ---------------------------- */
\r
1311 #define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Pos (2UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bit 2) */
\r
1312 #define PCR_PCR_PWR_RST_STS_VCC_PWRGD_STATUS_Msk (0x4UL) /*!< PCR PCR_PWR_RST_STS: VCC_PWRGD_STATUS (Bitfield-Mask: 0x01) */
\r
1313 #define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Pos (3UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bit 3) */
\r
1314 #define PCR_PCR_PWR_RST_STS_RESET_HOST_STATUS_Msk (0x8UL) /*!< PCR PCR_PWR_RST_STS: RESET_HOST_STATUS (Bitfield-Mask: 0x01) */
\r
1315 #define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Pos (5UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bit 5) */
\r
1316 #define PCR_PCR_PWR_RST_STS_VBAT_RESET_STATUS_Msk (0x20UL) /*!< PCR PCR_PWR_RST_STS: VBAT_RESET_STATUS (Bitfield-Mask: 0x01) */
\r
1317 #define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Pos (6UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bit 6) */
\r
1318 #define PCR_PCR_PWR_RST_STS_VTR_RESET_STATUS_Msk (0x40UL) /*!< PCR PCR_PWR_RST_STS: VTR_RESET_STATUS (Bitfield-Mask: 0x01) */
\r
1319 #define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Pos (7UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bit 7) */
\r
1320 #define PCR_PCR_PWR_RST_STS_JTAG_RESET_STATUS_Msk (0x80UL) /*!< PCR PCR_PWR_RST_STS: JTAG_RESET_STATUS (Bitfield-Mask: 0x01) */
\r
1321 #define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bit 10) */
\r
1322 #define PCR_PCR_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR PCR_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */
\r
1323 #define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */
\r
1324 #define PCR_PCR_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR PCR_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */
\r
1325 #define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Pos (12UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bit 12) */
\r
1326 #define PCR_PCR_PWR_RST_STS_ESPI_CLK_ACTIVE_Msk (0x1000UL) /*!< PCR PCR_PWR_RST_STS: ESPI_CLK_ACTIVE (Bitfield-Mask: 0x01) */
\r
1328 /* ------------------------------ PCR_PWR_RST_CNTRL ----------------------------- */
\r
1329 #define PCR_PWR_RST_CNTRL_PWR_INV_Pos (0UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bit 0) */
\r
1330 #define PCR_PWR_RST_CNTRL_PWR_INV_Msk (0x1UL) /*!< PCR PWR_RST_CNTRL: PWR_INV (Bitfield-Mask: 0x01) */
\r
1331 #define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Pos (8UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bit 8) */
\r
1332 #define PCR_PWR_RST_CNTRL_HOST_RESET_SELECT_Msk (0x100UL) /*!< PCR PWR_RST_CNTRL: HOST_RESET_SELECT (Bitfield-Mask: 0x01) */
\r
1334 /* --------------------------------- PCR_SYS_RST -------------------------------- */
\r
1335 #define PCR_SYS_RST_SOFT_SYS_RESET_Pos (8UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bit 8) */
\r
1336 #define PCR_SYS_RST_SOFT_SYS_RESET_Msk (0x100UL) /*!< PCR SYS_RST: SOFT_SYS_RESET (Bitfield-Mask: 0x01) */
\r
1338 /* -------------------------------- PCR_SLP_EN_0 -------------------------------- */
\r
1339 #define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bit 0) */
\r
1340 #define PCR_SLP_EN_0_JTAG_STAP_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_0: JTAG_STAP_SLP_EN (Bitfield-Mask: 0x01) */
\r
1341 #define PCR_SLP_EN_0_EFUSE_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bit 1) */
\r
1342 #define PCR_SLP_EN_0_EFUSE_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_0: EFUSE_SLP_EN (Bitfield-Mask: 0x01) */
\r
1343 #define PCR_SLP_EN_0_ISPI_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bit 2) */
\r
1344 #define PCR_SLP_EN_0_ISPI_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_0: ISPI_SLP_EN (Bitfield-Mask: 0x01) */
\r
1346 /* -------------------------------- PCR_SLP_EN_1 -------------------------------- */
\r
1347 #define PCR_SLP_EN_1_INT_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bit 0) */
\r
1348 #define PCR_SLP_EN_1_INT_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_1: INT_SLP_EN (Bitfield-Mask: 0x01) */
\r
1349 #define PCR_SLP_EN_1_PECI_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bit 1) */
\r
1350 #define PCR_SLP_EN_1_PECI_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_1: PECI_SLP_EN (Bitfield-Mask: 0x01) */
\r
1351 #define PCR_SLP_EN_1_TACH0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bit 2) */
\r
1352 #define PCR_SLP_EN_1_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_1: TACH0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1353 #define PCR_SLP_EN_1_PWM0_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bit 4) */
\r
1354 #define PCR_SLP_EN_1_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_1: PWM0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1355 #define PCR_SLP_EN_1_PMC_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bit 5) */
\r
1356 #define PCR_SLP_EN_1_PMC_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_1: PMC_SLP_EN (Bitfield-Mask: 0x01) */
\r
1357 #define PCR_SLP_EN_1_DMA_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bit 6) */
\r
1358 #define PCR_SLP_EN_1_DMA_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_1: DMA_SLP_EN (Bitfield-Mask: 0x01) */
\r
1359 #define PCR_SLP_EN_1_TFDP_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bit 7) */
\r
1360 #define PCR_SLP_EN_1_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_1: TFDP_SLP_EN (Bitfield-Mask: 0x01) */
\r
1361 #define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bit 8) */
\r
1362 #define PCR_SLP_EN_1_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_1: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */
\r
1363 #define PCR_SLP_EN_1_WDT_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bit 9) */
\r
1364 #define PCR_SLP_EN_1_WDT_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_1: WDT_SLP_EN (Bitfield-Mask: 0x01) */
\r
1365 #define PCR_SLP_EN_1_SMB0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bit 10) */
\r
1366 #define PCR_SLP_EN_1_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_1: SMB0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1367 #define PCR_SLP_EN_1_TACH1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bit 11) */
\r
1368 #define PCR_SLP_EN_1_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_1: TACH1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1369 #define PCR_SLP_EN_1_TACH2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bit 12) */
\r
1370 #define PCR_SLP_EN_1_TACH2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_1: TACH2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1371 #define PCR_SLP_EN_1_PWM1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bit 20) */
\r
1372 #define PCR_SLP_EN_1_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_1: PWM1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1373 #define PCR_SLP_EN_1_PWM2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bit 21) */
\r
1374 #define PCR_SLP_EN_1_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_1: PWM2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1375 #define PCR_SLP_EN_1_PWM3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bit 22) */
\r
1376 #define PCR_SLP_EN_1_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_1: PWM3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1377 #define PCR_SLP_EN_1_PWM4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bit 23) */
\r
1378 #define PCR_SLP_EN_1_PWM4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_1: PWM4_SLP_EN (Bitfield-Mask: 0x01) */
\r
1379 #define PCR_SLP_EN_1_PWM5_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bit 24) */
\r
1380 #define PCR_SLP_EN_1_PWM5_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_1: PWM5_SLP_EN (Bitfield-Mask: 0x01) */
\r
1381 #define PCR_SLP_EN_1_PWM6_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bit 25) */
\r
1382 #define PCR_SLP_EN_1_PWM6_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_1: PWM6_SLP_EN (Bitfield-Mask: 0x01) */
\r
1383 #define PCR_SLP_EN_1_PWM7_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bit 26) */
\r
1384 #define PCR_SLP_EN_1_PWM7_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_1: PWM7_SLP_EN (Bitfield-Mask: 0x01) */
\r
1385 #define PCR_SLP_EN_1_PWM8_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bit 27) */
\r
1386 #define PCR_SLP_EN_1_PWM8_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_1: PWM8_SLP_EN (Bitfield-Mask: 0x01) */
\r
1387 #define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bit 29) */
\r
1388 #define PCR_SLP_EN_1_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_1: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */
\r
1389 #define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bit 30) */
\r
1390 #define PCR_SLP_EN_1_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_1: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1391 #define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bit 31) */
\r
1392 #define PCR_SLP_EN_1_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_1: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1394 /* -------------------------------- PCR_SLP_EN_2 -------------------------------- */
\r
1395 #define PCR_SLP_EN_2_LPC_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bit 0) */
\r
1396 #define PCR_SLP_EN_2_LPC_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_2: LPC_SLP_EN (Bitfield-Mask: 0x01) */
\r
1397 #define PCR_SLP_EN_2_UART_0_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bit 1) */
\r
1398 #define PCR_SLP_EN_2_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_2: UART_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1399 #define PCR_SLP_EN_2_UART_1_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bit 2) */
\r
1400 #define PCR_SLP_EN_2_UART_1_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_2: UART_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1401 #define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bit 12) */
\r
1402 #define PCR_SLP_EN_2_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_2: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */
\r
1403 #define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bit 13) */
\r
1404 #define PCR_SLP_EN_2_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_2: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1405 #define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bit 14) */
\r
1406 #define PCR_SLP_EN_2_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_2: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1407 #define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bit 15) */
\r
1408 #define PCR_SLP_EN_2_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_2: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1409 #define PCR_SLP_EN_2_KBCEM_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bit 16) */
\r
1410 #define PCR_SLP_EN_2_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_2: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */
\r
1411 #define PCR_SLP_EN_2_MBX_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bit 17) */
\r
1412 #define PCR_SLP_EN_2_MBX_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_2: MBX_SLP_EN (Bitfield-Mask: 0x01) */
\r
1413 #define PCR_SLP_EN_2_RTC_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bit 18) */
\r
1414 #define PCR_SLP_EN_2_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_2: RTC_SLP_EN (Bitfield-Mask: 0x01) */
\r
1415 #define PCR_SLP_EN_2_ESPI_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bit 19) */
\r
1416 #define PCR_SLP_EN_2_ESPI_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_2: ESPI_SLP_EN (Bitfield-Mask: 0x01) */
\r
1417 #define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bit 21) */
\r
1418 #define PCR_SLP_EN_2_ACPI_EC_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_2: ACPI_EC_2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1419 #define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bit 22) */
\r
1420 #define PCR_SLP_EN_2_ACPI_EC_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_2: ACPI_EC_3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1421 #define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bit 23) */
\r
1422 #define PCR_SLP_EN_2_ACPI_EC_4_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_2: ACPI_EC_4_SLP_EN (Bitfield-Mask: 0x01) */
\r
1423 #define PCR_SLP_EN_2_ASIF_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bit 24) */
\r
1424 #define PCR_SLP_EN_2_ASIF_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_2: ASIF_SLP_EN (Bitfield-Mask: 0x01) */
\r
1425 #define PCR_SLP_EN_2_PORT80_0_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bit 25) */
\r
1426 #define PCR_SLP_EN_2_PORT80_0_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_2: PORT80_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1427 #define PCR_SLP_EN_2_PORT80_1_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bit 26) */
\r
1428 #define PCR_SLP_EN_2_PORT80_1_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_2: PORT80_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1430 /* -------------------------------- PCR_SLP_EN_3 -------------------------------- */
\r
1431 #define PCR_SLP_EN_3_ADC_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bit 3) */
\r
1432 #define PCR_SLP_EN_3_ADC_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_3: ADC_SLP_EN (Bitfield-Mask: 0x01) */
\r
1433 #define PCR_SLP_EN_3_PS2_0_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bit 5) */
\r
1434 #define PCR_SLP_EN_3_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_3: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1435 #define PCR_SLP_EN_3_PS2_1_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bit 6) */
\r
1436 #define PCR_SLP_EN_3_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_3: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1437 #define PCR_SLP_EN_3_PS2_2_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bit 7) */
\r
1438 #define PCR_SLP_EN_3_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_3: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1439 #define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bit 9) */
\r
1440 #define PCR_SLP_EN_3_GP_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_3: GP_SPI0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1441 #define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bit 10) */
\r
1442 #define PCR_SLP_EN_3_HTIMER_0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_3: HTIMER_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1443 #define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bit 11) */
\r
1444 #define PCR_SLP_EN_3_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_3: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */
\r
1445 #define PCR_SLP_EN_3_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bit 12) */
\r
1446 #define PCR_SLP_EN_3_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_3: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */
\r
1447 #define PCR_SLP_EN_3_SMB1_SLP_EN_Pos (13UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bit 13) */
\r
1448 #define PCR_SLP_EN_3_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR SLP_EN_3: SMB1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1449 #define PCR_SLP_EN_3_SMB2_SLP_EN_Pos (14UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bit 14) */
\r
1450 #define PCR_SLP_EN_3_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR SLP_EN_3: SMB2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1451 #define PCR_SLP_EN_3_SMB3_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bit 15) */
\r
1452 #define PCR_SLP_EN_3_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_3: SMB3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1453 #define PCR_SLP_EN_3_LED0_SLP_EN_Pos (16UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bit 16) */
\r
1454 #define PCR_SLP_EN_3_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR SLP_EN_3: LED0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1455 #define PCR_SLP_EN_3_LED1_SLP_EN_Pos (17UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bit 17) */
\r
1456 #define PCR_SLP_EN_3_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR SLP_EN_3: LED1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1457 #define PCR_SLP_EN_3_LED2_SLP_EN_Pos (18UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bit 18) */
\r
1458 #define PCR_SLP_EN_3_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR SLP_EN_3: LED2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1459 #define PCR_SLP_EN_3_BCM0_SLP_EN_Pos (19UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bit 19) */
\r
1460 #define PCR_SLP_EN_3_BCM0_SLP_EN_Msk (0x80000UL) /*!< PCR SLP_EN_3: BCM0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1461 #define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Pos (20UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bit 20) */
\r
1462 #define PCR_SLP_EN_3_GP_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR SLP_EN_3: GP_SPI1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1463 #define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bit 21) */
\r
1464 #define PCR_SLP_EN_3_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR SLP_EN_3: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1465 #define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bit 22) */
\r
1466 #define PCR_SLP_EN_3_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR SLP_EN_3: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1467 #define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bit 23) */
\r
1468 #define PCR_SLP_EN_3_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR SLP_EN_3: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1469 #define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bit 24) */
\r
1470 #define PCR_SLP_EN_3_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR SLP_EN_3: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1471 #define PCR_SLP_EN_3_LED3_SLP_EN_Pos (25UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bit 25) */
\r
1472 #define PCR_SLP_EN_3_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR SLP_EN_3: LED3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1473 #define PCR_SLP_EN_3_PKE_SLP_EN_Pos (26UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bit 26) */
\r
1474 #define PCR_SLP_EN_3_PKE_SLP_EN_Msk (0x4000000UL) /*!< PCR SLP_EN_3: PKE_SLP_EN (Bitfield-Mask: 0x01) */
\r
1475 #define PCR_SLP_EN_3_RNG_SLP_EN_Pos (27UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bit 27) */
\r
1476 #define PCR_SLP_EN_3_RNG_SLP_EN_Msk (0x8000000UL) /*!< PCR SLP_EN_3: RNG_SLP_EN (Bitfield-Mask: 0x01) */
\r
1477 #define PCR_SLP_EN_3_AES_HASH_SLP_EN_Pos (28UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bit 28) */
\r
1478 #define PCR_SLP_EN_3_AES_HASH_SLP_EN_Msk (0x10000000UL) /*!< PCR SLP_EN_3: AES_HASH_SLP_EN (Bitfield-Mask: 0x01) */
\r
1479 #define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Pos (29UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bit 29) */
\r
1480 #define PCR_SLP_EN_3_HTIMER_1_SLP_EN_Msk (0x20000000UL) /*!< PCR SLP_EN_3: HTIMER_1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1481 #define PCR_SLP_EN_3_CCTIMER_SLP_EN_Pos (30UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bit 30) */
\r
1482 #define PCR_SLP_EN_3_CCTIMER_SLP_EN_Msk (0x40000000UL) /*!< PCR SLP_EN_3: CCTIMER_SLP_EN (Bitfield-Mask: 0x01) */
\r
1483 #define PCR_SLP_EN_3_PWM9_SLP_EN_Pos (31UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bit 31) */
\r
1484 #define PCR_SLP_EN_3_PWM9_SLP_EN_Msk (0x80000000UL) /*!< PCR SLP_EN_3: PWM9_SLP_EN (Bitfield-Mask: 0x01) */
\r
1486 /* -------------------------------- PCR_SLP_EN_4 -------------------------------- */
\r
1487 #define PCR_SLP_EN_4_PWM10_SLP_EN_Pos (0UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bit 0) */
\r
1488 #define PCR_SLP_EN_4_PWM10_SLP_EN_Msk (0x1UL) /*!< PCR SLP_EN_4: PWM10_SLP_EN (Bitfield-Mask: 0x01) */
\r
1489 #define PCR_SLP_EN_4_PWM11_SLP_EN_Pos (1UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bit 1) */
\r
1490 #define PCR_SLP_EN_4_PWM11_SLP_EN_Msk (0x2UL) /*!< PCR SLP_EN_4: PWM11_SLP_EN (Bitfield-Mask: 0x01) */
\r
1491 #define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Pos (2UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bit 2) */
\r
1492 #define PCR_SLP_EN_4_CNT_TMER0_SLP_EN_Msk (0x4UL) /*!< PCR SLP_EN_4: CNT_TMER0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1493 #define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Pos (3UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bit 3) */
\r
1494 #define PCR_SLP_EN_4_CNT_TMER1_SLP_EN_Msk (0x8UL) /*!< PCR SLP_EN_4: CNT_TMER1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1495 #define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Pos (4UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bit 4) */
\r
1496 #define PCR_SLP_EN_4_CNT_TMER2_SLP_EN_Msk (0x10UL) /*!< PCR SLP_EN_4: CNT_TMER2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1497 #define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Pos (5UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bit 5) */
\r
1498 #define PCR_SLP_EN_4_CNT_TMER3_SLP_EN_Msk (0x20UL) /*!< PCR SLP_EN_4: CNT_TMER3_SLP_EN (Bitfield-Mask: 0x01) */
\r
1499 #define PCR_SLP_EN_4_RTOS_SLP_EN_Pos (6UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bit 6) */
\r
1500 #define PCR_SLP_EN_4_RTOS_SLP_EN_Msk (0x40UL) /*!< PCR SLP_EN_4: RTOS_SLP_EN (Bitfield-Mask: 0x01) */
\r
1501 #define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Pos (7UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bit 7) */
\r
1502 #define PCR_SLP_EN_4_RPMPWM1_SLP_EN_Msk (0x80UL) /*!< PCR SLP_EN_4: RPMPWM1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1503 #define PCR_SLP_EN_4_QSPI_SLP_EN_Pos (8UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bit 8) */
\r
1504 #define PCR_SLP_EN_4_QSPI_SLP_EN_Msk (0x100UL) /*!< PCR SLP_EN_4: QSPI_SLP_EN (Bitfield-Mask: 0x01) */
\r
1505 #define PCR_SLP_EN_4_BCM1_SLP_EN_Pos (9UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bit 9) */
\r
1506 #define PCR_SLP_EN_4_BCM1_SLP_EN_Msk (0x200UL) /*!< PCR SLP_EN_4: BCM1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1507 #define PCR_SLP_EN_4_RC_ID0_SLP_EN_Pos (10UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bit 10) */
\r
1508 #define PCR_SLP_EN_4_RC_ID0_SLP_EN_Msk (0x400UL) /*!< PCR SLP_EN_4: RC_ID0_SLP_EN (Bitfield-Mask: 0x01) */
\r
1509 #define PCR_SLP_EN_4_RC_ID1_SLP_EN_Pos (11UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bit 11) */
\r
1510 #define PCR_SLP_EN_4_RC_ID1_SLP_EN_Msk (0x800UL) /*!< PCR SLP_EN_4: RC_ID1_SLP_EN (Bitfield-Mask: 0x01) */
\r
1511 #define PCR_SLP_EN_4_RC_ID2_SLP_EN_Pos (12UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bit 12) */
\r
1512 #define PCR_SLP_EN_4_RC_ID2_SLP_EN_Msk (0x1000UL) /*!< PCR SLP_EN_4: RC_ID2_SLP_EN (Bitfield-Mask: 0x01) */
\r
1513 #define PCR_SLP_EN_4_FCL_SLP_EN_Pos (15UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bit 15) */
\r
1514 #define PCR_SLP_EN_4_FCL_SLP_EN_Msk (0x8000UL) /*!< PCR SLP_EN_4: FCL_SLP_EN (Bitfield-Mask: 0x01) */
\r
1516 /* -------------------------------- PCR_CLK_REQ_0 ------------------------------- */
\r
1517 #define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bit 0) */
\r
1518 #define PCR_CLK_REQ_0_JTAG_STAP_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_0: JTAG_STAP_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1519 #define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bit 1) */
\r
1520 #define PCR_CLK_REQ_0_EFUSE_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_0: EFUSE_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1521 #define PCR_CLK_REQ_0_ISPI_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bit 2) */
\r
1522 #define PCR_CLK_REQ_0_ISPI_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_0: ISPI_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1524 /* -------------------------------- PCR_CLK_REQ_1 ------------------------------- */
\r
1525 #define PCR_CLK_REQ_1_INT_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bit 0) */
\r
1526 #define PCR_CLK_REQ_1_INT_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_1: INT_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1527 #define PCR_CLK_REQ_1_PECI_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bit 1) */
\r
1528 #define PCR_CLK_REQ_1_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_1: PECI_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1529 #define PCR_CLK_REQ_1_TACH0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bit 2) */
\r
1530 #define PCR_CLK_REQ_1_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_1: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1531 #define PCR_CLK_REQ_1_PWM0_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bit 4) */
\r
1532 #define PCR_CLK_REQ_1_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_1: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1533 #define PCR_CLK_REQ_1_PMC_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bit 5) */
\r
1534 #define PCR_CLK_REQ_1_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_1: PMC_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1535 #define PCR_CLK_REQ_1_DMA_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bit 6) */
\r
1536 #define PCR_CLK_REQ_1_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_1: DMA_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1537 #define PCR_CLK_REQ_1_TFDP_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bit 7) */
\r
1538 #define PCR_CLK_REQ_1_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_1: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1539 #define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bit 8) */
\r
1540 #define PCR_CLK_REQ_1_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_1: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1541 #define PCR_CLK_REQ_1_WDT_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bit 9) */
\r
1542 #define PCR_CLK_REQ_1_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_1: WDT_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1543 #define PCR_CLK_REQ_1_SMB0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bit 10) */
\r
1544 #define PCR_CLK_REQ_1_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_1: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1545 #define PCR_CLK_REQ_1_TACH1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bit 11) */
\r
1546 #define PCR_CLK_REQ_1_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_1: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1547 #define PCR_CLK_REQ_1_TACH2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bit 12) */
\r
1548 #define PCR_CLK_REQ_1_TACH2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_1: TACH2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1549 #define PCR_CLK_REQ_1_PWM1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bit 20) */
\r
1550 #define PCR_CLK_REQ_1_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_1: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1551 #define PCR_CLK_REQ_1_PWM2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bit 21) */
\r
1552 #define PCR_CLK_REQ_1_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_1: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1553 #define PCR_CLK_REQ_1_PWM3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bit 22) */
\r
1554 #define PCR_CLK_REQ_1_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_1: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1555 #define PCR_CLK_REQ_1_PWM4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bit 23) */
\r
1556 #define PCR_CLK_REQ_1_PWM4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_1: PWM4_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1557 #define PCR_CLK_REQ_1_PWM5_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bit 24) */
\r
1558 #define PCR_CLK_REQ_1_PWM5_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_1: PWM5_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1559 #define PCR_CLK_REQ_1_PWM6_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bit 25) */
\r
1560 #define PCR_CLK_REQ_1_PWM6_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_1: PWM6_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1561 #define PCR_CLK_REQ_1_PWM7_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bit 26) */
\r
1562 #define PCR_CLK_REQ_1_PWM7_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_1: PWM7_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1563 #define PCR_CLK_REQ_1_PWM8_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bit 27) */
\r
1564 #define PCR_CLK_REQ_1_PWM8_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_1: PWM8_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1565 #define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bit 29) */
\r
1566 #define PCR_CLK_REQ_1_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_1: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1567 #define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bit 30) */
\r
1568 #define PCR_CLK_REQ_1_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_1: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1569 #define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bit 31) */
\r
1570 #define PCR_CLK_REQ_1_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_1: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1572 /* -------------------------------- PCR_CLK_REQ_2 ------------------------------- */
\r
1573 #define PCR_CLK_REQ_2_LPC_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bit 0) */
\r
1574 #define PCR_CLK_REQ_2_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_2: LPC_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1575 #define PCR_CLK_REQ_2_UART_0_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bit 1) */
\r
1576 #define PCR_CLK_REQ_2_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_2: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1577 #define PCR_CLK_REQ_2_UART_1_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bit 2) */
\r
1578 #define PCR_CLK_REQ_2_UART_1_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_2: UART_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1579 #define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bit 12) */
\r
1580 #define PCR_CLK_REQ_2_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_2: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1581 #define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bit 13) */
\r
1582 #define PCR_CLK_REQ_2_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_2: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1583 #define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bit 14) */
\r
1584 #define PCR_CLK_REQ_2_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_2: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1585 #define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bit 15) */
\r
1586 #define PCR_CLK_REQ_2_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_2: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1587 #define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bit 16) */
\r
1588 #define PCR_CLK_REQ_2_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_2: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1589 #define PCR_CLK_REQ_2_MBX_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bit 17) */
\r
1590 #define PCR_CLK_REQ_2_MBX_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_2: MBX_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1591 #define PCR_CLK_REQ_2_RTC_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bit 18) */
\r
1592 #define PCR_CLK_REQ_2_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_2: RTC_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1593 #define PCR_CLK_REQ_2_ESPI_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bit 19) */
\r
1594 #define PCR_CLK_REQ_2_ESPI_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_2: ESPI_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1595 #define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bit 21) */
\r
1596 #define PCR_CLK_REQ_2_ACPI_EC_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_2: ACPI_EC_2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1597 #define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bit 22) */
\r
1598 #define PCR_CLK_REQ_2_ACPI_EC_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_2: ACPI_EC_3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1599 #define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bit 23) */
\r
1600 #define PCR_CLK_REQ_2_ACPI_EC_4_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_2: ACPI_EC_4_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1601 #define PCR_CLK_REQ_2_ASIF_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bit 24) */
\r
1602 #define PCR_CLK_REQ_2_ASIF_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_2: ASIF_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1603 #define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bit 25) */
\r
1604 #define PCR_CLK_REQ_2_PORT80_0_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_2: PORT80_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1605 #define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bit 26) */
\r
1606 #define PCR_CLK_REQ_2_PORT80_1_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_2: PORT80_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1608 /* -------------------------------- PCR_CLK_REQ_3 ------------------------------- */
\r
1609 #define PCR_CLK_REQ_3_ADC_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bit 3) */
\r
1610 #define PCR_CLK_REQ_3_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_3: ADC_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1611 #define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bit 5) */
\r
1612 #define PCR_CLK_REQ_3_PS2_0_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_3: PS2_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1613 #define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bit 6) */
\r
1614 #define PCR_CLK_REQ_3_PS2_1_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_3: PS2_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1615 #define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bit 7) */
\r
1616 #define PCR_CLK_REQ_3_PS2_2_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_3: PS2_2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1617 #define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bit 9) */
\r
1618 #define PCR_CLK_REQ_3_GP_SPI0_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_3: GP_SPI0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1619 #define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bit 10) */
\r
1620 #define PCR_CLK_REQ_3_HTIMER_0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_3: HTIMER_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1621 #define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bit 11) */
\r
1622 #define PCR_CLK_REQ_3_KEYSCAN_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_3: KEYSCAN_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1623 #define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bit 12) */
\r
1624 #define PCR_CLK_REQ_3_RPMPWM0_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_3: RPMPWM0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1625 #define PCR_CLK_REQ_3_SMB1_CLK_REQ_Pos (13UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bit 13) */
\r
1626 #define PCR_CLK_REQ_3_SMB1_CLK_REQ_Msk (0x2000UL) /*!< PCR CLK_REQ_3: SMB1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1627 #define PCR_CLK_REQ_3_SMB2_CLK_REQ_Pos (14UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bit 14) */
\r
1628 #define PCR_CLK_REQ_3_SMB2_CLK_REQ_Msk (0x4000UL) /*!< PCR CLK_REQ_3: SMB2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1629 #define PCR_CLK_REQ_3_SMB3_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bit 15) */
\r
1630 #define PCR_CLK_REQ_3_SMB3_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_3: SMB3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1631 #define PCR_CLK_REQ_3_LED0_CLK_REQ_Pos (16UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bit 16) */
\r
1632 #define PCR_CLK_REQ_3_LED0_CLK_REQ_Msk (0x10000UL) /*!< PCR CLK_REQ_3: LED0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1633 #define PCR_CLK_REQ_3_LED1_CLK_REQ_Pos (17UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bit 17) */
\r
1634 #define PCR_CLK_REQ_3_LED1_CLK_REQ_Msk (0x20000UL) /*!< PCR CLK_REQ_3: LED1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1635 #define PCR_CLK_REQ_3_LED2_CLK_REQ_Pos (18UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bit 18) */
\r
1636 #define PCR_CLK_REQ_3_LED2_CLK_REQ_Msk (0x40000UL) /*!< PCR CLK_REQ_3: LED2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1637 #define PCR_CLK_REQ_3_BCM0_CLK_REQ_Pos (19UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bit 19) */
\r
1638 #define PCR_CLK_REQ_3_BCM0_CLK_REQ_Msk (0x80000UL) /*!< PCR CLK_REQ_3: BCM0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1639 #define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Pos (20UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bit 20) */
\r
1640 #define PCR_CLK_REQ_3_GP_SPI1_CLK_REQ_Msk (0x100000UL) /*!< PCR CLK_REQ_3: GP_SPI1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1641 #define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Pos (21UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bit 21) */
\r
1642 #define PCR_CLK_REQ_3_TIMER16_2_CLK_REQ_Msk (0x200000UL) /*!< PCR CLK_REQ_3: TIMER16_2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1643 #define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Pos (22UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bit 22) */
\r
1644 #define PCR_CLK_REQ_3_TIMER16_3_CLK_REQ_Msk (0x400000UL) /*!< PCR CLK_REQ_3: TIMER16_3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1645 #define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Pos (23UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bit 23) */
\r
1646 #define PCR_CLK_REQ_3_TIMER32_0_CLK_REQ_Msk (0x800000UL) /*!< PCR CLK_REQ_3: TIMER32_0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1647 #define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Pos (24UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bit 24) */
\r
1648 #define PCR_CLK_REQ_3_TIMER32_1_CLK_REQ_Msk (0x1000000UL) /*!< PCR CLK_REQ_3: TIMER32_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1649 #define PCR_CLK_REQ_3_LED3_CLK_REQ_Pos (25UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bit 25) */
\r
1650 #define PCR_CLK_REQ_3_LED3_CLK_REQ_Msk (0x2000000UL) /*!< PCR CLK_REQ_3: LED3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1651 #define PCR_CLK_REQ_3_PKE_CLK_REQ_Pos (26UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bit 26) */
\r
1652 #define PCR_CLK_REQ_3_PKE_CLK_REQ_Msk (0x4000000UL) /*!< PCR CLK_REQ_3: PKE_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1653 #define PCR_CLK_REQ_3_RNG_CLK_REQ_Pos (27UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bit 27) */
\r
1654 #define PCR_CLK_REQ_3_RNG_CLK_REQ_Msk (0x8000000UL) /*!< PCR CLK_REQ_3: RNG_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1655 #define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Pos (28UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bit 28) */
\r
1656 #define PCR_CLK_REQ_3_AES_HASH_CLK_REQ_Msk (0x10000000UL) /*!< PCR CLK_REQ_3: AES_HASH_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1657 #define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Pos (29UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bit 29) */
\r
1658 #define PCR_CLK_REQ_3_HTIMER_1_CLK_REQ_Msk (0x20000000UL) /*!< PCR CLK_REQ_3: HTIMER_1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1659 #define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Pos (30UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bit 30) */
\r
1660 #define PCR_CLK_REQ_3_CCTIMER_CLK_REQ_Msk (0x40000000UL) /*!< PCR CLK_REQ_3: CCTIMER_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1661 #define PCR_CLK_REQ_3_PWM9_CLK_REQ_Pos (31UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bit 31) */
\r
1662 #define PCR_CLK_REQ_3_PWM9_CLK_REQ_Msk (0x80000000UL) /*!< PCR CLK_REQ_3: PWM9_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1664 /* -------------------------------- PCR_CLK_REQ_4 ------------------------------- */
\r
1665 #define PCR_CLK_REQ_4_PWM10_CLK_REQ_Pos (0UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bit 0) */
\r
1666 #define PCR_CLK_REQ_4_PWM10_CLK_REQ_Msk (0x1UL) /*!< PCR CLK_REQ_4: PWM10_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1667 #define PCR_CLK_REQ_4_PWM11_CLK_REQ_Pos (1UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bit 1) */
\r
1668 #define PCR_CLK_REQ_4_PWM11_CLK_REQ_Msk (0x2UL) /*!< PCR CLK_REQ_4: PWM11_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1669 #define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Pos (2UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bit 2) */
\r
1670 #define PCR_CLK_REQ_4_CNT_TMER0_CLK_REQ_Msk (0x4UL) /*!< PCR CLK_REQ_4: CNT_TMER0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1671 #define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Pos (3UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bit 3) */
\r
1672 #define PCR_CLK_REQ_4_CNT_TMER1_CLK_REQ_Msk (0x8UL) /*!< PCR CLK_REQ_4: CNT_TMER1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1673 #define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Pos (4UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bit 4) */
\r
1674 #define PCR_CLK_REQ_4_CNT_TMER2_CLK_REQ_Msk (0x10UL) /*!< PCR CLK_REQ_4: CNT_TMER2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1675 #define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Pos (5UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bit 5) */
\r
1676 #define PCR_CLK_REQ_4_CNT_TMER3_CLK_REQ_Msk (0x20UL) /*!< PCR CLK_REQ_4: CNT_TMER3_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1677 #define PCR_CLK_REQ_4_RTOS_CLK_REQ_Pos (6UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bit 6) */
\r
1678 #define PCR_CLK_REQ_4_RTOS_CLK_REQ_Msk (0x40UL) /*!< PCR CLK_REQ_4: RTOS_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1679 #define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Pos (7UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bit 7) */
\r
1680 #define PCR_CLK_REQ_4_RPMPWM1_CLK_REQ_Msk (0x80UL) /*!< PCR CLK_REQ_4: RPMPWM1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1681 #define PCR_CLK_REQ_4_QSPI_CLK_REQ_Pos (8UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bit 8) */
\r
1682 #define PCR_CLK_REQ_4_QSPI_CLK_REQ_Msk (0x100UL) /*!< PCR CLK_REQ_4: QSPI_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1683 #define PCR_CLK_REQ_4_BCM1_CLK_REQ_Pos (9UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bit 9) */
\r
1684 #define PCR_CLK_REQ_4_BCM1_CLK_REQ_Msk (0x200UL) /*!< PCR CLK_REQ_4: BCM1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1685 #define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Pos (10UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bit 10) */
\r
1686 #define PCR_CLK_REQ_4_RC_ID0_CLK_REQ_Msk (0x400UL) /*!< PCR CLK_REQ_4: RC_ID0_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1687 #define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Pos (11UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bit 11) */
\r
1688 #define PCR_CLK_REQ_4_RC_ID1_CLK_REQ_Msk (0x800UL) /*!< PCR CLK_REQ_4: RC_ID1_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1689 #define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Pos (12UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bit 12) */
\r
1690 #define PCR_CLK_REQ_4_RC_ID2_CLK_REQ_Msk (0x1000UL) /*!< PCR CLK_REQ_4: RC_ID2_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1691 #define PCR_CLK_REQ_4_FCL_CLK_REQ_Pos (15UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bit 15) */
\r
1692 #define PCR_CLK_REQ_4_FCL_CLK_REQ_Msk (0x8000UL) /*!< PCR CLK_REQ_4: FCL_CLK_REQ (Bitfield-Mask: 0x01) */
\r
1694 /* -------------------------------- PCR_RST_EN_0 -------------------------------- */
\r
1695 #define PCR_RST_EN_0_JTAG_STAP_RST_EN_Pos (0UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bit 0) */
\r
1696 #define PCR_RST_EN_0_JTAG_STAP_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_0: JTAG_STAP_RST_EN (Bitfield-Mask: 0x01) */
\r
1697 #define PCR_RST_EN_0_EFUSE_RST_EN_Pos (1UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bit 1) */
\r
1698 #define PCR_RST_EN_0_EFUSE_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_0: EFUSE_RST_EN (Bitfield-Mask: 0x01) */
\r
1699 #define PCR_RST_EN_0_ISPI_RST_EN_Pos (2UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bit 2) */
\r
1700 #define PCR_RST_EN_0_ISPI_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_0: ISPI_RST_EN (Bitfield-Mask: 0x01) */
\r
1702 /* -------------------------------- PCR_RST_EN_1 -------------------------------- */
\r
1703 #define PCR_RST_EN_1_INT_RST_EN_Pos (0UL) /*!< PCR RST_EN_1: INT_RST_EN (Bit 0) */
\r
1704 #define PCR_RST_EN_1_INT_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_1: INT_RST_EN (Bitfield-Mask: 0x01) */
\r
1705 #define PCR_RST_EN_1_PECI_RST_EN_Pos (1UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bit 1) */
\r
1706 #define PCR_RST_EN_1_PECI_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_1: PECI_RST_EN (Bitfield-Mask: 0x01) */
\r
1707 #define PCR_RST_EN_1_TACH0_RST_EN_Pos (2UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bit 2) */
\r
1708 #define PCR_RST_EN_1_TACH0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_1: TACH0_RST_EN (Bitfield-Mask: 0x01) */
\r
1709 #define PCR_RST_EN_1_PWM0_RST_EN_Pos (4UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bit 4) */
\r
1710 #define PCR_RST_EN_1_PWM0_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_1: PWM0_RST_EN (Bitfield-Mask: 0x01) */
\r
1711 #define PCR_RST_EN_1_PMC_RST_EN_Pos (5UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bit 5) */
\r
1712 #define PCR_RST_EN_1_PMC_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_1: PMC_RST_EN (Bitfield-Mask: 0x01) */
\r
1713 #define PCR_RST_EN_1_DMA_RST_EN_Pos (6UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bit 6) */
\r
1714 #define PCR_RST_EN_1_DMA_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_1: DMA_RST_EN (Bitfield-Mask: 0x01) */
\r
1715 #define PCR_RST_EN_1_TFDP_RST_EN_Pos (7UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bit 7) */
\r
1716 #define PCR_RST_EN_1_TFDP_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_1: TFDP_RST_EN (Bitfield-Mask: 0x01) */
\r
1717 #define PCR_RST_EN_1_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bit 8) */
\r
1718 #define PCR_RST_EN_1_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_1: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */
\r
1719 #define PCR_RST_EN_1_WDT_RST_EN_Pos (9UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bit 9) */
\r
1720 #define PCR_RST_EN_1_WDT_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_1: WDT_RST_EN (Bitfield-Mask: 0x01) */
\r
1721 #define PCR_RST_EN_1_SMB0_RST_EN_Pos (10UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bit 10) */
\r
1722 #define PCR_RST_EN_1_SMB0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_1: SMB0_RST_EN (Bitfield-Mask: 0x01) */
\r
1723 #define PCR_RST_EN_1_TACH1_RST_EN_Pos (11UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bit 11) */
\r
1724 #define PCR_RST_EN_1_TACH1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_1: TACH1_RST_EN (Bitfield-Mask: 0x01) */
\r
1725 #define PCR_RST_EN_1_TACH2_RST_EN_Pos (12UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bit 12) */
\r
1726 #define PCR_RST_EN_1_TACH2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_1: TACH2_RST_EN (Bitfield-Mask: 0x01) */
\r
1727 #define PCR_RST_EN_1_PWM1_RST_EN_Pos (20UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bit 20) */
\r
1728 #define PCR_RST_EN_1_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_1: PWM1_RST_EN (Bitfield-Mask: 0x01) */
\r
1729 #define PCR_RST_EN_1_PWM2_RST_EN_Pos (21UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bit 21) */
\r
1730 #define PCR_RST_EN_1_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_1: PWM2_RST_EN (Bitfield-Mask: 0x01) */
\r
1731 #define PCR_RST_EN_1_PWM3_RST_EN_Pos (22UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bit 22) */
\r
1732 #define PCR_RST_EN_1_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_1: PWM3_RST_EN (Bitfield-Mask: 0x01) */
\r
1733 #define PCR_RST_EN_1_PWM4_RST_EN_Pos (23UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bit 23) */
\r
1734 #define PCR_RST_EN_1_PWM4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_1: PWM4_RST_EN (Bitfield-Mask: 0x01) */
\r
1735 #define PCR_RST_EN_1_PWM5_RST_EN_Pos (24UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bit 24) */
\r
1736 #define PCR_RST_EN_1_PWM5_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_1: PWM5_RST_EN (Bitfield-Mask: 0x01) */
\r
1737 #define PCR_RST_EN_1_PWM6_RST_EN_Pos (25UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bit 25) */
\r
1738 #define PCR_RST_EN_1_PWM6_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_1: PWM6_RST_EN (Bitfield-Mask: 0x01) */
\r
1739 #define PCR_RST_EN_1_PWM7_RST_EN_Pos (26UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bit 26) */
\r
1740 #define PCR_RST_EN_1_PWM7_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_1: PWM7_RST_EN (Bitfield-Mask: 0x01) */
\r
1741 #define PCR_RST_EN_1_PWM8_RST_EN_Pos (27UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bit 27) */
\r
1742 #define PCR_RST_EN_1_PWM8_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_1: PWM8_RST_EN (Bitfield-Mask: 0x01) */
\r
1743 #define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bit 29) */
\r
1744 #define PCR_RST_EN_1_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_1: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */
\r
1745 #define PCR_RST_EN_1_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bit 30) */
\r
1746 #define PCR_RST_EN_1_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_1: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1747 #define PCR_RST_EN_1_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bit 31) */
\r
1748 #define PCR_RST_EN_1_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_1: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1750 /* -------------------------------- PCR_RST_EN_2 -------------------------------- */
\r
1751 #define PCR_RST_EN_2_LPC_RST_EN_Pos (0UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bit 0) */
\r
1752 #define PCR_RST_EN_2_LPC_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_2: LPC_RST_EN (Bitfield-Mask: 0x01) */
\r
1753 #define PCR_RST_EN_2_UART_0_RST_EN_Pos (1UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bit 1) */
\r
1754 #define PCR_RST_EN_2_UART_0_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_2: UART_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1755 #define PCR_RST_EN_2_UART_1_RST_EN_Pos (2UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bit 2) */
\r
1756 #define PCR_RST_EN_2_UART_1_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_2: UART_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1757 #define PCR_RST_EN_2_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bit 12) */
\r
1758 #define PCR_RST_EN_2_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_2: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */
\r
1759 #define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bit 13) */
\r
1760 #define PCR_RST_EN_2_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_2: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1761 #define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bit 14) */
\r
1762 #define PCR_RST_EN_2_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_2: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1763 #define PCR_RST_EN_2_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bit 15) */
\r
1764 #define PCR_RST_EN_2_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_2: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */
\r
1765 #define PCR_RST_EN_2_KBCEM_RST_EN_Pos (16UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bit 16) */
\r
1766 #define PCR_RST_EN_2_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_2: KBCEM_RST_EN (Bitfield-Mask: 0x01) */
\r
1767 #define PCR_RST_EN_2_MBX_RST_EN_Pos (17UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bit 17) */
\r
1768 #define PCR_RST_EN_2_MBX_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_2: MBX_RST_EN (Bitfield-Mask: 0x01) */
\r
1769 #define PCR_RST_EN_2_RTC_RST_EN_Pos (18UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bit 18) */
\r
1770 #define PCR_RST_EN_2_RTC_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_2: RTC_RST_EN (Bitfield-Mask: 0x01) */
\r
1771 #define PCR_RST_EN_2_ESPI_RST_EN_Pos (19UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bit 19) */
\r
1772 #define PCR_RST_EN_2_ESPI_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_2: ESPI_RST_EN (Bitfield-Mask: 0x01) */
\r
1773 #define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bit 21) */
\r
1774 #define PCR_RST_EN_2_ACPI_EC_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_2: ACPI_EC_2_RST_EN (Bitfield-Mask: 0x01) */
\r
1775 #define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bit 22) */
\r
1776 #define PCR_RST_EN_2_ACPI_EC_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_2: ACPI_EC_3_RST_EN (Bitfield-Mask: 0x01) */
\r
1777 #define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Pos (23UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bit 23) */
\r
1778 #define PCR_RST_EN_2_ACPI_EC_4_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_2: ACPI_EC_4_RST_EN (Bitfield-Mask: 0x01) */
\r
1779 #define PCR_RST_EN_2_ASIF_RST_EN_Pos (24UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bit 24) */
\r
1780 #define PCR_RST_EN_2_ASIF_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_2: ASIF_RST_EN (Bitfield-Mask: 0x01) */
\r
1781 #define PCR_RST_EN_2_PORT80_0_RST_EN_Pos (25UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bit 25) */
\r
1782 #define PCR_RST_EN_2_PORT80_0_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_2: PORT80_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1783 #define PCR_RST_EN_2_PORT80_1_RST_EN_Pos (26UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bit 26) */
\r
1784 #define PCR_RST_EN_2_PORT80_1_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_2: PORT80_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1786 /* -------------------------------- PCR_RST_EN_3 -------------------------------- */
\r
1787 #define PCR_RST_EN_3_ADC_RST_EN_Pos (3UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bit 3) */
\r
1788 #define PCR_RST_EN_3_ADC_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_3: ADC_RST_EN (Bitfield-Mask: 0x01) */
\r
1789 #define PCR_RST_EN_3_PS2_0_RST_EN_Pos (5UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bit 5) */
\r
1790 #define PCR_RST_EN_3_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_3: PS2_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1791 #define PCR_RST_EN_3_PS2_1_RST_EN_Pos (6UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bit 6) */
\r
1792 #define PCR_RST_EN_3_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_3: PS2_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1793 #define PCR_RST_EN_3_PS2_2_RST_EN_Pos (7UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bit 7) */
\r
1794 #define PCR_RST_EN_3_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_3: PS2_2_RST_EN (Bitfield-Mask: 0x01) */
\r
1795 #define PCR_RST_EN_3_GP_SPI0_RST_EN_Pos (9UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bit 9) */
\r
1796 #define PCR_RST_EN_3_GP_SPI0_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_3: GP_SPI0_RST_EN (Bitfield-Mask: 0x01) */
\r
1797 #define PCR_RST_EN_3_HTIMER_0_RST_EN_Pos (10UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bit 10) */
\r
1798 #define PCR_RST_EN_3_HTIMER_0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_3: HTIMER_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1799 #define PCR_RST_EN_3_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bit 11) */
\r
1800 #define PCR_RST_EN_3_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_3: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */
\r
1801 #define PCR_RST_EN_3_RPMPWM0_RST_EN_Pos (12UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bit 12) */
\r
1802 #define PCR_RST_EN_3_RPMPWM0_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_3: RPMPWM0_RST_EN (Bitfield-Mask: 0x01) */
\r
1803 #define PCR_RST_EN_3_SMB1_RST_EN_Pos (13UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bit 13) */
\r
1804 #define PCR_RST_EN_3_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR RST_EN_3: SMB1_RST_EN (Bitfield-Mask: 0x01) */
\r
1805 #define PCR_RST_EN_3_SMB2_RST_EN_Pos (14UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bit 14) */
\r
1806 #define PCR_RST_EN_3_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR RST_EN_3: SMB2_RST_EN (Bitfield-Mask: 0x01) */
\r
1807 #define PCR_RST_EN_3_SMB3_RST_EN_Pos (15UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bit 15) */
\r
1808 #define PCR_RST_EN_3_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_3: SMB3_RST_EN (Bitfield-Mask: 0x01) */
\r
1809 #define PCR_RST_EN_3_LED0_RST_EN_Pos (16UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bit 16) */
\r
1810 #define PCR_RST_EN_3_LED0_RST_EN_Msk (0x10000UL) /*!< PCR RST_EN_3: LED0_RST_EN (Bitfield-Mask: 0x01) */
\r
1811 #define PCR_RST_EN_3_LED1_RST_EN_Pos (17UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bit 17) */
\r
1812 #define PCR_RST_EN_3_LED1_RST_EN_Msk (0x20000UL) /*!< PCR RST_EN_3: LED1_RST_EN (Bitfield-Mask: 0x01) */
\r
1813 #define PCR_RST_EN_3_LED2_RST_EN_Pos (18UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bit 18) */
\r
1814 #define PCR_RST_EN_3_LED2_RST_EN_Msk (0x40000UL) /*!< PCR RST_EN_3: LED2_RST_EN (Bitfield-Mask: 0x01) */
\r
1815 #define PCR_RST_EN_3_BCM0_RST_EN_Pos (19UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bit 19) */
\r
1816 #define PCR_RST_EN_3_BCM0_RST_EN_Msk (0x80000UL) /*!< PCR RST_EN_3: BCM0_RST_EN (Bitfield-Mask: 0x01) */
\r
1817 #define PCR_RST_EN_3_GP_SPI1_RST_EN_Pos (20UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bit 20) */
\r
1818 #define PCR_RST_EN_3_GP_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR RST_EN_3: GP_SPI1_RST_EN (Bitfield-Mask: 0x01) */
\r
1819 #define PCR_RST_EN_3_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bit 21) */
\r
1820 #define PCR_RST_EN_3_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR RST_EN_3: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */
\r
1821 #define PCR_RST_EN_3_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bit 22) */
\r
1822 #define PCR_RST_EN_3_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR RST_EN_3: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */
\r
1823 #define PCR_RST_EN_3_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bit 23) */
\r
1824 #define PCR_RST_EN_3_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR RST_EN_3: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */
\r
1825 #define PCR_RST_EN_3_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bit 24) */
\r
1826 #define PCR_RST_EN_3_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR RST_EN_3: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1827 #define PCR_RST_EN_3_LED3_RST_EN_Pos (25UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bit 25) */
\r
1828 #define PCR_RST_EN_3_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR RST_EN_3: LED3_RST_EN (Bitfield-Mask: 0x01) */
\r
1829 #define PCR_RST_EN_3_PKE_RST_EN_Pos (26UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bit 26) */
\r
1830 #define PCR_RST_EN_3_PKE_RST_EN_Msk (0x4000000UL) /*!< PCR RST_EN_3: PKE_RST_EN (Bitfield-Mask: 0x01) */
\r
1831 #define PCR_RST_EN_3_RNG_RST_EN_Pos (27UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bit 27) */
\r
1832 #define PCR_RST_EN_3_RNG_RST_EN_Msk (0x8000000UL) /*!< PCR RST_EN_3: RNG_RST_EN (Bitfield-Mask: 0x01) */
\r
1833 #define PCR_RST_EN_3_AES_HASH_RST_EN_Pos (28UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bit 28) */
\r
1834 #define PCR_RST_EN_3_AES_HASH_RST_EN_Msk (0x10000000UL) /*!< PCR RST_EN_3: AES_HASH_RST_EN (Bitfield-Mask: 0x01) */
\r
1835 #define PCR_RST_EN_3_HTIMER_1_RST_EN_Pos (29UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bit 29) */
\r
1836 #define PCR_RST_EN_3_HTIMER_1_RST_EN_Msk (0x20000000UL) /*!< PCR RST_EN_3: HTIMER_1_RST_EN (Bitfield-Mask: 0x01) */
\r
1837 #define PCR_RST_EN_3_CCTIMER_RST_EN_Pos (30UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bit 30) */
\r
1838 #define PCR_RST_EN_3_CCTIMER_RST_EN_Msk (0x40000000UL) /*!< PCR RST_EN_3: CCTIMER_RST_EN (Bitfield-Mask: 0x01) */
\r
1839 #define PCR_RST_EN_3_PWM9_RST_EN_Pos (31UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bit 31) */
\r
1840 #define PCR_RST_EN_3_PWM9_RST_EN_Msk (0x80000000UL) /*!< PCR RST_EN_3: PWM9_RST_EN (Bitfield-Mask: 0x01) */
\r
1842 /* -------------------------------- PCR_RST_EN_4 -------------------------------- */
\r
1843 #define PCR_RST_EN_4_PWM10_RST_EN_Pos (0UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bit 0) */
\r
1844 #define PCR_RST_EN_4_PWM10_RST_EN_Msk (0x1UL) /*!< PCR RST_EN_4: PWM10_RST_EN (Bitfield-Mask: 0x01) */
\r
1845 #define PCR_RST_EN_4_PWM11_RST_EN_Pos (1UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bit 1) */
\r
1846 #define PCR_RST_EN_4_PWM11_RST_EN_Msk (0x2UL) /*!< PCR RST_EN_4: PWM11_RST_EN (Bitfield-Mask: 0x01) */
\r
1847 #define PCR_RST_EN_4_CNT_TMER0_RST_EN_Pos (2UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bit 2) */
\r
1848 #define PCR_RST_EN_4_CNT_TMER0_RST_EN_Msk (0x4UL) /*!< PCR RST_EN_4: CNT_TMER0_RST_EN (Bitfield-Mask: 0x01) */
\r
1849 #define PCR_RST_EN_4_CNT_TMER1_RST_EN_Pos (3UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bit 3) */
\r
1850 #define PCR_RST_EN_4_CNT_TMER1_RST_EN_Msk (0x8UL) /*!< PCR RST_EN_4: CNT_TMER1_RST_EN (Bitfield-Mask: 0x01) */
\r
1851 #define PCR_RST_EN_4_CNT_TMER2_RST_EN_Pos (4UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bit 4) */
\r
1852 #define PCR_RST_EN_4_CNT_TMER2_RST_EN_Msk (0x10UL) /*!< PCR RST_EN_4: CNT_TMER2_RST_EN (Bitfield-Mask: 0x01) */
\r
1853 #define PCR_RST_EN_4_CNT_TMER3_RST_EN_Pos (5UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bit 5) */
\r
1854 #define PCR_RST_EN_4_CNT_TMER3_RST_EN_Msk (0x20UL) /*!< PCR RST_EN_4: CNT_TMER3_RST_EN (Bitfield-Mask: 0x01) */
\r
1855 #define PCR_RST_EN_4_RTOS_RST_EN_Pos (6UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bit 6) */
\r
1856 #define PCR_RST_EN_4_RTOS_RST_EN_Msk (0x40UL) /*!< PCR RST_EN_4: RTOS_RST_EN (Bitfield-Mask: 0x01) */
\r
1857 #define PCR_RST_EN_4_RPMPWM1_RST_EN_Pos (7UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bit 7) */
\r
1858 #define PCR_RST_EN_4_RPMPWM1_RST_EN_Msk (0x80UL) /*!< PCR RST_EN_4: RPMPWM1_RST_EN (Bitfield-Mask: 0x01) */
\r
1859 #define PCR_RST_EN_4_QSPI_RST_EN_Pos (8UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bit 8) */
\r
1860 #define PCR_RST_EN_4_QSPI_RST_EN_Msk (0x100UL) /*!< PCR RST_EN_4: QSPI_RST_EN (Bitfield-Mask: 0x01) */
\r
1861 #define PCR_RST_EN_4_BCM1_RST_EN_Pos (9UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bit 9) */
\r
1862 #define PCR_RST_EN_4_BCM1_RST_EN_Msk (0x200UL) /*!< PCR RST_EN_4: BCM1_RST_EN (Bitfield-Mask: 0x01) */
\r
1863 #define PCR_RST_EN_4_RC_ID0_RST_EN_Pos (10UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bit 10) */
\r
1864 #define PCR_RST_EN_4_RC_ID0_RST_EN_Msk (0x400UL) /*!< PCR RST_EN_4: RC_ID0_RST_EN (Bitfield-Mask: 0x01) */
\r
1865 #define PCR_RST_EN_4_RC_ID1_RST_EN_Pos (11UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bit 11) */
\r
1866 #define PCR_RST_EN_4_RC_ID1_RST_EN_Msk (0x800UL) /*!< PCR RST_EN_4: RC_ID1_RST_EN (Bitfield-Mask: 0x01) */
\r
1867 #define PCR_RST_EN_4_RC_ID2_RST_EN_Pos (12UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bit 12) */
\r
1868 #define PCR_RST_EN_4_RC_ID2_RST_EN_Msk (0x1000UL) /*!< PCR RST_EN_4: RC_ID2_RST_EN (Bitfield-Mask: 0x01) */
\r
1869 #define PCR_RST_EN_4_FCL_RST_EN_Pos (15UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bit 15) */
\r
1870 #define PCR_RST_EN_4_FCL_RST_EN_Msk (0x8000UL) /*!< PCR RST_EN_4: FCL_RST_EN (Bitfield-Mask: 0x01) */
\r
1873 /* ================================================================================ */
\r
1874 /* ================ struct 'INTS' Position & Mask ================ */
\r
1875 /* ================================================================================ */
\r
1878 /* ---------------------------- INTS_BLOCK_ENABLE_SET --------------------------- */
\r
1879 #define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Pos (0UL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bit 0) */
\r
1880 #define INTS_BLOCK_ENABLE_SET_IRQ_VECTOR_ENABLE_SET_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_SET: IRQ_VECTOR_ENABLE_SET (Bitfield-Mask: 0x7fffffff) */
\r
1882 /* --------------------------- INTS_BLOCK_ENABLE_CLEAR -------------------------- */
\r
1883 #define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Pos (0UL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bit 0) */
\r
1884 #define INTS_BLOCK_ENABLE_CLEAR_IRQ_VECTOR_ENABLE_CLEAR_Msk (0x7fffffffUL) /*!< INTS BLOCK_ENABLE_CLEAR: IRQ_VECTOR_ENABLE_CLEAR (Bitfield-Mask: 0x7fffffff) */
\r
1886 /* ---------------------------- INTS_BLOCK_IRQ_VECTOR --------------------------- */
\r
1887 #define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Pos (0UL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bit 0) */
\r
1888 #define INTS_BLOCK_IRQ_VECTOR_IRQ_VECTOR_Msk (0x1ffffffUL) /*!< INTS BLOCK_IRQ_VECTOR: IRQ_VECTOR (Bitfield-Mask: 0x1ffffff) */
\r
1891 /* ================================================================================ */
\r
1892 /* ================ struct 'WDT' Position & Mask ================ */
\r
1893 /* ================================================================================ */
\r
1896 /* ------------------------------- WDT_WDT_CONTROL ------------------------------ */
\r
1897 #define WDT_WDT_CONTROL_WDT_ENABLE_Pos (0UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bit 0) */
\r
1898 #define WDT_WDT_CONTROL_WDT_ENABLE_Msk (0x1UL) /*!< WDT WDT_CONTROL: WDT_ENABLE (Bitfield-Mask: 0x01) */
\r
1899 #define WDT_WDT_CONTROL_WDT_STATUS_Pos (1UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bit 1) */
\r
1900 #define WDT_WDT_CONTROL_WDT_STATUS_Msk (0x2UL) /*!< WDT WDT_CONTROL: WDT_STATUS (Bitfield-Mask: 0x01) */
\r
1901 #define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Pos (2UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bit 2) */
\r
1902 #define WDT_WDT_CONTROL_HIBERNATION_TIMER0_STALL_Msk (0x4UL) /*!< WDT WDT_CONTROL: HIBERNATION_TIMER0_STALL (Bitfield-Mask: 0x01) */
\r
1903 #define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Pos (3UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bit 3) */
\r
1904 #define WDT_WDT_CONTROL_WEEK_TIMER_STALL_Msk (0x8UL) /*!< WDT WDT_CONTROL: WEEK_TIMER_STALL (Bitfield-Mask: 0x01) */
\r
1905 #define WDT_WDT_CONTROL_JTAG_STALL_Pos (4UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bit 4) */
\r
1906 #define WDT_WDT_CONTROL_JTAG_STALL_Msk (0x10UL) /*!< WDT WDT_CONTROL: JTAG_STALL (Bitfield-Mask: 0x01) */
\r
1909 /* ================================================================================ */
\r
1910 /* ================ struct 'TIMER0' Position & Mask ================ */
\r
1911 /* ================================================================================ */
\r
1914 /* -------------------------------- TIMER0_STATUS ------------------------------- */
\r
1915 #define TIMER0_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
1916 #define TIMER0_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER0 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
1918 /* -------------------------------- TIMER0_INT_EN ------------------------------- */
\r
1919 #define TIMER0_INT_EN_ENABLE_Pos (0UL) /*!< TIMER0 INT_EN: ENABLE (Bit 0) */
\r
1920 #define TIMER0_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER0 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
1922 /* ------------------------------- TIMER0_CONTROL ------------------------------- */
\r
1923 #define TIMER0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER0 CONTROL: ENABLE (Bit 0) */
\r
1924 #define TIMER0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
1925 #define TIMER0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER0 CONTROL: COUNT_UP (Bit 2) */
\r
1926 #define TIMER0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
1927 #define TIMER0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bit 3) */
\r
1928 #define TIMER0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
1929 #define TIMER0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bit 4) */
\r
1930 #define TIMER0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
1931 #define TIMER0_CONTROL_START_Pos (5UL) /*!< TIMER0 CONTROL: START (Bit 5) */
\r
1932 #define TIMER0_CONTROL_START_Msk (0x20UL) /*!< TIMER0 CONTROL: START (Bitfield-Mask: 0x01) */
\r
1933 #define TIMER0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER0 CONTROL: RELOAD (Bit 6) */
\r
1934 #define TIMER0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
1935 #define TIMER0_CONTROL_HALT_Pos (7UL) /*!< TIMER0 CONTROL: HALT (Bit 7) */
\r
1936 #define TIMER0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER0 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
1937 #define TIMER0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bit 16) */
\r
1938 #define TIMER0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
1941 /* ================================================================================ */
\r
1942 /* ================ struct 'TIMER1' Position & Mask ================ */
\r
1943 /* ================================================================================ */
\r
1946 /* -------------------------------- TIMER1_STATUS ------------------------------- */
\r
1947 #define TIMER1_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
1948 #define TIMER1_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER1 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
1950 /* -------------------------------- TIMER1_INT_EN ------------------------------- */
\r
1951 #define TIMER1_INT_EN_ENABLE_Pos (0UL) /*!< TIMER1 INT_EN: ENABLE (Bit 0) */
\r
1952 #define TIMER1_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER1 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
1954 /* ------------------------------- TIMER1_CONTROL ------------------------------- */
\r
1955 #define TIMER1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER1 CONTROL: ENABLE (Bit 0) */
\r
1956 #define TIMER1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
1957 #define TIMER1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER1 CONTROL: COUNT_UP (Bit 2) */
\r
1958 #define TIMER1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
1959 #define TIMER1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bit 3) */
\r
1960 #define TIMER1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
1961 #define TIMER1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bit 4) */
\r
1962 #define TIMER1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
1963 #define TIMER1_CONTROL_START_Pos (5UL) /*!< TIMER1 CONTROL: START (Bit 5) */
\r
1964 #define TIMER1_CONTROL_START_Msk (0x20UL) /*!< TIMER1 CONTROL: START (Bitfield-Mask: 0x01) */
\r
1965 #define TIMER1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER1 CONTROL: RELOAD (Bit 6) */
\r
1966 #define TIMER1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
1967 #define TIMER1_CONTROL_HALT_Pos (7UL) /*!< TIMER1 CONTROL: HALT (Bit 7) */
\r
1968 #define TIMER1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER1 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
1969 #define TIMER1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bit 16) */
\r
1970 #define TIMER1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
1973 /* ================================================================================ */
\r
1974 /* ================ struct 'TIMER2' Position & Mask ================ */
\r
1975 /* ================================================================================ */
\r
1978 /* -------------------------------- TIMER2_STATUS ------------------------------- */
\r
1979 #define TIMER2_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
1980 #define TIMER2_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER2 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
1982 /* -------------------------------- TIMER2_INT_EN ------------------------------- */
\r
1983 #define TIMER2_INT_EN_ENABLE_Pos (0UL) /*!< TIMER2 INT_EN: ENABLE (Bit 0) */
\r
1984 #define TIMER2_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER2 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
1986 /* ------------------------------- TIMER2_CONTROL ------------------------------- */
\r
1987 #define TIMER2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER2 CONTROL: ENABLE (Bit 0) */
\r
1988 #define TIMER2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
1989 #define TIMER2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER2 CONTROL: COUNT_UP (Bit 2) */
\r
1990 #define TIMER2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
1991 #define TIMER2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bit 3) */
\r
1992 #define TIMER2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
1993 #define TIMER2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bit 4) */
\r
1994 #define TIMER2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
1995 #define TIMER2_CONTROL_START_Pos (5UL) /*!< TIMER2 CONTROL: START (Bit 5) */
\r
1996 #define TIMER2_CONTROL_START_Msk (0x20UL) /*!< TIMER2 CONTROL: START (Bitfield-Mask: 0x01) */
\r
1997 #define TIMER2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER2 CONTROL: RELOAD (Bit 6) */
\r
1998 #define TIMER2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
1999 #define TIMER2_CONTROL_HALT_Pos (7UL) /*!< TIMER2 CONTROL: HALT (Bit 7) */
\r
2000 #define TIMER2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER2 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
2001 #define TIMER2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bit 16) */
\r
2002 #define TIMER2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
2005 /* ================================================================================ */
\r
2006 /* ================ struct 'TIMER3' Position & Mask ================ */
\r
2007 /* ================================================================================ */
\r
2010 /* -------------------------------- TIMER3_STATUS ------------------------------- */
\r
2011 #define TIMER3_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
2012 #define TIMER3_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER3 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
2014 /* -------------------------------- TIMER3_INT_EN ------------------------------- */
\r
2015 #define TIMER3_INT_EN_ENABLE_Pos (0UL) /*!< TIMER3 INT_EN: ENABLE (Bit 0) */
\r
2016 #define TIMER3_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER3 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
2018 /* ------------------------------- TIMER3_CONTROL ------------------------------- */
\r
2019 #define TIMER3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER3 CONTROL: ENABLE (Bit 0) */
\r
2020 #define TIMER3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
2021 #define TIMER3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER3 CONTROL: COUNT_UP (Bit 2) */
\r
2022 #define TIMER3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
2023 #define TIMER3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bit 3) */
\r
2024 #define TIMER3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
2025 #define TIMER3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bit 4) */
\r
2026 #define TIMER3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2027 #define TIMER3_CONTROL_START_Pos (5UL) /*!< TIMER3 CONTROL: START (Bit 5) */
\r
2028 #define TIMER3_CONTROL_START_Msk (0x20UL) /*!< TIMER3 CONTROL: START (Bitfield-Mask: 0x01) */
\r
2029 #define TIMER3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER3 CONTROL: RELOAD (Bit 6) */
\r
2030 #define TIMER3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
2031 #define TIMER3_CONTROL_HALT_Pos (7UL) /*!< TIMER3 CONTROL: HALT (Bit 7) */
\r
2032 #define TIMER3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER3 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
2033 #define TIMER3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bit 16) */
\r
2034 #define TIMER3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
2037 /* ================================================================================ */
\r
2038 /* ================ struct 'TIMER4' Position & Mask ================ */
\r
2039 /* ================================================================================ */
\r
2042 /* -------------------------------- TIMER4_STATUS ------------------------------- */
\r
2043 #define TIMER4_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
2044 #define TIMER4_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER4 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
2046 /* -------------------------------- TIMER4_INT_EN ------------------------------- */
\r
2047 #define TIMER4_INT_EN_ENABLE_Pos (0UL) /*!< TIMER4 INT_EN: ENABLE (Bit 0) */
\r
2048 #define TIMER4_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER4 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
2050 /* ------------------------------- TIMER4_CONTROL ------------------------------- */
\r
2051 #define TIMER4_CONTROL_ENABLE_Pos (0UL) /*!< TIMER4 CONTROL: ENABLE (Bit 0) */
\r
2052 #define TIMER4_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER4 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
2053 #define TIMER4_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER4 CONTROL: COUNT_UP (Bit 2) */
\r
2054 #define TIMER4_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER4 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
2055 #define TIMER4_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bit 3) */
\r
2056 #define TIMER4_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER4 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
2057 #define TIMER4_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bit 4) */
\r
2058 #define TIMER4_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER4 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2059 #define TIMER4_CONTROL_START_Pos (5UL) /*!< TIMER4 CONTROL: START (Bit 5) */
\r
2060 #define TIMER4_CONTROL_START_Msk (0x20UL) /*!< TIMER4 CONTROL: START (Bitfield-Mask: 0x01) */
\r
2061 #define TIMER4_CONTROL_RELOAD_Pos (6UL) /*!< TIMER4 CONTROL: RELOAD (Bit 6) */
\r
2062 #define TIMER4_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER4 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
2063 #define TIMER4_CONTROL_HALT_Pos (7UL) /*!< TIMER4 CONTROL: HALT (Bit 7) */
\r
2064 #define TIMER4_CONTROL_HALT_Msk (0x80UL) /*!< TIMER4 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
2065 #define TIMER4_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bit 16) */
\r
2066 #define TIMER4_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER4 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
2069 /* ================================================================================ */
\r
2070 /* ================ struct 'TIMER5' Position & Mask ================ */
\r
2071 /* ================================================================================ */
\r
2074 /* -------------------------------- TIMER5_STATUS ------------------------------- */
\r
2075 #define TIMER5_STATUS_EVENT_INTERRUPT_Pos (0UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bit 0) */
\r
2076 #define TIMER5_STATUS_EVENT_INTERRUPT_Msk (0x1UL) /*!< TIMER5 STATUS: EVENT_INTERRUPT (Bitfield-Mask: 0x01) */
\r
2078 /* -------------------------------- TIMER5_INT_EN ------------------------------- */
\r
2079 #define TIMER5_INT_EN_ENABLE_Pos (0UL) /*!< TIMER5 INT_EN: ENABLE (Bit 0) */
\r
2080 #define TIMER5_INT_EN_ENABLE_Msk (0x1UL) /*!< TIMER5 INT_EN: ENABLE (Bitfield-Mask: 0x01) */
\r
2082 /* ------------------------------- TIMER5_CONTROL ------------------------------- */
\r
2083 #define TIMER5_CONTROL_ENABLE_Pos (0UL) /*!< TIMER5 CONTROL: ENABLE (Bit 0) */
\r
2084 #define TIMER5_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER5 CONTROL: ENABLE (Bitfield-Mask: 0x01) */
\r
2085 #define TIMER5_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER5 CONTROL: COUNT_UP (Bit 2) */
\r
2086 #define TIMER5_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER5 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */
\r
2087 #define TIMER5_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bit 3) */
\r
2088 #define TIMER5_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER5 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */
\r
2089 #define TIMER5_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bit 4) */
\r
2090 #define TIMER5_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER5 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2091 #define TIMER5_CONTROL_START_Pos (5UL) /*!< TIMER5 CONTROL: START (Bit 5) */
\r
2092 #define TIMER5_CONTROL_START_Msk (0x20UL) /*!< TIMER5 CONTROL: START (Bitfield-Mask: 0x01) */
\r
2093 #define TIMER5_CONTROL_RELOAD_Pos (6UL) /*!< TIMER5 CONTROL: RELOAD (Bit 6) */
\r
2094 #define TIMER5_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER5 CONTROL: RELOAD (Bitfield-Mask: 0x01) */
\r
2095 #define TIMER5_CONTROL_HALT_Pos (7UL) /*!< TIMER5 CONTROL: HALT (Bit 7) */
\r
2096 #define TIMER5_CONTROL_HALT_Msk (0x80UL) /*!< TIMER5 CONTROL: HALT (Bitfield-Mask: 0x01) */
\r
2097 #define TIMER5_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bit 16) */
\r
2098 #define TIMER5_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER5 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */
\r
2101 /* ================================================================================ */
\r
2102 /* ================ struct 'EC_REG_BANK' Position & Mask ================ */
\r
2103 /* ================================================================================ */
\r
2106 /* -------------------------- EC_REG_BANK_DEBUG_Enable -------------------------- */
\r
2107 #define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Pos (0UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bit 0) */
\r
2108 #define EC_REG_BANK_DEBUG_Enable_DEBUG_EN_Msk (0x1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_EN (Bitfield-Mask: 0x01) */
\r
2109 #define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Pos (1UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bit 1) */
\r
2110 #define EC_REG_BANK_DEBUG_Enable_DEBUG_PIN_CFG_Msk (0x6UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PIN_CFG (Bitfield-Mask: 0x03) */
\r
2111 #define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Pos (3UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bit 3) */
\r
2112 #define EC_REG_BANK_DEBUG_Enable_DEBUG_PU_EN_Msk (0x8UL) /*!< EC_REG_BANK DEBUG_Enable: DEBUG_PU_EN (Bitfield-Mask: 0x01) */
\r
2114 /* ------------------- EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL ------------------- */
\r
2115 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Pos (0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bit 0) */
\r
2116 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BYTE_SWAP_ENABLE_Msk (0x1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */
\r
2117 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Pos (1UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bit 1) */
\r
2118 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BYTE_SWAP_ENABLE_Msk (0x2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BYTE_SWAP_ENABLE (Bitfield-Mask: 0x01) */
\r
2119 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Pos (2UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bit 2) */
\r
2120 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_INPUT_BLOCK_SWAP_ENABLE_Msk (0x1cUL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: INPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */
\r
2121 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Pos (5UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bit 5) */
\r
2122 #define EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL_OUTPUT_BLOCK_SWAP_ENABLE_Msk (0xe0UL) /*!< EC_REG_BANK AES_HASH_BYTE_SWAP_CONTROL: OUTPUT_BLOCK_SWAP_ENABLE (Bitfield-Mask: 0x07) */
\r
2124 /* ---------------------- EC_REG_BANK_SYSTEM_SHUTDOWN_RESET --------------------- */
\r
2125 #define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Pos (0UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bit 0) */
\r
2126 #define EC_REG_BANK_SYSTEM_SHUTDOWN_RESET_SYS_SHDN_RST_Msk (0x1UL) /*!< EC_REG_BANK SYSTEM_SHUTDOWN_RESET: SYS_SHDN_RST (Bitfield-Mask: 0x01) */
\r
2128 /* ---------------------------- EC_REG_BANK_MISC_TRIM --------------------------- */
\r
2129 #define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Pos (0UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bit 0) */
\r
2130 #define EC_REG_BANK_MISC_TRIM_PECI_DISABLE_Msk (0x1UL) /*!< EC_REG_BANK MISC_TRIM: PECI_DISABLE (Bitfield-Mask: 0x01) */
\r
2132 /* ------------------------ EC_REG_BANK_CRYPTO_SOFT_RESET ----------------------- */
\r
2133 #define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Pos (0UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bit 0) */
\r
2134 #define EC_REG_BANK_CRYPTO_SOFT_RESET_RNG_SOFT_RESET_Msk (0x1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: RNG_SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2135 #define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Pos (1UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bit 1) */
\r
2136 #define EC_REG_BANK_CRYPTO_SOFT_RESET_PUBLIC_KEY_SOFT_RESET_Msk (0x2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: PUBLIC_KEY_SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2137 #define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Pos (2UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bit 2) */
\r
2138 #define EC_REG_BANK_CRYPTO_SOFT_RESET_AES_HASH_SOFT_RESET_Msk (0x4UL) /*!< EC_REG_BANK CRYPTO_SOFT_RESET: AES_HASH_SOFT_RESET (Bitfield-Mask: 0x01) */
\r
2140 /* ------------------------- EC_REG_BANK_GPIO_BANK_POWER ------------------------ */
\r
2141 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Pos (0UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bit 0) */
\r
2142 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL1_Msk (0x1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL1 (Bitfield-Mask: 0x01) */
\r
2143 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Pos (1UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bit 1) */
\r
2144 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL2_Msk (0x2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL2 (Bitfield-Mask: 0x01) */
\r
2145 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Pos (2UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bit 2) */
\r
2146 #define EC_REG_BANK_GPIO_BANK_POWER_VTR_LEVEL3_Msk (0x4UL) /*!< EC_REG_BANK GPIO_BANK_POWER: VTR_LEVEL3 (Bitfield-Mask: 0x01) */
\r
2148 /* ------------------------- EC_REG_BANK_JTAG_MASTER_CFG ------------------------ */
\r
2149 #define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bit 0) */
\r
2150 #define EC_REG_BANK_JTAG_MASTER_CFG_JTM_CLK_Msk (0x7UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: JTM_CLK (Bitfield-Mask: 0x07) */
\r
2151 #define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Pos (3UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bit 3) */
\r
2152 #define EC_REG_BANK_JTAG_MASTER_CFG_MASTER_SLAVE_Msk (0x8UL) /*!< EC_REG_BANK JTAG_MASTER_CFG: MASTER_SLAVE (Bitfield-Mask: 0x01) */
\r
2154 /* ------------------------- EC_REG_BANK_JTAG_MASTER_STS ------------------------ */
\r
2155 #define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bit 0) */
\r
2156 #define EC_REG_BANK_JTAG_MASTER_STS_JTM_DONE_Msk (0x1UL) /*!< EC_REG_BANK JTAG_MASTER_STS: JTM_DONE (Bitfield-Mask: 0x01) */
\r
2158 /* ------------------------- EC_REG_BANK_JTAG_MASTER_TDO ------------------------ */
\r
2159 #define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bit 0) */
\r
2160 #define EC_REG_BANK_JTAG_MASTER_TDO_JTM_TDO_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDO: JTM_TDO (Bitfield-Mask: 0xffffffff) */
\r
2162 /* ------------------------- EC_REG_BANK_JTAG_MASTER_TDI ------------------------ */
\r
2163 #define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bit 0) */
\r
2164 #define EC_REG_BANK_JTAG_MASTER_TDI_JTM_TDI_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TDI: JTM_TDI (Bitfield-Mask: 0xffffffff) */
\r
2166 /* ------------------------- EC_REG_BANK_JTAG_MASTER_TMS ------------------------ */
\r
2167 #define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bit 0) */
\r
2168 #define EC_REG_BANK_JTAG_MASTER_TMS_JTM_TMS_Msk (0xffffffffUL) /*!< EC_REG_BANK JTAG_MASTER_TMS: JTM_TMS (Bitfield-Mask: 0xffffffff) */
\r
2170 /* ------------------------- EC_REG_BANK_JTAG_MASTER_CMD ------------------------ */
\r
2171 #define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Pos (0UL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bit 0) */
\r
2172 #define EC_REG_BANK_JTAG_MASTER_CMD_JTM_COUNT_Msk (0x1fUL) /*!< EC_REG_BANK JTAG_MASTER_CMD: JTM_COUNT (Bitfield-Mask: 0x1f) */
\r
2175 /* ================================================================================ */
\r
2176 /* ================ Peripheral memory map ================ */
\r
2177 /* ================================================================================ */
\r
2179 #define PCR_BASE 0x40080100UL
\r
2180 #define INTS_BASE 0x4000E000UL
\r
2181 #define TIMER0_BASE 0x40000C00UL
\r
2182 #define TIMER1_BASE 0x40000C20UL
\r
2183 #define TIMER2_BASE 0x40000C40UL
\r
2184 #define TIMER3_BASE 0x40000C60UL
\r
2185 #define TIMER4_BASE 0x40000C80UL
\r
2186 #define TIMER5_BASE 0x40000CA0UL
\r
2187 #define EC_REG_BANK_BASE 0x4000FC00UL
\r
2190 /* ================================================================================ */
\r
2191 /* ================ Peripheral declaration ================ */
\r
2192 /* ================================================================================ */
\r
2194 #define MEC2016_PCR ((PCR_Type *) PCR_BASE)
\r
2195 #define MEC2016_INTS ((INTS_Type *) INTS_BASE)
\r
2196 #define MEC2016_TIMER0 ((TIMER0_Type *) TIMER0_BASE)
\r
2197 #define MEC2016_TIMER1 ((TIMER0_Type *) TIMER1_BASE)
\r
2198 #define MEC2016_TIMER2 ((TIMER0_Type *) TIMER2_BASE)
\r
2199 #define MEC2016_TIMER3 ((TIMER0_Type *) TIMER3_BASE)
\r
2200 #define MEC2016_TIMER4 ((TIMER0_Type *) TIMER4_BASE)
\r
2201 #define MEC2016_TIMER5 ((TIMER0_Type *) TIMER5_BASE)
\r
2202 #define MEC2016_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)
\r
2204 /** @} */ /* End of group Device_Peripheral_Registers */
\r
2205 /** @} */ /* End of group MCHP_device_internal */
\r
2206 /** @} */ /* End of group Microchip Technology Inc. */
\r
2208 #ifdef __cplusplus
\r
2213 #endif /* MCHP_device_internal_H */
\r
projects / freertos / blob