sunxi: Also set Auxiliary Ctl SMP bit in SPL

There is no reason not to and this make the #ifdef-ery easier to read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index c1b4cf5c2f9125b0c464c1e7758dec27b99e20ff..6471c6b7b2aab12740081f695dc17639023a4f13 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -94,8 +94,9 @@ void s_init(void)
         * access gets messed up (seems cache related) */
        setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
-               defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+#if defined CONFIG_MACH_SUN6I || \
+    defined CONFIG_MACH_SUN7I || \
+    defined CONFIG_MACH_SUN8I
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
        asm volatile(
                "mrc p15, 0, r0, c1, c0, 1\n"