wait_for_lock(base);
 }
 
-void setup_clocks_for_console(void)
+static void setup_clocks_for_console(void)
 {
        /* Do not add any spl_debug prints in this function */
        clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
                disable_clock_domain(clk_domains[i]);
 }
 
-void prcm_init(void)
+/**
+ * setup_early_clocks() - Setup early clocks needed for SoC
+ *
+ * Setup clocks for console, SPL basic initialization clocks and initialize
+ * the timer. This is invoked prior prcm_init.
+ */
+void setup_early_clocks(void)
 {
        switch (omap_hw_init_context()) {
        case OMAP_INIT_CONTEXT_SPL:
        case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
        case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+               setup_clocks_for_console();
                enable_basic_clocks();
                timer_init();
+               /* Fall through */
+       }
+}
+
+void prcm_init(void)
+{
+       switch (omap_hw_init_context()) {
+       case OMAP_INIT_CONTEXT_SPL:
+       case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+       case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
                scale_vcores(*omap_vcores);
                setup_dplls();
                setup_warmreset_time();
 
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);