qspi_write32(priv->flags, ®s->mcr, mcr_reg);
 }
 
-static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf)
+static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 {
        struct fsl_qspi_regs *regs = priv->regs;
        u32 mcr_reg, reg, data;
                if (reg & QSPI_RBSR_RDBFL_MASK) {
                        data = qspi_read32(priv->flags, ®s->rbdr[0]);
                        data = qspi_endian_xchg(data);
-                       memcpy(rxbuf, &data, 4);
+                       memcpy(rxbuf, &data, len);
                        qspi_write32(priv->flags, ®s->mcr,
                                     qspi_read32(priv->flags, ®s->mcr) |
                                     QSPI_MCR_CLR_RXF_MASK);
                } else if (priv->cur_seqid == QSPI_CMD_RDID)
                        qspi_op_rdid(priv, din, bytes);
                else if (priv->cur_seqid == QSPI_CMD_RDSR)
-                       qspi_op_rdsr(priv, din);
+                       qspi_op_rdsr(priv, din, bytes);
 #ifdef CONFIG_SPI_FLASH_BAR
                else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
                         (priv->cur_seqid == QSPI_CMD_RDEAR)) {