#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
+#define DRA762_ABZ_PACKAGE 0x2
+#define DRA762_ACD_PACKAGE 0x3
+
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
u32 cortex_rev(void);
void save_omap_boot_params(void);
void init_omap_revision(void);
+void init_package_revision(void);
void do_io_settings(void);
void sri2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA76X;
}
+
+static inline u8 is_dra76x_abz(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xF) == 3;
+}
#endif
/*
#define DRA722_ES2_0 0x07220200
#define DRA722_ES2_1 0x07220210
+#define DRA762_ABZ_ES1_0 0x07620102
+#define DRA762_ACD_ES1_0 0x07620103
/*
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- const char *sec_s;
+ const char *sec_s, *package = NULL;
switch (get_device_type()) {
case TST_DEVICE:
sec_s = "?";
}
+#if defined(CONFIG_DRA7XX)
+ if (is_dra76x()) {
+ switch (omap_rev & 0xF) {
+ case DRA762_ABZ_PACKAGE:
+ package = "ABZ";
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ package = "ACD";
+ break;
+ }
+ }
+#endif
+
if (soc_variant)
printf("OMAP");
else
printf("DRA");
- printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
+ printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
+ if (package)
+ printf(" %s package\n", package);
+ else
+ puts("\n");
}
#ifdef CONFIG_SPL_BUILD
{
}
+/**
+ * init_package_revision() - Initialize package revision
+ *
+ * Function to get the pacakage information. This is expected to be
+ * overridden in the SoC family file where desired.
+ */
+void __weak init_package_revision(void)
+{
+}
+
/**
* early_system_init - Does Early system initialization.
*
{
init_omap_revision();
hw_data_init();
+ init_package_revision();
#ifdef CONFIG_SPL_BUILD
if (warm_reset())
*ctrl = &omap5_ctrl;
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA762_ES1_0:
+ case DRA762_ACD_ES1_0:
+ case DRA762_ABZ_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
init_cpu_configuration();
}
+void init_package_revision(void)
+{
+ unsigned int die_id[4] = { 0 };
+ u8 package;
+
+ omap_die_id(die_id);
+ package = (die_id[2] >> 16) & 0x3;
+
+ if (is_dra76x()) {
+ switch (package) {
+ case DRA762_ABZ_PACKAGE:
+ *omap_si_rev = DRA762_ABZ_ES1_0;
+ break;
+ case DRA762_ACD_PACKAGE:
+ default:
+ *omap_si_rev = DRA762_ACD_ES1_0;
+ break;
+ }
+ }
+}
+
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
case DRA762_ES1_0:
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA722_ES2_0:
case DRA722_ES2_1:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
break;
}
break;
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
if (emif_nr == 1)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
+ case DRA762_ABZ_ES1_0:
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
name = "dra71x";
else
name = "dra72x";
- } else if (is_dra76x()) {
- name = "dra76x";
+ } else if (is_dra76x_abz()) {
+ name = "dra76x_abz";
+ } else if (is_dra76x_acd()) {
+ name = "dra76x_acd";
} else {
name = "dra7xx";
}
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
+ case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
pads = dra76x_core_padconf_array;
npads = ARRAY_SIZE(dra76x_core_padconf_array);
break;
default:
case DRA752_ES2_0:
+ case DRA762_ABZ_ES1_0:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
- } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+ } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
return 0;
- } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
+ } else if (!is_dra72x() && !is_dra76x_acd() &&
+ !strcmp(name, "dra7-evm")) {
return 0;
}