]> git.sur5r.net Git - u-boot/commitdiff
arm: dra762: Add support for device package identification
authorLokesh Vutla <lokeshvutla@ti.com>
Fri, 29 Dec 2017 06:17:51 +0000 (11:47 +0530)
committerTom Rini <trini@konsulko.com>
Fri, 19 Jan 2018 20:49:26 +0000 (15:49 -0500)
DRA762 comes in two packages:
- ABZ: Pin compatible package with DRA742 with DDR@1333MHz
- ACD: High performance(OPP_PLUS) package with new IPs

Both the above packages uses the same IDCODE hence needs to
differentiate using package information in DIE_ID_2.
Add support for the same. Also update clock, ddr, emif information.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/omap_common.h
arch/arm/mach-omap2/hwinit-common.c
arch/arm/mach-omap2/omap5/hw_data.c
arch/arm/mach-omap2/omap5/hwinit.c
arch/arm/mach-omap2/omap5/sdram.c
board/ti/dra7xx/evm.c

index 81feac704aae5b34cf86c10fcea608c699e17083..f8e7f06442970fbd0d1a0647d963f4b52e1da836 100644 (file)
@@ -66,6 +66,9 @@
 #define DRA722_CONTROL_ID_CODE_ES2_0           0x1B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_1           0x2B9BC02F
 
+#define DRA762_ABZ_PACKAGE                     0x2
+#define DRA762_ACD_PACKAGE                     0x3
+
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE             (OMAP54XX_L4_PER_BASE + 0x6c000)
index ab0e7fae9c7276b7ce0b5a18107f0f98cdf0d859..a6b3557b503bc376930c108b678881ecea7fdc65 100644 (file)
@@ -62,6 +62,7 @@ u32 omap_sdram_size(void);
 u32 cortex_rev(void);
 void save_omap_boot_params(void);
 void init_omap_revision(void);
+void init_package_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
index 481e9389c455a6a1e0cd114542af776f3649b74d..9624fb81fa559fbff529401df2efee7abb021f8e 100644 (file)
@@ -743,6 +743,18 @@ static inline u8 is_dra76x(void)
        extern u32 *const omap_si_rev;
        return (*omap_si_rev & 0xFFF00000) == DRA76X;
 }
+
+static inline u8 is_dra76x_abz(void)
+{
+       extern u32 *const omap_si_rev;
+       return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+       extern u32 *const omap_si_rev;
+       return (*omap_si_rev & 0xF) == 3;
+}
 #endif
 
 /*
@@ -778,6 +790,8 @@ static inline u8 is_dra76x(void)
 #define DRA722_ES2_0   0x07220200
 #define DRA722_ES2_1   0x07220210
 
+#define DRA762_ABZ_ES1_0       0x07620102
+#define DRA762_ACD_ES1_0       0x07620103
 /*
  * silicon device type
  * Moving to common from cpu.h, since it is shared by various omap devices
index 56890a0c545caf215f16cc82c6248f044d5c519c..4f491e60f2d9de372ebf7ee69f6135e6b0da1352 100644 (file)
@@ -66,7 +66,7 @@ static void omap_rev_string(void)
        u32 major_rev = (omap_rev & 0x00000F00) >> 8;
        u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
-       const char *sec_s;
+       const char *sec_s, *package = NULL;
 
        switch (get_device_type()) {
        case TST_DEVICE:
@@ -85,11 +85,29 @@ static void omap_rev_string(void)
                sec_s = "?";
        }
 
+#if defined(CONFIG_DRA7XX)
+       if (is_dra76x()) {
+               switch (omap_rev & 0xF) {
+               case DRA762_ABZ_PACKAGE:
+                       package = "ABZ";
+                       break;
+               case DRA762_ACD_PACKAGE:
+               default:
+                       package = "ACD";
+                       break;
+               }
+       }
+#endif
+
        if (soc_variant)
                printf("OMAP");
        else
                printf("DRA");
-       printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
+       printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
+       if (package)
+               printf(" %s package\n", package);
+       else
+               puts("\n");
 }
 
 #ifdef CONFIG_SPL_BUILD
@@ -127,6 +145,16 @@ void s_init(void)
 {
 }
 
+/**
+ * init_package_revision() - Initialize package revision
+ *
+ * Function to get the pacakage information. This is expected to be
+ * overridden in the SoC family file where desired.
+ */
+void __weak init_package_revision(void)
+{
+}
+
 /**
  * early_system_init - Does Early system initialization.
  *
@@ -146,6 +174,7 @@ void early_system_init(void)
 {
        init_omap_revision();
        hw_data_init();
+       init_package_revision();
 
 #ifdef CONFIG_SPL_BUILD
        if (warm_reset())
index 3bdb114bb6bcd2afd8dcf371d0d5ac30554ef433..bb05e1920b962f8b0e4c2018f67a1d8459f309b7 100644 (file)
@@ -746,6 +746,8 @@ void __weak hw_data_init(void)
        *ctrl = &omap5_ctrl;
        break;
 
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
        case DRA762_ES1_0:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra76x_dplls;
@@ -792,6 +794,8 @@ void get_ioregs(const struct ctrl_ioregs **regs)
        case DRA752_ES1_1:
        case DRA752_ES2_0:
        case DRA762_ES1_0:
+       case DRA762_ACD_ES1_0:
+       case DRA762_ABZ_ES1_0:
                *regs = &ioregs_dra7xx_es1;
                break;
        case DRA722_ES1_0:
index 14a35dd284692eb50877d8f107354003e2434c0c..57f2a8664c8808ba8f0b01343bcbc3d6c472839d 100644 (file)
@@ -389,6 +389,27 @@ void init_omap_revision(void)
        init_cpu_configuration();
 }
 
+void init_package_revision(void)
+{
+       unsigned int die_id[4] = { 0 };
+       u8 package;
+
+       omap_die_id(die_id);
+       package = (die_id[2] >> 16) & 0x3;
+
+       if (is_dra76x()) {
+               switch (package) {
+               case DRA762_ABZ_PACKAGE:
+                       *omap_si_rev = DRA762_ABZ_ES1_0;
+                       break;
+               case DRA762_ACD_PACKAGE:
+               default:
+                       *omap_si_rev = DRA762_ACD_ES1_0;
+                       break;
+               }
+       }
+}
+
 void omap_die_id(unsigned int *die_id)
 {
        die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
index 8fb962e39dcb020a17935063a0aada77bdcf6d78..c0e0e0888c370fb62a7fccc00b746af587da8147 100644 (file)
@@ -481,6 +481,8 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
                break;
        case DRA762_ES1_0:
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
        case DRA722_ES2_0:
        case DRA722_ES2_1:
                *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
@@ -711,6 +713,8 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
                *iterations = sizeof(omap5_bug_00339_regs)/
                             sizeof(omap5_bug_00339_regs[0]);
                break;
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
        case DRA762_ES1_0:
        case DRA752_ES1_0:
        case DRA752_ES1_1:
index ddcbe31f0eed59fe13d024ab786eff53bc021e92..6ecf971a92bf789a246f4b83c37e0064555f8bf6 100644 (file)
@@ -285,6 +285,8 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
                        break;
                }
                break;
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
        case DRA762_ES1_0:
                if (emif_nr == 1)
                        *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
@@ -347,6 +349,8 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
        ram_size = board_ti_get_emif_size();
 
        switch (omap_revision()) {
+       case DRA762_ABZ_ES1_0:
+       case DRA762_ACD_ES1_0:
        case DRA762_ES1_0:
        case DRA752_ES1_0:
        case DRA752_ES1_1:
@@ -655,8 +659,10 @@ int board_late_init(void)
                        name = "dra71x";
                else
                        name = "dra72x";
-       } else if (is_dra76x()) {
-               name = "dra76x";
+       } else if (is_dra76x_abz()) {
+               name = "dra76x_abz";
+       } else if (is_dra76x_acd()) {
+               name = "dra76x_acd";
        } else {
                name = "dra7xx";
        }
@@ -793,6 +799,7 @@ void recalibrate_iodelay(void)
                iodelay = dra742_es1_1_iodelay_cfg_array;
                niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
                break;
+       case DRA762_ACD_ES1_0:
        case DRA762_ES1_0:
                pads = dra76x_core_padconf_array;
                npads = ARRAY_SIZE(dra76x_core_padconf_array);
@@ -801,6 +808,7 @@ void recalibrate_iodelay(void)
                break;
        default:
        case DRA752_ES2_0:
+       case DRA762_ABZ_ES1_0:
                pads = dra74x_core_padconf_array;
                npads = ARRAY_SIZE(dra74x_core_padconf_array);
                iodelay = dra742_es2_0_iodelay_cfg_array;
@@ -1130,9 +1138,10 @@ int board_fit_config_name_match(const char *name)
                } else if (!strcmp(name, "dra72-evm")) {
                        return 0;
                }
-       } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+       } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
                return 0;
-       } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
+       } else if (!is_dra72x() && !is_dra76x_acd() &&
+                  !strcmp(name, "dra7-evm")) {
                return 0;
        }