]> git.sur5r.net Git - u-boot/commitdiff
spi: ti_qspi: Fix baudrate divider calculation
authorVignesh R <vigneshr@ti.com>
Sat, 5 Nov 2016 10:35:16 +0000 (16:05 +0530)
committerTom Rini <trini@konsulko.com>
Sun, 13 Nov 2016 20:54:37 +0000 (15:54 -0500)
Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
drivers/spi/ti_qspi.c

index 52520dff6325ff3e298502c0bb09a0eb2f9a3171..da0488659049cd8f781838de0e6d813fa943ed2b 100644 (file)
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)
                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+       /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+       if (clk_div > QSPI_CLK_DIV_MAX)
+               clk_div = QSPI_CLK_DIV_MAX;
 
        debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);
-
-       /* assign clk_div values */
-       if (clk_div < 0)
-               clk_div = 0;
-       else if (clk_div > QSPI_CLK_DIV_MAX)
-               clk_div = QSPI_CLK_DIV_MAX;
-
-       /* enable SCLK */
+       /* enable SCLK and program the clk divider */
        writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }