powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support

Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

diff --git a/README b/README
index ca2d10f8ed804317aa7f4fa30c51e64448b58ac8..44cd65a52feb00fe15c4ea4f459092aa17a2783f 100644 (file)
--- a/README
+++ b/README
@@ -2653,6 +2653,10 @@ FIT uImage format:
                CONFIG_SPL_TEXT_BASE
                TEXT_BASE for linking the SPL binary.
 
+               CONFIG_SPL_RELOC_TEXT_BASE
+               Address to relocate to.  If unspecified, this is equal to
+               CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
                CONFIG_SPL_BSS_START_ADDR
                Link address for the BSS within the SPL binary.
 
@@ -2662,6 +2666,11 @@ FIT uImage format:
                CONFIG_SPL_STACK
                Adress of the start of the stack SPL will use
 
+               CONFIG_SPL_RELOC_STACK
+               Adress of the start of the stack SPL will use after
+               relocation.  If unspecified, this is equal to
+               CONFIG_SPL_STACK.
+
                CONFIG_SYS_SPL_MALLOC_START
                Starting address of the malloc pool used in SPL.
 

diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index 0dcf7d1ab17e7262fc1db420261acfb37743cef0..5b45d72f511252e838be98bbfe16b2fdc28f9b05 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y        += spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index aa39260ca7ed084589a444f52e9ac546dbdb0058..5b5b86c822e968db065913406700462d5f66af16 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -177,7 +177,7 @@ void board_gpio_init(void)
         */
 
        setbits_be32(&pgpio->gpdir, 0x02130000);
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
        /* init DDR3 reset signal */
        setbits_be32(&pgpio->gpdir, 0x00200000);
        setbits_be32(&pgpio->gpodr, 0x00200000);

diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
new file mode 100644 (file)
index 0000000..5c893ee
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+void sdram_init(void)
+{
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+       __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+       __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+       __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+       __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+
+       __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+       __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+       __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+
+       __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+       __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+       __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+
+       __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+       __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+       __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+       __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
+
+       /* Set, but do not enable the memory */
+       __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+       asm volatile("sync;isync");
+       udelay(500);
+
+       /* Let the controller go */
+       out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+       set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifndef CONFIG_QE
+       ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+#endif
+
+       /* initialize selected port with appropriate baud rate */
+       plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+       plat_ratio >>= 1;
+       gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                       gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+       puts("\nNAND boot... ");
+
+#ifndef CONFIG_QE
+       /* init DDR3 reset signal */
+       __raw_writel(0x02000000, &pgpio->gpdir);
+       __raw_writel(0x00200000, &pgpio->gpodr);
+       __raw_writel(0x00000000, &pgpio->gpdat);
+       udelay(1000);
+       __raw_writel(0x00200000, &pgpio->gpdat);
+       udelay(1000);
+       __raw_writel(0x00000000, &pgpio->gpdir);
+#endif
+
+       /* Initialize the DDR3 */
+       sdram_init();
+
+       /* copy code to RAM and jump to it - this should not return */
+       /* NOTE - code has to be copied out of NAND buffer before
+        * other blocks can be read.
+        */
+       relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       nand_boot();
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+       NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 6d2246387a6967b17644e2c39417723802a909e0..0873dd750f1d5e026fc7c99d7f9093508bbce33b 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
        /* W**G* - Flash/promjet, localbus */
        /* This will be changed to *I*G* after relocation to RAM. */
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
+#endif /* not SPL */
 
 #ifdef CONFIG_SYS_NAND_BASE
        /* *I*G - NAND */
@@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        /* *I*G - eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -108,7 +108,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif
-
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);