Merge branch 'master' of git://git.denx.de/u-boot-blackfin

diff --git a/Makefile b/Makefile
index c532e5b146d2ffefabb936e056aaefe29db5cba3..ecde92b4c1942e6fad3e5a6d51f88d9100dee880 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -348,7 +348,7 @@ $(obj)u-boot:               depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
 $(OBJS):       depend $(obj)include/autoconf.mk
                $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
 
-$(LIBS):       depend $(obj)include/autoconf.mk
+$(LIBS):       depend $(obj)include/autoconf.mk $(SUBDIRS)
                $(MAKE) -C $(dir $(subst $(obj),,$@))
 
 $(LIBBOARD):   depend $(LIBS) $(obj)include/autoconf.mk
@@ -2602,6 +2602,7 @@ at91sam9260ek_nandflash_config \
 at91sam9260ek_dataflash_cs0_config \
 at91sam9260ek_dataflash_cs1_config \
 at91sam9260ek_config   :       unconfig
+       @mkdir -p $(obj)include
        @if [ "$(findstring _nandflash,$@)" ] ; then \
                echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
                $(XECHO) "... with environment variable in NAND FLASH" ; \
@@ -2614,10 +2615,28 @@ at91sam9260ek_config    :       unconfig
        fi;
        @$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
 
+at91sam9xeek_nandflash_config \
+at91sam9xeek_dataflash_cs0_config \
+at91sam9xeek_dataflash_cs1_config \
+at91sam9xeek_config    :       unconfig
+       @mkdir -p $(obj)include
+       @if [ "$(findstring _nandflash,$@)" ] ; then \
+               echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
+               $(XECHO) "... with environment variable in NAND FLASH" ; \
+       elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+               echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"   >>$(obj)include/config.h ; \
+               $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+       else \
+               echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"   >>$(obj)include/config.h ; \
+               $(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+       fi;
+       @$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
+
 at91sam9261ek_nandflash_config \
 at91sam9261ek_dataflash_cs0_config \
 at91sam9261ek_dataflash_cs3_config \
 at91sam9261ek_config   :       unconfig
+       @mkdir -p $(obj)include
        @if [ "$(findstring _nandflash,$@)" ] ; then \
                echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
                $(XECHO) "... with environment variable in NAND FLASH" ; \
@@ -2634,6 +2653,7 @@ at91sam9263ek_nandflash_config \
 at91sam9263ek_dataflash_config \
 at91sam9263ek_dataflash_cs0_config \
 at91sam9263ek_config   :       unconfig
+       @mkdir -p $(obj)include
        @if [ "$(findstring _nandflash,$@)" ] ; then \
                echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
                $(XECHO) "... with environment variable in NAND FLASH" ; \
@@ -2647,6 +2667,7 @@ at91sam9rlek_nandflash_config \
 at91sam9rlek_dataflash_config \
 at91sam9rlek_dataflash_cs0_config \
 at91sam9rlek_config    :       unconfig
+       @mkdir -p $(obj)include
        @if [ "$(findstring _nandflash,$@)" ] ; then \
                echo "#define CONFIG_SYS_USE_NANDFLASH 1"       >>$(obj)include/config.h ; \
                $(XECHO) "... with environment variable in NAND FLASH" ; \

diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile
index c562c600a412f8286a3b6d8722adba180d0b8153..aec3d1c7c0705de8950e46b05ccd5b48e0d37fac 100644 (file)
--- a/board/m501sk/Makefile
+++ b/board/m501sk/Makefile
@@ -27,8 +27,6 @@ LIB   = $(obj)lib$(BOARD).a
 
 COBJS  := m501sk.o eeprom.o
 
-SOBJS  := memsetup.o
-
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
 SOBJS  := $(addprefix $(obj),$(SOBJS))

diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S
deleted file mode 100644 (file)
index 6aea723..0000000
--- a/board/m501sk/memsetup.S
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *               Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifdef CONFIG_BOOTBINFUNC
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP 0xFFFFFF50
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER 0xFFFFFF54
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR 0xFFFFFF04
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR 0xFFFFFF08
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR 0xFFFFFF64
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0 0xFFFFFF70
-#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR 0xFFFFFC2C
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR 0xFFFFFC30
-/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-#define MCKR_VAL       0x00000202
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR 0xFFFFF804
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA 0xFFFFFF60
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR 0xFFFFFF94
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-_TEXT_BASE:
-       .word   TEXT_BASE
-
-.globl lowlevelinit
-lowlevelinit:
-       /* memory control configuration */
-       /* this isn't very elegant, but  what the heck */
-       ldr     r0, =SMRDATA
-       ldr     r1, _TEXT_BASE
-       sub     r0, r0, r1
-       add     r2, r0, #80
-0:
-       /* the address */
-       ldr     r1, [r0], #4
-       /* the value */
-       ldr     r3, [r0], #4
-       str     r3, [r1]
-       cmp     r2, r0
-       bne     0b
-       /* delay - this is all done by guess */
-       ldr     r0, =0x00010000
-1:
-       subs    r0, r0, #1
-       bhi     1b
-       ldr     r0, =SMRDATA1
-       ldr     r1, _TEXT_BASE
-       sub     r0, r0, r1
-       add     r2, r0, #176
-2:
-       /* the address */
-       ldr     r1, [r0], #4
-       /* the value */
-       ldr     r3, [r0], #4
-       str     r3, [r1]
-       cmp     r2, r0
-       bne     2b
-
-       /* everything is fine now */
-       mov     pc, lr
-
-       .ltorg
-
-SMRDATA:
-       .word MC_PUIA
-       .word MC_PUIA_VAL
-       .word MC_PUP
-       .word MC_PUP_VAL
-       .word MC_PUER
-       .word MC_PUER_VAL
-       .word MC_ASR
-       .word MC_ASR_VAL
-       .word MC_AASR
-       .word MC_AASR_VAL
-       .word EBI_CFGR
-       .word EBI_CFGR_VAL
-       .word SMC_CSR0
-       .word SMC_CSR0_VAL
-       .word PLLAR
-       .word PLLAR_VAL
-       .word PLLBR
-       .word PLLBR_VAL
-       .word MCKR
-       .word MCKR_VAL
-       /* SMRDATA is 80 bytes long */
-       /* here there's a delay of 100 */
-SMRDATA1:
-       .word PIOC_ASR
-       .word PIOC_ASR_VAL
-       .word PIOC_BSR
-       .word PIOC_BSR_VAL
-       .word PIOC_PDR
-       .word PIOC_PDR_VAL
-       .word EBI_CSA
-       .word EBI_CSA_VAL
-       .word SDRC_CR
-       .word SDRC_CR_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL1
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL2
-       .word SDRAM1
-       .word SDRAM_VAL
-       .word SDRC_TR
-       .word SDRC_TR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL3
-       .word SDRAM
-       .word SDRAM_VAL
-       /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 66b07da08b668f4ba33e05f49dc3d02013b9efb6..0913284e793ab8a00c03900fa962a54941303d40 100644 (file)
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -38,33 +38,7 @@
  * turn is based on the boot.bin code from ATMEL
  *
  */
-
-/* flash */
-#define MC_PUIA                0xFFFFFF10
-#define MC_PUP         0xFFFFFF50
-#define MC_PUER                0xFFFFFF54
-#define MC_ASR         0xFFFFFF04
-#define MC_AASR                0xFFFFFF08
-#define EBI_CFGR       0xFFFFFF64
-#define SMC_CSR0       0xFFFFFF70
-
-/* clocks */
-#define PLLAR          0xFFFFFC28
-#define PLLBR          0xFFFFFC2C
-#define MCKR           0xFFFFFC30
-
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-
-/* sdram */
-#define PIOC_ASR       0xFFFFF870
-#define PIOC_BSR       0xFFFFF874
-#define PIOC_PDR       0xFFFFF804
-#define EBI_CSA                0xFFFFFF60
-#define SDRC_CR                0xFFFFFF98
-#define SDRC_MR                0xFFFFFF90
-#define SDRC_TR                0xFFFFFF94
-
+#include <asm/arch/AT91RM9200.h>
 
 _MTEXT_BASE:
 #undef START_FROM_MEM
@@ -84,7 +58,7 @@ lowlevel_init:
 #else
        ldr     r0, =0x0000FF00         /* Disable main oscillator, OSCOUNT = 0xFF */
 #endif
-       str     r0, [r1, #CKGR_MOR]
+       str     r0, [r1, #AT91C_CKGR_MOR]
        /* Add loop to compensate Main Oscillator startup time */
        ldr     r0, =0x00000010
 LoopOsc:
@@ -134,72 +108,72 @@ LoopOsc:
        .ltorg
 
 SMRDATA:
-       .word MC_PUIA
-       .word MC_PUIA_VAL
-       .word MC_PUP
-       .word MC_PUP_VAL
-       .word MC_PUER
-       .word MC_PUER_VAL
-       .word MC_ASR
-       .word MC_ASR_VAL
-       .word MC_AASR
-       .word MC_AASR_VAL
-       .word EBI_CFGR
-       .word EBI_CFGR_VAL
-       .word SMC_CSR0
-       .word SMC_CSR0_VAL
-       .word PLLAR
-       .word PLLAR_VAL
-       .word PLLBR
-       .word PLLBR_VAL
-       .word MCKR
-       .word MCKR_VAL
+       .word AT91C_MC_PUIA
+       .word CONFIG_SYS_MC_PUIA_VAL
+       .word AT91C_MC_PUP
+       .word CONFIG_SYS_MC_PUP_VAL
+       .word AT91C_MC_PUER
+       .word CONFIG_SYS_MC_PUER_VAL
+       .word AT91C_MC_ASR
+       .word CONFIG_SYS_MC_ASR_VAL
+       .word AT91C_MC_AASR
+       .word CONFIG_SYS_MC_AASR_VAL
+       .word AT91C_EBI_CFGR
+       .word CONFIG_SYS_EBI_CFGR_VAL
+       .word AT91C_SMC_CSR0
+       .word CONFIG_SYS_SMC_CSR0_VAL
+       .word AT91C_PLLAR
+       .word CONFIG_SYS_PLLAR_VAL
+       .word AT91C_PLLBR
+       .word CONFIG_SYS_PLLBR_VAL
+       .word AT91C_MCKR
+       .word CONFIG_SYS_MCKR_VAL
        /* SMRDATA is 80 bytes long */
        /* here there's a delay of 100 */
 SMRDATA1:
-       .word PIOC_ASR
-       .word PIOC_ASR_VAL
-       .word PIOC_BSR
-       .word PIOC_BSR_VAL
-       .word PIOC_PDR
-       .word PIOC_PDR_VAL
-       .word EBI_CSA
-       .word EBI_CSA_VAL
-       .word SDRC_CR
-       .word SDRC_CR_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL1
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL2
-       .word SDRAM1
-       .word SDRAM_VAL
-       .word SDRC_TR
-       .word SDRC_TR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL3
-       .word SDRAM
-       .word SDRAM_VAL
+       .word AT91C_PIOC_ASR
+       .word CONFIG_SYS_PIOC_ASR_VAL
+       .word AT91C_PIOC_BSR
+       .word CONFIG_SYS_PIOC_BSR_VAL
+       .word AT91C_PIOC_PDR
+       .word CONFIG_SYS_PIOC_PDR_VAL
+       .word AT91C_EBI_CSA
+       .word CONFIG_SYS_EBI_CSA_VAL
+       .word AT91C_SDRC_CR
+       .word CONFIG_SYS_SDRC_CR_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL1
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL2
+       .word CONFIG_SYS_SDRAM1
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_TR
+       .word CONFIG_SYS_SDRC_TR_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL3
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
        /* SMRDATA1 is 176 bytes long */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/doc/README.at91 b/doc/README.at91
index 838769a9084c0461c528f0de1ac56cb0746a6305..4e3928a475f5589cfd47ca3c4adcea0b9a52c68f 100644 (file)
--- a/doc/README.at91
+++ b/doc/README.at91
@@ -3,7 +3,7 @@ Atmel AT91 Evaluation kits
 http://atmel.com/dyn/products/tools.asp?family_id=605#1443
 
 ------------------------------------------------------------------------------
-AT91SAM9260EK
+AT91SAM9260EK & AT91SAM9XEEK
 ------------------------------------------------------------------------------
 
 Memory map

diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 95db0177cd43dbf23b2c8b0d10b77f3a263b476b..00bae1c4d5762318ecda916dce554c5cb34542c6 100644 (file)
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -781,5 +781,32 @@ typedef struct _AT91S_PDC
 #define AT91C_PIOB_ODR         ((AT91_REG *)   0xFFFFF614) /* (PIOB) Output Disable Registerr */
 #define AT91C_PIOB_PDSR                ((AT91_REG *)   0xFFFFF63C) /* (PIOB) Pin Data Status Register */
 
+#else
+/* flash */
+#define AT91C_MC_PUIA          0xFFFFFF10
+#define AT91C_MC_PUP           0xFFFFFF50
+#define AT91C_MC_PUER          0xFFFFFF54
+#define AT91C_MC_ASR           0xFFFFFF04
+#define AT91C_MC_AASR          0xFFFFFF08
+#define AT91C_EBI_CFGR         0xFFFFFF64
+#define AT91C_SMC_CSR0         0xFFFFFF70
+
+/* clocks */
+#define AT91C_PLLAR            0xFFFFFC28
+#define AT91C_PLLBR            0xFFFFFC2C
+#define AT91C_MCKR             0xFFFFFC30
+
+#define AT91C_BASE_CKGR                0xFFFFFC20
+#define AT91C_CKGR_MOR         0
+
+/* sdram */
+#define AT91C_PIOC_ASR         0xFFFFF870
+#define AT91C_PIOC_BSR         0xFFFFF874
+#define AT91C_PIOC_PDR         0xFFFFF804
+#define AT91C_EBI_CSA          0xFFFFFF60
+#define AT91C_SDRC_CR          0xFFFFFF98
+#define AT91C_SDRC_MR          0xFFFFFF90
+#define AT91C_SDRC_TR          0xFFFFFF94
+
 #endif /* __ASSEMBLY__ */
 #endif /* AT91RM9200_H */

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 746f0ef102e181d1fad998a74612c3d1d59f3a04..c7e83ccfc14e1859986eb73fb2c8ee1f8b67f347 100644 (file)
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -45,33 +45,33 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define MC_PUIA_VAL    0x00000000
-#define MC_PUP_VAL     0x00000000
-#define MC_PUER_VAL    0x00000000
-#define MC_ASR_VAL     0x00000000
-#define MC_AASR_VAL    0x00000000
-#define EBI_CFGR_VAL   0x00000000
-#define SMC_CSR0_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL      0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL   0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL    0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL   0x00000000
-#define PIOC_PDR_VAL   0xFFFF0000
-#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL    0x2188c155 /* set up the SDRAM */
-#define SDRAM          0x20000000 /* address of the SDRAM */
-#define SDRAM1         0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL    0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1   0x00000004 /* refresh */
-#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 #else
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index cdd308d8b91bd7abeccde673e73bd311e6238dd7..d9acb470fedbab874d328b48f4f6a040b1e313ef 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -44,33 +44,33 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define MC_PUIA_VAL    0x00000000
-#define MC_PUP_VAL     0x00000000
-#define MC_PUER_VAL    0x00000000
-#define MC_ASR_VAL     0x00000000
-#define MC_AASR_VAL    0x00000000
-#define EBI_CFGR_VAL   0x00000000
-#define SMC_CSR0_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL      0x2026BE04 /* 179,712 MHz for PCK */
-#define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL   0x2026BE04 /* 179,712 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL    0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL   0x00000000
-#define PIOC_PDR_VAL   0xFFFF0000
-#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL    0x3399c1d4 /* set up the SDRAM */
-#define SDRAM          0x20000000 /* address of the SDRAM */
-#define SDRAM1         0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL    0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1   0x00000004 /* refresh */
-#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 #else
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index 682db447dd81cd5939b6126df659c8f5b4e8eec9..2df77cfa7dddfea661592c407cb95196e35110ca 100644 (file)
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -45,33 +45,33 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
 /* flash */
-#define MC_PUIA_VAL    0x00000000
-#define MC_PUP_VAL     0x00000000
-#define MC_PUER_VAL    0x00000000
-#define MC_ASR_VAL     0x00000000
-#define MC_AASR_VAL    0x00000000
-#define EBI_CFGR_VAL   0x00000000
-#define SMC_CSR0_VAL   0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL      0x2031BE01 /* 184.320000 MHz for PCK */
-#define PLLBR_VAL      0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
-#define MCKR_VAL       0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL   0x2031BE01 /* 184.320000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL    0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL   0x00000000
-#define PIOC_PDR_VAL   0xFFFF0000
-#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL    0x21914159 /* set up the SDRAM */
-#define SDRAM          0x20000000 /* address of the SDRAM */
-#define SDRAM1         0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL    0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1   0x00000004 /* refresh */
-#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 #else
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index f09214dce9c37d5b76c57f4a2653a5e541000755..eab37df22dd0f305e8a4fc21f28b12a142b8da5f 100644 (file)
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -41,6 +41,39 @@
 #define CONFIG_INITRD_TAG              1
 
 #define CONFIG_MENUPROMPT              "."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR         1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL   0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL    0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 
 /*
  * Size of malloc() pool

diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index cbbdb0c77edc53142a373b350201ba168fa65925..fb10616c30893a27f60f27a1e63ed8572a7cc918 100644 (file)
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -49,33 +49,33 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
 /* flash */
-#define MC_PUIA_VAL    0x00000000
-#define MC_PUP_VAL     0x00000000
-#define MC_PUER_VAL    0x00000000
-#define MC_ASR_VAL     0x00000000
-#define MC_AASR_VAL    0x00000000
-#define EBI_CFGR_VAL   0x00000000
-#define SMC_CSR0_VAL   0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL  0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL  0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL        0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL        0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL      0x20263E04 /* 180 MHz for PCK */
-#define PLLBR_VAL      0x1048bE0E /* 48 MHz (divider by 2 for USB) */
-#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL   0x20263E04 /* 180 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL   0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL    0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
 
 /* sdram */
-#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL   0x00000000
-#define PIOC_PDR_VAL   0xFFFF0000
-#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL    0x3211295A /* set up the SDRAM */
-#define SDRAM          0x20000000 /* address of the SDRAM */
-#define SDRAM1         0x20000020 /* address of the SDRAM */
-#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL    0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1   0x00000004 /* refresh */
-#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL        0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL        0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL        0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM       0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1      0x20000020 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL   0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1        0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2        0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3        0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
 #else
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */