Code cleanup.
--- /dev/null
-
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+#TEXT_BASE = 0x9ffe0000
+TEXT_BASE = 0xa3008000
+
+# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
+BOARDLIBS = drivers/nand/libnand.a
--- /dev/null
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
- ldr r2, =OSCR
- mov r3, #0
- str r3, [r2]
++.macro CPWAIT reg
++ mrc p15,0,\reg,c2,c0,0
++ mov \reg,\reg
++ sub pc,pc,#4
++.endm
+
+
+.macro wait time
- ldr r3, [r2]
- cmp r3, \time
- bls 0b
++ ldr r2, =OSCR
++ mov r3, #0
++ str r3, [r2]
+0:
- * Memory setup
++ ldr r3, [r2]
++ cmp r3, \time
++ bls 0b
+.endm
+
+/*
- mov r10, lr
-
- /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
++ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
-
- /* tebrandt - ASCR, clear the RDH bit */
- ldr r0, =ASCR
- ldr r1, [r0]
- bic r1, r1, #0x80000000
- str r1, [r0]
-
++ mov r10, lr
++
++ /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
+ ldr r0, =GPIO97
+ ldr r1, =0x801
+ str r1, [r0]
+
+ ldr r0, =GPIO98
+ ldr r1, =0x801
+ str r1, [r0]
- /* Enable memory interface */
++
++ /* tebrandt - ASCR, clear the RDH bit */
++ ldr r0, =ASCR
++ ldr r1, [r0]
++ bic r1, r1, #0x80000000
++ str r1, [r0]
++
+ /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
++ /* Enable memory interface */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
- ; wait #300
-
++ /* Step 1: Wait for at least 200 microsedonds to allow internal */
++ /* clocks to settle. Only necessary after hard reset... */
++ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
- /* ldr r1, =0x80000403 */
++; wait #300
++
+mem_init:
+
+#define NEW_SDRAM_INIT 1
+#ifdef NEW_SDRAM_INIT
+
+ /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
+ ldr r0, =ACCR
+ ldr r1, [r0]
+ orr r1, r1, #0x3000
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
+ ldr r0, =MDCNFG
+ ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
- /* 3. wait nop power up waiting period (200ms)
++ /* ldr r1, =0x80000403 */
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+
-
++ /* 3. wait nop power up waiting period (200ms)
+ * optimization: Steps 4+6 can be done during this
+ */
+ wait #300
+
+ /* 4. Perform an initial Rcomp-calibration cycle */
+ ldr r0, =RCOMP
+ ldr r1, =0x80000000
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+ /* missing: program for automatic rcomp evaluation cycles */
+
+ /* 5. DDR DRAM strobe delay calibration */
+ ldr r0, =DDR_HCAL
+ ldr r1, =0x88000007
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0] /* delay until written */
+
+ /* Set MDMRS */
+ ldr r0, =MDMRS
+ ldr r1, =0x60000033
+ str r1, [r0]
+ wait #300
-
++
+ /* Configure MDREFR */
+ ldr r0, =MDREFR
+ ldr r1, =0x00000006
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Enable the dynamic memory controller */
+ ldr r0, =MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #MDCNFG_DMCEN
+ str r1, [r0]
+
+
+#else /* NEW_SDRAM_INIT */
- ldr r1, =MEMCLKCFG
- ldr r2, =0x00010001
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++
+ /* configure the MEMCLKCFG register */
- ldr r1, =CSADRCFG0
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =MEMCLKCFG
++ ldr r2, =0x00010001
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[0] to data flash SRAM mode */
- ldr r1, =CSADRCFG1
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =CSADRCFG0
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[1] to data flash SRAM mode */
- ldr r1, =MSC0
- ldr r2, =0x11191119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =CSADRCFG1
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set MSC 0 register for SRAM memory */
- ldr r1, =CSADRCFG2
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =MSC0
++ ldr r2, =0x11191119
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[2] to data flash SRAM mode */
- ldr r1, =CSADRCFG3
- ldr r2, =0x0032080B
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
++ ldr r1, =CSADRCFG2
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[3] to VLIO mode */
- ldr r1, =MSC1
- ldr r2, =0x123C1119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
++ ldr r1, =CSADRCFG3
++ ldr r2, =0x0032080B
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
++ ldr r1, =MSC1
++ ldr r2, =0x123C1119
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
- ldr r1, [r0]
++ ldr r0, =DDR_HCAL @ DDR_HCAL
++ ldr r1, =0x803ffc07 @ the offset is correct? -SC
++ str r1, [r0]
+ wait #5
-
++ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+#endif /* NEW_SDRAM_INIT */
- mov r2, #0
++
+#ifndef CFG_SKIP_DRAM_SCRUB
+ /* scrub/init SDRAM if enabled/present */
+ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
+ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
- mov r4, #0
++ mov r2, #0
+ mov r3, #0
- mov r6, #0
++ mov r4, #0
+ mov r5, #0
- 10: /* fastScrubLoop */
++ mov r6, #0
+ mov r7, #0
- mcr p15,0,r0,c14,c8,0 // ibcr0
- mcr p15,0,r0,c14,c9,0 // ibcr1
- mcr p15,0,r0,c14,c4,0 // dbcon
++10: /* fastScrubLoop */
+ subs r9, r9, #32 /* 8 words/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+#endif /* CFG_SKIP_DRAM_SCRUB */
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
- mcr p14,0,r0,c10,c0,0 // dcsr
++ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
++ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
++ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
- mov pc, lr
++ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+endlowlevel_init:
+
- @
++ mov pc, lr
+
+
+/*
+@********************************************************************************
+@ DDR calibration
- @ Monahans supports three ways to do it. One is software
++@
+@ This function is used to calibrate DQS delay lines.
- @ Configure DDR_SCAL Register
- ldr r0, =DDR_SCAL @ DDR_SCAL
- q ldr r1, =0xaf2f2f2f
- str r1, [r0]
- ldr r1, [r0]
++@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
- ldr r5, =0x0faf0faf @ Data Pattern
++ @ Configure DDR_SCAL Register
++ ldr r0, =DDR_SCAL @ DDR_SCAL
++q ldr r1, =0xaf2f2f2f
++ str r1, [r0]
++ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
- mov r0, r1, lsl #30
++ ldr r5, =0x0faf0faf @ Data Pattern
+ ldr r4, =0xa0000000 @ DDR ram
+ str r5, [r4]
+
+ mov r1, =0x0 @ delay count
+ mov r6, =0x0
+ mov r7, =0x0
+ddr_loop1:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
- mov r0, r1, lsl #22
++ mov r0, r1, lsl #30
+ orr r3, r3, r0
- mov r0, r1, lsl #14
++ mov r0, r1, lsl #22
+ orr r3, r3, r0
- mov r3, r1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
- str r3, [r2]
++ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ bne ddr_loop1
+ mov r6, r1
+ddr_loop2:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
-
++ mov r3, r1
++ mov r0, r1, lsl #30
++ orr r3, r3, r0
++ mov r0, r1, lsl #22
++ orr r3, r3, r0
++ mov r0, r1, lsl #14
++ orr r3, r3, r0
++ orr r3, r3, =0x80000000
++ ldr r2, =DDR_SCAL
++ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ be ddr_loop2
+ mov r7, r2
+
+ add r3, r6, r7
+ lsr r3, r3, =0x1
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
++ mov r0, r1, lsl #30
++ orr r3, r3, r0
++ mov r0, r1, lsl #22
++ orr r3, r3, r0
++ mov r0, r1, lsl #14
++ orr r3, r3, r0
++ orr r3, r3, =0x80000000
++ ldr r2, =DDR_SCAL
++
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
- ldr r1, [r0]
- mov pc, lr
++ ldr r0, =DDR_HCAL @ DDR_HCAL
++ ldr r1, =0x803ffc07 @ the offset is correct? -SC
++ str r1, [r0]
+ wait #5
++ ldr r1, [r0]
++ mov pc, lr
+*/
--- /dev/null
-
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y) ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+ .eccbytes = 6,
+ .eccpos = {2, 3, 4, 5, 6, 7},
+ .oobfree = { {8, 2}, {12, 4} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+ if(NDSR & NDSR_RDY)
+ return 1;
+ else
+ return 0;
+ return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+ int i;
- /*
++
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ NDDB = *long_buf;
+ }
+ }
+ if(rest) {
+ printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+ }
+ return;
+}
+
+
-
++/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+ printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+ int i=0, j;
+
+ /* we have to be carefull not to overflow the buffer if len is
+ * not a multiple of 4 */
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+
+ DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+ /* if there are any, first copy multiple of 4 bytes */
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ *long_buf = NDDB;
+ }
+ }
- /*
++
+ /* ...then the rest */
+ if(rest) {
+ unsigned long rest_data = NDDB;
+ for(j=0;j<rest; j++)
+ buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+ }
+
+ return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+ printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
- dummy = NDDB;
++/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+ unsigned char byte;
+ unsigned long dummy;
+
+ if(bytes_read < 0) {
+ read_buf = NDDB;
-
++ dummy = NDDB;
+ bytes_read = 0;
+ }
+ byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+ if(bytes_read >= 4)
+ bytes_read = -1;
+
+ DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+ return byte;
+}
+
+/* calculate delta between OSCR values start and now */
+static unsigned long get_delta(unsigned long start)
+{
+ unsigned long cur = OSCR;
-
++
+ if(cur < start) /* OSCR overflowed */
+ return (cur + (start^0xffffffff));
+ else
+ return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+ unsigned long start = OSCR;
+ us *= OSCR_CLK_FREQ;
+
+ while (get_delta(start) < us) {
+ /* do nothing */
+ }
+}
+
+static void dfc_clear_nddb()
+{
+ NDCR &= ~NDCR_ND_RUN;
+ wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+ unsigned long ndsr, timeout, start = OSCR;
-
++
+ if(!event)
+ return 0xff000000;
+ else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+ timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ else
+ timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
-
++
+ while(1) {
+ ndsr = NDSR;
+ if(ndsr & event) {
+ NDSR |= event;
+ break;
+ }
+ if(get_delta(start) > timeout) {
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ return 0xff000000;
+ }
-
++
+ }
+ return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd()
+{
+ int retry = 0;
+ unsigned long status;
+
+ while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ /* Clear NDSR */
+ NDSR = 0xFFF;
-
++
+ /* set NDCR[NDRUN] */
+ if(!(NDCR & NDCR_ND_RUN))
+ NDCR |= NDCR_ND_RUN;
-
++
+ status = dfc_wait_event(NDSR_WRCMDREQ);
-
++
+ if(status & NDSR_WRCMDREQ)
+ return;
+
+ DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+ dfc_clear_nddb();
+ }
+ DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+ unsigned long ndsr=0, event=0;
+
+ /* mk@tbd set appropriate timeouts */
+ /* if (state == FL_ERASING) */
+ /* timeo = CFG_HZ * 400; */
+ /* else */
+ /* timeo = CFG_HZ * 20; */
+ if(state == FL_WRITING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ } else if(state == FL_ERASING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ }
- static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
++
+ ndsr = dfc_wait_event(event);
+
+ if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+ return(0x1); /* Status Read error */
+ return 0;
+}
+
+/* cmdfunc send commands to the DFC */
-
++static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ /* register struct nand_chip *this = mtd->priv; */
+ unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+ /* clear the ugly byte read buffer */
+ bytes_read = -1;
+ read_buf = 0;
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (NAND_CMD_READ0 | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_READ1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+ goto end;
+ case NAND_CMD_READOOB:
+ DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+ goto end;
+ case NAND_CMD_READID:
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+ ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_PAGEPROG:
+ /* sent as a multicommand in NAND_CMD_SEQIN */
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_ERASE1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+ ndcb1 = (page_addr & 0x00ffffff);
+ goto write_cmd;
+ case NAND_CMD_ERASE2:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_SEQIN:
+ /* send PAGE_PROG command(0x1080) */
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_WRDREQ;
+ goto write_cmd;
+ case NAND_CMD_STATUS:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+ dfc_new_cmd();
+ ndcb0 = NAND_CMD_STATUS | (4<<21);
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_RESET:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+ ndcb0 = NAND_CMD_RESET | (5<<21);
+ event = NDSR_CS0_CMDD;
+ goto write_cmd;
+ default:
+ printk("dfc_cmdfunc: error, unsupported command.\n");
+ goto end;
+ }
+
+ write_cmd:
+ NDCB0 = ndcb0;
+ NDCB0 = ndcb1;
+ NDCB0 = ndcb2;
+
+ /* wait_event: */
+ dfc_wait_event(event);
+ end:
+ return;
+}
+
+static void dfc_gpio_init()
+{
+ DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see zylonite.c */
+ GPIO4 = 0x1;
- #ifndef CFG_TIMING_TIGHT
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
++
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+ /* set up GPIO Control Registers */
+ dfc_gpio_init();
+
+ /* turn on the NAND Controller Clock (104 MHz @ D0) */
+ CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
++#ifndef CFG_TIMING_TIGHT
++ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCH);
- tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
++ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tAR);
+#else /* this is the tight timing */
+
- tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
++ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+ DFC_MAX_tCH);
-
++ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+ DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+ /* tRP value is split in the register */
+ if(tRP & (1 << 4)) {
+ tRP_high = 1;
+ tRP &= ~(1 << 4);
+ } else {
+ tRP_high = 0;
+ }
+
+ NDTR0CS0 = (tCH << 19) |
+ (tCS << 16) |
+ (tWH << 11) |
+ (tWP << 8) |
+ (tRP_high << 6) |
+ (tRH << 3) |
+ (tRP << 0);
-
-
++
+ NDTR1CS0 = (tR << 16) |
+ (tWHR << 4) |
+ (tAR << 0);
+
-
+ /* If it doesn't work (unlikely) think about:
+ * - ecc enable
+ * - chip select don't care
+ * - read id byte count
+ *
+ * Intentionally enabled by not setting bits:
+ * - dma (DMA_EN)
+ * - page size = 512
+ * - cs don't care, see if we can enable later!
+ * - row address start position (after second cycle)
+ * - pages per block = 32
+ * - ND_RDY : clears command buffer
+ */
+ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR_DBERRM | /* double bit error ir masked */
++
+ NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ NDCR_DWIDTH_C | /* 16bit DFC data bus width */
+ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
+ (2 << 16) | /* read id count = 7 ???? mk@tbd */
+ NDCR_ND_ARB_EN | /* enable bus arbiter */
+ NDCR_RDYM | /* flash device ready ir masked */
+ NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
+ NDCR_CS1_PAGEDM |
+ NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
+ NDCR_CS1_CMDDM |
+ NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
+ NDCR_CS1_BBDM |
-
++ NDCR_DBERRM | /* double bit error ir masked */
+ NDCR_SBERRM | /* single bit error ir masked */
+ NDCR_WRDREQM | /* write data request ir masked */
+ NDCR_RDDREQM | /* read data request ir masked */
+ NDCR_WRCMDREQM); /* write command request ir masked */
-
-
++
+
+ /* wait 10 us due to cmd buffer clear reset */
+ /* wait(10); */
++
++
+ nand->hwcontrol = dfc_hwcontrol;
+/* nand->dev_ready = dfc_device_ready; */
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_DELAY_US;
+ nand->options = NAND_BUSWIDTH_16;
+ nand->waitfunc = dfc_wait;
+ nand->read_byte = dfc_read_byte;
+ nand->write_byte = dfc_write_byte;
+ nand->read_word = dfc_read_word;
+ nand->write_word = dfc_write_word;
+ nand->read_buf = dfc_read_buf;
+ nand->write_buf = dfc_write_buf;
+
+ nand->cmdfunc = dfc_cmdfunc;
+ nand->autooob = &delta_oob;
+ nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif
--- /dev/null
-#define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register\97MBAR + 0x0100
-#define SDRAM_CONTROL 0x504f0000 // Control Register\97MBAR + 0x0104
-#define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1\97MBAR + 0x0108
-#define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2\97MBAR + 0x010C
+ /*
+ * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
+ */
+
+ #define SDRAM_DDR 0 /* is SDR */
+
+ /* Settings for XLB = 132 MHz */
+
++#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
++#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
++#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
++#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
--- /dev/null
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
- ldr r2, =OSCR
- mov r3, #0
- str r3, [r2]
++.macro CPWAIT reg
++ mrc p15,0,\reg,c2,c0,0
++ mov \reg,\reg
++ sub pc,pc,#4
++.endm
+
+
+.macro wait time
- ldr r3, [r2]
- cmp r3, \time
- bls 0b
++ ldr r2, =OSCR
++ mov r3, #0
++ str r3, [r2]
+0:
-
++ ldr r3, [r2]
++ cmp r3, \time
++ bls 0b
+.endm
- * Memory setup
++
+/*
- mov r10, lr
-
- /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
- ldr r0, =0x40E10438 @ GPIO41 FFRXD
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E1043C @ GPIO42 FFTXD
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E10440 @ GPIO43 FFCTS
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E10444 @ GPIO 44 FFDCD
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E10448 @ GPIO 45 FFDSR
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E1044C @ GPIO 46 FFRI
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E10450 @ GPIO 47 FFDTR
- ldr r1, =0x802
- str r1, [r0]
-
- ldr r0, =0x40E10454 @ GPIO 48
- ldr r1, =0x802
- str r1, [r0]
-
- /* tebrandt - ASCR, clear the RDH bit */
- ldr r0, =ASCR
- ldr r1, [r0]
- bic r1, r1, #0x80000000
- str r1, [r0]
-
++ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
++ mov r10, lr
++
++ /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
++ ldr r0, =0x40E10438 @ GPIO41 FFRXD
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E1043C @ GPIO42 FFTXD
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E10440 @ GPIO43 FFCTS
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E10444 @ GPIO 44 FFDCD
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E10448 @ GPIO 45 FFDSR
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E1044C @ GPIO 46 FFRI
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E10450 @ GPIO 47 FFDTR
++ ldr r1, =0x802
++ str r1, [r0]
++
++ ldr r0, =0x40E10454 @ GPIO 48
++ ldr r1, =0x802
++ str r1, [r0]
++
++ /* tebrandt - ASCR, clear the RDH bit */
++ ldr r0, =ASCR
++ ldr r1, [r0]
++ bic r1, r1, #0x80000000
++ str r1, [r0]
++
+ /* ---------------------------------------------------------------- */
- /* Chapter 10. */
++ /* Enable memory interface */
++ /* */
++ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
++ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
- /* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
- /* mov r2, #0 */
- /* str r2, [r3] */
- /* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
- /* /\* so 0x300 should be plenty *\/ */
++ /* Step 1: Wait for at least 200 microsedonds to allow internal */
++ /* clocks to settle. Only necessary after hard reset... */
++ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ /* mk: replaced with wait macro */
- /* ldr r2, [r3] */
- /* cmp r4, r2 */
- /* bgt 1b */
++/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
++/* mov r2, #0 */
++/* str r2, [r3] */
++/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
++/* /\* so 0x300 should be plenty *\/ */
+/* 1: */
-
++/* ldr r2, [r3] */
++/* cmp r4, r2 */
++/* bgt 1b */
+ wait #300
- ldr r1, =MEMCLKCFG
- ldr r2, =0x00010001
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++
+mem_init:
+
+ /* configure the MEMCLKCFG register */
- ldr r1, =CSADRCFG0
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =MEMCLKCFG
++ ldr r2, =0x00010001
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[0] to data flash SRAM mode */
- ldr r1, =CSADRCFG1
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =CSADRCFG0
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[1] to data flash SRAM mode */
- ldr r1, =MSC0
- ldr r2, =0x11191119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =CSADRCFG1
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set MSC 0 register for SRAM memory */
- ldr r1, =CSADRCFG2
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
++ ldr r1, =MSC0
++ ldr r2, =0x11191119
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[2] to data flash SRAM mode */
- ldr r1, =CSADRCFG3
- ldr r2, =0x0032080B
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
++ ldr r1, =CSADRCFG2
++ ldr r2, =0x00320809
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
++
+ /* set CSADRCFG[3] to VLIO mode */
- ldr r1, =MSC1
- ldr r2, =0x123C1119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
++ ldr r1, =CSADRCFG3
++ ldr r2, =0x0032080B
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
++ ldr r1, =MSC1
++ ldr r2, =0x123C1119
++ str r2, [r1] @ WRITE
++ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
- ldr r1, [r0]
++ ldr r0, =DDR_HCAL @ DDR_HCAL
++ ldr r1, =0x803ffc07 @ the offset is correct? -SC
++ str r1, [r0]
+ wait #5
- /* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
- /* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
- /* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
- ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
- ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
++ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+ /* scrub/init SDRAM if enabled/present */
- mov r2, #0
++/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
++/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
++/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
++ ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
++ ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
- mov r4, #0
++ mov r2, #0
+ mov r3, #0
- mov r6, #0
++ mov r4, #0
+ mov r5, #0
- 10: /* fastScrubLoop */
- subs r9, r9, #32 // 32 bytes/line
++ mov r6, #0
+ mov r7, #0
- mcr p15,0,r0,c14,c8,0 // ibcr0
- mcr p15,0,r0,c14,c9,0 // ibcr1
- mcr p15,0,r0,c14,c4,0 // dbcon
++10: /* fastScrubLoop */
++ subs r9, r9, #32 /* 32 bytes/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
- mcr p14,0,r0,c10,c0,0 // dcsr
-
++ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
++ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
++ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
-
++ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
-
+ /* We are finished with Intel's memory controller initialisation */
+
- /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
- mov pc, lr
-
++ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
- @
++ mov pc, lr
+
+/*
+@********************************************************************************
+@ DDR calibration
- @ Monahans supports three ways to do it. One is software
++@
+@ This function is used to calibrate DQS delay lines.
- @ Configure DDR_SCAL Register
- ldr r0, =DDR_SCAL @ DDR_SCAL
- q ldr r1, =0xaf2f2f2f
- str r1, [r0]
- ldr r1, [r0]
++@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
- ldr r5, =0x0faf0faf @ Data Pattern
- ldr r4, =0xa0000000 @ DDR ram
- str r5, [r4]
++ @ Configure DDR_SCAL Register
++ ldr r0, =DDR_SCAL @ DDR_SCAL
++q ldr r1, =0xaf2f2f2f
++ str r1, [r0]
++ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
- mov r1, =0x0 @ delay count
- mov r6, =0x0
- mov r7, =0x0
++ ldr r5, =0x0faf0faf @ Data Pattern
++ ldr r4, =0xa0000000 @ DDR ram
++ str r5, [r4]
+
- add r1, r1, =0x1
- cmp r1, =0xf
- ble end_loop
- mov r3, r1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
- str r3, [r2]
-
- ldr r2, [r4]
- cmp r2, r5
- bne ddr_loop1
- mov r6, r1
++ mov r1, =0x0 @ delay count
++ mov r6, =0x0
++ mov r7, =0x0
+ddr_loop1:
- add r1, r1, =0x1
- cmp r1, =0xf
- ble end_loop
- mov r3, r1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
- str r3, [r2]
-
- ldr r2, [r4]
- cmp r2, r5
- be ddr_loop2
- mov r7, r2
-
- add r3, r6, r7
- lsr r3, r3, =0x1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
-
++ add r1, r1, =0x1
++ cmp r1, =0xf
++ ble end_loop
++ mov r3, r1
++ mov r0, r1, lsl #30
++ orr r3, r3, r0
++ mov r0, r1, lsl #22
++ orr r3, r3, r0
++ mov r0, r1, lsl #14
++ orr r3, r3, r0
++ orr r3, r3, =0x80000000
++ ldr r2, =DDR_SCAL
++ str r3, [r2]
++
++ ldr r2, [r4]
++ cmp r2, r5
++ bne ddr_loop1
++ mov r6, r1
+ddr_loop2:
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
- wait #5
- ldr r1, [r0]
- mov pc, lr
++ add r1, r1, =0x1
++ cmp r1, =0xf
++ ble end_loop
++ mov r3, r1
++ mov r0, r1, lsl #30
++ orr r3, r3, r0
++ mov r0, r1, lsl #22
++ orr r3, r3, r0
++ mov r0, r1, lsl #14
++ orr r3, r3, r0
++ orr r3, r3, =0x80000000
++ ldr r2, =DDR_SCAL
++ str r3, [r2]
++
++ ldr r2, [r4]
++ cmp r2, r5
++ be ddr_loop2
++ mov r7, r2
++
++ add r3, r6, r7
++ lsr r3, r3, =0x1
++ mov r0, r1, lsl #30
++ orr r3, r3, r0
++ mov r0, r1, lsl #22
++ orr r3, r3, r0
++ mov r0, r1, lsl #14
++ orr r3, r3, r0
++ orr r3, r3, =0x80000000
++ ldr r2, =DDR_SCAL
++
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
++ ldr r0, =DDR_HCAL @ DDR_HCAL
++ ldr r1, =0x803ffc07 @ the offset is correct? -SC
++ str r1, [r0]
++ wait #5
++ ldr r1, [r0]
++ mov pc, lr
+*/
gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
}
-
+#endif /* CONFIG_CPU_MONAHANS */
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
-- * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
-- * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
++ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
++ * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
*
* See file CREDITS for list of people who contributed to this
* project.
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
-- cmp r0, r1 /* don't reloc during debug */
-- beq stack_setup
++ cmp r0, r1 /* don't reloc during debug */
++ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
-- sub r2, r3, r2 /* r2 <- size of armboot */
-- add r2, r0, r2 /* r2 <- source end address */
++ sub r2, r3, r2 /* r2 <- size of armboot */
++ add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
-- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
++ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
++ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
-- ldr r0, _bss_start /* find start of bss segment */
-- ldr r1, _bss_end /* stop here */
-- mov r2, #0x00000000 /* clear */
++ ldr r0, _bss_start /* find start of bss segment */
++ ldr r1, _bss_end /* stop here */
++ mov r2, #0x00000000 /* clear */
--clbss_l:str r2, [r0] /* clear loop... */
++clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
/* - setup memory timing */
/* */
/****************************************************************************/
-
- /* Interrupt-Controller base address */
+/* mk@tbd: Fix this! */
+#ifdef CONFIG_CPU_MONAHANS
+#undef ICMR
+#undef OSMR3
+#undef OSCR
+#undef OWER
+#undef OIER
+#endif
-/* Interrupt-Controller base address */
+
++/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#define ICMR 0x04
#define OWER 0x18
#define OIER 0x1C
--/* Clock Manager Registers */
++/* Clock Manager Registers */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
#else
#error "You have to define CFG_CPUSPEED!!"
#endif
-
-
- /* RS: ??? */
- .macro CPWAIT
- mrc p15,0,r0,c2,c0,0
- mov r0,r0
+ /* takes care the CP15 update has taken place */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
sub pc,pc,#4
.endm
--
cpu_init_crit:
/* mask all IRQs */
-
+#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
- mrc p15, 0, r1, c15, c1, 0 @ read CPAR
- orr r1, r1, #0x40
- mcr p15, 0, r1, c15, c1, 0
- CPWAIT r1
+#else
+ /* Step 1 - Enable CP6 permission */
- /* Step 2 - Mask ICMR & ICMR2 */
- mov r1, #0
- mcr p6, 0, r1, c1, c0, 0 @ ICMR
- mcr p6, 0, r1, c7, c0, 0 @ ICMR2
++ mrc p15, 0, r1, c15, c1, 0 @ read CPAR
++ orr r1, r1, #0x40
++ mcr p15, 0, r1, c15, c1, 0
++ CPWAIT r1
+
- ldr r1, =CKENA
- ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
- str r2, [r1]
- ldr r1, =CKENB
- ldr r2, =(CKENB_6_IRQ)
- str r2, [r1]
-
++ /* Step 2 - Mask ICMR & ICMR2 */
++ mov r1, #0
++ mcr p6, 0, r1, c1, c0, 0 @ ICMR
++ mcr p6, 0, r1, c7, c0, 0 @ ICMR2
+
+ /* turn off all clocks but the ones we will definitly require */
++ ldr r1, =CKENA
++ ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
++ str r2, [r1]
++ ldr r1, =CKENB
++ ldr r2, =(CKENB_6_IRQ)
++ str r2, [r1]
+#endif
-#if defined(CFG_CPUSPEED)
-
- /* set clock speed */
+#ifndef CONFIG_CPU_MONAHANS
+#ifdef CFG_CPUSPEED
-
+ /* set clock speed tbd@mk: required for monahans? */
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
mcr p14, 0, r0, c6, c0, 0
setspeed_done:
-
-#endif
++
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
-
/*
* before relocating, we have to setup RAM timing
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
- /* mk: hmm, this is not in the monahans docs, leave it now but
++ /* mk: hmm, this is not in the monahans docs, leave it now but
+ * check here if it doesn't work :-) */
ldr r0, =0x2001 /* enable access to all coproc. */
mcr p15, 0, r0, c15, c1, 0
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
++ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
#endif
/****************************************************************************/
--/* */
++/* */
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
--/* perform a watchdog timeout for a soft reset. */
--/* */
++/* perform a watchdog timeout for a soft reset. */
++/* */
/****************************************************************************/
.align 5
.globl reset_cpu
-- /* FIXME: this code is PXA250 specific. How is this handled on */
-- /* other XScale processors? */
++ /* FIXME: this code is PXA250 specific. How is this handled on */
++ /* other XScale processors? */
reset_cpu:
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
-- orr r1, r1, #0x0001 /* bit0: WME */
++ orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
/* OS timer does only wrap every 1165 seconds, so we have to set */
-- /* the match register as well. */
++ /* the match register as well. */
-- ldr r1, [r0, #OSCR] /* read OS timer */
++ ldr r1, [r0, #OSCR] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]
#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
- #define GPIO0 __REG(0x40e10124)
+#ifdef CONFIG_CPU_MONAHANS
+#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
+#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
+
+/* Multi-funktion Pin Registers, uncomplete, only:
+ * - GPIO
+ * - Data Flash DF_* pins defined.
+ */
++#define GPIO0 __REG(0x40e10124)
+#define GPIO1 __REG(0x40e10128)
+#define GPIO2 __REG(0x40e1012c)
+#define GPIO3 __REG(0x40e10130)
+#define GPIO4 __REG(0x40e10134)
+#define nXCVREN __REG(0x40e10138)
+
+#define DF_CLE_NOE __REG(0x40e10204)
+#define DF_ALE_WE1 __REG(0x40e10208)
+
+#define DF_SCLK_E __REG(0x40e10210)
+#define nBE0 __REG(0x40e10214)
+#define nBE1 __REG(0x40e10218)
+#define DF_ALE_WE2 __REG(0x40e1021c)
+#define DF_INT_RnB __REG(0x40e10220)
+#define DF_nCS0 __REG(0x40e10224)
+#define DF_nCS1 __REG(0x40e10228)
+#define DF_nWE __REG(0x40e1022c)
+#define DF_nRE __REG(0x40e10230)
+#define nLUA __REG(0x40e10234)
+#define nLLA __REG(0x40e10238)
+#define DF_ADDR0 __REG(0x40e1023c)
+#define DF_ADDR1 __REG(0x40e10240)
+#define DF_ADDR2 __REG(0x40e10244)
+#define DF_ADDR3 __REG(0x40e10248)
+#define DF_IO0 __REG(0x40e1024c)
+#define DF_IO8 __REG(0x40e10250)
+#define DF_IO1 __REG(0x40e10254)
+#define DF_IO9 __REG(0x40e10258)
+#define DF_IO2 __REG(0x40e1025c)
+#define DF_IO10 __REG(0x40e10260)
+#define DF_IO3 __REG(0x40e10264)
+#define DF_IO11 __REG(0x40e10268)
+#define DF_IO4 __REG(0x40e1026c)
+#define DF_IO12 __REG(0x40e10270)
+#define DF_IO5 __REG(0x40e10274)
+#define DF_IO13 __REG(0x40e10278)
+#define DF_IO6 __REG(0x40e1027c)
+#define DF_IO14 __REG(0x40e10280)
+#define DF_IO7 __REG(0x40e10284)
+#define DF_IO15 __REG(0x40e10288)
+
+#define GPIO5 __REG(0x40e1028c)
+#define GPIO6 __REG(0x40e10290)
+#define GPIO7 __REG(0x40e10294)
+#define GPIO8 __REG(0x40e10298)
+#define GPIO9 __REG(0x40e1029c)
+
+#define GPIO11 __REG(0x40e102a0)
+#define GPIO12 __REG(0x40e102a4)
+#define GPIO13 __REG(0x40e102a8)
+#define GPIO14 __REG(0x40e102ac)
+#define GPIO15 __REG(0x40e102b0)
+#define GPIO16 __REG(0x40e102b4)
+#define GPIO17 __REG(0x40e102b8)
+#define GPIO18 __REG(0x40e102bc)
+#define GPIO19 __REG(0x40e102c0)
+#define GPIO20 __REG(0x40e102c4)
+#define GPIO21 __REG(0x40e102c8)
+#define GPIO22 __REG(0x40e102cc)
+#define GPIO23 __REG(0x40e102d0)
+#define GPIO24 __REG(0x40e102d4)
+#define GPIO25 __REG(0x40e102d8)
+#define GPIO26 __REG(0x40e102dc)
+
+#define GPIO27 __REG(0x40e10400)
+#define GPIO28 __REG(0x40e10404)
+#define GPIO29 __REG(0x40e10408)
+#define GPIO30 __REG(0x40e1040c)
+#define GPIO31 __REG(0x40e10410)
+#define GPIO32 __REG(0x40e10414)
+#define GPIO33 __REG(0x40e10418)
+#define GPIO34 __REG(0x40e1041c)
+#define GPIO35 __REG(0x40e10420)
+#define GPIO36 __REG(0x40e10424)
+#define GPIO37 __REG(0x40e10428)
+#define GPIO38 __REG(0x40e1042c)
+#define GPIO39 __REG(0x40e10430)
+#define GPIO40 __REG(0x40e10434)
+#define GPIO41 __REG(0x40e10438)
+#define GPIO42 __REG(0x40e1043c)
+#define GPIO43 __REG(0x40e10440)
+#define GPIO44 __REG(0x40e10444)
+#define GPIO45 __REG(0x40e10448)
+#define GPIO46 __REG(0x40e1044c)
+#define GPIO47 __REG(0x40e10450)
+#define GPIO48 __REG(0x40e10454)
+
+#define GPIO10 __REG(0x40e10458)
+
+#define GPIO49 __REG(0x40e1045c)
+#define GPIO50 __REG(0x40e10460)
+#define GPIO51 __REG(0x40e10464)
+#define GPIO52 __REG(0x40e10468)
+#define GPIO53 __REG(0x40e1046c)
+#define GPIO54 __REG(0x40e10470)
+#define GPIO55 __REG(0x40e10474)
+#define GPIO56 __REG(0x40e10478)
+#define GPIO57 __REG(0x40e1047c)
+#define GPIO58 __REG(0x40e10480)
+#define GPIO59 __REG(0x40e10484)
+#define GPIO60 __REG(0x40e10488)
+#define GPIO61 __REG(0x40e1048c)
+#define GPIO62 __REG(0x40e10490)
+
+#define GPIO6_2 __REG(0x40e10494)
+#define GPIO7_2 __REG(0x40e10498)
+#define GPIO8_2 __REG(0x40e1049c)
+#define GPIO9_2 __REG(0x40e104a0)
+#define GPIO10_2 __REG(0x40e104a4)
+#define GPIO11_2 __REG(0x40e104a8)
+#define GPIO12_2 __REG(0x40e104ac)
+#define GPIO13_2 __REG(0x40e104b0)
+
+#define GPIO63 __REG(0x40e104b4)
+#define GPIO64 __REG(0x40e104b8)
+#define GPIO65 __REG(0x40e104bc)
+#define GPIO66 __REG(0x40e104c0)
+#define GPIO67 __REG(0x40e104c4)
+#define GPIO68 __REG(0x40e104c8)
+#define GPIO69 __REG(0x40e104cc)
+#define GPIO70 __REG(0x40e104d0)
+#define GPIO71 __REG(0x40e104d4)
+#define GPIO72 __REG(0x40e104d8)
+#define GPIO73 __REG(0x40e104dc)
+
+#define GPIO14_2 __REG(0x40e104e0)
+#define GPIO15_2 __REG(0x40e104e4)
+#define GPIO16_2 __REG(0x40e104e8)
+#define GPIO17_2 __REG(0x40e104ec)
+
+#define GPIO74 __REG(0x40e104f0)
+#define GPIO75 __REG(0x40e104f4)
+#define GPIO76 __REG(0x40e104f8)
+#define GPIO77 __REG(0x40e104fc)
+#define GPIO78 __REG(0x40e10500)
+#define GPIO79 __REG(0x40e10504)
+#define GPIO80 __REG(0x40e10508)
+#define GPIO81 __REG(0x40e1050c)
+#define GPIO82 __REG(0x40e10510)
+#define GPIO83 __REG(0x40e10514)
+#define GPIO84 __REG(0x40e10518)
+#define GPIO85 __REG(0x40e1051c)
+#define GPIO86 __REG(0x40e10520)
+#define GPIO87 __REG(0x40e10524)
+#define GPIO88 __REG(0x40e10528)
+#define GPIO89 __REG(0x40e1052c)
+#define GPIO90 __REG(0x40e10530)
+#define GPIO91 __REG(0x40e10534)
+#define GPIO92 __REG(0x40e10538)
+#define GPIO93 __REG(0x40e1053c)
+#define GPIO94 __REG(0x40e10540)
+#define GPIO95 __REG(0x40e10544)
+#define GPIO96 __REG(0x40e10548)
+#define GPIO97 __REG(0x40e1054c)
+#define GPIO98 __REG(0x40e10550)
+
+#define GPIO99 __REG(0x40e10600)
+#define GPIO100 __REG(0x40e10604)
+#define GPIO101 __REG(0x40e10608)
+#define GPIO102 __REG(0x40e1060c)
+#define GPIO103 __REG(0x40e10610)
+#define GPIO104 __REG(0x40e10614)
+#define GPIO105 __REG(0x40e10618)
+#define GPIO106 __REG(0x40e1061c)
+#define GPIO107 __REG(0x40e10620)
+#define GPIO108 __REG(0x40e10624)
+#define GPIO109 __REG(0x40e10628)
+#define GPIO110 __REG(0x40e1062c)
+#define GPIO111 __REG(0x40e10630)
+#define GPIO112 __REG(0x40e10634)
+
+#define GPIO113 __REG(0x40e10638)
+#define GPIO114 __REG(0x40e1063c)
+#define GPIO115 __REG(0x40e10640)
+#define GPIO116 __REG(0x40e10644)
+#define GPIO117 __REG(0x40e10648)
+#define GPIO118 __REG(0x40e1064c)
+#define GPIO119 __REG(0x40e10650)
+#define GPIO120 __REG(0x40e10654)
+#define GPIO121 __REG(0x40e10658)
+#define GPIO122 __REG(0x40e1065c)
+#define GPIO123 __REG(0x40e10660)
+#define GPIO124 __REG(0x40e10664)
+#define GPIO125 __REG(0x40e10668)
+#define GPIO126 __REG(0x40e1066c)
+#define GPIO127 __REG(0x40e10670)
+
+#define GPIO0_2 __REG(0x40e10674)
+#define GPIO1_2 __REG(0x40e10678)
+#define GPIO2_2 __REG(0x40e1067c)
+#define GPIO3_2 __REG(0x40e10680)
+#define GPIO4_2 __REG(0x40e10684)
+#define GPIO5_2 __REG(0x40e10688)
+
+/* MFPR Bit Definitions, see 4-10, Vol. 1 */
+#define PULL_SEL 0x8000
+#define PULLUP_EN 0x4000
+#define PULLDOWN_EN 0x2000
+
+#define DRIVE_FAST_1mA 0x0
+#define DRIVE_FAST_2mA 0x400
+#define DRIVE_FAST_3mA 0x800
+#define DRIVE_FAST_4mA 0xC00
+#define DRIVE_SLOW_6mA 0x1000
+#define DRIVE_FAST_6mA 0x1400
+#define DRIVE_SLOW_10mA 0x1800
+#define DRIVE_FAST_10mA 0x1C00
+
+#define SLEEP_SEL 0x200
+#define SLEEP_DATA 0x100
+#define SLEEP_OE_N 0x80
+#define EDGE_CLEAR 0x40
+#define EDGE_FALL_EN 0x20
+#define EDGE_RISE_EN 0x10
+
+#define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */
+#define AF_SEL_1 0x1 /* Alternate function 1 */
+#define AF_SEL_2 0x2 /* Alternate function 2 */
+#define AF_SEL_3 0x3 /* Alternate function 3 */
+#define AF_SEL_4 0x4 /* Alternate function 4 */
+#define AF_SEL_5 0x5 /* Alternate function 5 */
+#define AF_SEL_6 0x6 /* Alternate function 6 */
+#define AF_SEL_7 0x7 /* Alternate function 7 */
+
+
+#else /* CONFIG_CPU_MONAHANS */
+
#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
/*
* Memory controller
*/
-
-
+
+#ifdef CONFIG_CPU_MONAHANS
+/* Static Memory Controller Registers */
+#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
+#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
+#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
+#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
+#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
+#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
+#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
+#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
+#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
+#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
+#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
+#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */
+#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */
+
+/* Dynamic Memory Controller Registers */
+#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
+#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
+#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
+#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
+#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */
+#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
+#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
+#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
+#define EMPI __REG_2(0x48100090) /* EMPI Control Register */
+#define RCOMP __REG_2(0x48100100)
+#define PAD_MA __REG_2(0x48100110)
+#define PAD_MDMSB __REG_2(0x48100114)
+#define PAD_MDLSB __REG_2(0x48100118)
+#define PAD_DMEM __REG_2(0x4810011c)
+#define PAD_SDCLK __REG_2(0x48100120)
+#define PAD_SDCS __REG_2(0x48100124)
+#define PAD_SMEM __REG_2(0x48100128)
+#define PAD_SCLK __REG_2(0x4810012C)
+#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+
+/* Some frequently used bits */
+#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
+#define MDCNFG_DTC_1 0x100
+#define MDCNFG_DTC_2 0x200
+#define MDCNFG_DTC_3 0x300
+
+#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
+#define MDCNFG_DRAC_13 0x20
+#define MDCNFG_DRAC_14 0x40
+
+#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10 0x08
+#define MDCNFG_DCAC_11 0x10
+
+#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
+
+
+/* Data Flash Controller Registers */
+
+#define NDCR __REG(0x43100000) /* Data Flash Control register */
+#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR __REG(0x43100014) /* Data Controller Status Register */
+#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
+#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
+#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
+#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
+#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
+#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
+#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
+
+#define NDCR_SPARE_EN (0x1<<31)
+#define NDCR_ECC_EN (0x1<<30)
+#define NDCR_DMA_EN (0x1<<29)
+#define NDCR_ND_RUN (0x1<<28)
+#define NDCR_DWIDTH_C (0x1<<27)
+#define NDCR_DWIDTH_M (0x1<<26)
+#define NDCR_PAGE_SZ (0x3<<24)
+#define NDCR_NCSX (0x1<<23)
+#define NDCR_ND_STOP (0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE (0x3<<21)
+ * #define NDCR_NAND_MODE 0x0 */
+#define NDCR_CLR_PG_CNT (0x1<<20)
+#define NDCR_CLR_ECC (0x1<<19)
+#define NDCR_RD_ID_CNT (0x7<<16)
+#define NDCR_RA_START (0x1<<15)
+#define NDCR_PG_PER_BLK (0x1<<14)
+#define NDCR_ND_ARB_EN (0x1<<12)
+#define NDCR_RDYM (0x1<<11)
+#define NDCR_CS0_PAGEDM (0x1<<10)
+#define NDCR_CS1_PAGEDM (0x1<<9)
+#define NDCR_CS0_CMDDM (0x1<<8)
+#define NDCR_CS1_CMDDM (0x1<<7)
+#define NDCR_CS0_BBDM (0x1<<6)
+#define NDCR_CS1_BBDM (0x1<<5)
+#define NDCR_DBERRM (0x1<<4)
+#define NDCR_SBERRM (0x1<<3)
+#define NDCR_WRDREQM (0x1<<2)
+#define NDCR_RDDREQM (0x1<<1)
+#define NDCR_WRCMDREQM (0x1)
+
+#define NDSR_RDY (0x1<<11)
+#define NDSR_CS0_PAGED (0x1<<10)
+#define NDSR_CS1_PAGED (0x1<<9)
+#define NDSR_CS0_CMDD (0x1<<8)
+#define NDSR_CS1_CMDD (0x1<<7)
+#define NDSR_CS0_BBD (0x1<<6)
+#define NDSR_CS1_BBD (0x1<<5)
+#define NDSR_DBERR (0x1<<4)
+#define NDSR_SBERR (0x1<<3)
+#define NDSR_WRDREQ (0x1<<2)
+#define NDSR_RDDREQ (0x1<<1)
+#define NDSR_WRCMDREQ (0x1)
+
+#define NDCB0_AUTO_RS (0x1<<25)
+#define NDCB0_CSEL (0x1<<24)
+#define NDCB0_CMD_TYPE (0x7<<21)
+#define NDCB0_NC (0x1<<20)
+#define NDCB0_DBC (0x1<<19)
+#define NDCB0_ADDR_CYC (0x7<<16)
+#define NDCB0_CMD2 (0xff<<8)
+#define NDCB0_CMD1 (0xff)
+#define MCMEM(s) MCMEM0
+#define MCATT(s) MCATT0
+#define MCIO(s) MCIO0
+#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH 7
+#define DFC_MAX_tCS 7
+#define DFC_MAX_tWH 7
+#define DFC_MAX_tWP 7
+#define DFC_MAX_tRH 7
+#define DFC_MAX_tRP 15
+#define DFC_MAX_tR 65535
+#define DFC_MAX_tWHR 15
+#define DFC_MAX_tAR 15
+
+#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
+
+#else /* CONFIG_CPU_MONAHANS */
+
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
#define MDCNFG_OFFSET 0x0
#define MDREFR_OFFSET 0x4
--- /dev/null
- /* nand timeout values */
+/*
+ * Configuation settings for the Delta board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_DELTA 1 /* Delta board */
+
+/* #define CONFIG_LCD 1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC 1 */
+#define BOARD_LATE_INIT 1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#undef TURN_ON_ETHERNET
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111_BASE 0x14000300
+# define CONFIG_SMC91111_EXT_PHY
+# define CONFIG_SMC_USE_32_BIT
+# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
+#endif
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#ifdef TURN_ON_ETHERNET
+# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+#else
+# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NAND) \
+ & ~(CFG_CMD_NET | CFG_CMD_FLASH | \
+ CFG_CMD_ENV | CFG_CMD_IMLS))
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY -1
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_IPADDR 192.168.0.21
+#define CONFIG_SERVERIP 192.168.0.250
+#define CONFIG_BOOTCOMMAND "bootm 80000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE 0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
+#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
+
+#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
+#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
+
+#undef CFG_SKIP_DRAM_SCRUB
+
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
+#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
+#undef CFG_NAND1_BASE
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
+
++/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 3000
+#define CFG_NAND_OTHER_TO 100
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH 10
+#define NAND_TIMING_tCS 0
+#define NAND_TIMING_tWH 20
+#define NAND_TIMING_tWP 40
+
+#define NAND_TIMING_tRH 20
+#define NAND_TIMING_tRP 40
+
+#define NAND_TIMING_tR 11123
+/* #define NAND_TIMING_tWHR 110 */
+#define NAND_TIMING_tWHR 100
+#define NAND_TIMING_tAR 10
+
+/* NAND debugging */
+#define CFG_DFC_DEBUG1 /* usefull */
+#undef CFG_DFC_DEBUG2 /* noisy */
+#undef CFG_DFC_DEBUG3 /* extremly noisy */
+
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NO_FLASH 1
+#ifndef CGF_NO_FLASH
+/* these are required by the environment code */
+#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
+#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
+#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00008000
+#define CFG_GPSR1_VAL 0x00FC0382
+#define CFG_GPSR2_VAL 0x0001FFFF
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x0060A800
+#define CFG_GPDR1_VAL 0x00FF0382
+#define CFG_GPDR2_VAL 0x0001C000
+#define CFG_GAFR0_L_VAL 0x98400000
+#define CFG_GAFR0_U_VAL 0x00002950
+#define CFG_GAFR1_L_VAL 0x000A9558
+#define CFG_GAFR1_U_VAL 0x0005AAAA
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x00000002
+
+#define CFG_PSSR_VAL 0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x23F223F2
+#define CFG_MSC1_VAL 0x3FF1A441
+#define CFG_MSC2_VAL 0x7FF97FF1
+#define CFG_MDCNFG_VAL 0x00001AC9
+#define CFG_MDREFR_VAL 0x00018018
+#define CFG_MDMRS_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000000
+#define CFG_MCMEM0_VAL 0x00010504
+#define CFG_MCMEM1_VAL 0x00010504
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00004715
+#define CFG_MCIO1_VAL 0x00004715
+
+#define _LED 0x08000010
+#define LED_BLANK 0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#ifndef CFG_NO_FLASH
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
+
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment. You have been warned!
+ */
+#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+#endif /* #ifndef CFG_NO_FLASH */
+
+#define CFG_ENV_IS_NOWHERE
+/* #define CFG_ENV_IS_IN_NAND 1 */
+#define CFG_ENV_OFFSET 0x40000
+#define CFG_ENV_SIZE 0x4000
+
+#endif /* __CONFIG_H */
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