]> git.sur5r.net Git - u-boot/commitdiff
db410: added pinctrl node and serial bindings
authorRamon Fried <ramon.fried@gmail.com>
Wed, 16 May 2018 09:13:41 +0000 (12:13 +0300)
committerTom Rini <trini@konsulko.com>
Sat, 26 May 2018 22:19:16 +0000 (18:19 -0400)
Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
arch/arm/dts/dragonboard410c.dts

index d9d5831f4f8b781c17026d4ee4cae33adb53444d..182a865b0ab50e4fc888b61609082f55dc77764a 100644 (file)
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
        model = "Qualcomm Technologies, Inc. Dragonboard 410c";
                ranges = <0x0 0x0 0x0 0xffffffff>;
                compatible = "simple-bus";
 
+               pinctrl: qcom,tlmm@1000000 {
+                       compatible = "qcom,tlmm-apq8016";
+                       reg = <0x1000000 0x400000>;
+
+                       blsp1_uart: uart {
+                               function = "blsp1_uart";
+                               pins = "GPIO_4", "GPIO_5";
+                               drive-strength = <DRIVE_STRENGTH_8MA>;
+                               bias-disable;
+                       };
+               };
                clkc: qcom,gcc@1800000 {
                        compatible = "qcom,gcc-apq8016";
                        reg = <0x1800000 0x80000>;
@@ -49,6 +61,8 @@
                        compatible = "qcom,msm-uartdm-v1.4";
                        reg = <0x78b0000 0x200>;
                        clock = <&clkc 4>;
+                       pinctrl-names = "uart";
+                       pinctrl-0 = <&blsp1_uart>;
                };
 
                soc_gpios: pinctrl@1000000 {