VDC_MAWR = 0 ; Memory Address Write Register
VDC_MARR = 1 ; Memory Address Read Register
-VDC_VWR = 2 ; VRAM Write Register (write only)
-VDC_VRR = 2 ; VRAM Read Register (read only)
+VDC_VWR = 2 ; VRAM Write Register
+VDC_VRR = 2 ; VRAM Read Register
VDC_UNK03 = 3 ; (unknown)
VDC_UNK04 = 4 ; (unknown)
VDC_CR = 5 ; Control Register
; VDC port
; Note: The zero-page addressing mode is redirected to page $20.
-; Therefore, absolute addressing mode must be used when writing to this port.
-; We force it by using mirror locations that are outside of zero page.
+; We avoid it by using mirror locations that are outside of the zero page.
VDC_CTRL := $0200
VDC_DATA_LO := $0202
; HuC6260 -- Video Color Encoder (VCE)
; The DAC has a palette of 512 colours.
-; The bitmap of the palette data is this: 0000000gggrrrbbb.
+; The bitmap of that data is 0000000gggrrrbbb (Green, Red, Blue).
; You can read and write the DAC registers.
VCE := $0400 ; base
CDR_MEM_DISABLE := $1803
CDR_MEM_ENABLE := $1807
-; Write VDC register
-.macro VREG arg1,arg2
+; Write to a VDC register.
+.macro VREG arg1, arg2
st0 #arg1
st1 #<(arg2)
st2 #>(arg2)
__STACKSIZE__: type = weak, value = $0300; # 3 pages stack
}
MEMORY {
- ZP: file = "", start = $0000, size = $0100, define = yes;
+ ZP: file = "", start = $0000, define = yes, size = $0100;
# RAM bank
- MAIN: file = "", start = $2200, size = $1E00 - __STACKSIZE__, define = yes;
+ MAIN: file = "", start = $2200, define = yes, size = $1E00 - __STACKSIZE__;
# ROM banks, before swapping, and after mapping
ROM: file = %O, start = $10000 - __CARTSIZE__, size = __CARTSIZE__, fill = yes, fillval = $FF;
}
;
.export _clock
- .constructor initclock, 24
+ .constructor initclock
- .forceimport ticktock
+ .forceimport ticktock ; make sure that tickcount changes
.importzp sreg
.include "extzp.inc"
rts
.endproc
+
+; Make the process clock start at zero.
+
.segment "ONCE"
initclock:
lda #0
+;
+; Clear (erase) the screen.
+;
+; Support the full 128- x 64-tile background.
+;
+
.export _clrscr
.import plot
rowloop:
ldx #$80
colloop:
- lda #' '
+ lda #' ' ; low byte of char. index
sta VDC_DATA_LO
- lda #$02
+ lda #$02 ; background color, high nybble of char. index
sta VDC_DATA_HI
dex
.include "pce.inc"
.include "extzp.inc"
-_bordercolor := return0
+_bordercolor := return0 ; always black
_textcolor:
- ldx CHARCOLOR ; get old value
- sta CHARCOLOR ; set new value
+ ldx CHARCOLOR ; get old value
+ sta CHARCOLOR ; set new value
txa
rts
_bgcolor:
- ldx BGCOLOR ; get old value
- sta BGCOLOR ; set new value
+ ldx BGCOLOR ; get old value
+ sta BGCOLOR ; set new value
asl a
tay
.word ((7<<6)+(7<<3)+(7)) ; $1 white
.word ((0<<6)+(7<<3)+(0)) ; $2 red
.word ((7<<6)+(0<<3)+(7)) ; $3 cyan
- .word ((0<<6)+(5<<3)+(7)) ; $4 violett
+ .word ((0<<6)+(5<<3)+(7)) ; $4 violet
.word ((7<<6)+(0<<3)+(0)) ; $5 green
.word ((0<<6)+(0<<3)+(7)) ; $6 blue
.word ((7<<6)+(7<<3)+(0)) ; $7 yellow
ldx #0
@lp:
- ldy #16
+ ldy #16 ; size of a pallette
@lp1:
lda colors,x
sta VCE_DATA_LO
cpx #16 * 2
jne @lp
+; Set background to black.
+
stz VCE_ADDR_LO
stz VCE_ADDR_HI
stz VCE_DATA_LO
rts
+;----------------------------------------------------------------------------
+; The character tiles use only two colors from each pallette. Color zero
+; comes from pallette zero; color one is different in each pallette. The
+; color of a character is set by choosing one of the 16 pallettes.
+
conio_init:
; Load font
st0 #VDC_MAWR
st1 #<$2000
st2 #>$2000
- ; ptr to font data
+ ; pointer to font data
lda #<font
sta ptr1
lda #>font
sta tmp1
jsr copy
- ldx #0
+ ldx #0 ; white on black
stx BGCOLOR
inx
stx CHARCOLOR
adc #$00
sta ptr1+1
dex
- bne lineloop ; next bitplane 0 byte
- ldx #$08 ; fill bitplane 2/3 with 0
+ bne lineloop ; next bitplane-0 byte
+ ldx #$08 ; fill bitplanes 2 and 3 with 0
fillloop:
- st1 #$00
- st2 #$00
+ st1 #<$0000
+ st2 #>$0000
dex
bne fillloop ; next byte
dey
bne L1
lda #0
sta CURS_X
- beq plot ; Recalculate pointers
+ beq plot ; Recalculate pointer
L1: cmp #$0A ; LF?
- beq newline ; Recalculate pointers
+ beq newline ; Recalculate pointer
; Printable char of some sort
newline:
inc CURS_Y
-; Set cursor position, calculate RAM pointers
+; Set cursor position; calculate VRAM pointer.
plot: ldy CURS_X
ldx CURS_Y
clc
jmp PLOT ; Set the new cursor
-; Write one character to the screen without doing anything else, return X
-; position in Y
+; Write one character to the screen without doing anything else.
putchar:
-
ora RVS ; Set revers bit
tax
- st0 #VDC_MAWR ; Memory Adress Write
+ st0 #VDC_MAWR ; Memory Address Write
lda SCREEN_PTR
sta VDC_DATA_LO
txa
sta VDC_DATA_LO ; character
- lda CHARCOLOR
-
+ lda CHARCOLOR ; pallette number
asl a
asl a
asl a
csh ; Set high-speed CPU mode
nop
- ; Set up stack and memory mapping
+ ; Set up stack and memory mapping.
ldx #$FF ; Stack top ($21FF)
txs
; Turn on background and VD interrupt/IRQ1
lda #$05
- sta IRQ_MASK ; IRQ1=on
+ sta IRQ_MASK ; IRQ1 = on
; Copy the .data segment to RAM
tii __DATA_LOAD__, __DATA_RUN__, __DATA_SIZE__
lda #<(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
ldx #>(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
sta sp
- stx sp + 1
+ stx sp+1
; Call module constructors
jsr initlib
.include "ctype.inc"
-; The tables are readonly, put them into the rodata segment
+; The tables are read-only; put them into the RODATA segment.
.rodata
;
; * We save some code in the isxxx functions.
-
__ctype:
.repeat 2
.byte CT_CTRL ; 0/00 ___ctrl_@___
;
-; void gotoxy (unsigned char x, unsigned char y);
+; void __fastcall__ gotoxy (unsigned char x, unsigned char y);
;
.export gotoxy, _gotoxy
;
.export _joy_static_stddrv
- .import _pce_stdjoy_joy
-.rodata
+ .import _pce_stdjoy_joy
_joy_static_stddrv := _pce_stdjoy_joy
.segment "ONCE"
psg_init:
clx
- stz PSG_GLOBAL_PAN ; Clear global balance
+ stz PSG_GLOBAL_PAN ; Silence global balance
psg_clear_loop:
stx PSG_CHAN_SELECT ; Select channel
+;
+; Ullrich von Bassewitz, 07.08.1998
+;
+; unsigned char revers (unsigned char onoff);
+;
.export _revers
- .include "pce.inc"
.include "extzp.inc"
.proc _revers
tya ; Load low byte, set CC
rts
.endproc
-
-;-------------------------------------------------------------------------------
-; force the init constructor to be imported
-
- .import initconio
-conio_init = initconio
-
.export vdc_init
.include "pce.inc"
VREG $06, $0000 ; RCR
VREG $07, $0000 ; BXR
VREG $08, $0000 ; BYR
- VREG $09, $0070 ; MAWR
+ VREG $09, $0070 ; MWR
VREG $0C, $1702 ; CRTC - VSR
VREG $0D, $00DF ; CRTC - VDS
VREG $0E, $000C ; CRTC - VDE
.export _waitvsync
- .forceimport ticktock
+ .forceimport ticktock ; make sure that tickcount changes
- .include "pce.inc"
.include "extzp.inc"
.proc _waitvsync