]> git.sur5r.net Git - u-boot/commitdiff
ARM: AM33xx: Cleanup clocks layer
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 30 Jul 2013 05:18:53 +0000 (10:48 +0530)
committerTom Rini <trini@ti.com>
Thu, 15 Aug 2013 12:51:10 +0000 (08:51 -0400)
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/clock_ti814x.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
board/isee/igep0033/board.c
board/ti/am335x/board.c
board/ti/ti814x/evm.c

index f1623db13df48c3d7a06037f80464ed8e5a3bea1..64a3af79020af7b3ad8a4fb53f6236d4f1a0597a 100644 (file)
@@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void setup_clocks_for_console(void)
-{
-       /* Not yet implemented */
-       return;
-}
-
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
        (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
index 15f4a2c32617549bbf85d39d76b85e2745d3c615..8e5f3c671503be332e2870694fa640ff82b9e70c 100644 (file)
@@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
        wait_for_lock(dpll_regs);
 }
 
-void setup_dplls(void)
+static void setup_dplls(void)
 {
        const struct dpll_params *params;
        do_setup_dpll(&dpll_core_regs, &dpll_core);
@@ -109,3 +109,63 @@ void setup_dplls(void)
        params = get_dpll_ddr_params();
        do_setup_dpll(&dpll_ddr_regs, params);
 }
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+       u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+       u32 bound = LDELAY;
+
+       while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+               (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+               clkctrl = readl(clkctrl_addr);
+               idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+                        MODULE_CLKCTRL_IDLEST_SHIFT;
+               if (--bound == 0) {
+                       printf("Clock enable failed for 0x%p idlest 0x%x\n",
+                              clkctrl_addr, clkctrl);
+                       return;
+               }
+       }
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+                                      u32 wait_for_enable)
+{
+       clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+                       enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       debug("Enable clock module - %p\n", clkctrl_addr);
+       if (wait_for_enable)
+               wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+       clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+                       enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+       debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+                     u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+       u32 i, max = 100;
+
+       /* Put the clock domains in SW_WKUP mode */
+       for (i = 0; (i < max) && clk_domains[i]; i++) {
+               enable_clock_domain(clk_domains[i],
+                                   CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+       }
+
+       /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+       for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+               enable_clock_module(clk_modules_explicit_en[i],
+                                   MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+                                   wait_for_enable);
+       };
+}
+
+void prcm_init()
+{
+       enable_basic_clocks();
+       setup_dplls();
+}
index d5d47ad74b6a0fd240b4e4655417e412f014eac0..e5f287b338217479da49fecbf7d2669fc1cd85cd 100644 (file)
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
-#define PRCM_MOD_EN            0x2
-#define PRCM_FORCE_WAKEUP      0x2
-#define PRCM_FUNCTL            0x0
-
-#define CPGMAC0_IDLE           0x30000
 #define OSC    (V_OSCK/1000000)
 
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
 const struct dpll_regs dpll_mpu_regs = {
        .cm_clkmode_dpll        = CM_WKUP + 0x88,
@@ -63,199 +58,85 @@ const struct dpll_params dpll_core = {
 const struct dpll_params dpll_per = {
                960, OSC-1, 5, -1, -1, -1, -1};
 
-static void enable_interface_clocks(void)
-{
-       /* Enable all the Interconnect Modules */
-       writel(PRCM_MOD_EN, &cmper->l3clkctrl);
-       while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
-       while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
-       while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
-       while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
-       while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
-       while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
-               ;
-
-       writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
-       while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
-               ;
-}
-
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
+void setup_clocks_for_console(void)
 {
-       writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
-       writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
-       writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
-       writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
-       writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+       clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+                       CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+                       CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+       clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+                       CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+                       CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+       clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       clrsetbits_le32(&cmper->uart1clkctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       clrsetbits_le32(&cmper->uart2clkctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       clrsetbits_le32(&cmper->uart3clkctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       clrsetbits_le32(&cmper->uart4clkctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
+       clrsetbits_le32(&cmper->uart5clkctrl,
+                       MODULE_CLKCTRL_MODULEMODE_MASK,
+                       MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+                       MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
+void enable_basic_clocks(void)
 {
-       /* Enable the control module though RBL would have done it*/
-       writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
-       while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* Enable the module clock */
-       writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
-       while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
-               ;
+       u32 *const clk_domains[] = {
+               &cmper->l3clkstctrl,
+               &cmper->l4fwclkstctrl,
+               &cmper->l3sclkstctrl,
+               &cmper->l4lsclkstctrl,
+               &cmwkup->wkclkstctrl,
+               &cmper->emiffwclkctrl,
+               &cmrtc->clkstctrl,
+               0
+       };
+
+       u32 *const clk_modules_explicit_en[] = {
+               &cmper->l3clkctrl,
+               &cmper->l4lsclkctrl,
+               &cmper->l4fwclkctrl,
+               &cmwkup->wkl4wkclkctrl,
+               &cmper->l3instrclkctrl,
+               &cmper->l4hsclkctrl,
+               &cmwkup->wkgpio0clkctrl,
+               &cmwkup->wkctrlclkctrl,
+               &cmper->timer2clkctrl,
+               &cmper->gpmcclkctrl,
+               &cmper->elmclkctrl,
+               &cmper->mmc0clkctrl,
+               &cmper->mmc1clkctrl,
+               &cmwkup->wkup_i2c0ctrl,
+               &cmper->gpio1clkctrl,
+               &cmper->gpio2clkctrl,
+               &cmper->gpio3clkctrl,
+               &cmper->i2c1clkctrl,
+               &cmper->cpgmac0clkctrl,
+               &cmper->spi0clkctrl,
+               &cmrtc->rtcclkctrl,
+               &cmper->usb0clkctrl,
+               &cmper->emiffwclkctrl,
+               &cmper->emifclkctrl,
+               0
+       };
+
+       do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 
        /* Select the Master osc 24 MHZ as Timer2 clock source */
        writel(0x1, &cmdpll->clktimer2clk);
-
-       /* UART0 */
-       writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
-       while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
-               ;
-
-       /* UART1 */
-#ifdef CONFIG_SERIAL2
-       writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
-       while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
-               ;
-#endif /* CONFIG_SERIAL2 */
-
-       /* UART2 */
-#ifdef CONFIG_SERIAL3
-       writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
-       while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
-               ;
-#endif /* CONFIG_SERIAL3 */
-
-       /* UART3 */
-#ifdef CONFIG_SERIAL4
-       writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
-       while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
-               ;
-#endif /* CONFIG_SERIAL4 */
-
-       /* UART4 */
-#ifdef CONFIG_SERIAL5
-       writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
-       while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
-               ;
-#endif /* CONFIG_SERIAL5 */
-
-       /* UART5 */
-#ifdef CONFIG_SERIAL6
-       writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
-       while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
-               ;
-#endif /* CONFIG_SERIAL6 */
-
-       /* GPMC */
-       writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
-       while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* ELM */
-       writel(PRCM_MOD_EN, &cmper->elmclkctrl);
-       while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* MMC0*/
-       writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
-       while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* MMC1 */
-       writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
-       while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* i2c0 */
-       writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
-       while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
-               ;
-
-       /* gpio1 module */
-       writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
-       while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* gpio2 module */
-       writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
-       while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* gpio3 module */
-       writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
-       while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* i2c1 */
-       writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
-       while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* Ethernet */
-       writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
-       while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
-               ;
-
-       /* spi0 */
-       writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
-       while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* RTC */
-       writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
-       while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
-               ;
-
-       /* MUSB */
-       writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
-       while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
-               ;
-}
-
-void enable_emif_clocks(void)
-{
-       /* Enable the  EMIF_FW Functional clock */
-       writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
-       /* Enable EMIF0 Clock */
-       writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-       /* Poll if module is functional */
-       while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
-               ;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
-       setup_dplls();
-       /* Enable the required interconnect clocks */
-       enable_interface_clocks();
-
-       /* Power domain wake up transition */
-       power_domain_wkup_transition();
-
-       /* Enable the required peripherals */
-       enable_per_clocks();
 }
index 658772bbe39598a414b4b9243d099bcfa5c90a64..965e875575f468dd7255bfd2f5cca6b3ea5f24dd 100644 (file)
@@ -264,11 +264,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
  */
 static void enable_per_clocks(void)
 {
-       /* UART0 */
-       writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
-       while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
-               ;
-
        /* HSMMC1 */
        writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
        while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
@@ -455,8 +450,6 @@ void sata_pll_config(void)
                ;
 }
 
-void enable_emif_clocks(void) {};
-
 void enable_dmm_clocks(void)
 {
        writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
@@ -477,13 +470,19 @@ void enable_dmm_clocks(void)
                ;
 }
 
+void setup_clocks_for_console(void)
+{
+       unlock_pll_control_mmr();
+       /* UART0 */
+       writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+       while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+               ;
+}
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */
-void pll_init()
+void prcm_init(void)
 {
-       unlock_pll_control_mmr();
-
        /* Enable the control module */
        writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 
index 15c4734b2718cca1003547b112b00dfc33efaca1..21cefd41372af7bbd752aeb1bcf57f655393306c 100644 (file)
@@ -87,7 +87,6 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs, int nr)
 {
-       enable_emif_clocks();
        ddr_pll_config(pll);
        config_vtp(nr);
        config_cmd_ctrl(ctrl, nr);
index 703b80e51839e6c4159fc4435edb46da6d5b4eae..0d4b9ae6f8a28b1c536614defaeda67f7b36fe88 100644 (file)
 
 #define LDELAY 1000000
 
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT             0
+#define CD_CLKCTRL_CLKTRCTRL_MASK              3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP          0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP          1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP           2
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT                0
+#define MODULE_CLKCTRL_MODULEMODE_MASK         3
+#define MODULE_CLKCTRL_IDLEST_SHIFT            16
+#define MODULE_CLKCTRL_IDLEST_MASK             (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE           0
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN       2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING    1
+#define MODULE_CLKCTRL_IDLEST_IDLE             2
+#define MODULE_CLKCTRL_IDLEST_DISABLED         3
+
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT         11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK          (1 << 11)
@@ -77,10 +99,12 @@ extern const struct dpll_params dpll_core;
 extern const struct dpll_params dpll_per;
 extern const struct dpll_params dpll_ddr;
 
-extern const struct cm_wkuppll *cmwkup;
+extern struct cm_wkuppll *const cmwkup;
 
-void setup_dplls(void);
 const struct dpll_params *get_dpll_ddr_params(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+void prcm_init(void);
+void enable_basic_clocks(void);
+void do_enable_clocks(u32 *const *, u32 *const *, u8);
 
 #endif
index 683ba8ea99ef3776fcc89a86c9923c06b085c1a5..18d7d99a4ca1009d6bf88b590768eee2529933d6 100644 (file)
@@ -146,8 +146,6 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 
-void ddr_pll_config(unsigned int ddrpll_m);
-
 struct ddr_cmd_regs {
        unsigned int resv0[7];
        unsigned int cm0csratio;        /* offset 0x01C */
index 034a8aa7cebfa904d255a69cd4647a408faf9f61..a065a7422f4740ae579774d2af44b33c4cd7874b 100644 (file)
@@ -103,11 +103,7 @@ void s_init(void)
                ;
 
 #ifdef CONFIG_SPL_BUILD
-       /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       /* Enable RTC32K clock */
-       rtc32k_enable();
+       setup_clocks_for_console();
 
        enable_uart0_pin_mux();
 
@@ -116,6 +112,11 @@ void s_init(void)
 
        preloader_console_init();
 
+       prcm_init();
+
+       /* Enable RTC32K clock */
+       rtc32k_enable();
+
        /* Configure board pin mux */
        enable_board_pin_mux();
 
index 2be229746b99768f54bff3ef3d04c1e9a47154ae..a6edc2d62706cfae061e268e00409dcb97926237 100644 (file)
@@ -317,10 +317,7 @@ void s_init(void)
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
        /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       /* Enable RTC32K clock */
-       rtc32k_enable();
+       setup_clocks_for_console();
 
 #ifdef CONFIG_SERIAL1
        enable_uart0_pin_mux();
@@ -354,12 +351,14 @@ void s_init(void)
        preloader_console_init();
 #endif
 
-       /* Initalize the board header */
-       enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       prcm_init();
+
        if (read_eeprom(&header) < 0)
                puts("Could not get board ID.\n");
 
+       /* Enable RTC32K clock */
+       rtc32k_enable();
+
        enable_board_pin_mux(&header);
        if (board_is_evm_sk(&header)) {
                /*
index c469645ff3d5a991595f42a990c88a1b8f0a8cd7..bd708bb367399e99806cce30077ebed85eb4a540 100644 (file)
@@ -125,11 +125,7 @@ void s_init(void)
        /* Enable timer */
        timer_init();
 
-       /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       /* Enable RTC32K clock */
-       rtc32k_enable();
+       setup_clocks_for_console();
 
        /* Set UART pins */
        enable_uart0_pin_mux();
@@ -147,6 +143,12 @@ void s_init(void)
 
        preloader_console_init();
 
+       /* Setup the PLLs and the clocks for the peripherals */
+       prcm_init();
+
+       /* Enable RTC32K clock */
+       rtc32k_enable();
+
        config_dmm(&evm_lisa_map_regs);
 
        config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,