soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations

Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 706b21d09a419288af21c20c770f6b570bef989d..28de3f5010703c0dc636ccad06263758f84385f4 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -79,6 +79,9 @@
 #define KS2_DDR3B_EMIF_DATA_BASE       0x60000000
 #define KS2_DDR3B_DDRPHYC              0x02328000
 
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES     4
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS                   8
 

diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 0441b291cc8f22200e245f068cddf48962ae74a3..6e2e939bf49890423bca28ad2652a9521fbd1b8e 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -177,6 +177,9 @@ typedef volatile unsigned int   *dv_reg_p;
 
 #define KS2_MAC_ID_BASE_ADDR           (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
 
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES_BASE          0x0232a000
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif

diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c
index dc4e78d575847c8c8684e9c9681e26dfe04dbc7d..3632c22be29adaf9fbf76067902c1618805d4d2c 100644 (file)
--- a/drivers/soc/keystone/keystone_serdes.c
+++ b/drivers/soc/keystone/keystone_serdes.c
@@ -9,92 +9,94 @@
 
 #include <common.h>
 
+#define SERDES_LANE_REGS(x)            (0x0200 + (0x200 * (x)))
+
+struct serdes_cfg {
+       u32 ofs;
+       u32 val;
+       u32 mask;
+};
+
+static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
+       {0x0000, 0x00800000, 0xffff0000},
+       {0x0014, 0x00008282, 0x0000ffff},
+       {0x0060, 0x00142438, 0x00ffffff},
+       {0x0064, 0x00c3c700, 0x00ffff00},
+       {0x0078, 0x0000c000, 0x0000ff00}
+};
+
+static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
+       {0x0a00, 0x00000800, 0x0000ff00},
+       {0x0a08, 0x38a20000, 0xffff0000},
+       {0x0a30, 0x008a8a00, 0x00ffff00},
+       {0x0a84, 0x00000600, 0x0000ff00},
+       {0x0a94, 0x10000000, 0xff000000},
+       {0x0aa0, 0x81000000, 0xff000000},
+       {0x0abc, 0xff000000, 0xff000000},
+       {0x0ac0, 0x0000008b, 0x000000ff},
+       {0x0b08, 0x583f0000, 0xffff0000},
+       {0x0b0c, 0x0000004e, 0x000000ff}
+};
+
+static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
+       {0x0004, 0x38000080, 0xff0000ff},
+       {0x0008, 0x00000000, 0x000000ff},
+       {0x000c, 0x02000000, 0xff000000},
+       {0x0010, 0x1b000000, 0xff000000},
+       {0x0014, 0x00006fb8, 0x0000ffff},
+       {0x0018, 0x758000e4, 0xffff00ff},
+       {0x00ac, 0x00004400, 0x0000ff00},
+       {0x002c, 0x00100800, 0x00ffff00},
+       {0x0080, 0x00820082, 0x00ff00ff},
+       {0x0084, 0x1d0f0385, 0xffffffff}
+
+};
+
+static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
+{
+       writel(((readl(addr) & (~mask)) | (value & mask)), addr);
+}
+
+static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
+{
+       u32 i;
+
+       for (i = 0; i < size; i++)
+               ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
+}
+
+static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
+                                  u32 size, u32 lane)
+{
+       u32 i;
+
+       for (i = 0; i < size; i++)
+               ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
+                              cfg_lane[i].val, cfg_lane[i].mask);
+}
+
+static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
+{
+       u32 i;
+
+       ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
+                            ARRAY_SIZE(cfg_cmu_156p25m_5g));
+       ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
+                            ARRAY_SIZE(cfg_comlane_156p25m_5g));
+
+       for (i = 0; i < num_lanes; i++)
+               ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
+                                      ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
+
+       return 0;
+}
+
 void ks2_serdes_sgmii_156p25mhz_setup(void)
 {
        unsigned int cnt;
 
-       /*
-        * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
-        * hardware vendor published only register addresses and their values
-        * to be used for configuring SerDes. So had to use hardcoded values
-        * below.
-        */
-       clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
-       clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
-       clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
-       clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
-       clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
-
-       clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
-       clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
-       clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
-       clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
-       clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
-       clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
-       clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
-       clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
-       clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
-       clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
-
-       clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
-       clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
-       clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
-       clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
-       clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
-       clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
-       clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
-       clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
-       clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
-       clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
-
-       clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
-       clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
-       clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
-       clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
-       clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
-       clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
-       clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
-       clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
-       clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
-       clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
-
-       clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
-       clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
-       clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
-       clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
-       clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
-       clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
-       clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
-       clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
-       clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
-       clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
-
-       clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
-       clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
-       clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
-       clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
-       clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
-       clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
-       clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
-       clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
-       clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
-       clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
-       clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
-       clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
-
-       clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
-       clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
-       clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
-       clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
-       clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
-       clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
-       clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
-       clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
-       clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
-       clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
-       clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
-       clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
-       clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
+       ks2_serdes_init_156p25m_5g(CONFIG_KS2_SERDES_SGMII_BASE,
+                                  CONFIG_KS2_SERDES_LANES_PER_SGMII);
 
        /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
        clrbits_le32(0x0232a010, 1 << 28);

diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index ec3f72effd7a9c30dbe3bca5fd086119d3356e0a..8037c3e6e297e4161b2df0f91cf469fccc77efa4 100644 (file)
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -319,4 +319,8 @@
    which is NOT applicable for DDR ECC test */
 #define CONFIG_MAX_UBOOT_MEM_SIZE      (4 << 20)       /* 4 MiB */
 
+/* SGMII SerDes */
+#define CONFIG_KS2_SERDES_SGMII_BASE           KS2_SGMII_SERDES_BASE
+#define CONFIG_KS2_SERDES_LANES_PER_SGMII      KS2_LANES_PER_SGMII_SERDES
+
 #endif /* __CONFIG_KS2_EVM_H */