powerpc/t104xrdb: Update DDR initialization related settings

Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 9009afa3ad890625346b7046b370ce789b9bc8a6..57d0f9cfd867bbe83375aa998f7748ee7b2d26b9 100644 (file)
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
        pbsp = udimms[0];
 
-       /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+       /* Get clk_adjust according to the board ddr
         * freqency and n_banks specified in board_specific_parameters table.
         */
        ddr_freq = get_ddr_freq(0) / 1000000;
@@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                if (pbsp->n_ranks == pdimm->n_ranks &&
                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
-                               popts->cpo_override = pbsp->cpo;
-                               popts->write_data_delay =
-                                       pbsp->write_data_delay;
                                popts->clk_adjust = pbsp->clk_adjust;
                                popts->wrlvl_start = pbsp->wrlvl_start;
                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                printf("for data rate %lu MT/s\n", ddr_freq);
                printf("Trying to use the highest speed (%u) parameters\n",
                       pbsp_highest->datarate_mhz_high);
-               popts->cpo_override = pbsp_highest->cpo;
-               popts->write_data_delay = pbsp_highest->write_data_delay;
                popts->clk_adjust = pbsp_highest->clk_adjust;
                popts->wrlvl_start = pbsp_highest->wrlvl_start;
                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }
@@ -112,8 +105,8 @@ found:
        popts->zq_en = 1;
 
        /* DHC_EN =1, ODT = 75 Ohm */
-       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
 }
 
 phys_size_t initdram(int board_type)

diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index 9276b596ac0e20a07e107152fddd41c5277932ce..09b30b9aac7f041a620dd67f1478122e55f302ef 100644 (file)
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -6,7 +6,6 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
-
 dimm_params_t ddr_raw_timing = {
        .n_ranks = 2,
        .rank_density = 2147483648u,
@@ -14,22 +13,21 @@ dimm_params_t ddr_raw_timing = {
        .primary_sdram_width = 64,
        .ec_sdram_width = 8,
        .registered_dimm = 0,
-       .mirrored_dimm = 1,
+       .mirrored_dimm = 0,
        .n_row_addr = 15,
        .n_col_addr = 10,
        .n_banks_per_sdram_device = 8,
        .edc_config = 2,        /* ECC */
        .burst_lengths_bitmask = 0x0c,
-
        .tckmin_x_ps = 1071,
-       .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
-       .taa_ps = 13910,
+       .caslat_x = 0xfe << 4,  /* 5,6,7,8,9,10,11 */
+       .taa_ps = 13125,
        .twr_ps = 15000,
-       .trcd_ps = 13910,
+       .trcd_ps = 13125,
        .trrd_ps = 6000,
-       .trp_ps = 13910,
+       .trp_ps = 13125,
        .tras_ps = 34000,
-       .trc_ps = 48910,
+       .trc_ps = 48125,
        .trfc_ps = 260000,
        .twtr_ps = 7500,
        .trtp_ps = 7500,
@@ -45,9 +43,6 @@ struct board_specific_parameters {
        u32 wrlvl_start;
        u32 wrlvl_ctl_2;
        u32 wrlvl_ctl_3;
-       u32 cpo;
-       u32 write_data_delay;
-       u32 force_2t;
 };
 
 /*
@@ -59,14 +54,21 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
        /*
         * memory controller 0
-        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl
+        * ranks| mhz| GB  |adjst| start |   ctl2
         */
-       {2,  1066, 4, 8,     4, 0x05070609, 0x08090a08,   0xff,    2,  0},
-       {2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-       {2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+       {2,  833,  4, 4,     6, 0x06060607, 0x08080807},
+       {2,  833,  0, 4,     6, 0x06060607, 0x08080807},
+       {2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+       {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+       {2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+       {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+       {1,  833,  4, 4,     6, 0x06060607, 0x08080807},
+       {1,  833,  0, 4,     6, 0x06060607, 0x08080807},
+       {1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
+       {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
+       {1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
+       {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
        {}
 };
 

diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h
index fd010c057c38f96067d59bf4bb3d9a3e7e55bcad..395845bd68d1889d094eba4c75f217699935dc4f 100644 (file)
--- a/include/configs/T1040RDB.h
+++ b/include/configs/T1040RDB.h
@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING

diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h
index 6d07805ffd039898f6771a230cd5a3f8db7cd4fb..68656e6ef15fc4e1d9efa7ae49e8b4f36970f4e9 100644 (file)
--- a/include/configs/T1042RDB_PI.h
+++ b/include/configs/T1042RDB_PI.h
@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING