powerpc/mpc85xx: Update serdes protocols for T1040

T1040 has only one SerDes block. so update the code accordingly.

Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
0xA7 and 0xAA

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 25db899e5fb806948eb4bf28ffea25bb41216095..70e09eaed5994a9a8516bc7c597efa9ed575fbe4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -75,6 +75,8 @@ static const char *serdes_prtcl_str[] = {
        [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
        [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
        [INTERLAKEN] = "INTERLAKEN",
+       [QSGMII_SW1_A] = "QSGMII_SW1_A",
+       [QSGMII_SW1_B] = "QSGMII_SW1_B",
 };
 #endif
 

diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index 94814ac13e6f4a124d7ebba999c61c1d366e2171..d86bb2737246201e14a63508f2a6c8b3ab0b4015 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -8,68 +8,59 @@
 #include <asm/fsl_serdes.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include "fsl_corenet2_serdes.h"
 
-static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
-       {       /* SerDes 1 */
-       [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
-               PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+       [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
+               PCIE2, PCIE2, PCIE2, PCIE2},
+       [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
+               PCIE2, PCIE3, PCIE4, SATA1},
+       [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
+               PCIE2, PCIE3, SATA2, SATA1},
+       [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               PCIE2, PCIE2, PCIE2, PCIE2},
+       [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+               PCIE2, PCIE2, PCIE2, PCIE2},
        [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
                PCIE2, PCIE3, PCIE4, SATA1},
        [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-       [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
-               PCIE2, PCIE2, PCIE2, PCIE2},
-       [0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
-               PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
-       [0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
-               PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
+       [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
+               PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
        [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                PCIE2, PCIE3, PCIE4, SATA1},
+       [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
        [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-       [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
-       [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-                PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-       [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               PCIE2, PCIE2, PCIE2, PCIE2},
-       [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
-               PCIE2, PCIE3, PCIE4, SATA1},
-       [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
-               PCIE2, PCIE3, SATA2, SATA1},
+       [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+               PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
+       [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
+               PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
        [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-       [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-               PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
        [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
-       [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
-               PCIE2, PCIE2, PCIE2, PCIE2},
-       },
-       {
-       },
-       {
-       },
-       {
-       },
+       [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+                PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
+       [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+                PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
 };
 
-
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
 {
-       return serdes_cfg_tbl[serdes][cfg][lane];
+       return serdes_cfg_tbl[cfg][lane];
 }
 
 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 {
        int i;
 
-       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
                return 0;
 
        for (i = 0; i < SRDS_MAX_LANES; i++) {
-               if (serdes_cfg_tbl[serdes][prtcl][i] != NONE)
+               if (serdes_cfg_tbl[prtcl][i] != NONE)
                        return 1;
        }
 

diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 404ded4580ac7b361f27f77b794b8eb4fa3a76be..f60cb0a6de22522cd7265c4d95134a30aacbfbea 100644 (file)
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -69,13 +69,7 @@ enum srds_prtcl {
        XFI_FM2_MAC9,
        XFI_FM2_MAC10,
        INTERLAKEN,
-       SGMII_SW1_DTSEC1,       /* SW indicates on L2 switch */
-       SGMII_SW1_DTSEC2,
-       SGMII_SW1_DTSEC3,
-       SGMII_SW1_DTSEC4,
-       SGMII_SW1_DTSEC5,
-       SGMII_SW1_DTSEC6,
-       QSGMII_SW1_A,           /* SW indicates on L2 swtich */
+       QSGMII_SW1_A,           /* Indicates ports on L2 Switch */
        QSGMII_SW1_B,
 };