* functions
*/
unsigned char get_random_hex(void);
-unsigned int kw_sdram_bar(enum memory_bank bank);
-unsigned int kw_sdram_bs(enum memory_bank bank);
-void kw_sdram_size_adjust(enum memory_bank bank);
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
+#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
#define KW_TWSI_BASE (KW_REGISTER(0x11000))
#define KW_UART0_BASE (KW_REGISTER(0x12000))
#define KW_UART1_BASE (KW_REGISTER(0x12100))
DECLARE_GLOBAL_DATA_PTR;
-struct kw_sdram_bank {
+struct sdram_bank {
u32 win_bar;
u32 win_sz;
};
-struct kw_sdram_addr_dec {
- struct kw_sdram_bank sdram_bank[4];
+struct sdram_addr_dec {
+ struct sdram_bank sdram_bank[4];
};
-#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
-#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
-#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
-#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+#define REG_CPUCS_WIN_ENABLE (1 << 0)
+#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
/*
- * kw_sdram_bar - reads SDRAM Base Address Register
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
*/
-u32 kw_sdram_bar(enum memory_bank bank)
+u32 mvebu_sdram_bar(enum memory_bank bank)
{
- struct kw_sdram_addr_dec *base =
- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
u32 result = 0;
u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
}
/*
- * kw_sdram_bs_set - writes SDRAM Bank size
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
*/
-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
{
- struct kw_sdram_addr_dec *base =
- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
/* Read current register value */
u32 reg = readl(&base->sdram_bank[bank].win_sz);
/* Clear window size */
- reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+ reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
/* Set new window size */
- reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+ reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
writel(reg, &base->sdram_bank[bank].win_sz);
}
/*
- * kw_sdram_bs - reads SDRAM Bank size
+ * mvebu_sdram_bs - reads SDRAM Bank size
*/
-u32 kw_sdram_bs(enum memory_bank bank)
+u32 mvebu_sdram_bs(enum memory_bank bank)
{
- struct kw_sdram_addr_dec *base =
- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
u32 result = 0;
u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
return result;
}
-void kw_sdram_size_adjust(enum memory_bank bank)
+void mvebu_sdram_size_adjust(enum memory_bank bank)
{
u32 size;
/* probe currently equipped RAM size */
- size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+ size = get_ram_size((void *)mvebu_sdram_bar(bank),
+ mvebu_sdram_bs(bank));
/* adjust SDRAM window size accordingly */
- kw_sdram_bs_set(bank, size);
+ mvebu_sdram_bs_set(bank, size);
}
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+ gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+ gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
/* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
#endif
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
/* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
/* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
set_led(LED_POWER_BLINKING);
int board_init(void)
{
/* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/* Boot parameters address */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
#endif
/* adjust SDRAM size for bank 0 */
- kw_sdram_size_adjust(0);
+ mvebu_sdram_size_adjust(0);
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* The KM_FLASH_GPIO_PIN switches between using a
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
projects / u-boot / commitdiff