phylib: add natsemi dp83630 phy

add natsemi dp83630 phy, used on the upcoming siemens boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
index ea60ac1b0e6513b930d2c3191cec090e68b5b69a..6dc7ed50598ea699b874460a9524bd1e6c7ba46f 100644 (file)
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -22,6 +22,42 @@
  */
 #include <phy.h>
 
+/* NatSemi DP83630 */
+
+#define DP83630_PHY_PAGESEL_REG                0x13
+#define DP83630_PHY_PTP_COC_REG                0x14
+#define DP83630_PHY_PTP_CLKOUT_EN      (1<<15)
+#define DP83630_PHY_RBR_REG            0x17
+
+static int dp83630_config(struct phy_device *phydev)
+{
+       int ptp_coc_reg;
+
+       phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+       phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
+       ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+                              DP83630_PHY_PTP_COC_REG);
+       ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
+       phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
+                 ptp_coc_reg);
+       phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
+
+       genphy_config_aneg(phydev);
+
+       return 0;
+}
+
+static struct phy_driver DP83630_driver = {
+       .name = "NatSemi DP83630",
+       .uid = 0x20005ce1,
+       .mask = 0xfffffff0,
+       .features = PHY_BASIC_FEATURES,
+       .config = &dp83630_config,
+       .startup = &genphy_startup,
+       .shutdown = &genphy_shutdown,
+};
+
+
 /* DP83865 Link and Auto-Neg Status Register */
 #define MIIM_DP83865_LANR      0x11
 #define MIIM_DP83865_SPD_MASK  0x0018
@@ -90,6 +126,7 @@ static struct phy_driver DP83865_driver = {
 
 int phy_natsemi_init(void)
 {
+       phy_register(&DP83630_driver);
        phy_register(&DP83865_driver);
 
        return 0;