sunxi: Fix pcDuino reliability by downclocking DRAM to 360MHz

Linksprite_pcDuino_defconfig is a generic config for pcDuino1 and
pcDuino2 boards. The pcDuino2 board exists at least in two variants
(with DDR3 chips from HYNIX or NANYA). At least one pcDuino2 board
with HYNIX DDR3 fails the lima-memtester reliability test unless
the DRAM clock speed is reduced to 360MHz.

A detailed analysis report, generated by the a10-tpr3-scan tool with
the explanations why the DRAM is failing at 408MHz, is available at:
    http://linux-sunxi.org/index.php?title=User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test&oldid=15152
    http://web.archive.org/web/20151008190210/http://linux-sunxi.org/User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index de448908ec8ef2ef7bcff032088c8db31376d50d..68d913731e436ce105fb102d2f4c24ea54179637 100644 (file)
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN4I=y
-CONFIG_DRAM_CLK=408
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y