MIPS: fix inconsistency in config option for cache operation mode

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 5ce0ec45fc3509fa81a27e0a5e7ea342d3ad1048..e683e8be8cb9e8b42c1f53ac300fafea7672bdff 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -30,6 +30,10 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 #define RA             t8
 
 /*
@@ -224,7 +228,7 @@ LEAF(dcache_enable)
        mfc0    t0, CP0_CONFIG
        ori     t0, CONF_CM_CMASK
        xori    t0, CONF_CM_CMASK
-       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       ori     t0, CONFIG_SYS_MIPS_CACHE_MODE
        mtc0    t0, CP0_CONFIG
        jr      ra
        END(dcache_enable)