]> git.sur5r.net Git - u-boot/commitdiff
Merge git://git.denx.de/u-boot-rockchip
authorTom Rini <trini@konsulko.com>
Tue, 9 Jan 2018 18:28:51 +0000 (13:28 -0500)
committerTom Rini <trini@konsulko.com>
Tue, 9 Jan 2018 18:28:51 +0000 (13:28 -0500)
arch/arm/mach-uniphier/dram_init.c
configs/uniphier_v8_defconfig
include/configs/uniphier.h

index e9672d2f1bc3211dd795479b07626f19d2e03e72..f67811425144627b19593003ba9b858df33c3eec 100644 (file)
@@ -205,6 +205,7 @@ int dram_init(void)
                return ret;
 
        for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
+               unsigned long max_size;
 
                if (!dram_map[i].size)
                        break;
@@ -218,9 +219,32 @@ int dram_init(void)
                                                        dram_map[i].base)
                        break;
 
+               /*
+                * Do not use memory that exceeds 32bit address range.  U-Boot
+                * relocates itself to the end of the effectively available RAM.
+                * This could be a problem for DMA engines that do not support
+                * 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
+                */
+               if (dram_map[i].base >= 1ULL << 32)
+                       break;
+
+               max_size = (1ULL << 32) - dram_map[i].base;
+
+               if (dram_map[i].size > max_size) {
+                       gd->ram_size += max_size;
+                       break;
+               }
+
                gd->ram_size += dram_map[i].size;
        }
 
+       /*
+        * LD20 uses the last 64 byte for each channel for dynamic
+        * DDR PHY training
+        */
+       if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
+               gd->ram_size -= 64;
+
        return 0;
 }
 
index bbcf3b09686ab27854fd202299132ab60519fc68..2edc3a953719956fb9ac1b466136fdc5a4c21fdf 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
 CONFIG_MMC_UNIPHIER=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_NAND=y
 CONFIG_NAND_DENALI_DT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
index 12cbe9b79dbb5d084f77bbe4ee149353fd63b1b5..5ab06f6072dd5d8bf21fb23ecd93e6d11db30499 100644 (file)
 
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 #define CONFIG_NR_DRAM_BANKS           3
-/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
-#define CONFIG_SYS_MEM_TOP_HIDE                64
 
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE)