/*
* Freescale Three Speed Ethernet Controller driver
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
{
- /* Access TBI PHY registers at given TSEC register offset as opposed
- * to the register offset used for external PHY accesses */
+ /*
+ * Access TBI PHY registers at given TSEC register offset as opposed
+ * to the register offset used for external PHY accesses
+ */
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_ANA, TBIANA_SETTINGS);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
/* Set the appropriate hash bit for the given addr */
-/* The algorithm works like so:
+/*
+ * The algorithm works like so:
* 1) Take the Destination Address (ie the multicast address), and
* do a CRC on it (little endian), and reverse the bits of the
* result.
* hash index which gaddr register to use, and the 5 other bits
* indicate which bit (assuming an IBM numbering scheme, which
* for PowerPC (tm) is usually the case) in the register holds
- * the entry. */
-static int
-tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+ * the entry.
+ */
+static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
}
#endif /* Multicast TFTP ? */
-/* Initialized required registers to appropriate values, zeroing
+/*
+ * Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
* choose a more appropriate value)
*/
}
-/* Configure maccfg2 based on negotiated speed and duplex
+/*
+ * Configure maccfg2 based on negotiated speed and duplex
* reported by PHY handling code
*/
static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
case 10:
maccfg2 |= MACCFG2_MII;
- /* Set R100 bit in all modes although
+ /*
+ * Set R100 bit in all modes although
* it is only used in RGMII mode
*/
if (phydev->speed == 100)
}
#endif
-/* Set up the buffers and their descriptors, and bring up the
+/*
+ * Set up the buffers and their descriptors, and bring up the
* interface
*/
static void startup_tsec(struct eth_device *dev)
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
}
-/* This returns the status bits of the device. The return value
+/*
+ * This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
- * do the same. Presumably, this would be zero if there were no
+ * do the same. Presumably, this would be zero if there were no
* errors
*/
static int tsec_send(struct eth_device *dev, void *packet, int length)
}
return -1;
-
}
/* Stop the interface */
phy_shutdown(priv->phydev);
}
-/* Initializes data structures and registers for the controller,
- * and brings the interface up. Returns the link status, meaning
+/*
+ * Initializes data structures and registers for the controller,
+ * and brings the interface up. Returns the link status, meaning
* that it returns success if the link is up, failure otherwise.
- * This allows u-boot to find the first active controller.
+ * This allows U-Boot to find the first active controller.
*/
static int tsec_init(struct eth_device *dev, bd_t * bd)
{
/* Init ECNTRL */
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
- /* Copy the station address into the address registers.
+ /*
+ * Copy the station address into the address registers.
* For a station address of 0x12345678ABCD in transmission
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
* MACnADDR2 is set to 0x34120000.
* be set by the platform code.
*/
if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
- (interface == PHY_INTERFACE_MODE_RGMII_RXID))
+ (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
+ (interface == PHY_INTERFACE_MODE_RGMII_RXID))
return interface;
return PHY_INTERFACE_MODE_RGMII;
return PHY_INTERFACE_MODE_MII;
}
-
-/* Discover which PHY is attached to the device, and configure it
+/*
+ * Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
*/
return 1;
}
-/* Initialize device structure. Returns success if PHY
+/*
+ * Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
dev->mcast = tsec_mcast_addr;
#endif
- /* Tell u-boot to get the addr from the env */
+ /* Tell U-Boot to get the addr from the env */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
*
* Driver for the Motorola Triple Speed Ethernet Controller
*
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TSEC_H
x.mii_devname = DEFAULT_MII_NAME;\
}
-#define MAC_ADDR_LEN 6
+#define MAC_ADDR_LEN 6
/* #define TSEC_TIMEOUT 1000000 */
-#define TSEC_TIMEOUT 1000
-#define TOUT_LOOP 1000000
+#define TSEC_TIMEOUT 1000
+#define TOUT_LOOP 1000000
/* TBI register addresses */
#define TBI_CR 0x00
/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT 0x0020
-#define TBIANA_ASYMMETRIC_PAUSE 0x0100
-#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
#define TBIANA_HALF_DUPLEX 0x0040
#define TBIANA_FULL_DUPLEX 0x0020
#define TBICR_PHY_RESET 0x8000
#define TBICR_FULL_DUPLEX 0x0100
#define TBICR_SPEED1_SET 0x0040
-
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MACCFG1_RESET_TX_MC 0x00040000
#define MACCFG1_RESET_RX_FUN 0x00020000
-#define MACCFG1_RESET_TX_FUN 0x00010000
+#define MACCFG1_RESET_TX_FUN 0x00010000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define ECNTRL_SGMII_MODE 0x00000002
#ifndef CONFIG_SYS_TBIPA_VALUE
- #define CONFIG_SYS_TBIPA_VALUE 0x1f
+# define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
#define TSTAT_CLEAR_THALT 0x80000000
#define RSTAT_CLEAR_RHALT 0x00800000
-
#define IEVENT_INIT_CLEAR 0xffffffff
#define IEVENT_BABR 0x80000000
#define IEVENT_RXC 0x40000000
#define IMASK_TXFEN 0x00100000
#define IMASK_RXFEN0 0x00000080
-
/* Default Attribute fields */
-#define ATTR_INIT_SETTINGS 0x000000c0
-#define ATTRELI_INIT_SETTINGS 0x00000000
-
+#define ATTR_INIT_SETTINGS 0x000000c0
+#define ATTRELI_INIT_SETTINGS 0x00000000
/* TxBD status field bits */
#define TXBD_READY 0x8000
#define TXBD_HUGEFRAME 0x0080
#define TXBD_LATECOLLISION 0x0080
#define TXBD_RETRYLIMIT 0x0040
-#define TXBD_RETRYCOUNTMASK 0x003c
+#define TXBD_RETRYCOUNTMASK 0x003c
#define TXBD_UNDERRUN 0x0002
#define TXBD_STATS 0x03ff
#define RXBD_STATS 0x003f
struct txbd8 {
- uint16_t status; /* Status Fields */
- uint16_t length; /* Buffer length */
- uint32_t bufptr; /* Buffer Pointer */
+ uint16_t status; /* Status Fields */
+ uint16_t length; /* Buffer length */
+ uint32_t bufptr; /* Buffer Pointer */
};
struct rxbd8 {
- uint16_t status; /* Status Fields */
- uint16_t length; /* Buffer Length */
- uint32_t bufptr; /* Buffer Pointer */
+ uint16_t status; /* Status Fields */
+ uint16_t length; /* Buffer Length */
+ uint32_t bufptr; /* Buffer Pointer */
};
struct tsec_rmon_mib {
u32 rbdlen; /* RxBD Data Length */
u32 res310[4];
u32 res320;
- u32 crbptr; /* Current Receive Buffer Pointer */
+ u32 crbptr; /* Current Receive Buffer Pointer */
u32 res328[6];
- u32 mrblr; /* Maximum Receive Buffer Length */
+ u32 mrblr; /* Maximum Receive Buffer Length */
u32 res344[16];
- u32 rbptr; /* RxBD Pointer */
+ u32 rbptr; /* RxBD Pointer */
u32 res388[30];
/* (0x2_n400) */
u32 res400;
- u32 rbase; /* RxBD Base Address */
+ u32 rbase; /* RxBD Base Address */
u32 res408[62];
/* MAC Registers (0x2_n500) */
u32 resc00[256];
};
-#define TSEC_GIGABIT (1 << 0)
+#define TSEC_GIGABIT (1 << 0)
/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
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