ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs

This is in preperation of using generic cross OMAP code.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
new file mode 100644 (file)
index 0000000..194b93b
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE                   0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE             0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE              0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE             0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE       0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE     0x48300000
+#define OMAP34XX_ID_L4_IO_BASE         0x4830A200
+#define OMAP34XX_L4_PER                        0x49000000
+#define OMAP34XX_L4_IO_BASE            OMAP34XX_CORE_L4_IO_BASE
+
+/* DMA4/SDMA */
+#define OMAP34XX_DMA4_BASE              0x48056000
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE             (OMAP34XX_L4_IO_BASE + 0x2000)
+
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+       unsigned char res[0x408];
+       unsigned int io2;               /* 0x408 */
+       unsigned char res2[0x38];
+       unsigned int io0;               /* 0x444 */
+       unsigned int io1;               /* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX            0x00000001
+
+/* UART */
+#define OMAP34XX_UART1                 (OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2                 (OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3                 (OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4                 (OMAP34XX_L4_PER + 0x42000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1                  0x48318000
+#define OMAP34XX_GPT2                  0x49032000
+#define OMAP34XX_GPT3                  0x49034000
+#define OMAP34XX_GPT4                  0x49036000
+#define OMAP34XX_GPT5                  0x49038000
+#define OMAP34XX_GPT6                  0x4903A000
+#define OMAP34XX_GPT7                  0x4903C000
+#define OMAP34XX_GPT8                  0x4903E000
+#define OMAP34XX_GPT9                  0x49040000
+#define OMAP34XX_GPT10                 0x48086000
+#define OMAP34XX_GPT11                 0x48088000
+#define OMAP34XX_GPT12                 0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE                       0x4830C000
+#define WD2_BASE                       0x48314000
+#define WD3_BASE                       0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE             0x48320000
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+       unsigned char res[0x10];
+       unsigned int s32k_cr;           /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+struct gpio {
+       unsigned char res1[0x34];
+       unsigned int oe;                /* 0x34 */
+       unsigned int datain;            /* 0x38 */
+       unsigned char res2[0x54];
+       unsigned int cleardataout;      /* 0x90 */
+       unsigned int setdataout;        /* 0x94 */
+};
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0                          (0x1 << 0)
+#define GPIO1                          (0x1 << 1)
+#define GPIO2                          (0x1 << 2)
+#define GPIO3                          (0x1 << 3)
+#define GPIO4                          (0x1 << 4)
+#define GPIO5                          (0x1 << 5)
+#define GPIO6                          (0x1 << 6)
+#define GPIO7                          (0x1 << 7)
+#define GPIO8                          (0x1 << 8)
+#define GPIO9                          (0x1 << 9)
+#define GPIO10                         (0x1 << 10)
+#define GPIO11                         (0x1 << 11)
+#define GPIO12                         (0x1 << 12)
+#define GPIO13                         (0x1 << 13)
+#define GPIO14                         (0x1 << 14)
+#define GPIO15                         (0x1 << 15)
+#define GPIO16                         (0x1 << 16)
+#define GPIO17                         (0x1 << 17)
+#define GPIO18                         (0x1 << 18)
+#define GPIO19                         (0x1 << 19)
+#define GPIO20                         (0x1 << 20)
+#define GPIO21                         (0x1 << 21)
+#define GPIO22                         (0x1 << 22)
+#define GPIO23                         (0x1 << 23)
+#define GPIO24                         (0x1 << 24)
+#define GPIO25                         (0x1 << 25)
+#define GPIO26                         (0x1 << 26)
+#define GPIO27                         (0x1 << 27)
+#define GPIO28                         (0x1 << 28)
+#define GPIO29                         (0x1 << 29)
+#define GPIO30                         (0x1 << 30)
+#define GPIO31                         (0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0                   0x40000000
+#define SRAM_OFFSET1                   0x00200000
+#define SRAM_OFFSET2                   0x0000F800
+#define SRAM_VECT_CODE                 (SRAM_OFFSET0 | SRAM_OFFSET1 | \
+                                        SRAM_OFFSET2)
+#define SRAM_CLK_CODE                  (SRAM_VECT_CODE + 64)
+
+#define NON_SECURE_SRAM_START          0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END            0x40210000
+
+#define LOW_LEVEL_SRAM_STACK           0x4020FFFC
+
+/* scratch area - accessible on both EMU and GP */
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
+
+#define DEBUG_LED1                     149     /* gpio */
+#define DEBUG_LED2                     150     /* gpio */
+
+#define XDR_POP                5       /* package on package part */
+#define SDR_DISCRETE   4       /* 128M memory SDR module */
+#define DDR_STACKED    3       /* stacked part on 2422 */
+#define DDR_COMBO      2       /* combo part on cpu daughter card */
+#define DDR_DISCRETE   1       /* 2x16 parts on daughter card */
+
+#define DDR_100                100     /* type found on most mem d-boards */
+#define DDR_111                111     /* some combo parts */
+#define DDR_133                133     /* most combo, some mem d-boards */
+#define DDR_165                165     /* future parts */
+
+#define CPU_3430       0x3430
+
+/*
+ * 343x real hardware:
+ *  ES1     = rev 0
+ *
+ *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ *
+ * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
+ */
+#define CPU_3XX_ES10           0
+#define CPU_3XX_ES20           1
+#define CPU_3XX_ES21           2
+#define CPU_3XX_ES30           3
+#define CPU_3XX_ES31           4
+#define CPU_3XX_ES312          7
+#define CPU_3XX_MAX_REV                8
+
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10          0
+#define CPU_37XX_ES11          1
+#define CPU_37XX_ES12          2
+#define CPU_37XX_MAX_REV       3
+
+#define CPU_3XX_ID_SHIFT       28
+
+#define WIDTH_8BIT             0x0000
+#define WIDTH_16BIT            0x1000  /* bit pos for 16 bit in gpmc */
+
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX       0xb7ae
+#define HAWKEYE_AM35XX         0xb868
+#define HAWKEYE_OMAP36XX       0xb891
+
+#define HAWKEYE_SHIFT          12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX           0x3400  /* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX             0x3500  /* AM35xx devices          */
+#define CPU_OMAP36XX           0x3600  /* OMAP36xx devices        */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503               0x5c00
+#define OMAP3515               0x1c00
+#define OMAP3525               0x4c00
+#define OMAP3530               0x0c00
+
+#define AM3505                 0x5c00
+#define AM3517                 0x1c00
+
+#define OMAP3730               0x0c00
+
+/*
+ * ROM code API related flags
+ */
+#define OMAP3_GP_ROMCODE_API_L2_INVAL          1
+#define OMAP3_GP_ROMCODE_API_WRITE_ACR         3
+
+/*
+ * EMU device PPA HAL related flags
+ */
+#define OMAP3_EMU_HAL_API_L2_INVAL             40
+#define OMAP3_EMU_HAL_API_WRITE_ACR            42
+
+#define OMAP3_EMU_HAL_START_HAL_CRITICAL       4
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME         30
+#define OMAP_ABB_CLOCK_CYCLES          8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK       (0x1 << 26)
+
+#endif

diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
deleted file mode 100644 (file)
index 194b93b..0000000
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef _OMAP3_H_
-#define _OMAP3_H_
-
-/* Stuff on L3 Interconnect */
-#define SMX_APE_BASE                   0x68000000
-
-/* GPMC */
-#define OMAP34XX_GPMC_BASE             0x6E000000
-
-/* SMS */
-#define OMAP34XX_SMS_BASE              0x6C000000
-
-/* SDRC */
-#define OMAP34XX_SDRC_BASE             0x6D000000
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP34XX_CORE_L4_IO_BASE       0x48000000
-#define OMAP34XX_WAKEUP_L4_IO_BASE     0x48300000
-#define OMAP34XX_ID_L4_IO_BASE         0x4830A200
-#define OMAP34XX_L4_PER                        0x49000000
-#define OMAP34XX_L4_IO_BASE            OMAP34XX_CORE_L4_IO_BASE
-
-/* DMA4/SDMA */
-#define OMAP34XX_DMA4_BASE              0x48056000
-
-/* CONTROL */
-#define OMAP34XX_CTRL_BASE             (OMAP34XX_L4_IO_BASE + 0x2000)
-
-#ifndef __ASSEMBLY__
-/* Signal Integrity Parameter Control Registers */
-struct control_prog_io {
-       unsigned char res[0x408];
-       unsigned int io2;               /* 0x408 */
-       unsigned char res2[0x38];
-       unsigned int io0;               /* 0x444 */
-       unsigned int io1;               /* 0x448 */
-};
-#endif /* __ASSEMBLY__ */
-
-/* Bit definition for CONTROL_PROG_IO1 */
-#define PRG_I2C2_PULLUPRESX            0x00000001
-
-/* UART */
-#define OMAP34XX_UART1                 (OMAP34XX_L4_IO_BASE + 0x6a000)
-#define OMAP34XX_UART2                 (OMAP34XX_L4_IO_BASE + 0x6c000)
-#define OMAP34XX_UART3                 (OMAP34XX_L4_PER + 0x20000)
-#define OMAP34XX_UART4                 (OMAP34XX_L4_PER + 0x42000)
-
-/* General Purpose Timers */
-#define OMAP34XX_GPT1                  0x48318000
-#define OMAP34XX_GPT2                  0x49032000
-#define OMAP34XX_GPT3                  0x49034000
-#define OMAP34XX_GPT4                  0x49036000
-#define OMAP34XX_GPT5                  0x49038000
-#define OMAP34XX_GPT6                  0x4903A000
-#define OMAP34XX_GPT7                  0x4903C000
-#define OMAP34XX_GPT8                  0x4903E000
-#define OMAP34XX_GPT9                  0x49040000
-#define OMAP34XX_GPT10                 0x48086000
-#define OMAP34XX_GPT11                 0x48088000
-#define OMAP34XX_GPT12                 0x48304000
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE                       0x4830C000
-#define WD2_BASE                       0x48314000
-#define WD3_BASE                       0x49030000
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE             0x48320000
-
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
-       unsigned char res[0x10];
-       unsigned int s32k_cr;           /* 0x10 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-struct gpio {
-       unsigned char res1[0x34];
-       unsigned int oe;                /* 0x34 */
-       unsigned int datain;            /* 0x38 */
-       unsigned char res2[0x54];
-       unsigned int cleardataout;      /* 0x90 */
-       unsigned int setdataout;        /* 0x94 */
-};
-#endif /* __ASSEMBLY__ */
-
-#define GPIO0                          (0x1 << 0)
-#define GPIO1                          (0x1 << 1)
-#define GPIO2                          (0x1 << 2)
-#define GPIO3                          (0x1 << 3)
-#define GPIO4                          (0x1 << 4)
-#define GPIO5                          (0x1 << 5)
-#define GPIO6                          (0x1 << 6)
-#define GPIO7                          (0x1 << 7)
-#define GPIO8                          (0x1 << 8)
-#define GPIO9                          (0x1 << 9)
-#define GPIO10                         (0x1 << 10)
-#define GPIO11                         (0x1 << 11)
-#define GPIO12                         (0x1 << 12)
-#define GPIO13                         (0x1 << 13)
-#define GPIO14                         (0x1 << 14)
-#define GPIO15                         (0x1 << 15)
-#define GPIO16                         (0x1 << 16)
-#define GPIO17                         (0x1 << 17)
-#define GPIO18                         (0x1 << 18)
-#define GPIO19                         (0x1 << 19)
-#define GPIO20                         (0x1 << 20)
-#define GPIO21                         (0x1 << 21)
-#define GPIO22                         (0x1 << 22)
-#define GPIO23                         (0x1 << 23)
-#define GPIO24                         (0x1 << 24)
-#define GPIO25                         (0x1 << 25)
-#define GPIO26                         (0x1 << 26)
-#define GPIO27                         (0x1 << 27)
-#define GPIO28                         (0x1 << 28)
-#define GPIO29                         (0x1 << 29)
-#define GPIO30                         (0x1 << 30)
-#define GPIO31                         (0x1 << 31)
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0                   0x40000000
-#define SRAM_OFFSET1                   0x00200000
-#define SRAM_OFFSET2                   0x0000F800
-#define SRAM_VECT_CODE                 (SRAM_OFFSET0 | SRAM_OFFSET1 | \
-                                        SRAM_OFFSET2)
-#define SRAM_CLK_CODE                  (SRAM_VECT_CODE + 64)
-
-#define NON_SECURE_SRAM_START          0x40208000 /* Works for GP & EMU */
-#define NON_SECURE_SRAM_END            0x40210000
-
-#define LOW_LEVEL_SRAM_STACK           0x4020FFFC
-
-/* scratch area - accessible on both EMU and GP */
-#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
-
-#define DEBUG_LED1                     149     /* gpio */
-#define DEBUG_LED2                     150     /* gpio */
-
-#define XDR_POP                5       /* package on package part */
-#define SDR_DISCRETE   4       /* 128M memory SDR module */
-#define DDR_STACKED    3       /* stacked part on 2422 */
-#define DDR_COMBO      2       /* combo part on cpu daughter card */
-#define DDR_DISCRETE   1       /* 2x16 parts on daughter card */
-
-#define DDR_100                100     /* type found on most mem d-boards */
-#define DDR_111                111     /* some combo parts */
-#define DDR_133                133     /* most combo, some mem d-boards */
-#define DDR_165                165     /* future parts */
-
-#define CPU_3430       0x3430
-
-/*
- * 343x real hardware:
- *  ES1     = rev 0
- *
- *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
- *
- * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
- */
-#define CPU_3XX_ES10           0
-#define CPU_3XX_ES20           1
-#define CPU_3XX_ES21           2
-#define CPU_3XX_ES30           3
-#define CPU_3XX_ES31           4
-#define CPU_3XX_ES312          7
-#define CPU_3XX_MAX_REV                8
-
-/*
- * 37xx real hardware:
- * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
- */
-
-#define CPU_37XX_ES10          0
-#define CPU_37XX_ES11          1
-#define CPU_37XX_ES12          2
-#define CPU_37XX_MAX_REV       3
-
-#define CPU_3XX_ID_SHIFT       28
-
-#define WIDTH_8BIT             0x0000
-#define WIDTH_16BIT            0x1000  /* bit pos for 16 bit in gpmc */
-
-/*
- * Hawkeye values
- */
-#define HAWKEYE_OMAP34XX       0xb7ae
-#define HAWKEYE_AM35XX         0xb868
-#define HAWKEYE_OMAP36XX       0xb891
-
-#define HAWKEYE_SHIFT          12
-
-/*
- * Define CPU families
- */
-#define CPU_OMAP34XX           0x3400  /* OMAP34xx/OMAP35 devices */
-#define CPU_AM35XX             0x3500  /* AM35xx devices          */
-#define CPU_OMAP36XX           0x3600  /* OMAP36xx devices        */
-
-/*
- * Control status register values corresponding to cpu variants
- */
-#define OMAP3503               0x5c00
-#define OMAP3515               0x1c00
-#define OMAP3525               0x4c00
-#define OMAP3530               0x0c00
-
-#define AM3505                 0x5c00
-#define AM3517                 0x1c00
-
-#define OMAP3730               0x0c00
-
-/*
- * ROM code API related flags
- */
-#define OMAP3_GP_ROMCODE_API_L2_INVAL          1
-#define OMAP3_GP_ROMCODE_API_WRITE_ACR         3
-
-/*
- * EMU device PPA HAL related flags
- */
-#define OMAP3_EMU_HAL_API_L2_INVAL             40
-#define OMAP3_EMU_HAL_API_WRITE_ACR            42
-
-#define OMAP3_EMU_HAL_START_HAL_CRITICAL       4
-
-/* ABB settings */
-#define OMAP_ABB_SETTLING_TIME         30
-#define OMAP_ABB_CLOCK_CYCLES          8
-
-/* ABB tranxdone mask */
-#define OMAP_ABB_MPU_TXDONE_MASK       (0x1 << 26)
-
-#endif

diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 290a6a3e0640399cce117d6b404ab2b29d66f0bb..87c850e05df19c30e7d361751a50a68274adcdfc 100644 (file)
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 3de50799621ebf82ab2da404a55fb2385cf1a3ee..c4e19e79b95afa6e2866daf9b3d51055e5f3410e 100644 (file)
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 9feca1b47b381f6a40ba295c80a4102f2fc6127e..e2d5bbb0955d266b952bc05d5e4075c0a2e05149 100644 (file)
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -30,7 +30,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 918032bd753a81eefd94b5e4d91576a9cefe456c..ee1b7a0cb5a763fe32f3a05be5238463c21a3af5 100644 (file)
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -30,7 +30,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index c8739ed29490e58864b34f6bba55ca8691c5837d..8791199fc61da333ca0cb77643525881077b5dc2 100644 (file)
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -36,7 +36,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 26eb2203540f350b608e392817dc115f8844af28..2cf66c40d6fee15cf0727fae4217bd0685467302 100644 (file)
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -26,7 +26,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_FIT

diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 46fc91e5e197bb4428c8b75c619c84ac2e3e3a9d..442e16ae686b45615ed45e984ec69619989b0a6d 100644 (file)
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -42,7 +42,7 @@
 #define CONFIG_SDRC                    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/mem.h>
 #include <linux/stringify.h>
 

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 8bdc08f5864c7f6bf27afaeabec0bbba6c4fa820..4e587e10ffd3015dc3582ab6b1301aceb7e51e34 100644 (file)
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -18,7 +18,7 @@
 #define __OMAP3EVM_CONFIG_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands

diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index 1185f425501f8b5e6b39b03341be104df1345fde..a7acc1becbeb42584533cf595e7cf420dc9d2140 100644 (file)
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_MMC_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands

diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index 4427e88b7e4b32b135968a98799ad8ef7a888172..c6cad9388961684e44f15cdfca892a5c100bf782 100644 (file)
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_NAND_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index aeb385f5ff6b4d289c085a2f33897b3eded01ece..fcef46735835a44a3f8cd08881770396454a6fa4 100644 (file)
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -24,7 +24,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>      /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index bf1d34dedb4dd475db9d04431dc627330e12400a..20ec3ad15439f2564096c628d0c01f922a7f5635 100644 (file)
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 45feeb577320a847ac6abed9bf5c1ae83f09c03d..b92d67abccf904b0e910ab09098b4cc8a4496d42 100644 (file)
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -21,7 +21,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>      /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index ac307eb45629bafc3c99fdcc0cdcd8eab95a12ca..bf5c7a8faf779b611a30328b0f9d515d9fc41c6b 100644 (file)
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * NOTE:  these #defines presume standard SDP jumper settings.

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index c5d742c2bd801c35349a56856be2e51c4c8eba9c..611cd5e1a35028062fba3dbd74fd57369e560ff1 100644 (file)
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -22,7 +22,7 @@
 #define CONFIG_NAND
 #define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <configs/ti_omap3_common.h>
 
 /* Remove SPL boot option - we do not support that on LDP yet */

diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 38288f69aaa5584dd97949522247138ae1cfdfc8..dea4044d9fbb5b5ab19032e4d94748427d19edbe 100644 (file)
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -25,7 +25,7 @@
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index dd69d4ebabfe11ed83174fcf551dddc8c4650d05..f3e0088d5a00b6abe724a5d89be42214c57d4821 100644 (file)
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC                    /* Has an SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information

diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 840e108e053674088189b9ed9eda0e81d3d68b9b..4b4f104105433b202b4e06ec50818fee32a1b5a1 100644 (file)
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -16,7 +16,7 @@
 
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_OMAP_SERIAL

diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 10ac4a46bc4a38a7d13577ddbdba34f06aa81e7f..b105ffd9f18b13e7564f4320d4140c95a3665df7 100644 (file)
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -32,7 +32,7 @@
 #define CONFIG_SDRC                    /* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_SYS_GENERIC_BOARD