]> git.sur5r.net Git - u-boot/commitdiff
mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance
authorJoe Hershberger <joe.hershberger@ni.com>
Wed, 12 Oct 2011 04:57:13 +0000 (23:57 -0500)
committerKim Phillips <kim.phillips@freescale.com>
Thu, 3 Nov 2011 23:27:53 +0000 (18:27 -0500)
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
include/configs/MPC832XEMDS.h

index 823b9f127ee96cbc9181e227bc25a811e94d3d4a..2a86262c442712a7c6ce81413eb8a472e1a5d379 100644 (file)
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDRCDR              0x73000002      /* DDR II voltage is 1.8V */
+#define CONFIG_SYS_DDRCDR      0x73000002      /* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)
  */
 #define CONFIG_SYS_DDR_SIZE            128     /* MB */
 #define CONFIG_SYS_DDR_CS0_CONFIG      0x80840102
-#define CONFIG_SYS_DDR_TIMING_0        0x00220802
-#define CONFIG_SYS_DDR_TIMING_1        0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2        0x0f9048ca
-#define CONFIG_SYS_DDR_TIMING_3        0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL        0x02000000
+#define CONFIG_SYS_DDR_TIMING_0                0x00220802
+#define CONFIG_SYS_DDR_TIMING_1                0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2                0x0f9048ca
+#define CONFIG_SYS_DDR_TIMING_3                0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL                0x02000000
 #define CONFIG_SYS_DDR_MODE            0x44400232
 #define CONFIG_SYS_DDR_MODE2           0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL        0x03200064
-#define CONFIG_SYS_DDR_CS0_BNDS        0x00000007
+#define CONFIG_SYS_DDR_INTERVAL                0x03200064
+#define CONFIG_SYS_DDR_CS0_BNDS                0x00000007
 #define CONFIG_SYS_DDR_SDRAM_CFG       0x43080000
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #endif
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024)    /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN  (128 * 1024)    /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK       1
-#define CONFIG_SYS_INIT_RAM_ADDR       0xE6000000      /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x1000          /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR       0xE6000000      /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET     \
+                       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * Local Bus Configuration & Clock Setup
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI           /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER        /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE          0xFE000000      /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE          16      /* FLASH size is 16M */
-#define CONFIG_SYS_FLASH_PROTECTION    1               /* Use h/w Flash protection. */
+#define CONFIG_FLASH_CFI_DRIVER                /* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE  0xFE000000      /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE  16      /* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION    1       /* Use h/w Flash protection. */
 
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE   /* Window base at flash base */
+                                       /* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000018      /* 32MB window size */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE |        /* Flash Base address */ \
-                       (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
-                       BR_V)                   /* valid */
-#define CONFIG_SYS_OR0_PRELIM          0xfe006ff7      /* 16MB Flash size */
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
+                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR0_PRELIM  0xfe006ff7              /* 16MB Flash size */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      128             /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      128     /* sectors per device */
 
 #undef CONFIG_SYS_FLASH_CHECKSUM
 
 /*
  * BCSR on the Local Bus
  */
-#define CONFIG_SYS_BCSR                0xF8000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_BCSR /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E      /* Access window size 32K */
+#define CONFIG_SYS_BCSR                        0xF8000000
+                                       /* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_BCSR
+                                       /* Access window size 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E
 
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR|0x00000801)    /* Port size=8bit, MSEL=GPCM */
+                                       /* Port size=8bit, MSEL=GPCM */
+#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR|0x00000801)
 #define CONFIG_SYS_OR1_PRELIM          0xFFFFE9f7      /* length 32K */
 
 /*
  * SDRAM on the Local Bus
  */
-#undef CONFIG_SYS_LB_SDRAM             /* The board has not SRDAM on local bus */
+#undef CONFIG_SYS_LB_SDRAM     /* The board has not SRDAM on local bus */
 
 #ifdef CONFIG_SYS_LB_SDRAM
 #define CONFIG_SYS_LBC_SDRAM_BASE      0xF0000000      /* SDRAM base address */
 
 #define CONFIG_SYS_OR2_PRELIM  0xfc006901
 
-#define CONFIG_SYS_LBC_LSRT    0x32000000      /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR   0x20000000      /* LB refresh timer prescal, 266MHz/32 */
+                               /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT    0x32000000
+                               /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR   0x20000000
 
 #define CONFIG_SYS_LBC_LSDMR_COMMON    0x0063b723
 
 /*
  * Windows to access PIB via local bus
  */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM    0xf8008000      /* windows base 0xf8008000 */
-#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000f      /* windows size 64KB */
+                                       /* windows base 0xf8008000 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM    0xf8008000
+                                       /* windows size 64KB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000f
 
 /*
  * CS2 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR2_PRELIM  0xf8008801      /* CS2 base address at 0xf8008000 */
-#define CONFIG_SYS_OR2_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
+                               /* CS2 base address at 0xf8008000 */
+#define CONFIG_SYS_BR2_PRELIM  0xf8008801
+                               /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR2_PRELIM  0xffffe9f7
 
 /*
  * CS3 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR3_PRELIM  0xf8010801      /* CS3 base address at 0xf8010000 */
-#define CONFIG_SYS_OR3_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
+                               /* CS3 base address at 0xf8010000 */
+#define CONFIG_SYS_BR3_PRELIM  0xf8010801
+                               /* size 32KB, port size 8bit, GPCM */
+#define CONFIG_SYS_OR3_PRELIM  0xffffe9f7
 
 /*
  * Serial Port
 #define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
 
 #define CONFIG_SYS_BAUDRATE_TABLE  \
-       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+               {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
  */
 #ifndef CONFIG_SYS_RAMBOOT
        #define CONFIG_ENV_IS_IN_FLASH  1
-       #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+       #define CONFIG_ENV_ADDR         \
+                       (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
        #define CONFIG_ENV_SECT_SIZE    0x20000
        #define CONFIG_ENV_SIZE         0x2000
 #else
-       #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
+       #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
        #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
        #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
        #define CONFIG_ENV_SIZE         0x2000
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP            /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR           0x2000000       /* default load address */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP    /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "   /* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
        #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
        #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 #endif
 
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)     /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
+                               /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+                               /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ          1000    /* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ           (256 << 20)     /* Initial Memory map for Linux */
+                                       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ           (256 << 20)
 
 /*
  * Core HID Setup
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
 
 /* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 
 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR | BATL_PP_10 | \
-                       BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR \
+                               | BATU_BL_4M \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT1L      CONFIG_SYS_IBAT1L
 #define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
 
 /* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_BCSR | BATL_PP_10 | \
-                       BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_BCSR \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_BCSR \
+                               | BATU_BL_128K \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U      (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
-                       BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_FLASH_BASE \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U      (CONFIG_SYS_FLASH_BASE \
+                               | BATU_BL_32M \
+                               | BATU_VS \
+                               | BATU_VP)
+#define CONFIG_SYS_DBAT3L      (CONFIG_SYS_FLASH_BASE \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 
 #define CONFIG_SYS_IBAT4L      (0)
 
 /* Stack in dcache: cacheable, no memory coherence */
 #define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_INIT_RAM_ADDR \
+                               | BATU_BL_128K \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI1_MEM_PHYS \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI1_MEM_PHYS \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
-                       BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI1_MMIO_PHYS \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI1_MMIO_PHYS \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 #define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
 #else
 #undef  CONFIG_BOOTARGS                /* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS                                      \
-   "netdev=eth0\0"                                                     \
-   "consoledev=ttyS0\0"                                                        \
-   "ramdiskaddr=1000000\0"                                             \
-   "ramdiskfile=ramfs.83xx\0"                                          \
-   "fdtaddr=780000\0"                                                  \
-   "fdtfile=mpc832x_mds.dtb\0"                                         \
-   ""
+       "netdev=eth0\0"                                                 \
+       "consoledev=ttyS0\0"                                            \
+       "ramdiskaddr=1000000\0"                                         \
+       "ramdiskfile=ramfs.83xx\0"                                      \
+       "fdtaddr=780000\0"                                              \
+       "fdtfile=mpc832x_mds.dtb\0"                                     \
+       ""
 
 #define CONFIG_NFSBOOTCOMMAND                                          \
-   "setenv bootargs root=/dev/nfs rw "                                 \
-      "nfsroot=$serverip:$rootpath "                                   \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "        \
-      "console=$consoledev,$baudrate $othbootargs;"                    \
-   "tftp $loadaddr $bootfile;"                                         \
-   "tftp $fdtaddr $fdtfile;"                                           \
-   "bootm $loadaddr - $fdtaddr"
+       "setenv bootargs root=/dev/nfs rw "                             \
+               "nfsroot=$serverip:$rootpath "                          \
+               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
+                                                       "$netdev:off "  \
+               "console=$consoledev,$baudrate $othbootargs;"           \
+       "tftp $loadaddr $bootfile;"                                     \
+       "tftp $fdtaddr $fdtfile;"                                       \
+       "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND                                          \
-   "setenv bootargs root=/dev/ram rw "                                 \
-      "console=$consoledev,$baudrate $othbootargs;"                    \
-   "tftp $ramdiskaddr $ramdiskfile;"                                   \
-   "tftp $loadaddr $bootfile;"                                         \
-   "tftp $fdtaddr $fdtfile;"                                           \
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+       "setenv bootargs root=/dev/ram rw "                             \
+               "console=$consoledev,$baudrate $othbootargs;"           \
+       "tftp $ramdiskaddr $ramdiskfile;"                               \
+       "tftp $loadaddr $bootfile;"                                     \
+       "tftp $fdtaddr $fdtfile;"                                       \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 
 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND