dma: Add i.MX6 support to drivers/dma/apbh_dma.c

This will be used by the i.MX6 NAND support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 09be97461dcecea19da184cd7c6088ecaa392467..0e4d8fa73d69c5606921ec7d86b422038dfc0cd6 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -45,6 +45,11 @@
 #define DTCP_ARB_BASE_ADDR              0x00138000
 #define DTCP_ARB_END_ADDR               0x0013BFFF
 #endif /* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE                  APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE                  (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
 /* GPV - PL301 configuration ports */
 #ifdef CONFIG_MX6SL
 #define GPV2_BASE_ADDR                  0x00D00000

diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 1ac8696e64e5903423b38c4b5cdaa00e3e7cbfbd..cb74528970dcb78dcec36cb300551dcbbb8b4aa0 100644 (file)
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -72,6 +72,18 @@ enum {
        MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
        MXS_MAX_DMA_CHANNELS,
 };
+#elif defined(CONFIG_MX6)
+enum {
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+       MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+       MXS_MAX_DMA_CHANNELS,
+};
 #endif
 
 /*

diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
index a5de9276ebd3496534dc9f94181e2ce96351bcb7..bcec6e0b95aaeb92bda39bf1b55eb38615b118e9 100644 (file)
--- a/arch/arm/include/asm/imx-common/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -109,7 +109,7 @@ struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_version)
 };
 
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0)
        mxs_reg_32(hw_apbh_ctrl1)
@@ -288,6 +288,17 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 #define        APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
+#elif defined(CONFIG_MX6)
+#define        APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x0004
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x0008
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND4                0x0010
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND5                0x0020
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND6                0x0040
+#define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0080
+#define        APBH_CTRL0_CLKGATE_CHANNEL_SSP                  0x0100
 #endif
 
 #define        APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN                 (1 << 31)
@@ -393,6 +404,10 @@ struct mxs_apbh_regs {
 #define        APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 #endif
 
+#if defined(CONFIG_MX6)
+#define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
+#endif
+
 #if defined(CONFIG_MX23)
 #define        APBH_DEVSEL_CH7_MASK                            (0xf << 28)
 #define        APBH_DEVSEL_CH7_OFFSET                          28

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index eb46bcfcbfa4aee2c8ec839332154ed9a1626ba5..510cb28ad5cdb7eb747ea6a3343a784bdffa97f3 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -227,7 +227,7 @@ static int mxs_dma_reset(int channel)
 #if defined(CONFIG_MX23)
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
        uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
        uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif