]> git.sur5r.net Git - u-boot/commitdiff
ARM: tegra: add/edit headers for Tegra124
authorTom Warren <twarren.nvidia@gmail.com>
Fri, 24 Jan 2014 19:46:13 +0000 (12:46 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 3 Feb 2014 16:46:46 +0000 (09:46 -0700)
These headers define the Tegra124 hardware. Add them to the usual
place.

Add Tegra124 chip ID/SKU ID definitions to common headers.

There's no real HW change on Tegra124 for 90% of the toys, so it might
make sense for a future patch to unify some of the content of these
files in a common location.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
18 files changed:
arch/arm/include/asm/arch-tegra/clk_rst.h
arch/arm/include/asm/arch-tegra/gp_padctrl.h
arch/arm/include/asm/arch-tegra/pmc.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/arch-tegra124/ahb.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/clock-tables.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/flow.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/funcmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/gp_padctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/pinmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/pmu.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/sysctr.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/tegra.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/usb.h [new file with mode: 0644]

index cc608258b4e80f4253cf16fa1fbc0242f8c7f45f..7d28e16f1c5b8710d82977974cc51476685d522d 100644 (file)
@@ -11,7 +11,8 @@
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
        uint pll_base;          /* the control register */
-       uint pll_out[2];        /* output control */
+       /* pll_out[0] is output A control, pll_out[1] is output B control */
+       uint pll_out[2];
        uint pll_misc;          /* other misc things */
 };
 
@@ -21,6 +22,13 @@ struct clk_pll_simple {
        uint pll_misc;          /* other misc things */
 };
 
+struct clk_pllm {
+       uint pllm_base;         /* the control register */
+       uint pllm_out;          /* output control */
+       uint pllm_misc1;        /* misc1 */
+       uint pllm_misc2;        /* misc2 */
+};
+
 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
 struct clk_set_clr {
        uint set;
@@ -38,7 +46,8 @@ enum {
        TEGRA_CLK_REGS          = 3,    /* Number of clock enable regs L/H/U */
        TEGRA_CLK_SOURCES       = 64,   /* Number of ppl clock sources L/H/U */
        TEGRA_CLK_REGS_VW       = 2,    /* Number of clock enable regs V/W */
-       TEGRA_CLK_SOURCES_VW    = 32,   /* Number of ppl clock sources V/W*/
+       TEGRA_CLK_SOURCES_VW    = 32,   /* Number of ppl clock sources V/W */
+       TEGRA_CLK_SOURCES_X     = 32,   /* Number of ppl clock sources X */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -47,7 +56,7 @@ struct clk_rst_ctlr {
        uint crc_rst_dev[TEGRA_CLK_REGS];       /* _RST_DEVICES_L/H/U_0 */
        uint crc_clk_out_enb[TEGRA_CLK_REGS];   /* _CLK_OUT_ENB_L/H/U_0 */
        uint crc_reserved0;             /* reserved_0,          0x1C */
-       uint crc_cclk_brst_pol;         /* _CCLK_BURST_POLICY_0,0x20 */
+       uint crc_cclk_brst_pol;         /* _CCLK_BURST_POLICY_0, 0x20 */
        uint crc_super_cclk_div;        /* _SUPER_CCLK_DIVIDER_0,0x24 */
        uint crc_sclk_brst_pol;         /* _SCLK_BURST_POLICY_0, 0x28 */
        uint crc_super_sclk_div;        /* _SUPER_SCLK_DIVIDER_0,0x2C */
@@ -75,7 +84,21 @@ struct clk_rst_ctlr {
 
        uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...       0x100-1fc */
 
-       uint crc_reserved20[64];        /* _reserved_20,        0x200-2fc */
+       uint crc_reserved20[32];        /* _reserved_20,        0x200-27c */
+
+       uint crc_clk_out_enb_x;         /* _CLK_OUT_ENB_X_0,    0x280 */
+       uint crc_clk_enb_x_set;         /* _CLK_ENB_X_SET_0,    0x284 */
+       uint crc_clk_enb_x_clr;         /* _CLK_ENB_X_CLR_0,    0x288 */
+
+       uint crc_rst_devices_x;         /* _RST_DEVICES_X_0,    0x28c */
+       uint crc_rst_dev_x_set;         /* _RST_DEV_X_SET_0,    0x290 */
+       uint crc_rst_dev_x_clr;         /* _RST_DEV_X_CLR_0,    0x294 */
+
+       uint crc_reserved21[23];        /* _reserved_21,        0x298-2f0 */
+
+       uint crc_dfll_base;             /* _DFLL_BASE_0,        0x2f4 */
+
+       uint crc_reserved22[2];         /* _reserved_22,        0x2f8-2fc */
 
        /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
        struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
@@ -105,10 +128,10 @@ struct clk_rst_ctlr {
        uint crc_clk_cpug_cmplx;        /* _CLK_CPUG_CMPLX_0,       0x378 */
        uint crc_clk_cpulp_cmplx;       /* _CLK_CPULP_CMPLX_0,      0x37C */
        uint crc_cpu_softrst_ctrl;      /* _CPU_SOFTRST_CTRL_0,     0x380 */
-       uint crc_cpu_softrst_ctrl1;     /* _CPU_SOFTRST_CTR1L_0,    0x384 */
+       uint crc_cpu_softrst_ctrl1;     /* _CPU_SOFTRST_CTRL1_0,    0x384 */
        uint crc_cpu_softrst_ctrl2;     /* _CPU_SOFTRST_CTRL2_0,    0x388 */
        uint crc_reserved33[9];         /* _reserved_33,        0x38c-3ac */
-       uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+       uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];      /* 0x3B0-0x42C */
        /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
        struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
        /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
@@ -142,6 +165,47 @@ struct clk_rst_ctlr {
        uint crc_audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
        uint crc_audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
        uint crc_audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+       uint crc_plld2_base;            /* _PLLD2_BASE_0, 0x4B8 */
+       uint crc_plld2_misc;            /* _PLLD2_MISC_0, 0x4BC */
+       uint crc_utmip_pll_cfg3;        /* _UTMIP_PLL_CFG3_0, 0x4C0 */
+       uint crc_pllrefe_base;          /* _PLLREFE_BASE_0, 0x4C4 */
+       uint crc_pllrefe_misc;          /* _PLLREFE_MISC_0, 0x4C8 */
+       uint crs_reserved_50[7];        /* _reserved_50, 0x4CC-0x4E4 */
+       uint crc_pllc2_base;            /* _PLLC2_BASE_0, 0x4E8 */
+       uint crc_pllc2_misc0;           /* _PLLC2_MISC_0_0, 0x4EC */
+       uint crc_pllc2_misc1;           /* _PLLC2_MISC_1_0, 0x4F0 */
+       uint crc_pllc2_misc2;           /* _PLLC2_MISC_2_0, 0x4F4 */
+       uint crc_pllc2_misc3;           /* _PLLC2_MISC_3_0, 0x4F8 */
+       uint crc_pllc3_base;            /* _PLLC3_BASE_0, 0x4FC */
+       uint crc_pllc3_misc0;           /* _PLLC3_MISC_0_0, 0x500 */
+       uint crc_pllc3_misc1;           /* _PLLC3_MISC_1_0, 0x504 */
+       uint crc_pllc3_misc2;           /* _PLLC3_MISC_2_0, 0x508 */
+       uint crc_pllc3_misc3;           /* _PLLC3_MISC_3_0, 0x50C */
+       uint crc_pllx_misc1;            /* _PLLX_MISC_1_0, 0x510 */
+       uint crc_pllx_misc2;            /* _PLLX_MISC_2_0, 0x514 */
+       uint crc_pllx_misc3;            /* _PLLX_MISC_3_0, 0x518 */
+       uint crc_xusbio_pll_cfg0;       /* _XUSBIO_PLL_CFG0_0, 0x51C */
+       uint crc_xusbio_pll_cfg1;       /* _XUSBIO_PLL_CFG0_1, 0x520 */
+       uint crc_plle_aux1;             /* _PLLE_AUX1_0, 0x524 */
+       uint crc_pllp_reshift;          /* _PLLP_RESHIFT_0, 0x528 */
+       uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+       uint crc_pllu_hw_pwrdn_cfg0;    /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+       uint crc_xusb_pll_cfg0;         /* _XUSB_PLL_CFG0_0, 0x534 */
+       uint crc_reserved51[1];         /* _reserved_51, 0x538 */
+       uint crc_clk_cpu_misc;          /* _CLK_CPU_MISC_0, 0x53C */
+       uint crc_clk_cpug_misc;         /* _CLK_CPUG_MISC_0, 0x540 */
+       uint crc_clk_cpulp_misc;        /* _CLK_CPULP_MISC_0, 0x544 */
+       uint crc_pllx_hw_ctrl_cfg;      /* _PLLX_HW_CTRL_CFG_0, 0x548 */
+       uint crc_pllx_sw_ramp_cfg;      /* _PLLX_SW_RAMP_CFG_0, 0x54C */
+       uint crc_pllx_hw_ctrl_status;   /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+       uint crc_reserved52[1];         /* _reserved_52, 0x554 */
+       uint crc_super_gr3d_clk_div;    /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+       uint crc_spare_reg0;            /* _SPARE_REG0_0, 0x55C */
+
+       /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+       uint crc_reserved60[40];        /* _reserved_60, 0x560 - 0x5FC */
+       uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -236,9 +300,15 @@ enum {
 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN                (1 << 2)
 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN                (1 << 0)
 
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_XOBP_SHIFT         1
-#define OSC_XOBP_MASK          (1U << OSC_XOBP_SHIFT)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT                  0
+#define OSC_XOE_MASK                   (1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE                 (1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT                 1
+#define OSC_XOBP_MASK                  (1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT                 4
+#define OSC_XOFS_MASK                  (0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH             7
 
 /*
  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
@@ -311,7 +381,7 @@ enum {
 #define SUPER_SCLK_DIVISOR_SHIFT       0
 #define SUPER_SCLK_DIVISOR_MASK                (0xff << SUPER_SCLK_DIVISOR_SHIFT)
 
-/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
 #define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
 #define CLK_SYS_RATE_AHB_RATE_SHIFT     4
@@ -321,23 +391,53 @@ enum {
 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 
-/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
-#define CLR_CPURESET0   (1 << 0)
-#define CLR_CPURESET1   (1 << 1)
-#define CLR_CPURESET2   (1 << 2)
-#define CLR_CPURESET3   (1 << 3)
-#define CLR_DBGRESET0   (1 << 12)
-#define CLR_DBGRESET1   (1 << 13)
-#define CLR_DBGRESET2   (1 << 14)
-#define CLR_DBGRESET3   (1 << 15)
-#define CLR_CORERESET0  (1 << 16)
-#define CLR_CORERESET1  (1 << 17)
-#define CLR_CORERESET2  (1 << 18)
-#define CLR_CORERESET3  (1 << 19)
-#define CLR_CXRESET0    (1 << 20)
-#define CLR_CXRESET1    (1 << 21)
-#define CLR_CXRESET2    (1 << 22)
-#define CLR_CXRESET3    (1 << 23)
-#define CLR_NONCPURESET (1 << 29)
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0                  (1 << 0)
+#define CLR_CPURESET1                  (1 << 1)
+#define CLR_CPURESET2                  (1 << 2)
+#define CLR_CPURESET3                  (1 << 3)
+#define CLR_DBGRESET0                  (1 << 12)
+#define CLR_DBGRESET1                  (1 << 13)
+#define CLR_DBGRESET2                  (1 << 14)
+#define CLR_DBGRESET3                  (1 << 15)
+#define CLR_CORERESET0                 (1 << 16)
+#define CLR_CORERESET1                 (1 << 17)
+#define CLR_CORERESET2                 (1 << 18)
+#define CLR_CORERESET3                 (1 << 19)
+#define CLR_CXRESET0                   (1 << 20)
+#define CLR_CXRESET1                   (1 << 21)
+#define CLR_CXRESET2                   (1 << 22)
+#define CLR_CXRESET3                   (1 << 23)
+#define CLR_L2RESET                    (1 << 24)
+#define CLR_NONCPURESET                        (1 << 29)
+#define CLR_PRESETDBG                  (1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP               (1 << 8)
+#define CLR_CPU1_CLK_STP               (1 << 9)
+#define CLR_CPU2_CLK_STP               (1 << 10)
+#define CLR_CPU3_CLK_STP               (1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0      (0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE                (1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE       (1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE     (1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN           (1 << 12)
+#define PLL_ENABLE_POWERDOWN           (1 << 14)
+#define PLLU_POWERDOWN                 (1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN        (1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN        (1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN        (1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT                        3
+#define PLLX_IDDQ_MASK                 (1U << PLLX_IDDQ_SHIFT)
 
 #endif /* _TEGRA_CLK_RST_H_ */
index c840c08a89b997b8f44b0dcbeec5aae11b35ea7c..7a86acb1b2d8fa11b2474f4746d89f9342dfd423 100644 (file)
@@ -20,5 +20,6 @@
 #define CHIPID_TEGRA20                 0x20
 #define CHIPID_TEGRA30                 0x30
 #define CHIPID_TEGRA114                        0x35
+#define CHIPID_TEGRA124                        0x40
 
 #endif /* _TEGRA_GP_PADCTRL_H_ */
index 9f05a14c175749015c447681834307beaa0cd7cd..4c3264b3859b05bbad10b5a455c51e5bee6564d2 100644 (file)
@@ -107,6 +107,179 @@ struct pmc_ctlr {
        uint pmc_sys_33v_en;            /* _SYS_33V_EN_0, offset 154 */
        uint pmc_bo_mirror_access;      /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
        uint pmc_gate;                  /* _GATE_0, offset 15C */
+       /* The following fields are in Tegra124 and later only */
+       uint pmc_wake2_mask;            /* _WAKE2_MASK_0, offset 160 */
+       uint pmc_wake2_lvl;             /* _WAKE2_LVL_0,  offset 164 */
+       uint pmc_wake2_stat;            /* _WAKE2_STATUS_0, offset 168 */
+       uint pmc_sw_wake2_stat;         /* _SW_WAKE2_STATUS_0, offset 16C */
+       uint pmc_auto_wake2_lvl_mask;   /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+       uint pmc_pg_mask2;              /* _PG_MASK_2_0, offset 174 */
+       uint pmc_pg_mask_ce1;           /* _PG_MASK_CE1_0, offset 178 */
+       uint pmc_pg_mask_ce2;           /* _PG_MASK_CE2_0, offset 17C */
+       uint pmc_pg_mask_ce3;           /* _PG_MASK_CE3_0, offset 180 */
+       uint pmc_pwrgate_timer_ce0;     /* _PWRGATE_TIMER_CE_0_0, offset 184 */
+       uint pmc_pwrgate_timer_ce1;     /* _PWRGATE_TIMER_CE_1_0, offset 188 */
+       uint pmc_pwrgate_timer_ce2;     /* _PWRGATE_TIMER_CE_2_0, offset 18C */
+       uint pmc_pwrgate_timer_ce3;     /* _PWRGATE_TIMER_CE_3_0, offset 190 */
+       uint pmc_pwrgate_timer_ce4;     /* _PWRGATE_TIMER_CE_4_0, offset 194 */
+       uint pmc_pwrgate_timer_ce5;     /* _PWRGATE_TIMER_CE_5_0, offset 198 */
+       uint pmc_pwrgate_timer_ce6;     /* _PWRGATE_TIMER_CE_6_0, offset 19C */
+       uint pmc_pcx_edpd_cntrl;        /* _PCX_EDPD_CNTRL_0, offset 1A0 */
+       uint pmc_osc_edpd_over;         /* _OSC_EDPD_OVER_0, offset 1A4 */
+       uint pmc_clk_out_cntrl;         /* _CLK_OUT_CNTRL_0, offset 1A8 */
+       uint pmc_sata_pwrgate;          /* _SATA_PWRGT_0, offset 1AC */
+       uint pmc_sensor_ctrl;           /* _SENSOR_CTRL_0, offset 1B0 */
+       uint pmc_reset_status;          /* _RTS_STATUS_0, offset 1B4 */
+       uint pmc_io_dpd_req;            /* _IO_DPD_REQ_0, offset 1B8 */
+       uint pmc_io_dpd_stat;           /* _IO_DPD_STATUS_0, offset 1BC */
+       uint pmc_io_dpd2_req;           /* _IO_DPD2_REQ_0, offset 1C0 */
+       uint pmc_io_dpd2_stat;          /* _IO_DPD2_STATUS_0, offset 1C4 */
+       uint pmc_sel_dpd_tim;           /* _SEL_DPD_TIM_0, offset 1C8 */
+       uint pmc_vddp_sel;              /* _VDDP_SEL_0, offset 1CC */
+
+       uint pmc_ddr_cfg;               /* _DDR_CFG_0, offset 1D0 */
+       uint pmc_e_no_vttgen;           /* _E_NO_VTTGEN_0, offset 1D4 */
+       uint pmc_reserved0;             /* _RESERVED, offset 1D8 */
+       uint pmc_pllm_wb0_ovrride_frq;  /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+       uint pmc_test_pwrgate;          /* _TEST_PWRGATE_0, offset 1E0 */
+       uint pmc_pwrgate_timer_mult;    /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+       uint pmc_dsi_sel_dpd;           /* _DSI_SEL_DPD_0, offset 1E8 */
+       uint pmc_utmip_uhsic_triggers;  /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+       uint pmc_utmip_uhsic_saved_st;  /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+       uint pmc_utmip_pad_cfg;         /* _UTMIP_PAD_CFG_0, offset 1F4 */
+       uint pmc_utmip_term_pad_cfg;    /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+       uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+       uint pmc_todo_0[9];             /* offset 200-220 */
+       uint pmc_secure_scratch6;       /* _SECURE_SCRATCH6_0, offset 224 */
+       uint pmc_secure_scratch7;       /* _SECURE_SCRATCH7_0, offset 228 */
+       uint pmc_scratch43;             /* _SCRATCH43_0, offset 22C */
+       uint pmc_scratch44;             /* _SCRATCH44_0, offset 230 */
+       uint pmc_scratch45;
+       uint pmc_scratch46;
+       uint pmc_scratch47;
+       uint pmc_scratch48;
+       uint pmc_scratch49;
+       uint pmc_scratch50;
+       uint pmc_scratch51;
+       uint pmc_scratch52;
+       uint pmc_scratch53;
+       uint pmc_scratch54;
+       uint pmc_scratch55;             /* _SCRATCH55_0, offset 25C */
+       uint pmc_scratch0_eco;          /* _SCRATCH0_ECO_0, offset 260 */
+       uint pmc_por_dpd_ctrl;          /* _POR_DPD_CTRL_0, offset 264 */
+       uint pmc_scratch2_eco;          /* _SCRATCH2_ECO_0, offset 268 */
+       uint pmc_todo_1[17];            /* TODO: 26C ~ 2AC */
+       uint pmc_pllm_wb0_override2;    /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+       uint pmc_tsc_mult;              /* _TSC_MULT_0, offset 2B4 */
+       uint pmc_cpu_vsense_override;   /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+       uint pmc_glb_amap_cfg;          /* _GLB_AMAP_CFG_0, offset 2BC */
+       uint pmc_sticky_bits;           /* _STICKY_BITS_0, offset 2C0 */
+       uint pmc_sec_disable2;          /* _SEC_DISALBE2, offset 2C4 */
+       uint pmc_weak_bias;             /* _WEAK_BIAS_0, offset 2C8 */
+       uint pmc_todo_3[13];            /* TODO: 2CC ~ 2FC */
+       uint pmc_secure_scratch8;       /* _SECURE_SCRATCH8_0, offset 300 */
+       uint pmc_secure_scratch9;
+       uint pmc_secure_scratch10;
+       uint pmc_secure_scratch11;
+       uint pmc_secure_scratch12;
+       uint pmc_secure_scratch13;
+       uint pmc_secure_scratch14;
+       uint pmc_secure_scratch15;
+       uint pmc_secure_scratch16;
+       uint pmc_secure_scratch17;
+       uint pmc_secure_scratch18;
+       uint pmc_secure_scratch19;
+       uint pmc_secure_scratch20;
+       uint pmc_secure_scratch21;
+       uint pmc_secure_scratch22;
+       uint pmc_secure_scratch23;
+       uint pmc_secure_scratch24;      /* _SECURE_SCRATCH24_0, offset 340 */
+       uint pmc_secure_scratch25;
+       uint pmc_secure_scratch26;
+       uint pmc_secure_scratch27;
+       uint pmc_secure_scratch28;
+       uint pmc_secure_scratch29;
+       uint pmc_secure_scratch30;
+       uint pmc_secure_scratch31;
+       uint pmc_secure_scratch32;
+       uint pmc_secure_scratch33;
+       uint pmc_secure_scratch34;
+       uint pmc_secure_scratch35;      /* _SECURE_SCRATCH35_0, offset 36C */
+
+       uint pmc_reserved1[52];         /* RESERVED: 370 ~ 43C */
+       uint pmc_cntrl2;                /* _CNTRL2_0, offset 440 */
+       uint pmc_reserved2[6];          /* RESERVED: 444 ~ 458 */
+       uint pmc_io_dpd3_req;           /* _IO_DPD3_REQ_0, offset 45c */
+       uint pmc_io_dpd3_stat;          /* _IO_DPD3_STATUS_0, offset 460 */
+       uint pmc_strap_opt_a;           /* _STRAPPING_OPT_A_0, offset 464 */
+       uint pmc_reserved3[102];        /* RESERVED: 468 ~ 5FC */
+
+       uint pmc_scratch56;             /* _SCRATCH56_0, offset 600 */
+       uint pmc_scratch57;
+       uint pmc_scratch58;
+       uint pmc_scratch59;
+       uint pmc_scratch60;
+       uint pmc_scratch61;
+       uint pmc_scratch62;
+       uint pmc_scratch63;
+       uint pmc_scratch64;
+       uint pmc_scratch65;
+       uint pmc_scratch66;
+       uint pmc_scratch67;
+       uint pmc_scratch68;
+       uint pmc_scratch69;
+       uint pmc_scratch70;
+       uint pmc_scratch71;
+       uint pmc_scratch72;
+       uint pmc_scratch73;
+       uint pmc_scratch74;
+       uint pmc_scratch75;
+       uint pmc_scratch76;
+       uint pmc_scratch77;
+       uint pmc_scratch78;
+       uint pmc_scratch79;
+       uint pmc_scratch80;
+       uint pmc_scratch81;
+       uint pmc_scratch82;
+       uint pmc_scratch83;
+       uint pmc_scratch84;
+       uint pmc_scratch85;
+       uint pmc_scratch86;
+       uint pmc_scratch87;
+       uint pmc_scratch88;
+       uint pmc_scratch89;
+       uint pmc_scratch90;
+       uint pmc_scratch91;
+       uint pmc_scratch92;
+       uint pmc_scratch93;
+       uint pmc_scratch94;
+       uint pmc_scratch95;
+       uint pmc_scratch96;
+       uint pmc_scratch97;
+       uint pmc_scratch98;
+       uint pmc_scratch99;
+       uint pmc_scratch100;
+       uint pmc_scratch101;
+       uint pmc_scratch102;
+       uint pmc_scratch103;
+       uint pmc_scratch104;
+       uint pmc_scratch105;
+       uint pmc_scratch106;
+       uint pmc_scratch107;
+       uint pmc_scratch108;
+       uint pmc_scratch109;
+       uint pmc_scratch110;
+       uint pmc_scratch111;
+       uint pmc_scratch112;
+       uint pmc_scratch113;
+       uint pmc_scratch114;
+       uint pmc_scratch115;
+       uint pmc_scratch116;
+       uint pmc_scratch117;
+       uint pmc_scratch118;
+       uint pmc_scratch119;
+       uint pmc_scratch1_eco;  /* offset 700 */
 };
 
 #define CPU_PWRED      1
@@ -122,4 +295,86 @@ struct pmc_ctlr {
 #define CE0            14
 #define C0NC           15
 
+#define PMC_XOFS_SHIFT 1
+#define PMC_XOFS_MASK  (0x3F << PMC_XOFS_SHIFT)
+
+#define TIMER_MULT_SHIFT       0
+#define TIMER_MULT_MASK                (3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT   2
+#define TIMER_MULT_CPU_MASK    (3 << TIMER_MULT_CPU_SHIFT)
+#define MULT_1                 0
+#define MULT_2                 1
+#define MULT_4                 2
+#define MULT_8                 3
+
+#define AMAP_WRITE_SHIFT       20
+#define AMAP_WRITE_ON          (1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON                  (1 << 4)
+#define SEC_DISABLE_READ0_ON                   (1 << 5)
+#define SEC_DISABLE_WRITE1_ON                  (1 << 6)
+#define SEC_DISABLE_READ1_ON                   (1 << 7)
+#define SEC_DISABLE_WRITE2_ON                  (1 << 8)
+#define SEC_DISABLE_READ2_ON                   (1 << 9)
+#define SEC_DISABLE_WRITE3_ON                  (1 << 10)
+#define SEC_DISABLE_READ3_ON                   (1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON              (1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL            0
+#define PWRGATE_TOGGLE_PARTID_TD               1
+#define PWRGATE_TOGGLE_PARTID_VE               2
+#define PWRGATE_TOGGLE_PARTID_PCX              3
+#define PWRGATE_TOGGLE_PARTID_VDE              4
+#define PWRGATE_TOGGLE_PARTID_L2C              5
+#define PWRGATE_TOGGLE_PARTID_MPE              6
+#define PWRGATE_TOGGLE_PARTID_HEG              7
+#define PWRGATE_TOGGLE_PARTID_SAX              8
+#define PWRGATE_TOGGLE_PARTID_CE1              9
+#define PWRGATE_TOGGLE_PARTID_CE2              10
+#define PWRGATE_TOGGLE_PARTID_CE3              11
+#define PWRGATE_TOGGLE_PARTID_CELP             12
+#define PWRGATE_TOGGLE_PARTID_CE0              14
+#define PWRGATE_TOGGLE_PARTID_C0NC             15
+#define PWRGATE_TOGGLE_PARTID_C1NC             16
+#define PWRGATE_TOGGLE_PARTID_SOR              17
+#define PWRGATE_TOGGLE_PARTID_DIS              18
+#define PWRGATE_TOGGLE_PARTID_DISB             19
+#define PWRGATE_TOGGLE_PARTID_XUSBA            20
+#define PWRGATE_TOGGLE_PARTID_XUSBB            21
+#define PWRGATE_TOGGLE_PARTID_XUSBC            22
+#define PWRGATE_TOGGLE_PARTID_VIC              23
+#define PWRGATE_TOGGLE_PARTID_IRAM             24
+#define PWRGATE_TOGGLE_START                   (1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE            (1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE               (1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE               (1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE              (1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE              (1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE              (1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE              (1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE              (1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE              (1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE              (1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE              (1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE              (1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE             (1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE              (1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE             (1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE             (1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE              (1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE              (1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE             (1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE            (1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE            (1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE            (1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE              (1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE             (1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN                                (1 << 12)
+
 #endif /* PMC_H */
index e99f681ffddbaadf796f0f25a4e09a98d357d34e..5fe19ae1ac137f534ba951c1bfa0593775af5848 100644 (file)
@@ -68,6 +68,7 @@ enum {
        SKU_ID_TM30MQS_P_A3     = 0xb1,
        SKU_ID_T114_ENG         = 0x00, /* Dalmore value, unfused */
        SKU_ID_T114_1           = 0x01,
+       SKU_ID_T124_ENG         = 0x00, /* Venice2 value, unfused */
 };
 
 /*
@@ -81,6 +82,7 @@ enum {
        TEGRA_SOC_T25,
        TEGRA_SOC_T30,
        TEGRA_SOC_T114,
+       TEGRA_SOC_T124,
 
        TEGRA_SOC_CNT,
        TEGRA_SOC_UNKNOWN       = -1,
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644 (file)
index 0000000..4e48c43
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+       u32 reserved0;                  /* 00h */
+       u32 arbitration_disable;        /* _ARBITRATION_DISABLE_0,      04h */
+       u32 arbitration_priority_ctrl;  /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+       u32 arbitration_usr_protect;    /* _ARBITRATION_USR_PROTECT_0,  0ch */
+       u32 gizmo_ahb_mem;              /* _GIZMO_AHB_MEM_0,            10h */
+       u32 gizmo_apb_dma;              /* _GIZMO_APB_DMA_0,            14h */
+       u32 reserved6[2];               /* 18h, 1ch */
+       u32 gizmo_usb;                  /* _GIZMO_USB_0,                20h */
+       u32 gizmo_ahb_xbar_bridge;      /* _GIZMO_AHB_XBAR_BRIDGE_0,    24h */
+       u32 gizmo_cpu_ahb_bridge;       /* _GIZMO_CPU_AHB_BRIDGE_0,     28h */
+       u32 gizmo_cop_ahb_bridge;       /* _GIZMO_COP_AHB_BRIDGE_0,     2ch */
+       u32 gizmo_xbar_apb_ctlr;        /* _GIZMO_XBAR_APB_CTLR_0,      30h */
+       u32 gizmo_vcp_ahb_bridge;       /* _GIZMO_VCP_AHB_BRIDGE_0,     34h */
+       u32 reserved13[2];              /* 38h, 3ch */
+       u32 gizmo_nand;                 /* _GIZMO_NAND_0,               40h */
+       u32 reserved15;                 /* 44h */
+       u32 gizmo_sdmmc4;               /* _GIZMO_SDMMC4_0,             48h */
+       u32 reserved17;                 /* 4ch */
+       u32 gizmo_se;                   /* _GIZMO_SE_0,                 50h */
+       u32 gizmo_tzram;                /* _GIZMO_TZRAM_0,              54h */
+       u32 reserved20[3];              /* 58h, 5ch, 60h */
+       u32 gizmo_bsev;                 /* _GIZMO_BSEV_0,               64h */
+       u32 reserved22[3];              /* 68h, 6ch, 70h */
+       u32 gizmo_bsea;                 /* _GIZMO_BSEA_0,               74h */
+       u32 gizmo_nor;                  /* _GIZMO_NOR_0,                78h */
+       u32 gizmo_usb2;                 /* _GIZMO_USB2_0,               7ch */
+       u32 gizmo_usb3;                 /* _GIZMO_USB3_0,               80h */
+       u32 gizmo_sdmmc1;               /* _GIZMO_SDMMC1_0,             84h */
+       u32 gizmo_sdmmc2;               /* _GIZMO_SDMMC2_0,             88h */
+       u32 gizmo_sdmmc3;               /* _GIZMO_SDMMC3_0,             8ch */
+       u32 reserved30[13];             /* 90h ~ c0h */
+       u32 ahb_wrq_empty;              /* _AHB_WRQ_EMPTY_0,            c4h */
+       u32 reserved32[5];              /* c8h ~ d8h */
+       u32 ahb_mem_prefetch_cfg_x;     /* _AHB_MEM_PREFETCH_CFG_X_0,   dch */
+       u32 arbitration_xbar_ctrl;      /* _ARBITRATION_XBAR_CTRL_0,    e0h */
+       u32 ahb_mem_prefetch_cfg3;      /* _AHB_MEM_PREFETCH_CFG3_0,    e4h */
+       u32 ahb_mem_prefetch_cfg4;      /* _AHB_MEM_PREFETCH_CFG3_0,    e8h */
+       u32 avp_ppcs_rd_coh_status;     /* _AVP_PPCS_RD_COH_STATUS_0,   ech */
+       u32 ahb_mem_prefetch_cfg1;      /* _AHB_MEM_PREFETCH_CFG1_0,    f0h */
+       u32 ahb_mem_prefetch_cfg2;      /* _AHB_MEM_PREFETCH_CFG2_0,    f4h */
+       u32 ahbslvmem_status;           /* _AHBSLVMEM_STATUS_0, f8h */
+       /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+       u32 arbitration_ahb_mem_wrque_mst_id;
+       u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+       u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+       u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+       u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+       u32 reserved46[4];              /* 110h ~ 11ch */
+       u32 avpc_mccif_fifoctrl;        /* _AVPC_MCCIF_FIFOCTRL_0,      120h */
+       u32 timeout_wcoal_avpc;         /* _TIMEOUT_WCOAL_AVPC_0,       124h */
+       u32 mpcorelp_mccif_fifoctrl;    /* _MPCORELP_MCCIF_FIFOCTRL_0,  128h */
+       u32 mpcore_mccif_fifoctrl;      /* _MPCORE_MCCIF_FIFOCTRL_0,    12ch */
+       u32 axicif_fastsync_ctrl;       /* AXICIF_FASTSYNC_CTRL_0,      130h */
+       u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+       /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
+       u32 axicif_fastsync0_cpuclk_to_mcclk;
+       /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+       u32 axicif_fastsync1_cpuclk_to_mcclk;
+       /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+       u32 axicif_fastsync2_cpuclk_to_mcclk;
+       /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+       u32 axicif_fastsync0_mcclk_to_cpuclk;
+       /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+       u32 axicif_fastsync1_mcclk_to_cpuclk;
+       /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+       u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE    (1 << 2)
+
+#define GIZ_ENABLE_SPLIT       (1 << 0)
+#define GIZ_ENB_FAST_REARB     (1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR  (1 << 7)
+
+#define GIZ_USB_IMMEDIATE      (1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE      (1 << 2)
+
+#endif /* _TEGRA124_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644 (file)
index 0000000..daf9a2b
--- /dev/null
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+       CLOCK_ID_FIRST,
+       CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+       CLOCK_ID_MEMORY,
+       CLOCK_ID_PERIPH,
+       CLOCK_ID_AUDIO,
+       CLOCK_ID_USB,
+       CLOCK_ID_DISPLAY,
+
+       /* now the simple ones */
+       CLOCK_ID_FIRST_SIMPLE,
+       CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+       CLOCK_ID_EPCI,
+       CLOCK_ID_SFROM32KHZ,
+
+       /* These are the base clocks (inputs to the Tegra SoC) */
+       CLOCK_ID_32KHZ,
+       CLOCK_ID_OSC,
+
+       CLOCK_ID_COUNT, /* number of PLLs */
+
+       /*
+        * These are clock IDs that are used in table clock_source[][]
+        * but will not be assigned as a clock source for any peripheral.
+        */
+       CLOCK_ID_DISPLAY2,
+       CLOCK_ID_CGENERAL2,
+       CLOCK_ID_CGENERAL3,
+       CLOCK_ID_MEMORY2,
+       CLOCK_ID_SRC2,
+
+       CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+       PERIPH_ID_FIRST,
+
+       /* Low word: 31:0 (DEVICES_L) */
+       PERIPH_ID_CPU = PERIPH_ID_FIRST,
+       PERIPH_ID_COP,
+       PERIPH_ID_TRIGSYS,
+       PERIPH_ID_ISPB,
+       PERIPH_ID_RESERVED4,
+       PERIPH_ID_TMR,
+       PERIPH_ID_UART1,
+       PERIPH_ID_UART2,
+
+       /* 8 */
+       PERIPH_ID_GPIO,
+       PERIPH_ID_SDMMC2,
+       PERIPH_ID_SPDIF,
+       PERIPH_ID_I2S1,
+       PERIPH_ID_I2C1,
+       PERIPH_ID_RESERVED13,
+       PERIPH_ID_SDMMC1,
+       PERIPH_ID_SDMMC4,
+
+       /* 16 */
+       PERIPH_ID_TCW,
+       PERIPH_ID_PWM,
+       PERIPH_ID_I2S2,
+       PERIPH_ID_RESERVED19,
+       PERIPH_ID_VI,
+       PERIPH_ID_RESERVED21,
+       PERIPH_ID_USBD,
+       PERIPH_ID_ISP,
+
+       /* 24 */
+       PERIPH_ID_RESERVED24,
+       PERIPH_ID_RESERVED25,
+       PERIPH_ID_DISP2,
+       PERIPH_ID_DISP1,
+       PERIPH_ID_HOST1X,
+       PERIPH_ID_VCP,
+       PERIPH_ID_I2S0,
+       PERIPH_ID_CACHE2,
+
+       /* Middle word: 63:32 (DEVICES_H) */
+       PERIPH_ID_MEM,
+       PERIPH_ID_AHBDMA,
+       PERIPH_ID_APBDMA,
+       PERIPH_ID_RESERVED35,
+       PERIPH_ID_RESERVED36,
+       PERIPH_ID_STAT_MON,
+       PERIPH_ID_RESERVED38,
+       PERIPH_ID_FUSE,
+
+       /* 40 */
+       PERIPH_ID_KFUSE,
+       PERIPH_ID_SBC1,
+       PERIPH_ID_SNOR,
+       PERIPH_ID_RESERVED43,
+       PERIPH_ID_SBC2,
+       PERIPH_ID_XIO,
+       PERIPH_ID_SBC3,
+       PERIPH_ID_I2C5,
+
+       /* 48 */
+       PERIPH_ID_DSI,
+       PERIPH_ID_RESERVED49,
+       PERIPH_ID_HSI,
+       PERIPH_ID_HDMI,
+       PERIPH_ID_CSI,
+       PERIPH_ID_RESERVED53,
+       PERIPH_ID_I2C2,
+       PERIPH_ID_UART3,
+
+       /* 56 */
+       PERIPH_ID_MIPI_CAL,
+       PERIPH_ID_EMC,
+       PERIPH_ID_USB2,
+       PERIPH_ID_USB3,
+       PERIPH_ID_RESERVED60,
+       PERIPH_ID_VDE,
+       PERIPH_ID_BSEA,
+       PERIPH_ID_BSEV,
+
+       /* Upper word 95:64 (DEVICES_U) */
+       PERIPH_ID_RESERVED64,
+       PERIPH_ID_UART4,
+       PERIPH_ID_UART5,
+       PERIPH_ID_I2C3,
+       PERIPH_ID_SBC4,
+       PERIPH_ID_SDMMC3,
+       PERIPH_ID_PCIE,
+       PERIPH_ID_OWR,
+
+       /* 72 */
+       PERIPH_ID_AFI,
+       PERIPH_ID_CORESIGHT,
+       PERIPH_ID_PCIEXCLK,
+       PERIPH_ID_AVPUCQ,
+       PERIPH_ID_LA,
+       PERIPH_ID_TRACECLKIN,
+       PERIPH_ID_SOC_THERM,
+       PERIPH_ID_DTV,
+
+       /* 80 */
+       PERIPH_ID_RESERVED80,
+       PERIPH_ID_I2CSLOW,
+       PERIPH_ID_DSIB,
+       PERIPH_ID_TSEC,
+       PERIPH_ID_RESERVED84,
+       PERIPH_ID_RESERVED85,
+       PERIPH_ID_RESERVED86,
+       PERIPH_ID_EMUCIF,
+
+       /* 88 */
+       PERIPH_ID_RESERVED88,
+       PERIPH_ID_XUSB_HOST,
+       PERIPH_ID_RESERVED90,
+       PERIPH_ID_MSENC,
+       PERIPH_ID_RESERVED92,
+       PERIPH_ID_RESERVED93,
+       PERIPH_ID_RESERVED94,
+       PERIPH_ID_XUSB_DEV,
+
+       PERIPH_ID_VW_FIRST,
+       /* V word: 31:0 */
+       PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+       PERIPH_ID_CPULP,
+       PERIPH_ID_V_RESERVED2,
+       PERIPH_ID_MSELECT,
+       PERIPH_ID_V_RESERVED4,
+       PERIPH_ID_I2S3,
+       PERIPH_ID_I2S4,
+       PERIPH_ID_I2C4,
+
+       /* 104 */
+       PERIPH_ID_SBC5,
+       PERIPH_ID_SBC6,
+       PERIPH_ID_AUDIO,
+       PERIPH_ID_APBIF,
+       PERIPH_ID_DAM0,
+       PERIPH_ID_DAM1,
+       PERIPH_ID_DAM2,
+       PERIPH_ID_HDA2CODEC2X,
+
+       /* 112 */
+       PERIPH_ID_ATOMICS,
+       PERIPH_ID_V_RESERVED17,
+       PERIPH_ID_V_RESERVED18,
+       PERIPH_ID_V_RESERVED19,
+       PERIPH_ID_V_RESERVED20,
+       PERIPH_ID_V_RESERVED21,
+       PERIPH_ID_V_RESERVED22,
+       PERIPH_ID_ACTMON,
+
+       /* 120 */
+       PERIPH_ID_EXTPERIPH1,
+       PERIPH_ID_EXTPERIPH2,
+       PERIPH_ID_EXTPERIPH3,
+       PERIPH_ID_OOB,
+       PERIPH_ID_SATA,
+       PERIPH_ID_HDA,
+       PERIPH_ID_V_RESERVED30,
+       PERIPH_ID_V_RESERVED31,
+
+       /* W word: 31:0 */
+       PERIPH_ID_HDA2HDMICODEC,
+       PERIPH_ID_SATACOLD,
+       PERIPH_ID_W_RESERVED2,
+       PERIPH_ID_W_RESERVED3,
+       PERIPH_ID_W_RESERVED4,
+       PERIPH_ID_W_RESERVED5,
+       PERIPH_ID_W_RESERVED6,
+       PERIPH_ID_W_RESERVED7,
+
+       /* 136 */
+       PERIPH_ID_CEC,
+       PERIPH_ID_W_RESERVED9,
+       PERIPH_ID_W_RESERVED10,
+       PERIPH_ID_W_RESERVED11,
+       PERIPH_ID_W_RESERVED12,
+       PERIPH_ID_W_RESERVED13,
+       PERIPH_ID_XUSB_PADCTL,
+       PERIPH_ID_W_RESERVED15,
+
+       /* 144 */
+       PERIPH_ID_W_RESERVED16,
+       PERIPH_ID_W_RESERVED17,
+       PERIPH_ID_W_RESERVED18,
+       PERIPH_ID_W_RESERVED19,
+       PERIPH_ID_W_RESERVED20,
+       PERIPH_ID_ENTROPY,
+       PERIPH_ID_DDS,
+       PERIPH_ID_W_RESERVED23,
+
+       /* 152 */
+       PERIPH_ID_DP2,
+       PERIPH_ID_AMX0,
+       PERIPH_ID_ADX0,
+       PERIPH_ID_DVFS,
+       PERIPH_ID_XUSB_SS,
+       PERIPH_ID_W_RESERVED29,
+       PERIPH_ID_W_RESERVED30,
+       PERIPH_ID_W_RESERVED31,
+
+       PERIPH_ID_X_FIRST,
+       /* X word: 31:0 */
+       PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+       PERIPH_ID_X_RESERVED1,
+       PERIPH_ID_X_RESERVED2,
+       PERIPH_ID_X_RESERVED3,
+       PERIPH_ID_CAM_MCLK,
+       PERIPH_ID_CAM_MCLK2,
+       PERIPH_ID_I2C6,
+       PERIPH_ID_X_RESERVED7,
+
+       /* 168 */
+       PERIPH_ID_X_RESERVED8,
+       PERIPH_ID_X_RESERVED9,
+       PERIPH_ID_X_RESERVED10,
+       PERIPH_ID_VIM2_CLK,
+       PERIPH_ID_X_RESERVED12,
+       PERIPH_ID_X_RESERVED13,
+       PERIPH_ID_EMC_DLL,
+       PERIPH_ID_X_RESERVED15,
+
+       /* 176 */
+       PERIPH_ID_HDMI_AUDIO,
+       PERIPH_ID_CLK72MHZ,
+       PERIPH_ID_VIC,
+       PERIPH_ID_X_RESERVED19,
+       PERIPH_ID_ADX1,
+       PERIPH_ID_DPAUX,
+       PERIPH_ID_SOR0,
+       PERIPH_ID_X_RESERVED23,
+
+       /* 184 */
+       PERIPH_ID_GPU,
+       PERIPH_ID_AMX1,
+       PERIPH_ID_X_RESERVED26,
+       PERIPH_ID_X_RESERVED27,
+       PERIPH_ID_X_RESERVED28,
+       PERIPH_ID_X_RESERVED29,
+       PERIPH_ID_X_RESERVED30,
+       PERIPH_ID_X_RESERVED31,
+
+       PERIPH_ID_COUNT,
+       PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+       PLL_OUT1,
+       PLL_OUT2,
+       PLL_OUT3,
+       PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+       /* 0x00 */
+       PERIPHC_I2S1,
+       PERIPHC_I2S2,
+       PERIPHC_SPDIF_OUT,
+       PERIPHC_SPDIF_IN,
+       PERIPHC_PWM,
+       PERIPHC_05h,
+       PERIPHC_SBC2,
+       PERIPHC_SBC3,
+
+       /* 0x08 */
+       PERIPHC_08h,
+       PERIPHC_I2C1,
+       PERIPHC_I2C5,
+       PERIPHC_0bh,
+       PERIPHC_0ch,
+       PERIPHC_SBC1,
+       PERIPHC_DISP1,
+       PERIPHC_DISP2,
+
+       /* 0x10 */
+       PERIPHC_10h,
+       PERIPHC_11h,
+       PERIPHC_VI,
+       PERIPHC_13h,
+       PERIPHC_SDMMC1,
+       PERIPHC_SDMMC2,
+       PERIPHC_G3D,
+       PERIPHC_G2D,
+
+       /* 0x18 */
+       PERIPHC_18h,
+       PERIPHC_SDMMC4,
+       PERIPHC_VFIR,
+       PERIPHC_1Bh,
+       PERIPHC_1Ch,
+       PERIPHC_HSI,
+       PERIPHC_UART1,
+       PERIPHC_UART2,
+
+       /* 0x20 */
+       PERIPHC_HOST1X,
+       PERIPHC_21h,
+       PERIPHC_22h,
+       PERIPHC_HDMI,
+       PERIPHC_24h,
+       PERIPHC_25h,
+       PERIPHC_I2C2,
+       PERIPHC_EMC,
+
+       /* 0x28 */
+       PERIPHC_UART3,
+       PERIPHC_29h,
+       PERIPHC_VI_SENSOR,
+       PERIPHC_2bh,
+       PERIPHC_2ch,
+       PERIPHC_SBC4,
+       PERIPHC_I2C3,
+       PERIPHC_SDMMC3,
+
+       /* 0x30 */
+       PERIPHC_UART4,
+       PERIPHC_UART5,
+       PERIPHC_VDE,
+       PERIPHC_OWR,
+       PERIPHC_NOR,
+       PERIPHC_CSITE,
+       PERIPHC_I2S0,
+       PERIPHC_DTV,
+
+       /* 0x38 */
+       PERIPHC_38h,
+       PERIPHC_39h,
+       PERIPHC_3ah,
+       PERIPHC_3bh,
+       PERIPHC_MSENC,
+       PERIPHC_TSEC,
+       PERIPHC_3eh,
+       PERIPHC_OSC,
+
+       PERIPHC_VW_FIRST,
+       /* 0x40 */
+       PERIPHC_40h = PERIPHC_VW_FIRST,
+       PERIPHC_MSELECT,
+       PERIPHC_TSENSOR,
+       PERIPHC_I2S3,
+       PERIPHC_I2S4,
+       PERIPHC_I2C4,
+       PERIPHC_SBC5,
+       PERIPHC_SBC6,
+
+       /* 0x48 */
+       PERIPHC_AUDIO,
+       PERIPHC_49h,
+       PERIPHC_DAM0,
+       PERIPHC_DAM1,
+       PERIPHC_DAM2,
+       PERIPHC_HDA2CODEC2X,
+       PERIPHC_ACTMON,
+       PERIPHC_EXTPERIPH1,
+
+       /* 0x50 */
+       PERIPHC_EXTPERIPH2,
+       PERIPHC_EXTPERIPH3,
+       PERIPHC_52h,
+       PERIPHC_I2CSLOW,
+       PERIPHC_SYS,
+       PERIPHC_55h,
+       PERIPHC_56h,
+       PERIPHC_57h,
+
+       /* 0x58 */
+       PERIPHC_58h,
+       PERIPHC_59h,
+       PERIPHC_5ah,
+       PERIPHC_5bh,
+       PERIPHC_SATAOOB,
+       PERIPHC_SATA,
+       PERIPHC_HDA,            /* 0x428 */
+       PERIPHC_5fh,
+
+       PERIPHC_X_FIRST,
+       /* 0x60 */
+       PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,       /* 0x600 */
+       PERIPHC_XUSB_FALCON,
+       PERIPHC_XUSB_FS,
+       PERIPHC_XUSB_CORE_DEV,
+       PERIPHC_XUSB_SS,
+       PERIPHC_CILAB,
+       PERIPHC_CILCD,
+       PERIPHC_CILE,
+
+       /* 0x68 */
+       PERIPHC_DSIA_LP,
+       PERIPHC_DSIB_LP,
+       PERIPHC_ENTROPY,
+       PERIPHC_DVFS_REF,
+       PERIPHC_DVFS_SOC,
+       PERIPHC_TRACECLKIN,
+       PERIPHC_ADX0,
+       PERIPHC_AMX0,
+
+       /* 0x70 */
+       PERIPHC_EMC_LATENCY,
+       PERIPHC_SOC_THERM,
+       PERIPHC_72h,
+       PERIPHC_73h,
+       PERIPHC_74h,
+       PERIPHC_75h,
+       PERIPHC_VI_SENSOR2,
+       PERIPHC_I2C6,
+
+       /* 0x78 */
+       PERIPHC_78h,
+       PERIPHC_EMC_DLL,
+       PERIPHC_HDMI_AUDIO,
+       PERIPHC_CLK72MHZ,
+       PERIPHC_ADX1,
+       PERIPHC_AMX1,
+       PERIPHC_VIC,
+       PERIPHC_7fh,
+
+       PERIPHC_COUNT,
+
+       PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+       (id < PERIPH_ID_VW_FIRST) ? \
+               ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+               (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644 (file)
index 0000000..8e39d21
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644 (file)
index 0000000..0db1881
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+       u32 halt_cpu_events;    /* offset 0x00 */
+       u32 halt_cop_events;    /* offset 0x04 */
+       u32 cpu_csr;            /* offset 0x08 */
+       u32 cop_csr;            /* offset 0x0c */
+       u32 xrq_events;         /* offset 0x10 */
+       u32 halt_cpu1_events;   /* offset 0x14 */
+       u32 cpu1_csr;           /* offset 0x18 */
+       u32 halt_cpu2_events;   /* offset 0x1c */
+       u32 cpu2_csr;           /* offset 0x20 */
+       u32 halt_cpu3_events;   /* offset 0x24 */
+       u32 cpu3_csr;           /* offset 0x28 */
+       u32 cluster_control;    /* offset 0x2c */
+       u32 halt_cop1_events;   /* offset 0x30 */
+       u32 halt_cop1_csr;      /* offset 0x34 */
+       u32 cpu_pwr_csr;        /* offset 0x38 */
+       u32 mpid;               /* offset 0x3c */
+       u32 ram_repair;         /* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC             (1 << 24)
+#define EVENT_USEC             (1 << 25)
+#define EVENT_JTAG             (1 << 28)
+#define EVENT_MODE_STOP                (2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP              (1 << 0)
+
+#endif /*  _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644 (file)
index 0000000..df94d13
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+       FUNCMUX_DEFAULT = 0,    /* default config */
+
+       /* UART configs */
+       FUNCMUX_UART1_KBC = 0,
+       FUNCMUX_UART4_GPIO = 0,
+};
+#endif /* _TEGRA124_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644 (file)
index 0000000..440cbbf
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+       u32     modereg;        /* 0x00: APB_MISC_GP_MODEREG */
+       u32     hidrev;         /* 0x04: APB_MISC_GP_HIDREV */
+       u32     reserved0[22];  /* 0x08 - 0x5C: */
+       u32     emu_revid;      /* 0x60: APB_MISC_GP_EMU_REVID */
+       u32     xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+       u32     aocfg1;         /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+       u32     aocfg2;         /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+       u32     atcfg1;         /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+       u32     atcfg2;         /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+       u32     atcfg3;         /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+       u32     atcfg4;         /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+       u32     atcfg5;         /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+       u32     cdev1cfg;       /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+       u32     cdev2cfg;       /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+       u32     reserved1;      /* 0x8C: */
+       u32     dap1cfg;        /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+       u32     dap2cfg;        /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+       u32     dap3cfg;        /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+       u32     dap4cfg;        /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+       u32     dbgcfg;         /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+       u32     reserved2[3];   /* 0xA4 - 0xAC: */
+       u32     sdio3cfg;       /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+       u32     spicfg;         /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+       u32     uaacfg;         /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+       u32     uabcfg;         /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+       u32     uart2cfg;       /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+       u32     uart3cfg;       /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+       u32     reserved3[9];   /* 0xC8-0xE8: */
+       u32     sdio1cfg;       /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+       u32     reserved4[3];   /* 0xF0-0xF8: */
+       u32     ddccfg;         /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+       u32     gmacfg;         /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+       u32     reserved5[3];   /* 0x104-0x10C: */
+       u32     gmecfg;         /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+       u32     gmfcfg;         /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+       u32     gmgcfg;         /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+       u32     gmhcfg;         /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+       u32     owrcfg;         /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+       u32     uadcfg;         /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+       u32     reserved6;      /* 0x128: */
+       u32     dev3cfg;        /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+       u32     reserved7[2];   /* 0x130 - 0x134: */
+       u32     ceccfg;         /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+       u32     reserved8[22];  /* 0x13C - 0x190: */
+       u32     atcfg6;         /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+       u32     dap5cfg;        /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+       u32     vbuscfg;        /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+       u32     aocfg3;         /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+       u32     hvccfg0;        /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+       u32     sdio4cfg;       /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+       u32     aocfg0;         /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF     0
+#define SDIOCFG_DRVDN_SLWR     0
+#define SDIOCFG_DRVUP          0x24
+#define SDIOCFG_DRVDN          0x14
+
+#endif /* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644 (file)
index 0000000..1a6dcb8
--- /dev/null
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS       4       /* number of ports per bank */
+#define TEGRA_GPIO_BANKS       8       /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+       uint gpio_config[TEGRA_GPIO_PORTS];
+       uint gpio_dir_out[TEGRA_GPIO_PORTS];
+       uint gpio_out[TEGRA_GPIO_PORTS];
+       uint gpio_in[TEGRA_GPIO_PORTS];
+       uint gpio_int_status[TEGRA_GPIO_PORTS];
+       uint gpio_int_enable[TEGRA_GPIO_PORTS];
+       uint gpio_int_level[TEGRA_GPIO_PORTS];
+       uint gpio_int_clear[TEGRA_GPIO_PORTS];
+       uint gpio_masked_config[TEGRA_GPIO_PORTS];
+       uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+       uint gpio_masked_out[TEGRA_GPIO_PORTS];
+       uint gpio_masked_in[TEGRA_GPIO_PORTS];
+       uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+       uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+       uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+       uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+       struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+       GPIO_PA0 = 0,   /* pin 0 */
+       GPIO_PA1,
+       GPIO_PA2,
+       GPIO_PA3,
+       GPIO_PA4,
+       GPIO_PA5,
+       GPIO_PA6,
+       GPIO_PA7,
+       GPIO_PB0,       /* pin 8 */
+       GPIO_PB1,
+       GPIO_PB2,
+       GPIO_PB3,
+       GPIO_PB4,
+       GPIO_PB5,
+       GPIO_PB6,
+       GPIO_PB7,
+       GPIO_PC0,       /* pin 16 */
+       GPIO_PC1,
+       GPIO_PC2,
+       GPIO_PC3,
+       GPIO_PC4,
+       GPIO_PC5,
+       GPIO_PC6,
+       GPIO_PC7,
+       GPIO_PD0,       /* pin 24 */
+       GPIO_PD1,
+       GPIO_PD2,
+       GPIO_PD3,
+       GPIO_PD4,
+       GPIO_PD5,
+       GPIO_PD6,
+       GPIO_PD7,
+       GPIO_PE0,       /* pin 32 */
+       GPIO_PE1,
+       GPIO_PE2,
+       GPIO_PE3,
+       GPIO_PE4,
+       GPIO_PE5,
+       GPIO_PE6,
+       GPIO_PE7,
+       GPIO_PF0,       /* pin 40 */
+       GPIO_PF1,
+       GPIO_PF2,
+       GPIO_PF3,
+       GPIO_PF4,
+       GPIO_PF5,
+       GPIO_PF6,
+       GPIO_PF7,
+       GPIO_PG0,       /* pin 48 */
+       GPIO_PG1,
+       GPIO_PG2,
+       GPIO_PG3,
+       GPIO_PG4,
+       GPIO_PG5,
+       GPIO_PG6,
+       GPIO_PG7,
+       GPIO_PH0,       /* pin 56 */
+       GPIO_PH1,
+       GPIO_PH2,
+       GPIO_PH3,
+       GPIO_PH4,
+       GPIO_PH5,
+       GPIO_PH6,
+       GPIO_PH7,
+       GPIO_PI0,       /* pin 64 */
+       GPIO_PI1,
+       GPIO_PI2,
+       GPIO_PI3,
+       GPIO_PI4,
+       GPIO_PI5,
+       GPIO_PI6,
+       GPIO_PI7,
+       GPIO_PJ0,       /* pin 72 */
+       GPIO_PJ1,
+       GPIO_PJ2,
+       GPIO_PJ3,
+       GPIO_PJ4,
+       GPIO_PJ5,
+       GPIO_PJ6,
+       GPIO_PJ7,
+       GPIO_PK0,       /* pin 80 */
+       GPIO_PK1,
+       GPIO_PK2,
+       GPIO_PK3,
+       GPIO_PK4,
+       GPIO_PK5,
+       GPIO_PK6,
+       GPIO_PK7,
+       GPIO_PL0,       /* pin 88 */
+       GPIO_PL1,
+       GPIO_PL2,
+       GPIO_PL3,
+       GPIO_PL4,
+       GPIO_PL5,
+       GPIO_PL6,
+       GPIO_PL7,
+       GPIO_PM0,       /* pin 96 */
+       GPIO_PM1,
+       GPIO_PM2,
+       GPIO_PM3,
+       GPIO_PM4,
+       GPIO_PM5,
+       GPIO_PM6,
+       GPIO_PM7,
+       GPIO_PN0,       /* pin 104 */
+       GPIO_PN1,
+       GPIO_PN2,
+       GPIO_PN3,
+       GPIO_PN4,
+       GPIO_PN5,
+       GPIO_PN6,
+       GPIO_PN7,
+       GPIO_PO0,       /* pin 112 */
+       GPIO_PO1,
+       GPIO_PO2,
+       GPIO_PO3,
+       GPIO_PO4,
+       GPIO_PO5,
+       GPIO_PO6,
+       GPIO_PO7,
+       GPIO_PP0,       /* pin 120 */
+       GPIO_PP1,
+       GPIO_PP2,
+       GPIO_PP3,
+       GPIO_PP4,
+       GPIO_PP5,
+       GPIO_PP6,
+       GPIO_PP7,
+       GPIO_PQ0,       /* pin 128 */
+       GPIO_PQ1,
+       GPIO_PQ2,
+       GPIO_PQ3,
+       GPIO_PQ4,
+       GPIO_PQ5,
+       GPIO_PQ6,
+       GPIO_PQ7,
+       GPIO_PR0,       /* pin 136 */
+       GPIO_PR1,
+       GPIO_PR2,
+       GPIO_PR3,
+       GPIO_PR4,
+       GPIO_PR5,
+       GPIO_PR6,
+       GPIO_PR7,
+       GPIO_PS0,       /* pin 144 */
+       GPIO_PS1,
+       GPIO_PS2,
+       GPIO_PS3,
+       GPIO_PS4,
+       GPIO_PS5,
+       GPIO_PS6,
+       GPIO_PS7,
+       GPIO_PT0,       /* pin 152 */
+       GPIO_PT1,
+       GPIO_PT2,
+       GPIO_PT3,
+       GPIO_PT4,
+       GPIO_PT5,
+       GPIO_PT6,
+       GPIO_PT7,
+       GPIO_PU0,       /* pin 160 */
+       GPIO_PU1,
+       GPIO_PU2,
+       GPIO_PU3,
+       GPIO_PU4,
+       GPIO_PU5,
+       GPIO_PU6,
+       GPIO_PU7,
+       GPIO_PV0,       /* pin 168 */
+       GPIO_PV1,
+       GPIO_PV2,
+       GPIO_PV3,
+       GPIO_PV4,
+       GPIO_PV5,
+       GPIO_PV6,
+       GPIO_PV7,
+       GPIO_PW0,       /* pin 176 */
+       GPIO_PW1,
+       GPIO_PW2,
+       GPIO_PW3,
+       GPIO_PW4,
+       GPIO_PW5,
+       GPIO_PW6,
+       GPIO_PW7,
+       GPIO_PX0,       /* pin 184 */
+       GPIO_PX1,
+       GPIO_PX2,
+       GPIO_PX3,
+       GPIO_PX4,
+       GPIO_PX5,
+       GPIO_PX6,
+       GPIO_PX7,
+       GPIO_PY0,       /* pin 192 */
+       GPIO_PY1,
+       GPIO_PY2,
+       GPIO_PY3,
+       GPIO_PY4,
+       GPIO_PY5,
+       GPIO_PY6,
+       GPIO_PY7,
+       GPIO_PZ0,       /* pin 200 */
+       GPIO_PZ1,
+       GPIO_PZ2,
+       GPIO_PZ3,
+       GPIO_PZ4,
+       GPIO_PZ5,
+       GPIO_PZ6,
+       GPIO_PZ7,
+       GPIO_PAA0,      /* pin 208 */
+       GPIO_PAA1,
+       GPIO_PAA2,
+       GPIO_PAA3,
+       GPIO_PAA4,
+       GPIO_PAA5,
+       GPIO_PAA6,
+       GPIO_PAA7,
+       GPIO_PBB0,      /* pin 216 */
+       GPIO_PBB1,
+       GPIO_PBB2,
+       GPIO_PBB3,
+       GPIO_PBB4,
+       GPIO_PBB5,
+       GPIO_PBB6,
+       GPIO_PBB7,
+       GPIO_PCC0,      /* pin 224 */
+       GPIO_PCC1,
+       GPIO_PCC2,
+       GPIO_PCC3,
+       GPIO_PCC4,
+       GPIO_PCC5,
+       GPIO_PCC6,
+       GPIO_PCC7,
+       GPIO_PDD0,      /* pin 232 */
+       GPIO_PDD1,
+       GPIO_PDD2,
+       GPIO_PDD3,
+       GPIO_PDD4,
+       GPIO_PDD5,
+       GPIO_PDD6,
+       GPIO_PDD7,
+       GPIO_PEE0,      /* pin 240 */
+       GPIO_PEE1,
+       GPIO_PEE2,
+       GPIO_PEE3,
+       GPIO_PEE4,
+       GPIO_PEE5,
+       GPIO_PEE6,
+       GPIO_PEE7,
+       GPIO_PFF0,      /* pin 248 */
+       GPIO_PFF1,
+       GPIO_PFF2,
+       GPIO_PFF3,
+       GPIO_PFF4,
+       GPIO_PFF5,
+       GPIO_PFF6,
+       GPIO_PFF7,      /* pin 255 */
+};
+
+#endif /* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h
new file mode 100644 (file)
index 0000000..114fce8
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644 (file)
index 0000000..9662e2b
--- /dev/null
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *     - function
+ *     - pullup / pulldown
+ *     - tristate or normal
+ */
+enum pmux_pingrp {
+       PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+       PINGRP_ULPI_DATA1,
+       PINGRP_ULPI_DATA2,
+       PINGRP_ULPI_DATA3,
+       PINGRP_ULPI_DATA4,
+       PINGRP_ULPI_DATA5,
+       PINGRP_ULPI_DATA6,
+       PINGRP_ULPI_DATA7,
+       PINGRP_ULPI_CLK,
+       PINGRP_ULPI_DIR,
+       PINGRP_ULPI_NXT,
+       PINGRP_ULPI_STP,
+       PINGRP_DAP3_FS,
+       PINGRP_DAP3_DIN,
+       PINGRP_DAP3_DOUT,
+       PINGRP_DAP3_SCLK,
+       PINGRP_GPIO_PV0,
+       PINGRP_GPIO_PV1,
+       PINGRP_SDMMC1_CLK,
+       PINGRP_SDMMC1_CMD,
+       PINGRP_SDMMC1_DAT3,
+       PINGRP_SDMMC1_DAT2,
+       PINGRP_SDMMC1_DAT1,
+       PINGRP_SDMMC1_DAT0,
+       PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
+       PINGRP_CLK2_REQ,
+       PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
+       PINGRP_DDC_SCL,
+       PINGRP_DDC_SDA,
+       PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
+       PINGRP_UART2_TXD,
+       PINGRP_UART2_RTS_N,
+       PINGRP_UART2_CTS_N,
+       PINGRP_UART3_TXD,
+       PINGRP_UART3_RXD,
+       PINGRP_UART3_CTS_N,
+       PINGRP_UART3_RTS_N,
+       PINGRP_GPIO_PU0,
+       PINGRP_GPIO_PU1,
+       PINGRP_GPIO_PU2,
+       PINGRP_GPIO_PU3,
+       PINGRP_GPIO_PU4,
+       PINGRP_GPIO_PU5,
+       PINGRP_GPIO_PU6,
+       PINGRP_GEN1_I2C_SDA,
+       PINGRP_GEN1_I2C_SCL,
+       PINGRP_DAP4_FS,
+       PINGRP_DAP4_DIN,
+       PINGRP_DAP4_DOUT,
+       PINGRP_DAP4_SCLK,
+       PINGRP_CLK3_OUT,
+       PINGRP_CLK3_REQ,
+       /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
+       PINGRP_GPIO_PC7,                        /* offset 0x31c0 */
+       PINGRP_GPIO_PI5,
+       PINGRP_GPIO_PI7,
+       PINGRP_GPIO_PK0,
+       PINGRP_GPIO_PK1,
+       PINGRP_GPIO_PJ0,
+       PINGRP_GPIO_PJ2,
+       PINGRP_GPIO_PK3,
+       PINGRP_GPIO_PK4,
+       PINGRP_GPIO_PK2,
+       PINGRP_GPIO_PI3,
+       PINGRP_GPIO_PI6,
+       PINGRP_GPIO_PG0,
+       PINGRP_GPIO_PG1,
+       PINGRP_GPIO_PG2,
+       PINGRP_GPIO_PG3,
+       PINGRP_GPIO_PG4,
+       PINGRP_GPIO_PG5,
+       PINGRP_GPIO_PG6,
+       PINGRP_GPIO_PG7,
+       PINGRP_GPIO_PH0,
+       PINGRP_GPIO_PH1,
+       PINGRP_GPIO_PH2,
+       PINGRP_GPIO_PH3,
+       PINGRP_GPIO_PH4,
+       PINGRP_GPIO_PH5,
+       PINGRP_GPIO_PH6,
+       PINGRP_GPIO_PH7,
+       PINGRP_GPIO_PJ7,
+       PINGRP_GPIO_PB0,
+       PINGRP_GPIO_PB1,
+       PINGRP_GPIO_PK7,
+       PINGRP_GPIO_PI0,
+       PINGRP_GPIO_PI1,
+       PINGRP_GPIO_PI2,
+       PINGRP_GPIO_PI4,                        /* offset 0x324c */
+       PINGRP_GEN2_I2C_SCL,
+       PINGRP_GEN2_I2C_SDA,
+       PINGRP_SDMMC4_CLK,
+       PINGRP_SDMMC4_CMD,
+       PINGRP_SDMMC4_DAT0,
+       PINGRP_SDMMC4_DAT1,
+       PINGRP_SDMMC4_DAT2,
+       PINGRP_SDMMC4_DAT3,
+       PINGRP_SDMMC4_DAT4,
+       PINGRP_SDMMC4_DAT5,
+       PINGRP_SDMMC4_DAT6,
+       PINGRP_SDMMC4_DAT7,
+       PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
+       PINGRP_GPIO_PCC1,
+       PINGRP_GPIO_PBB0,
+       PINGRP_CAM_I2C_SCL,
+       PINGRP_CAM_I2C_SDA,
+       PINGRP_GPIO_PBB3,
+       PINGRP_GPIO_PBB4,
+       PINGRP_GPIO_PBB5,
+       PINGRP_GPIO_PBB6,
+       PINGRP_GPIO_PBB7,
+       PINGRP_GPIO_PCC2,
+       PINGRP_JTAG_RTCK,
+       PINGRP_PWR_I2C_SCL,
+       PINGRP_PWR_I2C_SDA,
+       PINGRP_KB_ROW0,
+       PINGRP_KB_ROW1,
+       PINGRP_KB_ROW2,
+       PINGRP_KB_ROW3,
+       PINGRP_KB_ROW4,
+       PINGRP_KB_ROW5,
+       PINGRP_KB_ROW6,
+       PINGRP_KB_ROW7,
+       PINGRP_KB_ROW8,
+       PINGRP_KB_ROW9,
+       PINGRP_KB_ROW10,
+       PINGRP_KB_ROW11,
+       PINGRP_KB_ROW12,
+       PINGRP_KB_ROW13,
+       PINGRP_KB_ROW14,
+       PINGRP_KB_ROW15,
+       PINGRP_KB_COL0,                         /* offset 0x32fc */
+       PINGRP_KB_COL1,
+       PINGRP_KB_COL2,
+       PINGRP_KB_COL3,
+       PINGRP_KB_COL4,
+       PINGRP_KB_COL5,
+       PINGRP_KB_COL6,
+       PINGRP_KB_COL7,
+       PINGRP_CLK_32K_OUT,
+       PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2,   /* offset 0x3324 */
+       PINGRP_CPU_PWR_REQ,
+       PINGRP_PWR_INT_N,
+       PINGRP_CLK_32K_IN,
+       PINGRP_OWR,
+       PINGRP_DAP1_FS,
+       PINGRP_DAP1_DIN,
+       PINGRP_DAP1_DOUT,
+       PINGRP_DAP1_SCLK,
+       PINGRP_CLK1_REQ,
+       PINGRP_CLK1_OUT,
+       PINGRP_SPDIF_IN,
+       PINGRP_SPDIF_OUT,
+       PINGRP_DAP2_FS,
+       PINGRP_DAP2_DIN,
+       PINGRP_DAP2_DOUT,
+       PINGRP_DAP2_SCLK,
+       PINGRP_DVFS_PWM,
+       PINGRP_GPIO_X1_AUD,
+       PINGRP_GPIO_X3_AUD,
+       PINGRP_DVFS_CLK,
+       PINGRP_GPIO_X4_AUD,
+       PINGRP_GPIO_X5_AUD,
+       PINGRP_GPIO_X6_AUD,
+       PINGRP_GPIO_X7_AUD,
+       PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
+       PINGRP_SDMMC3_CMD,
+       PINGRP_SDMMC3_DAT0,
+       PINGRP_SDMMC3_DAT1,
+       PINGRP_SDMMC3_DAT2,
+       PINGRP_SDMMC3_DAT3,
+       PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
+       PINGRP_PEX_L0_CLKREQ,
+       PINGRP_PEX_WAKE,
+       PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
+       PINGRP_PEX_L1_CLKREQ,
+       PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
+       PINGRP_SDMMC1_WP_N,
+       PINGRP_SDMMC3_CD_N,
+       PINGRP_GPIO_W2_AUD,
+       PINGRP_GPIO_W3_AUD,
+       PINGRP_USB_VBUS_EN0,
+       PINGRP_USB_VBUS_EN1,
+       PINGRP_SDMMC3_CLK_LB_IN,
+       PINGRP_SDMMC3_CLK_LB_OUT,
+       PINGRP_GMI_CLK_LB,
+       PINGRP_RESET_OUT_N,
+       PINGRP_KB_ROW16,                        /* offset 0x340c */
+       PINGRP_KB_ROW17,
+       PINGRP_USB_VBUS_EN2,
+       PINGRP_GPIO_PFF2,
+       PINGRP_DP_HPD,                          /* last reg offset = 0x3430 */
+       PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+       PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+       PDRIVE_PINGROUP_AO2,
+       PDRIVE_PINGROUP_AT1,
+       PDRIVE_PINGROUP_AT2,
+       PDRIVE_PINGROUP_AT3,
+       PDRIVE_PINGROUP_AT4,
+       PDRIVE_PINGROUP_AT5,
+       PDRIVE_PINGROUP_CDEV1,
+       PDRIVE_PINGROUP_CDEV2,
+       PDRIVE_PINGROUP_DAP1 = 10,      /* offset 0x890 */
+       PDRIVE_PINGROUP_DAP2,
+       PDRIVE_PINGROUP_DAP3,
+       PDRIVE_PINGROUP_DAP4,
+       PDRIVE_PINGROUP_DBG,
+       PDRIVE_PINGROUP_SDIO3 = 18,     /* offset 0x8B0 */
+       PDRIVE_PINGROUP_SPI,
+       PDRIVE_PINGROUP_UAA,
+       PDRIVE_PINGROUP_UAB,
+       PDRIVE_PINGROUP_UART2,
+       PDRIVE_PINGROUP_UART3,
+       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
+       PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
+       PDRIVE_PINGROUP_GMA,
+       PDRIVE_PINGROUP_GME = 42,       /* offset 0x910 */
+       PDRIVE_PINGROUP_GMF,
+       PDRIVE_PINGROUP_GMG,
+       PDRIVE_PINGROUP_GMH,
+       PDRIVE_PINGROUP_OWR,
+       PDRIVE_PINGROUP_UAD,
+       PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
+       PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
+       PDRIVE_PINGROUP_AT6 = 75,       /* offset 0x994 */
+       PDRIVE_PINGROUP_DAP5,
+       PDRIVE_PINGROUP_VBUS,
+       PDRIVE_PINGROUP_AO3,
+       PDRIVE_PINGROUP_HVC,
+       PDRIVE_PINGROUP_SDIO4,
+       PDRIVE_PINGROUP_AO0,
+       PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+       PMUX_FUNC_AHB_CLK,
+       PMUX_FUNC_APB_CLK,
+       PMUX_FUNC_AUDIO_SYNC,
+       PMUX_FUNC_CRT,
+       PMUX_FUNC_DAP1,
+       PMUX_FUNC_DAP2,
+       PMUX_FUNC_DAP3,
+       PMUX_FUNC_DAP4,
+       PMUX_FUNC_DAP5,
+       PMUX_FUNC_DISPA,
+       PMUX_FUNC_DISPB,
+       PMUX_FUNC_EMC_TEST0_DLL,
+       PMUX_FUNC_EMC_TEST1_DLL,
+       PMUX_FUNC_GMI,
+       PMUX_FUNC_GMI_INT,
+       PMUX_FUNC_HDMI,
+       PMUX_FUNC_I2C1,
+       PMUX_FUNC_I2C2,
+       PMUX_FUNC_I2C3,
+       PMUX_FUNC_IDE,
+       PMUX_FUNC_KBC,
+       PMUX_FUNC_MIO,
+       PMUX_FUNC_MIPI_HS,
+       PMUX_FUNC_NAND,
+       PMUX_FUNC_OSC,
+       PMUX_FUNC_OWR,
+       PMUX_FUNC_PCIE,
+       PMUX_FUNC_PLLA_OUT,
+       PMUX_FUNC_PLLC_OUT1,
+       PMUX_FUNC_PLLM_OUT1,
+       PMUX_FUNC_PLLP_OUT2,
+       PMUX_FUNC_PLLP_OUT3,
+       PMUX_FUNC_PLLP_OUT4,
+       PMUX_FUNC_PWM,
+       PMUX_FUNC_PWR_INTR,
+       PMUX_FUNC_PWR_ON,
+       PMUX_FUNC_RTCK,
+       PMUX_FUNC_SDMMC1,
+       PMUX_FUNC_SDMMC2,
+       PMUX_FUNC_SDMMC3,
+       PMUX_FUNC_SDMMC4,
+       PMUX_FUNC_SFLASH,
+       PMUX_FUNC_SPDIF,
+       PMUX_FUNC_SPI1,
+       PMUX_FUNC_SPI2,
+       PMUX_FUNC_SPI2_ALT,
+       PMUX_FUNC_SPI3,
+       PMUX_FUNC_SPI4,
+       PMUX_FUNC_TRACE,
+       PMUX_FUNC_TWC,
+       PMUX_FUNC_UARTA,
+       PMUX_FUNC_UARTB,
+       PMUX_FUNC_UARTC,
+       PMUX_FUNC_UARTD,
+       PMUX_FUNC_UARTE,
+       PMUX_FUNC_ULPI,
+       PMUX_FUNC_VI,
+       PMUX_FUNC_VI_SENSOR_CLK,
+       PMUX_FUNC_XIO,
+       /* End of Tegra2 MUX selectors */
+       PMUX_FUNC_BLINK,
+       PMUX_FUNC_CEC,
+       PMUX_FUNC_CLK12,
+       PMUX_FUNC_DAP,
+       PMUX_FUNC_DAPSDMMC2,
+       PMUX_FUNC_DDR,
+       PMUX_FUNC_DEV3,
+       PMUX_FUNC_DTV,
+       PMUX_FUNC_VI_ALT1,
+       PMUX_FUNC_VI_ALT2,
+       PMUX_FUNC_VI_ALT3,
+       PMUX_FUNC_EMC_DLL,
+       PMUX_FUNC_EXTPERIPH1,
+       PMUX_FUNC_EXTPERIPH2,
+       PMUX_FUNC_EXTPERIPH3,
+       PMUX_FUNC_GMI_ALT,
+       PMUX_FUNC_HDA,
+       PMUX_FUNC_HSI,
+       PMUX_FUNC_I2C4,
+       PMUX_FUNC_I2C5,
+       PMUX_FUNC_I2CPWR,
+       PMUX_FUNC_I2S0,
+       PMUX_FUNC_I2S1,
+       PMUX_FUNC_I2S2,
+       PMUX_FUNC_I2S3,
+       PMUX_FUNC_I2S4,
+       PMUX_FUNC_NAND_ALT,
+       PMUX_FUNC_POPSDIO4,
+       PMUX_FUNC_POPSDMMC4,
+       PMUX_FUNC_PWM0,
+       PMUX_FUNC_PWM1,
+       PMUX_FUNC_PWM2,
+       PMUX_FUNC_PWM3,
+       PMUX_FUNC_SATA,
+       PMUX_FUNC_SPI5,
+       PMUX_FUNC_SPI6,
+       PMUX_FUNC_SYSCLK,
+       PMUX_FUNC_VGP1,
+       PMUX_FUNC_VGP2,
+       PMUX_FUNC_VGP3,
+       PMUX_FUNC_VGP4,
+       PMUX_FUNC_VGP5,
+       PMUX_FUNC_VGP6,
+       /* End of Tegra3 MUX selectors */
+       PMUX_FUNC_USB,
+       PMUX_FUNC_SOC,
+       PMUX_FUNC_CPU,
+       PMUX_FUNC_CLK,
+       PMUX_FUNC_PWRON,
+       PMUX_FUNC_PMI,
+       PMUX_FUNC_CLDVFS,
+       PMUX_FUNC_RESET_OUT_N,
+       /* End of Tegra114 MUX selectors */
+
+       PMUX_FUNC_SAFE,
+       PMUX_FUNC_MAX,
+
+       PMUX_FUNC_INVALID = 0x4000,
+       PMUX_FUNC_RSVD1 = 0x8000,
+       PMUX_FUNC_RSVD2 = 0x8001,
+       PMUX_FUNC_RSVD3 = 0x8002,
+       PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+       ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
+       (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+       PMUX_PULL_NORMAL = 0,
+       PMUX_PULL_DOWN,
+       PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+                               ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+       PMUX_TRI_NORMAL = 0,
+       PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+       (((tristate) >= PMUX_TRI_NORMAL) && \
+       ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+       PMUX_PIN_OUTPUT = 0,
+       PMUX_PIN_INPUT = 1,
+       PMUX_PIN_NONE,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+                               ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+       PMUX_PIN_LOCK_DEFAULT = 0,
+       PMUX_PIN_LOCK_DISABLE,
+       PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+                               ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+       PMUX_PIN_OD_DEFAULT = 0,
+       PMUX_PIN_OD_DISABLE,
+       PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+                               ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+       PMUX_PIN_IO_RESET_DEFAULT = 0,
+       PMUX_PIN_IO_RESET_DISABLE,
+       PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+                               (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+                               ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+enum pmux_pin_rcv_sel {
+       PMUX_PIN_RCV_SEL_DEFAULT = 0,
+       PMUX_PIN_RCV_SEL_NORMAL,
+       PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+                               (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+                               ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+       PMUX_VDDIO_BB = 0,
+       PMUX_VDDIO_LCD,
+       PMUX_VDDIO_VI,
+       PMUX_VDDIO_UART,
+       PMUX_VDDIO_DDR,
+       PMUX_VDDIO_NAND,
+       PMUX_VDDIO_SYS,
+       PMUX_VDDIO_AUDIO,
+       PMUX_VDDIO_SD,
+       PMUX_VDDIO_CAM,
+       PMUX_VDDIO_GMI,
+       PMUX_VDDIO_PEXCTL,
+       PMUX_VDDIO_SDMMC1,
+       PMUX_VDDIO_SDMMC3,
+       PMUX_VDDIO_SDMMC4,
+
+       PMUX_VDDIO_NONE
+};
+
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX  3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX  PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE        -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE        PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE        -1
+#define PGRP_HSM_NONE  PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+                               (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+                               (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+                               (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+       PGRP_LPMD_X8 = 0,
+       PGRP_LPMD_X4,
+       PGRP_LPMD_X2,
+       PGRP_LPMD_X,
+       PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+       PGRP_SCHMT_DISABLE = 0,
+       PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+       PGRP_HSM_DISABLE = 0,
+       PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+       enum pdrive_pingrp padgrp;      /* pin group PDRIVE_PINGRP_x */
+       int slwf;                       /* falling edge slew         */
+       int slwr;                       /* rising edge slew          */
+       int drvup;                      /* pull-up drive strength    */
+       int drvdn;                      /* pull-down drive strength  */
+       enum pgrp_lpmd lpmd;            /* low-power mode selection  */
+       enum pgrp_schmt schmt;          /* schmidt enable            */
+       enum pgrp_hsm hsm;              /* high-speed mode enable    */
+};
+
+/* Tegra124 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET    ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+                               PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+       uint pmt_reserved0[9];          /* ABP_MISC_PP_ offsets 00-20 */
+       uint pmt_cfg_ctl;               /* _CONFIG_CTL_0, offset 24        */
+
+       uint pmt_reserved[528];         /* ABP_MISC_PP_ reserved offs 28-864 */
+
+       uint pmt_drive[PDRIVE_PINGROUP_COUNT];  /* pin drive grps offs 868 */
+       uint pmt_reserved5[PMUX_OFFSET];
+       uint pmt_ctl[PINGRP_COUNT];     /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+       enum pmux_pingrp pingroup;      /* pin group PINGRP_...             */
+       enum pmux_func func;            /* function to assign FUNC_...      */
+       enum pmux_pull pull;            /* pull up/down/normal PMUX_PULL_...*/
+       enum pmux_tristate tristate;    /* tristate or normal PMUX_TRI_...  */
+       enum pmux_pin_io io;            /* input or output PMUX_PIN_...  */
+       enum pmux_pin_lock lock;        /* lock enable/disable PMUX_PIN...  */
+       enum pmux_pin_od od;            /* open-drain or push-pull driver  */
+       enum pmux_pin_ioreset ioreset;  /* input/output reset PMUX_PIN...  */
+       enum pmux_pin_rcv_sel rcv_sel;  /* select between High and Normal  */
+                                       /* VIL/VIH receivers */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h
new file mode 100644 (file)
index 0000000..b10100a
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA124_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
new file mode 100644 (file)
index 0000000..e266395
--- /dev/null
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644 (file)
index 0000000..3f0309b
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+       u32 cntcr;              /* 0x00: SYSCTR0_CNTCR Counter Control */
+       u32 cntsr;              /* 0x04: SYSCTR0_CNTSR Counter Status */
+       u32 cntcv0;             /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+       u32 cntcv1;             /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+       u32 reserved1[4];       /* 0x10 - 0x1C */
+       u32 cntfid0;            /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+       u32 cntfid1;            /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+       u32 reserved2[1002];    /* 0x28 - 0xFCC */
+       u32 counterid[12];      /* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE       (1 << 0)        /* Enable */
+#define TSC_CNTCR_HDBG         (1 << 1)        /* Halt on debug */
+
+#endif /* _TEGRA124_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644 (file)
index 0000000..db3d837
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define NV_PA_SDRAM_BASE       0x80000000
+#define NV_PA_TSC_BASE         0x700F0000      /* System Counter TSC regs */
+#define NV_PA_MC_BASE          0x70019000      /* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE         0x6000C000      /* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET     1704    /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE        0x48    /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C    /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU            4
+#define MCB_EMEM_ARB_OVERRIDE  (NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE                0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h
new file mode 100644 (file)
index 0000000..7a2d785
--- /dev/null
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_USB_H_
+#define _TEGRA124_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+       /* 0x000 */
+       uint id;
+       uint reserved0;
+       uint host;
+       uint device;
+
+       /* 0x010 */
+       uint txbuf;
+       uint rxbuf;
+       uint reserved1[2];
+
+       /* 0x020 */
+       uint reserved2[56];
+
+       /* 0x100 */
+       u16 cap_length;
+       u16 hci_version;
+       uint hcs_params;
+       uint hcc_params;
+       uint reserved3[5];
+
+       /* 0x120 */
+       uint dci_version;
+       uint dcc_params;
+       uint reserved4[2];
+
+       /* 0x130 */
+       uint usb_cmd;
+       uint usb_sts;
+       uint usb_intr;
+       uint frindex;
+
+       /* 0x140 */
+       uint reserved5;
+       uint periodic_list_base;
+       uint async_list_addr;
+       uint reserved5_1;
+
+       /* 0x150 */
+       uint burst_size;
+       uint tx_fill_tuning;
+       uint reserved6;
+       uint icusb_ctrl;
+
+       /* 0x160 */
+       uint ulpi_viewport;
+       uint reserved7;
+       uint reserved7_0;
+       uint reserved7_1;
+
+       /* 0x170 */
+       uint reserved;
+       uint port_sc1;
+       uint reserved8[6];
+
+       /* 0x190 */
+       uint reserved9[8];
+
+       /* 0x1b0 */
+       uint reserved10;
+       uint hostpc1_devlc;
+       uint reserved10_1[2];
+
+       /* 0x1c0 */
+       uint reserved10_2[4];
+
+       /* 0x1d0 */
+       uint reserved10_3[4];
+
+       /* 0x1e0 */
+       uint reserved10_4[4];
+
+       /* 0x1f0 */
+       uint reserved10_5;
+       uint otgsc;
+       uint usb_mode;
+       uint reserved10_6;
+
+       /* 0x200 */
+       uint endpt_nak;
+       uint endpt_nak_enable;
+       uint endpt_setup_stat;
+       uint reserved11_1[0x7D];
+
+       /* 0x400 */
+       uint susp_ctrl;
+       uint phy_vbus_sensors;
+       uint phy_vbus_wakeup_id;
+       uint phy_alt_vbus_sys;
+
+       /* 0x410 */
+       uint usb1_legacy_ctrl;
+       uint reserved12[3];
+
+       /* 0x420 */
+       uint reserved13[56];
+
+       /* 0x500 */
+       uint reserved14[64 * 3];
+
+       /* 0x800 */
+       uint utmip_pll_cfg0;
+       uint utmip_pll_cfg1;
+       uint utmip_xcvr_cfg0;
+       uint utmip_bias_cfg0;
+
+       /* 0x810 */
+       uint utmip_hsrx_cfg0;
+       uint utmip_hsrx_cfg1;
+       uint utmip_fslsrx_cfg0;
+       uint utmip_fslsrx_cfg1;
+
+       /* 0x820 */
+       uint utmip_tx_cfg0;
+       uint utmip_misc_cfg0;
+       uint utmip_misc_cfg1;
+       uint utmip_debounce_cfg0;
+
+       /* 0x830 */
+       uint utmip_bat_chrg_cfg0;
+       uint utmip_spare_cfg0;
+       uint utmip_xcvr_cfg1;
+       uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE            1
+
+#define VBUS_SENSE_CTL_SHIFT                   1
+#define VBUS_SENSE_CTL_MASK                    (3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP             0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP      1
+#define VBUS_SENSE_CTL_AB_SESS_VLD             2
+#define VBUS_SENSE_CTL_A_SESS_VLD              3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB                          (1 << 12)
+#define UTMIP_RESET                            (1 << 11)
+#define USB_PHY_CLK_VALID                      (1 << 7)
+#define USB_SUSP_CLR                           (1 << 5)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE             (1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN                 (1 << 30)
+
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT          6
+#define UTMIP_PLLU_STABLE_COUNT_MASK           \
+                               (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT       18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK                \
+                               (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT      27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK       \
+                               (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT            0
+#define UTMIP_XTAL_FREQ_COUNT_MASK             0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB               (1 << 24)
+#define UTMIP_OTGPD                            (1 << 11)
+#define UTMIP_BIASPD                           (1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT             2
+#define UTMIP_HSDISCON_LEVEL_MASK              \
+                               (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT            0
+#define UTMIP_HSSQUELCH_LEVEL_MASK             \
+                               (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN            1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT           3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK            \
+                               (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT              0
+#define UTMIP_DEBOUNCE_CFG0_MASK               0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J                    (1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG                          1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL                         (1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT                  15
+#define UTMIP_IDLE_WAIT_MASK                   (0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT              10
+#define UTMIP_ELASTIC_LIMIT_MASK               \
+                               (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT          1
+#define UTMIP_HS_SYNC_START_DLY_MASK           \
+                               (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1                                        (1 << 3)
+
+/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
+#define PTS1_SHIFT                             31
+#define PTS1_MASK                              (1 << PTS1_SHIFT)
+#define STS1                                   (1 << 30)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT                              29
+#define PTS_MASK                               (0x7U << PTS_SHIFT)
+#define PTS_UTMI       0
+#define PTS_RESERVED   1
+#define PTS_ULPI       2
+#define PTS_ICUSB_SER  3
+#define PTS_HSIC       4
+
+#define STS                                    (1 << 28)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC                           (1 << 22)
+#define WKDS                           (1 << 21)
+#define WKCN                           (1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN               (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN              (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN             (1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE                   (1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT            25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK             \
+                       (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT     22
+#define UTMIP_XCVR_SETUP_MSB_MASK      (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT         0
+#define UTMIP_XCVR_SETUP_MASK          (0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK         \
+                       (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN           (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN           (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN             (1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS                   (1 << 26)
+
+#endif /* _TEGRA124_USB_H_ */