[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
[XAUI_FM1] = "XAUI_FM1",
[XAUI_FM2] = "XAUI_FM2",
[AURORA] = "DEBUG",
case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4:
+ case SGMII_FM2_DTSEC5:
case XAUI_FM1:
case XAUI_FM2:
case SRIO1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_4;
break;
+ case SGMII_FM2_DTSEC5:
+ serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+ FSL_CORENET_DEVDISR2_DTSEC2_5;
+ break;
case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
FSL_CORENET_DEVDISR2_10GEC1;
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+ FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
+ FM2_DTSEC5,
FM2_10GEC1,
NUM_FM_PORTS,
};