]> git.sur5r.net Git - u-boot/commitdiff
powerpc/85xx: add support for FM2 DTSEC5
authorTimur Tabi <timur@freescale.com>
Tue, 14 Aug 2012 06:47:21 +0000 (06:47 +0000)
committerAndy Fleming <afleming@freescale.com>
Thu, 23 Aug 2012 15:24:18 +0000 (10:24 -0500)
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/immap_85xx.h
drivers/net/fm/init.c
include/fm_eth.h

index 4b52dad56cefa08651bb349295569bd9efa96f52..8aac1dec0f2e2c27a4391c88f5e1c25694fc7478 100644 (file)
@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
        [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
        [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
        [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+       [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
        [XAUI_FM1] = "XAUI_FM1",
        [XAUI_FM2] = "XAUI_FM2",
        [AURORA] = "DEBUG",
@@ -658,6 +659,7 @@ void fsl_serdes_init(void)
                case SGMII_FM2_DTSEC2:
                case SGMII_FM2_DTSEC3:
                case SGMII_FM2_DTSEC4:
+               case SGMII_FM2_DTSEC5:
                case XAUI_FM1:
                case XAUI_FM2:
                case SRIO1:
@@ -717,6 +719,10 @@ void fsl_serdes_init(void)
                        serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
                                            FSL_CORENET_DEVDISR2_DTSEC2_4;
                        break;
+               case SGMII_FM2_DTSEC5:
+                       serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
+                                           FSL_CORENET_DEVDISR2_DTSEC2_5;
+                       break;
                case XAUI_FM1:
                        serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1    |
                                            FSL_CORENET_DEVDISR2_10GEC1;
index 0f31af1db320e8d9272eaefd8dbf9446a8b546a2..22525f1156121d04a54682a0bd4c04573a89e05e 100644 (file)
@@ -41,6 +41,7 @@ enum srds_prtcl {
        SGMII_FM2_DTSEC2,
        SGMII_FM2_DTSEC3,
        SGMII_FM2_DTSEC4,
+       SGMII_FM2_DTSEC5,
        SGMII_TSEC1,
        SGMII_TSEC2,
        SGMII_TSEC3,
index 83f8813db53ddc3a11a3c23f50ba3cb2ae13d9cb..9bdfd97da22471d9f11c41916a776207fb717f8f 100644 (file)
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5  0x00000800
 #define FSL_CORENET_NUM_DEVDISR                2
        u8      res7[8];
        u32     powmgtcsr;      /* Power management status & control */
index 953c359e6e45c1354e926b414124206c2bfc1b92..9834cd97053b768d2307d5e54e9a35276fea71c1 100644 (file)
@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
        FM_DTSEC_INFO_INITIALIZER(2, 4),
 #endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
+       FM_DTSEC_INFO_INITIALIZER(2, 5),
+#endif
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
        FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif
index c7c68820d57a7ef795139d82cb9b15a8eace85d9..05121ea8ef839994fdc663c6e481500533128e0d 100644 (file)
@@ -35,6 +35,7 @@ enum fm_port {
        FM2_DTSEC2,
        FM2_DTSEC3,
        FM2_DTSEC4,
+       FM2_DTSEC5,
        FM2_10GEC1,
        NUM_FM_PORTS,
 };