config TARGET_MPC8560ADS
        bool "Support MPC8560ADS"
+       select ARCH_MPC8560
 
 config TARGET_MPC8568MDS
        bool "Support MPC8568MDS"
 config ARCH_MPC8555
        bool
 
+config ARCH_MPC8560
+       bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
 
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-       defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_MPC8560)
+       defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
        unsigned long val, msr;
 
        /*
 
                 */
                lcrr_div *= 4;
 #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560)
+       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
                /*
                 * Yes, the entire PQ38 family use the same
                 * bit-representation for twice the clock divider values.
         * AN2919.
         */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-       defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
+       defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
        defined(CONFIG_P1022)
        gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_ARCH_MPC8544)
 
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 
-#elif defined(CONFIG_MPC8560)
+#elif defined(CONFIG_ARCH_MPC8560)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 
 #define LCRR_CLKDIV_SHIFT              0
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
        defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
-       defined(CONFIG_MPC8560)
+       defined(CONFIG_ARCH_MPC8560)
 #define LCRR_CLKDIV_2                  0x00000002
 #define LCRR_CLKDIV_4                  0x00000004
 #define LCRR_CLKDIV_8                  0x00000008
 
 #define CONFIG_E500            1       /* BOOKE e500 family */
 #define CONFIG_CPM2            1       /* has CPM2 */
 #define CONFIG_MPC8560ADS      1       /* MPC8560ADS board specific */
-#define CONFIG_MPC8560         1
 
 /*
  * default CCARBAR is at 0xff700000
 
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC855
-CONFIG_MPC8560
 CONFIG_MPC8560ADS
 CONFIG_MPC8568
 CONFIG_MPC8568MDS