}
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
+       /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
+        * multi-bit ECC errors which has impact on performance, so software
+        * should disable all ECC reporting from USB1 and USB2.
+        */
+       if (IS_SVR_REV(get_svr(), 1, 0)) {
+               struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
+                       (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+               setbits_be32(&dcfg->ecccr1,
+                               (DCSR_DCFG_ECC_DISABLE_USB1 |
+                                DCSR_DCFG_ECC_DISABLE_USB2));
+       }
+#endif
+
 #ifdef CONFIG_FMAN_ENET
        fman_enet_init();
 #endif
 
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+#define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+#define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_ERRATUM_A004699
 
 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define        CONFIG_SYS_DCSR_DCFG_OFFSET     0X20000
+struct dcsr_dcfg_regs {
+       u8  res_0[0x520];
+       u32 ecccr1;
+#define        DCSR_DCFG_ECC_DISABLE_USB1      0x00008000
+#define        DCSR_DCFG_ECC_DISABLE_USB2      0x00004000
+       u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
+};
 #endif /*__IMMAP_85xx__*/