#endif
/* Now bring in the rest of the common code. */
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
/* Always 64 KiB env size */
#define CONFIG_ENV_SIZE (64 << 10)
#endif
/* Now bring in the rest of the common code. */
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
#endif /* __CONFIG_TI_AM335X_COMMON_H__ */
#define __CONFIG_TI_ARMV7_COMMON_H__
/* Common define for many platforms. */
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
/*
#define CONFIG_I2C
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP24XX
/* MMC/SD IP block */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
/* McSPI IP block */
#define CONFIG_SPI
-#define CONFIG_OMAP3_SPI
#define CONFIG_CMD_SPI
/* GPIO block */
-#define CONFIG_OMAP_GPIO
#define CONFIG_CMD_GPIO
-/*
- * GPMC NAND block. We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE 0x8000000
-#endif
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
-#endif
-
/*
* The following are general good-enough settings for U-Boot. We set a
* large malloc pool as we generally have a lot of DDR, and we opt for
--- /dev/null
+/*
+ * ti_armv7_omap.h
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature. This is meant to isolate the features
+ * that are based on OMAP architecture.
+ */
+#ifndef __CONFIG_TI_ARMV7_OMAP_H__
+#define __CONFIG_TI_ARMV7_OMAP_H__
+
+/* Common defines for all OMAP architecture based SoCs */
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* MMC/SD IP block */
+#define CONFIG_OMAP_HSMMC
+
+/* SPI IP Block */
+#define CONFIG_OMAP3_SPI
+
+/* GPIO block */
+#define CONFIG_OMAP_GPIO
+
+/*
+ * GPMC NAND block. We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE 0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_CMD_NAND
+#endif
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */
#endif
/* Now bring in the rest of the common code. */
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
/*
* Hardware drivers
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
/*
* Hardware drivers