]> git.sur5r.net Git - u-boot/commitdiff
Driver/DDR: Add Freescale DDR driver for ARM
authorYork Sun <yorksun@freescale.com>
Mon, 30 Sep 2013 21:20:51 +0000 (14:20 -0700)
committerYork Sun <yorksun@freescale.com>
Mon, 25 Nov 2013 19:43:46 +0000 (11:43 -0800)
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.

Signed-off-by: York Sun <yorksun@freescale.com>
README
drivers/ddr/fsl/Makefile
drivers/ddr/fsl/arm_ddr_gen3.c [new file with mode: 0644]
drivers/ddr/fsl/main.c
drivers/ddr/fsl/util.c

diff --git a/README b/README
index 49f4b3af2f6710819b17cb56494b4eb0fc683158..d6006f50180f7df3f16340046e7b5ad39f069601 100644 (file)
--- a/README
+++ b/README
@@ -450,6 +450,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_ARM_GEN3
+               Freescale DDR3 controller for ARM-based SoCs.
+
                CONFIG_SYS_FSL_DDR1
                Board config to use DDR1. It can be enabled for SoCs with
                Freescale DDR1 or DDR2 controllers, depending on the board
index a328b43209934d07fe7a89dbef682decce803267..265204f31199bd7069c14175bf4a15d7615d3120 100644 (file)
@@ -31,4 +31,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN1)       += mpc85xx_ddr_gen1.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN2)        += mpc85xx_ddr_gen2.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN3)        += mpc85xx_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDR_86XX)         += mpc86xx_ddr.o
-obj-$(CONFIG_FSL_DDR_INTERACTIVE)      += interactive.o
+obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)    += arm_ddr_gen3.o
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
new file mode 100644 (file)
index 0000000..bf11390
--- /dev/null
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <fsl_immap.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ *       1 sets registers and returns before enabling controller
+ *       2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                            unsigned int ctrl_num, int step)
+{
+       unsigned int i, bus_width;
+       struct ccsr_ddr __iomem *ddr;
+       u32 temp_sdram_cfg;
+       u32 total_gb_size_per_controller;
+       int timeout;
+
+       switch (ctrl_num) {
+       case 0:
+               ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+               break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+       case 1:
+               ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+               break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+       case 2:
+               ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+               break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+       case 3:
+               ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+               break;
+#endif
+       default:
+               printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
+               return;
+       }
+
+       if (step == 2)
+               goto step2;
+
+       if (regs->ddr_eor)
+               out_be32(&ddr->eor, regs->ddr_eor);
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (i == 0) {
+                       out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs0_config, regs->cs[i].config);
+                       out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+               } else if (i == 1) {
+                       out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs1_config, regs->cs[i].config);
+                       out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+               } else if (i == 2) {
+                       out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs2_config, regs->cs[i].config);
+                       out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+               } else if (i == 3) {
+                       out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+                       out_be32(&ddr->cs3_config, regs->cs[i].config);
+                       out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+               }
+       }
+
+       out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+       out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+       out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+       out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+       out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+       out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
+       out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
+       out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
+       out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
+       out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
+       out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
+       out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+       out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+       out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+       out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+       out_be32(&ddr->init_addr, regs->ddr_init_addr);
+       out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+       out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+       out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+       out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+       out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+       /*
+        * Skip these two registers if running on emulator
+        * because emulator doesn't have skew between bytes.
+        */
+
+       if (regs->ddr_wrlvl_cntl_2)
+               out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+       if (regs->ddr_wrlvl_cntl_3)
+               out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
+
+       out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+       out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+       out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+       out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
+       out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       out_be32(&ddr->err_disable, regs->err_disable);
+       out_be32(&ddr->err_int_en, regs->err_int_en);
+       for (i = 0; i < 32; i++) {
+               if (regs->debug[i]) {
+                       debug("Write to debug_%d as %08x\n", i + 1,
+                             regs->debug[i]);
+                       out_be32(&ddr->debug[i], regs->debug[i]);
+               }
+       }
+
+       /*
+        * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+        * deasserted. Clocks start when any chip select is enabled and clock
+        * control register is set. Because all DDR components are connected to
+        * one reset signal, this needs to be done in two steps. Step 1 is to
+        * get the clocks started. Step 2 resumes after reset signal is
+        * deasserted.
+        */
+       if (step == 1) {
+               udelay(200);
+               return;
+       }
+
+step2:
+       /* Set, but do not enable the memory */
+       temp_sdram_cfg = regs->ddr_sdram_cfg;
+       temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+       /*
+        * 500 painful micro-seconds must elapse between
+        * the DDR clock setup and the DDR config enable.
+        * DDR2 need 200 us, and DDR3 need 500 us from spec,
+        * we choose the max, that is 500 us for all of case.
+        */
+       udelay(500);
+       asm volatile("dsb sy;isb");
+
+       /* Let the controller go */
+       temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+       asm volatile("dsb sy;isb");
+
+       total_gb_size_per_controller = 0;
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               if (!(regs->cs[i].config & 0x80000000))
+                       continue;
+               total_gb_size_per_controller += 1 << (
+                       ((regs->cs[i].config >> 14) & 0x3) + 2 +
+                       ((regs->cs[i].config >> 8) & 0x7) + 12 +
+                       ((regs->cs[i].config >> 0) & 0x7) + 8 +
+                       3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+                       26);                    /* minus 26 (count of 64M) */
+       }
+       if (regs->cs[0].config & 0x20000000) {
+               /* 2-way interleaving */
+               total_gb_size_per_controller <<= 1;
+       }
+       /*
+        * total memory / bus width = transactions needed
+        * transactions needed / data rate = seconds
+        * to add plenty of buffer, double the time
+        * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+        * Let's wait for 800ms
+        */
+       bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+                       >> SDRAM_CFG_DBW_SHIFT);
+       timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+               (get_ddr_freq(0) >> 20)) << 1;
+       total_gb_size_per_controller >>= 4;     /* shift down to gb size */
+       debug("total %d GB\n", total_gb_size_per_controller);
+       debug("Need to wait up to %d * 10ms\n", timeout);
+
+       /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
+       while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+               (timeout >= 0)) {
+               udelay(10000);          /* throttle polling rate */
+               timeout--;
+       }
+
+       if (timeout <= 0)
+               printf("Waiting for D_INIT timeout. Memory may not work.\n");
+}
index c1cdbdf95514c9521e00d8ffeccf8632585a26f1..b4988e194cfad3f20fcddabbc2dfb875181441b9 100644 (file)
 #include <common.h>
 #include <i2c.h>
 #include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
 #include <fsl_ddr.h>
 
+#ifdef CONFIG_PPC
+#include <asm/fsl_law.h>
+
 void fsl_ddr_set_lawbar(
                const common_timing_params_t *memctl_common_params,
                unsigned int memctl_interleaved,
                unsigned int ctrl_num);
-void fsl_ddr_set_intl3r(const unsigned int granule_size);
+#endif
 
+void fsl_ddr_set_intl3r(const unsigned int granule_size);
 #if defined(SPD_EEPROM_ADDRESS) || \
     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -549,7 +551,9 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 phys_size_t fsl_ddr_sdram(void)
 {
        unsigned int i;
+#ifdef CONFIG_PPC
        unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
+#endif
        unsigned long long total_memory;
        fsl_ddr_info_t info;
        int deassert_reset;
@@ -621,6 +625,7 @@ phys_size_t fsl_ddr_sdram(void)
                }
        }
 
+#ifdef CONFIG_PPC
        /* program LAWs */
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                if (info.memctl_opts[i].memctl_interleaving) {
@@ -681,6 +686,7 @@ phys_size_t fsl_ddr_sdram(void)
                                        law_memctl, i);
                }
        }
+#endif
 
        debug("total_memory by %s = %llu\n", __func__, total_memory);
 
index 5d6b3625104f1e408f3aa0a65956d8f469ba52ba..0658261d8dac86321416821d0d0fd034a316d528 100644 (file)
@@ -7,7 +7,9 @@
  */
 
 #include <common.h>
+#ifdef CONFIG_PPC
 #include <asm/fsl_law.h>
+#endif
 #include <div64.h>
 
 #include <fsl_ddr.h>
@@ -79,6 +81,7 @@ unsigned int mclk_to_picos(unsigned int mclk)
        return get_memory_clk_period_ps() * mclk;
 }
 
+#ifdef CONFIG_PPC
 void
 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
                           unsigned int law_memctl,
@@ -113,6 +116,7 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
                         unsigned int memctl_interleaved,
                         unsigned int ctrl_num);
+#endif
 
 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 {