Add memory barrier instructions to Tasking CM4F port.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1862 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
index 07995e3ea80c911067247cd223f749dc2f42ec93..f94d06f6ea17bc433effa1b12a2164198201006b 100644 (file)
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -83,12 +83,10 @@
 /* Constants required to manipulate the NVIC. */\r
 #define portNVIC_SYSTICK_CTRL          ( ( volatile unsigned long * ) 0xe000e010 )\r
 #define portNVIC_SYSTICK_LOAD          ( ( volatile unsigned long * ) 0xe000e014 )\r
-#define portNVIC_INT_CTRL                      ( ( volatile unsigned long * ) 0xe000ed04 )\r
 #define portNVIC_SYSPRI2                       ( ( volatile unsigned long * ) 0xe000ed20 )\r
 #define portNVIC_SYSTICK_CLK           0x00000004\r
 #define portNVIC_SYSTICK_INT           0x00000002\r
 #define portNVIC_SYSTICK_ENABLE                0x00000001\r
-#define portNVIC_PENDSVSET                     0x10000000\r
 #define portNVIC_PENDSV_PRI                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
 #define portNVIC_SYSTICK_PRI           ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
 \r
@@ -204,10 +202,15 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __DSB();\r
+       __ISB();\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -215,6 +218,8 @@ void vPortEnterCritical( void )
 {\r
        portDISABLE_INTERRUPTS();\r
        ulCriticalNesting++;\r
+       __DSB();\r
+       __ISB();\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r

diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
index b2631954a777e802d3b5c8f7f30052c8ce7d1af9..59d16b4cc62377c1f5ba2b9a02efc4fb0415c84c 100644 (file)
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -81,7 +81,7 @@ extern "C" {
 #endif\r
 \r
 /*-----------------------------------------------------------\r
- * Port specific definitions.  \r
+ * Port specific definitions.\r
  *\r
  * The settings in this file configure FreeRTOS correctly for the\r
  * given hardware and compiler.\r
@@ -106,40 +106,41 @@ extern "C" {
        typedef unsigned portLONG portTickType;\r
        #define portMAX_DELAY ( portTickType ) 0xffffffff\r
 #endif\r
-/*-----------------------------------------------------------*/        \r
+/*-----------------------------------------------------------*/\r
 \r
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
-#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
+#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
 #define portBYTE_ALIGNMENT                     8\r
-/*-----------------------------------------------------------*/        \r
+/*-----------------------------------------------------------*/\r
 \r
 \r
 /* Scheduler utilities. */\r
-extern void vPortYieldFromISR( void );\r
-\r
-#define portYIELD()                                    vPortYieldFromISR()\r
+extern void vPortYield( void );\r
+#define portNVIC_INT_CTRL                      ( ( volatile unsigned long * ) 0xe000ed04 )\r
+#define portNVIC_PENDSVSET                     0x10000000\r
+#define portYIELD()                                    vPortYield()\r
 \r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET\r
 /*-----------------------------------------------------------*/\r
 \r
 \r
 /* Critical section management. */\r
 \r
-/* \r
+/*\r
  * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other\r
  * registers.  r0 is clobbered.\r
- */ \r
+ */\r
 #define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
-       \r
+\r
 /*\r
  * Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see\r
  * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
  */\r
 #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )\r
 \r
-/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see \r
+/* FAQ:  Setting BASEPRI to 0 is not a bug.  Please see\r
 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              0;portSET_INTERRUPT_MASK()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   portCLEAR_INTERRUPT_MASK();(void)x\r
@@ -153,7 +154,7 @@ extern void vPortExitCritical( void );
 #define portENTER_CRITICAL()           vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                    vPortExitCritical()\r
 \r
-/* There are an uneven number of items on the initial stack, so \r
+/* There are an uneven number of items on the initial stack, so\r
 portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
 #define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
 \r